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* [PATCH v13 0/6] drm/i915: expose RCS topology to userspace
@ 2018-02-15 12:01 Lionel Landwerlin
  2018-02-15 12:01 ` [PATCH v13 1/6] drm/i915: store all subslice masks Lionel Landwerlin
                   ` (10 more replies)
  0 siblings, 11 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2018-02-15 12:01 UTC (permalink / raw)
  To: intel-gfx; +Cc: joonas.lahtinen

Hi all,

After some discussion with Joonas we agreed on changing some of the
rcs topology structs in the uAPI. It now uses a single struct instead
of 3.

I've also changed the bit the query uAPI to make it more sensible to
userspace (please see comment in patch 5).

Therefore dropping the Rb on patches 5 & 6.

Cheers,

Lionel Landwerlin (6):
  drm/i915: store all subslice masks
  drm/i915/debugfs: reuse max slice/subslices already stored in sseu
  drm/i915/debugfs: add rcs topology entry
  drm/i915: add rcs topology to error state
  drm/i915: add query uAPI
  drm/i915: expose rcs topology through query uAPI

 drivers/gpu/drm/i915/Makefile            |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c      |  63 +++++----
 drivers/gpu/drm/i915/i915_drv.c          |   4 +-
 drivers/gpu/drm/i915/i915_gpu_error.c    |   1 +
 drivers/gpu/drm/i915/i915_query.c        | 138 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_query.h        |  33 +++++
 drivers/gpu/drm/i915/intel_device_info.c | 226 ++++++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_device_info.h |  49 ++++++-
 drivers/gpu/drm/i915/intel_lrc.c         |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
 include/uapi/drm/i915_drm.h              |  81 +++++++++++
 11 files changed, 521 insertions(+), 79 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_query.c
 create mode 100644 drivers/gpu/drm/i915/i915_query.h

--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* [PATCH v13 1/6] drm/i915: store all subslice masks
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
@ 2018-02-15 12:01 ` Lionel Landwerlin
  2018-02-15 12:01 ` [PATCH v13 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu Lionel Landwerlin
                   ` (9 subsequent siblings)
  10 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2018-02-15 12:01 UTC (permalink / raw)
  To: intel-gfx; +Cc: joonas.lahtinen

Up to now, subslice mask was assumed to be uniform across slices. But
starting with Cannonlake, slices can be asymmetric (for example slice0
has different number of subslices as slice1+). This change stores all
subslices masks for all slices rather than having a single mask that
applies to all slices.

v2: Rework how we store total numbers in sseu_dev_info (Tvrtko)
    Fix CHV eu masks, was reading disabled as enabled (Tvrtko)
    Readability changes (Tvrtko)
    Add EU index helper (Tvrtko)

v3: Turn ALIGN(v, 8) / 8 into DIV_ROUND_UP(v, BITS_PER_BYTE) (Tvrtko)
    Reuse sseu_eu_idx() for setting eu_mask on CHV (Tvrtko)
    Reformat debug prints for subslices (Tvrtko)

v4: Change eu_mask helper into sseu_set_eus() (Tvrtko)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c      |  25 ++--
 drivers/gpu/drm/i915/i915_drv.c          |   2 +-
 drivers/gpu/drm/i915/intel_device_info.c | 201 +++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_device_info.h |  47 +++++++-
 drivers/gpu/drm/i915/intel_lrc.c         |   2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |   2 +-
 6 files changed, 216 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 960302668649..a5090e840c09 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4273,7 +4273,7 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
 			continue;
 
 		sseu->slice_mask = BIT(0);
-		sseu->subslice_mask |= BIT(ss);
+		sseu->subslice_mask[0] |= BIT(ss);
 		eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
 			 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
 			 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
@@ -4320,7 +4320,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
 			continue;
 
 		sseu->slice_mask |= BIT(s);
-		sseu->subslice_mask = info->sseu.subslice_mask;
+		sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
 		for (ss = 0; ss < ss_max; ss++) {
 			unsigned int eu_cnt;
@@ -4375,8 +4375,8 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 		sseu->slice_mask |= BIT(s);
 
 		if (IS_GEN9_BC(dev_priv))
-			sseu->subslice_mask =
-				INTEL_INFO(dev_priv)->sseu.subslice_mask;
+			sseu->subslice_mask[s] =
+				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
 
 		for (ss = 0; ss < ss_max; ss++) {
 			unsigned int eu_cnt;
@@ -4386,7 +4386,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 					/* skip disabled subslice */
 					continue;
 
-				sseu->subslice_mask |= BIT(ss);
+				sseu->subslice_mask[s] |= BIT(ss);
 			}
 
 			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
@@ -4408,9 +4408,12 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
 	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
 
 	if (sseu->slice_mask) {
-		sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
 		sseu->eu_per_subslice =
 				INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
+		for (s = 0; s < fls(sseu->slice_mask); s++) {
+			sseu->subslice_mask[s] =
+				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
+		}
 		sseu->eu_total = sseu->eu_per_subslice *
 				 sseu_subslice_total(sseu);
 
@@ -4429,6 +4432,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	const char *type = is_available_info ? "Available" : "Enabled";
+	int s;
 
 	seq_printf(m, "  %s Slice Mask: %04x\n", type,
 		   sseu->slice_mask);
@@ -4436,10 +4440,11 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
 		   hweight8(sseu->slice_mask));
 	seq_printf(m, "  %s Subslice Total: %u\n", type,
 		   sseu_subslice_total(sseu));
-	seq_printf(m, "  %s Subslice Mask: %04x\n", type,
-		   sseu->subslice_mask);
-	seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
-		   hweight8(sseu->subslice_mask));
+	for (s = 0; s < fls(sseu->slice_mask); s++) {
+		seq_printf(m, "  %s Slice%i %u subslices, mask=%04x\n", type,
+			   s, hweight8(sseu->subslice_mask[s]),
+			   sseu->subslice_mask[s]);
+	}
 	seq_printf(m, "  %s EU Total: %u\n", type,
 		   sseu->eu_total);
 	seq_printf(m, "  %s EU Per Subslice: %u\n", type,
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a9931b8ec0b3..47c9f5a7e6c4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -428,7 +428,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 			return -ENODEV;
 		break;
 	case I915_PARAM_SUBSLICE_MASK:
-		value = INTEL_INFO(dev_priv)->sseu.subslice_mask;
+		value = INTEL_INFO(dev_priv)->sseu.subslice_mask[0];
 		if (!value)
 			return -ENODEV;
 		break;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 298f8996cc54..2437ea157165 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -81,12 +81,16 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
 
 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
 {
+	int s;
+
 	drm_printf(p, "slice mask: %04x\n", sseu->slice_mask);
 	drm_printf(p, "slice total: %u\n", hweight8(sseu->slice_mask));
 	drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
-	drm_printf(p, "subslice mask %04x\n", sseu->subslice_mask);
-	drm_printf(p, "subslice per slice: %u\n",
-		   hweight8(sseu->subslice_mask));
+	for (s = 0; s < ARRAY_SIZE(sseu->subslice_mask); s++) {
+		drm_printf(p, "slice%d %u subslices mask=%04x\n",
+			   s, hweight8(sseu->subslice_mask[s]),
+			   sseu->subslice_mask[s]);
+	}
 	drm_printf(p, "EU total: %u\n", sseu->eu_total);
 	drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
 	drm_printf(p, "has slice power gating: %s\n",
@@ -120,22 +124,87 @@ void intel_device_info_dump(const struct intel_device_info *info,
 	intel_device_info_dump_flags(info, p);
 }
 
+static u16 compute_eu_total(const struct sseu_dev_info *sseu)
+{
+	u16 i, total = 0;
+
+	for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
+		total += hweight8(sseu->eu_mask[i]);
+
+	return total;
+}
+
+static u16 compute_subslice_total(const struct sseu_dev_info *sseu)
+{
+	u16 i, total = 0;
+
+	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
+		total += hweight8(sseu->subslice_mask[i]);
+
+	return total;
+}
+
 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
 	const u32 fuse2 = I915_READ(GEN8_FUSE2);
+	int s, ss;
+	const int eu_mask = 0xff;
+	u32 subslice_mask, eu_en;
 
 	sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
 			    GEN10_F2_S_ENA_SHIFT;
-	sseu->subslice_mask = (1 << 4) - 1;
-	sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
-				 GEN10_F2_SS_DIS_SHIFT);
+	sseu->max_slices = 6;
+	sseu->max_subslices = 4;
+	sseu->max_eus_per_subslice = 8;
 
-	sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
-	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
-	sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
-	sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
-				     GEN10_EU_DIS_SS_MASK));
+	subslice_mask = (1 << 4) - 1;
+	subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+			   GEN10_F2_SS_DIS_SHIFT);
+
+	/*
+	 * Slice0 can have up to 3 subslices, but there are only 2 in
+	 * slice1/2.
+	 */
+	sseu->subslice_mask[0] = subslice_mask;
+	for (s = 1; s < sseu->max_slices; s++)
+		sseu->subslice_mask[s] = subslice_mask & 0x3;
+
+	/* Slice0 */
+	eu_en = ~I915_READ(GEN8_EU_DISABLE0);
+	for (ss = 0; ss < sseu->max_subslices; ss++)
+		sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
+	/* Slice1 */
+	sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
+	eu_en = ~I915_READ(GEN8_EU_DISABLE1);
+	sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
+	/* Slice2 */
+	sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
+	sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
+	/* Slice3 */
+	sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
+	eu_en = ~I915_READ(GEN8_EU_DISABLE2);
+	sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
+	/* Slice4 */
+	sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
+	sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
+	/* Slice5 */
+	sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
+	eu_en = ~I915_READ(GEN10_EU_DISABLE3);
+	sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
+
+	/* Do a second pass where we mark the subslices disabled if all their
+	 * eus are off.
+	 */
+	for (s = 0; s < sseu->max_slices; s++) {
+		for (ss = 0; ss < sseu->max_subslices; ss++) {
+			if (sseu_get_eus(sseu, s, ss) == 0)
+				sseu->subslice_mask[s] &= ~BIT(ss);
+		}
+	}
+
+	sseu->subslice_total = compute_subslice_total(sseu);
+	sseu->eu_total = compute_eu_total(sseu);
 
 	/*
 	 * CNL is expected to always have a uniform distribution
@@ -156,26 +225,40 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
-	u32 fuse, eu_dis;
+	u32 fuse;
 
 	fuse = I915_READ(CHV_FUSE_GT);
 
 	sseu->slice_mask = BIT(0);
+	sseu->max_slices = 1;
+	sseu->max_subslices = 2;
+	sseu->max_eus_per_subslice = 8;
 
 	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
-		sseu->subslice_mask |= BIT(0);
-		eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
-				 CHV_FGT_EU_DIS_SS0_R1_MASK);
-		sseu->eu_total += 8 - hweight32(eu_dis);
+		u8 disabled_mask =
+			((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >>
+			 CHV_FGT_EU_DIS_SS0_R0_SHIFT) |
+			(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
+			  CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
+
+		sseu->subslice_mask[0] |= BIT(0);
+		sseu_set_eus(sseu, 0, 0, ~disabled_mask);
 	}
 
 	if (!(fuse & CHV_FGT_DISABLE_SS1)) {
-		sseu->subslice_mask |= BIT(1);
-		eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
-				 CHV_FGT_EU_DIS_SS1_R1_MASK);
-		sseu->eu_total += 8 - hweight32(eu_dis);
+		u8 disabled_mask =
+			((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >>
+			 CHV_FGT_EU_DIS_SS1_R0_SHIFT) |
+			(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
+			  CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
+
+		sseu->subslice_mask[0] |= BIT(1);
+		sseu_set_eus(sseu, 0, 1, ~disabled_mask);
 	}
 
+	sseu->subslice_total = compute_subslice_total(sseu);
+	sseu->eu_total = compute_eu_total(sseu);
+
 	/*
 	 * CHV expected to always have a uniform distribution of EU
 	 * across subslices.
@@ -197,41 +280,52 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_device_info *info = mkwrite_device_info(dev_priv);
 	struct sseu_dev_info *sseu = &info->sseu;
-	int s_max = 3, ss_max = 4, eu_max = 8;
 	int s, ss;
-	u32 fuse2, eu_disable;
-	u8 eu_mask = 0xff;
+	u32 fuse2, eu_disable, subslice_mask;
+	const u8 eu_mask = 0xff;
 
 	fuse2 = I915_READ(GEN8_FUSE2);
 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 
+	/* BXT has a single slice and at most 3 subslices. */
+	sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
+	sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
+	sseu->max_eus_per_subslice = 8;
+
 	/*
 	 * The subslice disable field is global, i.e. it applies
 	 * to each of the enabled slices.
 	*/
-	sseu->subslice_mask = (1 << ss_max) - 1;
-	sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
-				 GEN9_F2_SS_DIS_SHIFT);
+	subslice_mask = (1 << sseu->max_subslices) - 1;
+	subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
+			   GEN9_F2_SS_DIS_SHIFT);
 
 	/*
 	 * Iterate through enabled slices and subslices to
 	 * count the total enabled EU.
 	*/
-	for (s = 0; s < s_max; s++) {
+	for (s = 0; s < sseu->max_slices; s++) {
 		if (!(sseu->slice_mask & BIT(s)))
 			/* skip disabled slice */
 			continue;
 
+		sseu->subslice_mask[s] = subslice_mask;
+
 		eu_disable = I915_READ(GEN9_EU_DISABLE(s));
-		for (ss = 0; ss < ss_max; ss++) {
+		for (ss = 0; ss < sseu->max_subslices; ss++) {
 			int eu_per_ss;
+			u8 eu_disabled_mask;
 
-			if (!(sseu->subslice_mask & BIT(ss)))
+			if (!(sseu->subslice_mask[s] & BIT(ss)))
 				/* skip disabled subslice */
 				continue;
 
-			eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
-						      eu_mask);
+			eu_disabled_mask = (eu_disable >> (ss*8)) & eu_mask;
+
+			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+
+			eu_per_ss = sseu->max_eus_per_subslice -
+				hweight8(eu_disabled_mask);
 
 			/*
 			 * Record which subslice(s) has(have) 7 EUs. we
@@ -240,11 +334,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 			 */
 			if (eu_per_ss == 7)
 				sseu->subslice_7eu[s] |= BIT(ss);
-
-			sseu->eu_total += eu_per_ss;
 		}
 	}
 
+	sseu->subslice_total = compute_subslice_total(sseu);
+	sseu->eu_total = compute_eu_total(sseu);
+
 	/*
 	 * SKL is expected to always have a uniform distribution
 	 * of EU across subslices with the exception that any one
@@ -270,8 +365,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
 
 	if (IS_GEN9_LP(dev_priv)) {
-#define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask & BIT(ss)))
-		info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
+#define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask[0] & BIT(ss)))
+		info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3;
 
 		sseu->min_eu_in_pool = 0;
 		if (info->has_pooled_eu) {
@@ -289,19 +384,22 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
-	const int s_max = 3, ss_max = 3, eu_max = 8;
 	int s, ss;
-	u32 fuse2, eu_disable[3]; /* s_max */
+	u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */
 
 	fuse2 = I915_READ(GEN8_FUSE2);
 	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
+	sseu->max_slices = 3;
+	sseu->max_subslices = 3;
+	sseu->max_eus_per_subslice = 8;
+
 	/*
 	 * The subslice disable field is global, i.e. it applies
 	 * to each of the enabled slices.
 	 */
-	sseu->subslice_mask = GENMASK(ss_max - 1, 0);
-	sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
-				 GEN8_F2_SS_DIS_SHIFT);
+	subslice_mask = GENMASK(sseu->max_subslices - 1, 0);
+	subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
+			   GEN8_F2_SS_DIS_SHIFT);
 
 	eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 	eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
@@ -315,30 +413,39 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
 	 * Iterate through enabled slices and subslices to
 	 * count the total enabled EU.
 	 */
-	for (s = 0; s < s_max; s++) {
+	for (s = 0; s < sseu->max_slices; s++) {
 		if (!(sseu->slice_mask & BIT(s)))
 			/* skip disabled slice */
 			continue;
 
-		for (ss = 0; ss < ss_max; ss++) {
+		sseu->subslice_mask[s] = subslice_mask;
+
+		for (ss = 0; ss < sseu->max_subslices; ss++) {
+			u8 eu_disabled_mask;
 			u32 n_disabled;
 
-			if (!(sseu->subslice_mask & BIT(ss)))
+			if (!(sseu->subslice_mask[ss] & BIT(ss)))
 				/* skip disabled subslice */
 				continue;
 
-			n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
+			eu_disabled_mask =
+				eu_disable[s] >> (ss * sseu->max_eus_per_subslice);
+
+			sseu_set_eus(sseu, s, ss, ~eu_disabled_mask);
+
+			n_disabled = hweight8(eu_disabled_mask);
 
 			/*
 			 * Record which subslices have 7 EUs.
 			 */
-			if (eu_max - n_disabled == 7)
+			if (sseu->max_eus_per_subslice - n_disabled == 7)
 				sseu->subslice_7eu[s] |= 1 << ss;
-
-			sseu->eu_total += eu_max - n_disabled;
 		}
 	}
 
+	sseu->subslice_total = compute_subslice_total(sseu);
+	sseu->eu_total = compute_eu_total(sseu);
+
 	/*
 	 * BDW is expected to always have a uniform distribution of EU across
 	 * subslices with the exception that any one EU in any one subslice may
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 71fdfb0451ef..2a09e560fc93 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -112,10 +112,14 @@ enum intel_platform {
 	func(supports_tv); \
 	func(has_ipc);
 
+#define GEN_MAX_SLICES		(6) /* CNL upper bound */
+#define GEN_MAX_SUBSLICES	(7)
+
 struct sseu_dev_info {
 	u8 slice_mask;
-	u8 subslice_mask;
-	u8 eu_total;
+	u8 subslice_mask[GEN_MAX_SUBSLICES];
+	u16 subslice_total;
+	u16 eu_total;
 	u8 eu_per_subslice;
 	u8 min_eu_in_pool;
 	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
@@ -123,6 +127,17 @@ struct sseu_dev_info {
 	u8 has_slice_pg:1;
 	u8 has_subslice_pg:1;
 	u8 has_eu_pg:1;
+
+	/* Topology fields */
+	u8 max_slices;
+	u8 max_subslices;
+	u8 max_eus_per_subslice;
+
+	/* We don't have more than 8 eus per subslice at the moment and as we
+	 * store eus enabled using bits, no need to multiply by eus per
+	 * subslice.
+	 */
+	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
 };
 
 struct intel_device_info {
@@ -173,7 +188,33 @@ struct intel_driver_caps {
 
 static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
 {
-	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
+	return sseu->subslice_total;
+}
+
+static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
+			      int slice, int subslice)
+{
+	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
+					   BITS_PER_BYTE);
+	int slice_stride = sseu->max_subslices * subslice_stride;
+
+	return slice * slice_stride + subslice * subslice_stride;
+}
+
+/*
+ * The following functions prototypes should be updated with a larger type
+ * than u8 if we ever have more than 8 EUs per subslice.
+ */
+static inline u8 sseu_get_eus(const struct sseu_dev_info *sseu,
+			      int slice, int subslice)
+{
+	return sseu->eu_mask[sseu_eu_idx(sseu, slice, subslice)];
+}
+
+static inline void sseu_set_eus(struct sseu_dev_info *sseu,
+				int slice, int subslice, u8 eu_mask)
+{
+	sseu->eu_mask[sseu_eu_idx(sseu, slice, subslice)] = eu_mask;
 }
 
 const char *intel_platform_name(enum intel_platform platform);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2c8380a0121..0f829be830f3 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2129,7 +2129,7 @@ make_rpcs(struct drm_i915_private *dev_priv)
 
 	if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
 		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
-		rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
+		rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) <<
 			GEN8_RPCS_SS_CNT_SHIFT;
 		rpcs |= GEN8_RPCS_ENABLE;
 	}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 51523ad049de..bcb928e65e86 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -90,7 +90,7 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
 
 #define instdone_subslice_mask(dev_priv__) \
 	(INTEL_GEN(dev_priv__) == 7 ? \
-	 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
+	 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0])
 
 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
 	for ((slice__) = 0, (subslice__) = 0; \
-- 
2.16.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v13 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
  2018-02-15 12:01 ` [PATCH v13 1/6] drm/i915: store all subslice masks Lionel Landwerlin
@ 2018-02-15 12:01 ` Lionel Landwerlin
  2018-02-15 12:01 ` [PATCH v13 3/6] drm/i915/debugfs: add rcs topology entry Lionel Landwerlin
                   ` (8 subsequent siblings)
  10 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2018-02-15 12:01 UTC (permalink / raw)
  To: intel-gfx; +Cc: joonas.lahtinen

Now that we have that information in topology fields, let's just reuse it.

v2: Style tweaks (Tvrtko)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 27 +++++++++++----------------
 1 file changed, 11 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a5090e840c09..6dfe73899e4e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4288,11 +4288,11 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
 				     struct sseu_dev_info *sseu)
 {
 	const struct intel_device_info *info = INTEL_INFO(dev_priv);
-	int s_max = 6, ss_max = 4;
 	int s, ss;
-	u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+	u32 s_reg[info->sseu.max_slices];
+	u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
 
-	for (s = 0; s < s_max; s++) {
+	for (s = 0; s < info->sseu.max_slices; s++) {
 		/*
 		 * FIXME: Valid SS Mask respects the spec and read
 		 * only valid bits for those registers, excluding reserverd
@@ -4314,7 +4314,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
 		     GEN9_PGCTL_SSB_EU210_ACK |
 		     GEN9_PGCTL_SSB_EU311_ACK;
 
-	for (s = 0; s < s_max; s++) {
+	for (s = 0; s < info->sseu.max_slices; s++) {
 		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
 			/* skip disabled slice */
 			continue;
@@ -4322,7 +4322,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
 		sseu->slice_mask |= BIT(s);
 		sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
 
-		for (ss = 0; ss < ss_max; ss++) {
+		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
 			unsigned int eu_cnt;
 
 			if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
@@ -4342,17 +4342,12 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 				    struct sseu_dev_info *sseu)
 {
-	int s_max = 3, ss_max = 4;
+	const struct intel_device_info *info = INTEL_INFO(dev_priv);
 	int s, ss;
-	u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
-
-	/* BXT has a single slice and at most 3 subslices. */
-	if (IS_GEN9_LP(dev_priv)) {
-		s_max = 1;
-		ss_max = 3;
-	}
+	u32 s_reg[info->sseu.max_slices];
+	u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];
 
-	for (s = 0; s < s_max; s++) {
+	for (s = 0; s < info->sseu.max_slices; s++) {
 		s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
 		eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
 		eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
@@ -4367,7 +4362,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 		     GEN9_PGCTL_SSB_EU210_ACK |
 		     GEN9_PGCTL_SSB_EU311_ACK;
 
-	for (s = 0; s < s_max; s++) {
+	for (s = 0; s < info->sseu.max_slices; s++) {
 		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
 			/* skip disabled slice */
 			continue;
@@ -4378,7 +4373,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 			sseu->subslice_mask[s] =
 				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];
 
-		for (ss = 0; ss < ss_max; ss++) {
+		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
 			unsigned int eu_cnt;
 
 			if (IS_GEN9_LP(dev_priv)) {
-- 
2.16.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v13 3/6] drm/i915/debugfs: add rcs topology entry
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
  2018-02-15 12:01 ` [PATCH v13 1/6] drm/i915: store all subslice masks Lionel Landwerlin
  2018-02-15 12:01 ` [PATCH v13 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu Lionel Landwerlin
@ 2018-02-15 12:01 ` Lionel Landwerlin
  2018-02-15 12:02 ` [PATCH v13 4/6] drm/i915: add rcs topology to error state Lionel Landwerlin
                   ` (7 subsequent siblings)
  10 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2018-02-15 12:01 UTC (permalink / raw)
  To: intel-gfx; +Cc: joonas.lahtinen

While the end goal is to make this information available to userspace
through a new ioctl, there is no reason we can't display it in a human
readable fashion through debugfs.

slice0: 3 subslice(s) (0x7):
	subslice0: 8 EUs (0xff)
	subslice1: 8 EUs (0xff)
	subslice2: 8 EUs (0xff)
	subslice3: 0 EUs (0x0)
slice1: 3 subslice(s) (0x7):
	subslice0: 8 EUs (0xff)
	subslice1: 8 EUs (0xff)
	subslice2: 8 EUs (0xff)
	subslice3: 0 EUs (0x0)
slice2: 3 subslice(s) (0x7):
	subslice0: 8 EUs (0xff)
	subslice1: 8 EUs (0xff)
	subslice2: 8 EUs (0xff)
	subslice3: 0 EUs (0x0)

v2: Reformat debugfs printing (Tvrtko)
    Use the new EU mask helper (Tvrtko)

v3: Move printing code to intel_device_info.c to be shared with error
    state (Michal)

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c      | 11 +++++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  2 ++
 3 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6dfe73899e4e..6ce05fa1ac95 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3150,6 +3150,16 @@ static int i915_engine_info(struct seq_file *m, void *unused)
 	return 0;
 }
 
+static int i915_rcs_topology(struct seq_file *m, void *unused)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct drm_printer p = drm_seq_file_printer(m);
+
+	intel_device_info_dump_topology(&INTEL_INFO(dev_priv)->sseu, &p);
+
+	return 0;
+}
+
 static int i915_shrinker_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *i915 = node_to_i915(m->private);
@@ -4680,6 +4690,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_dmc_info", i915_dmc_info, 0},
 	{"i915_display_info", i915_display_info, 0},
 	{"i915_engine_info", i915_engine_info, 0},
+	{"i915_rcs_topology", i915_rcs_topology, 0},
 	{"i915_shrinker_info", i915_shrinker_info, 0},
 	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},
 	{"i915_dp_mst_info", i915_dp_mst_info, 0},
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 2437ea157165..f33b37738473 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -124,6 +124,31 @@ void intel_device_info_dump(const struct intel_device_info *info,
 	intel_device_info_dump_flags(info, p);
 }
 
+void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
+				     struct drm_printer *p)
+{
+	int s, ss;
+
+	if (sseu->max_slices == 0) {
+		drm_printf(p, "Unavailable\n");
+		return;
+	}
+
+	for (s = 0; s < sseu->max_slices; s++) {
+		drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+			   s, hweight8(sseu->subslice_mask[s]),
+			   sseu->subslice_mask[s]);
+
+		for (ss = 0; ss < sseu->max_subslices; ss++) {
+			u8 enabled_eus = sseu_get_eus(sseu, s, ss);
+
+			drm_printf(p, "\tsubslice%d: %u EUs (0x%hhx)\n",
+				   ss, hweight8(enabled_eus), enabled_eus);
+		}
+	}
+}
+
+
 static u16 compute_eu_total(const struct sseu_dev_info *sseu)
 {
 	u16 i, total = 0;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 2a09e560fc93..6eae9ee540b0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -226,6 +226,8 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
 				  struct drm_printer *p);
 void intel_device_info_dump_runtime(const struct intel_device_info *info,
 				    struct drm_printer *p);
+void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
+				     struct drm_printer *p);
 
 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 			     struct drm_printer *p);
-- 
2.16.1

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^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v13 4/6] drm/i915: add rcs topology to error state
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
                   ` (2 preceding siblings ...)
  2018-02-15 12:01 ` [PATCH v13 3/6] drm/i915/debugfs: add rcs topology entry Lionel Landwerlin
@ 2018-02-15 12:02 ` Lionel Landwerlin
  2018-02-15 12:02 ` [PATCH v13 5/6] drm/i915: add query uAPI Lionel Landwerlin
                   ` (6 subsequent siblings)
  10 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2018-02-15 12:02 UTC (permalink / raw)
  To: intel-gfx; +Cc: joonas.lahtinen

This might be useful information for developers looking at an error
state.

v2: Place topology towards the end of the error state (Chris)

v3: Reuse common printing code (Michal)

v4: Make this a one-liner (Chris)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 161d9103a65e..ee709e3f858a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -586,6 +586,7 @@ static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 
 	intel_device_info_dump_flags(info, &p);
 	intel_driver_caps_print(caps, &p);
+	intel_device_info_dump_topology(&info->sseu, &p);
 }
 
 static void err_print_params(struct drm_i915_error_state_buf *m,
-- 
2.16.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v13 5/6] drm/i915: add query uAPI
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
                   ` (3 preceding siblings ...)
  2018-02-15 12:02 ` [PATCH v13 4/6] drm/i915: add rcs topology to error state Lionel Landwerlin
@ 2018-02-15 12:02 ` Lionel Landwerlin
  2018-02-20 10:58   ` Tvrtko Ursulin
  2018-02-15 12:02 ` [PATCH v13 6/6] drm/i915: expose rcs topology through " Lionel Landwerlin
                   ` (5 subsequent siblings)
  10 siblings, 1 reply; 17+ messages in thread
From: Lionel Landwerlin @ 2018-02-15 12:02 UTC (permalink / raw)
  To: intel-gfx; +Cc: joonas.lahtinen

There are a number of information that are readable from hardware
registers and that we would like to make accessible to userspace. One
particular example is the topology of the execution units (how are
execution units grouped in subslices and slices and also which ones
have been fused off for die recovery).

At the moment the GET_PARAM ioctl covers some basic needs, but
generally is only able to return a single value for each defined
parameter. This is a bit problematic with topology descriptions which
are array/maps of available units.

This change introduces a new ioctl that can deal with requests to fill
structures of potentially variable lengths. The user is expected fill
a query with length fields set at 0 on the first call, the kernel then
sets the length fields to the their expected values. A second call to
the kernel with length fields at their expected values will trigger a
copy of the data to the pointed memory locations.

The scope of this uAPI is only to provide information to userspace,
not to allow configuration of the device.

v2: Simplify dispatcher code iteration (Tvrtko)
    Tweak uapi drm_i915_query_item structure (Tvrtko)

v3: Rename pad fields into flags (Chris)
    Return error on flags field != 0 (Chris)
    Only copy length back to userspace in drm_i915_query_item (Chris)

v4: Use array of functions instead of switch (Chris)

v5: More comments in uapi (Tvrtko)
    Return query item errors in length field (All)

v6: Tweak uapi comments style to match the coding style (Lionel)

v7: Add i915_query.h (Joonas)

v8: (Lionel) Change the behavior of the item iterator to report
    invalid queries into the query item rather than stopping the
    iteration. This enables userspace applications to query newer
    items on older kernels and only have failure on the items that are
    not supported.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |  1 +
 drivers/gpu/drm/i915/i915_drv.c   |  2 ++
 drivers/gpu/drm/i915/i915_query.c | 67 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_query.h | 33 +++++++++++++++++++
 include/uapi/drm/i915_drm.h       | 41 ++++++++++++++++++++++++
 5 files changed, 144 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/i915_query.c
 create mode 100644 drivers/gpu/drm/i915/i915_query.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f55cc028b2eb..e8e25bb3af81 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -70,6 +70,7 @@ i915-y += i915_cmd_parser.o \
 	  i915_gem_timeline.o \
 	  i915_gem_userptr.o \
 	  i915_gemfs.o \
+	  i915_query.o \
 	  i915_trace_points.o \
 	  i915_vma.o \
 	  intel_breadcrumbs.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 47c9f5a7e6c4..18350620cd06 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -49,6 +49,7 @@
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include "i915_pmu.h"
+#include "i915_query.h"
 #include "i915_vgpu.h"
 #include "intel_drv.h"
 #include "intel_uc.h"
@@ -2836,6 +2837,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
 	DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
 	DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
 };
 
 static struct drm_driver driver = {
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
new file mode 100644
index 000000000000..92ce3e24588e
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+#include <uapi/drm/i915_drm.h>
+
+static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
+					struct drm_i915_query_item *query_item) = {
+};
+
+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_query *args = data;
+	struct drm_i915_query_item __user *user_item_ptr =
+		u64_to_user_ptr(args->items_ptr);
+	u32 i;
+
+	if (args->flags != 0)
+		return -EINVAL;
+
+	for (i = 0; i < args->num_items; i++, user_item_ptr++) {
+		struct drm_i915_query_item item;
+		u64 func_idx;
+		int ret;
+
+		if (copy_from_user(&item, user_item_ptr, sizeof(item)))
+			return -EFAULT;
+
+		if (item.query_id == 0)
+			return -EINVAL;
+
+		func_idx = item.query_id - 1;
+
+		if (func_idx < ARRAY_SIZE(i915_query_funcs))
+			ret = i915_query_funcs[func_idx](dev_priv, &item);
+		else
+			ret = -EINVAL;
+
+		/* Only write the length back to userspace if they differ. */
+		if (ret != item.length && put_user(ret, &user_item_ptr->length))
+			return -EFAULT;
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/i915_query.h b/drivers/gpu/drm/i915/i915_query.h
new file mode 100644
index 000000000000..4550e8f21459
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_query.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _I915_QUERY_H_
+#define _I915_QUERY_H_
+
+struct drm_device;
+struct drm_file;
+
+int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+
+#endif
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 29fa48e4755d..7fd980176f25 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -318,6 +318,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_OPEN		0x36
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
+#define DRM_I915_QUERY			0x39
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -375,6 +376,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_OPEN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
+#define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -1615,6 +1617,45 @@ struct drm_i915_perf_oa_config {
 	__u64 flex_regs_ptr;
 };
 
+
+struct drm_i915_query_item {
+	__u64 query_id;
+
+	/*
+	 * When set to zero by userspace, this is filled with the size of the
+	 * data to be written at the data_ptr pointer. The kernel set this
+	 * value to a negative value to signal an error on a particular query
+	 * item.
+	 */
+	__s32 length;
+
+	/*
+	 * Unused for now.
+	 */
+	__u32 flags;
+
+	/*
+	 * Data will be written at the location pointed by data_ptr when the
+	 * value of length matches the length of the data to be written by the
+	 * kernel.
+	 */
+	__u64 data_ptr;
+};
+
+struct drm_i915_query {
+	__u32 num_items;
+
+	/*
+	 * Unused for now.
+	 */
+	__u32 flags;
+
+	/*
+	 * This point to an array of num_items drm_i915_query_item structures.
+	 */
+	__u64 items_ptr;
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.16.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* [PATCH v13 6/6] drm/i915: expose rcs topology through query uAPI
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
                   ` (4 preceding siblings ...)
  2018-02-15 12:02 ` [PATCH v13 5/6] drm/i915: add query uAPI Lionel Landwerlin
@ 2018-02-15 12:02 ` Lionel Landwerlin
  2018-02-16 12:28   ` Joonas Lahtinen
  2018-02-20 11:05   ` Tvrtko Ursulin
  2018-02-15 12:11 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: expose RCS topology to userspace Patchwork
                   ` (4 subsequent siblings)
  10 siblings, 2 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2018-02-15 12:02 UTC (permalink / raw)
  To: intel-gfx; +Cc: joonas.lahtinen

With the introduction of asymmetric slices in CNL, we cannot rely on
the previous SUBSLICE_MASK getparam to tell userspace what subslices
are available. Here we introduce a more detailed way of querying the
Gen's GPU topology that doesn't aggregate numbers.

This is essential for monitoring parts of the GPU with the OA unit,
because counters need to be normalized to the number of
EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
not gives us sufficient information.

As a bonus we can draw representations of the GPU :

        https://imgur.com/a/vuqpa

v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
    Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
    Add uapi macros to read data from *_info structs (Tvrtko)

v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)

v4: factorize query item writting (Tvrtko)
    tweak uapi struct/define names (Tvrtko)

v5: Replace ALIGN() macro (Chris)

v6: Updated uapi comments (Tvrtko)
    Moved flags != 0 checks into vfuncs (Tvrtko)

v7: Use access_ok() before copying anything, to avoid overflows (Chris)
    Switch BUG_ON() to GEM_WARN_ON() (Tvrtko)

v8: Tweak uapi comments style to match the coding style (Lionel)

v9: Fix error in comment about computation of enabled subslice (Tvrtko)

v10: Fix/update comments in uAPI (Sagar)

v11: Drop drm_i915_query_(slice|subslice|eu)_info in favor of a single
     drm_i915_query_topology_info (Joonas)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/i915_query.c | 71 +++++++++++++++++++++++++++++++++++++++
 include/uapi/drm/i915_drm.h       | 40 ++++++++++++++++++++++
 2 files changed, 111 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 92ce3e24588e..828f1ba19248 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -25,8 +25,79 @@
 #include "i915_drv.h"
 #include <uapi/drm/i915_drm.h>
 
+static int query_topology_info(struct drm_i915_private *dev_priv,
+			       struct drm_i915_query_item *query_item)
+{
+	const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
+	struct drm_i915_query_topology_info topo_info;
+	u32 slice_length, subslice_length, eu_length, total_length;
+
+	if (query_item->flags != 0)
+		return -EINVAL;
+
+	if (sseu->max_slices == 0)
+		return -ENODEV;
+
+	/*
+	 * If we ever change the internal slice mask data type, we'll need to
+	 * update this function.
+	 */
+	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
+
+	slice_length = sizeof(sseu->slice_mask);
+	subslice_length = sseu->max_slices *
+		DIV_ROUND_UP(sseu->max_subslices,
+			     sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE);
+	eu_length = sseu->max_slices * sseu->max_subslices *
+		DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
+
+	total_length = sizeof(topo_info) + slice_length + subslice_length + eu_length;
+
+	if (query_item->length == 0)
+		return total_length;
+
+	if (query_item->length < total_length)
+		return -EINVAL;
+
+	if (!access_ok(VERIFY_WRITE, u64_to_user_ptr(query_item->data_ptr),
+		       total_length))
+		return -EFAULT;
+
+	memset(&topo_info, 0, sizeof(topo_info));
+	topo_info.max_slices = sseu->max_slices;
+	topo_info.max_subslices = sseu->max_subslices;
+	topo_info.max_eus_per_subslice = sseu->max_eus_per_subslice;
+
+	topo_info.subslice_offset = slice_length;
+	topo_info.eu_offset = slice_length + subslice_length;
+
+	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
+			   &topo_info, sizeof(topo_info)))
+		return -EFAULT;
+
+	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+					   sizeof(topo_info)),
+			   &sseu->slice_mask, slice_length))
+		return -EFAULT;
+
+	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+					   sizeof(topo_info) +
+					   slice_length),
+			   sseu->subslice_mask, subslice_length))
+		return -EFAULT;
+
+	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr +
+					   sizeof(topo_info) +
+					   slice_length + subslice_length),
+			   sseu->eu_mask, eu_length))
+		return -EFAULT;
+
+	return total_length;
+}
+
 static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
 					struct drm_i915_query_item *query_item) = {
+	query_topology_info,
 };
 
 int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 7fd980176f25..9d5c4caf5a6d 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1620,6 +1620,7 @@ struct drm_i915_perf_oa_config {
 
 struct drm_i915_query_item {
 	__u64 query_id;
+#define DRM_I915_QUERY_TOPOLOGY_INFO    0x01
 
 	/*
 	 * When set to zero by userspace, this is filled with the size of the
@@ -1656,6 +1657,45 @@ struct drm_i915_query {
 	__u64 items_ptr;
 };
 
+/*
+ * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
+ *
+ * data: contains the 3 pieces of information :
+ *
+ * - the slice mask with one bit per slice telling whether a slice is
+ *   available. The availability of slice X can be queried with the following
+ *   formula :
+ *
+ *           (data[X / 8] >> (X % 8)) & 1
+ *
+ * - the subslice mask for each slice with one bit per subslice telling
+ *   whether a subslice is available. The availability of subslice Y in slice
+ *   X can be queried with the following formula :
+ *
+ *           (data[subslice_offset +
+ *                 X * DIV_ROUND_UP(max_subslices, 8) +
+ *                 Y / 8] >> (Y % 8)) & 1
+ *
+ * - the EU mask for each subslice in each slice with one bit per EU telling
+ *   whether an EU is available. The availability of EU Z in subslice Y in
+ *   slice X can be queried with the following formula :
+ *
+ *           (data[eu_offset +
+ *                 X * max_subslices * DIV_ROUND_UP(max_eus_per_subslice, 8) +
+ *                 Y * DIV_ROUND_UP(max_eus_per_subslice, 8) +
+ *                 Z / 8] >> (Z % 8)) & 1
+ */
+struct drm_i915_query_topology_info {
+	__u16 max_slices;
+	__u16 max_subslices;
+	__u16 max_eus_per_subslice;
+
+	__u16 subslice_offset;
+	__u16 eu_offset;
+
+	__u8 data[];
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.16.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 17+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: expose RCS topology to userspace
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
                   ` (5 preceding siblings ...)
  2018-02-15 12:02 ` [PATCH v13 6/6] drm/i915: expose rcs topology through " Lionel Landwerlin
@ 2018-02-15 12:11 ` Patchwork
  2018-02-15 12:13 ` ✗ Fi.CI.SPARSE: " Patchwork
                   ` (3 subsequent siblings)
  10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-02-15 12:11 UTC (permalink / raw)
  To: Lionel Landwerlin; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/38356/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b98af10ebabc drm/i915: store all subslice masks
-:344: CHECK: spaces preferred around that '*' (ctx:VxV)
#344: FILE: drivers/gpu/drm/i915/intel_device_info.c:323:
+			eu_disabled_mask = (eu_disable >> (ss*8)) & eu_mask;
 			                                     ^

-:431: WARNING: line over 80 characters
#431: FILE: drivers/gpu/drm/i915/intel_device_info.c:432:
+				eu_disable[s] >> (ss * sseu->max_eus_per_subslice);

total: 0 errors, 1 warnings, 1 checks, 483 lines checked
64190a6df1db drm/i915/debugfs: reuse max slice/subslices already stored in sseu
0b54af63ab85 drm/i915/debugfs: add rcs topology entry
-:97: CHECK: Please don't use multiple blank lines
#97: FILE: drivers/gpu/drm/i915/intel_device_info.c:151:
+
+

total: 0 errors, 0 warnings, 1 checks, 62 lines checked
e23c14155944 drm/i915: add rcs topology to error state
63c93eac311d drm/i915: add query uAPI
-:79: WARNING: line over 80 characters
#79: FILE: drivers/gpu/drm/i915/i915_drv.c:2840:
+	DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),

-:79: CHECK: spaces preferred around that '|' (ctx:VxV)
#79: FILE: drivers/gpu/drm/i915/i915_drv.c:2840:
+	DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
 	                                                            ^

-:84: WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#84: 
new file mode 100644

-:117: WARNING: line over 80 characters
#117: FILE: drivers/gpu/drm/i915/i915_query.c:29:
+					struct drm_i915_query_item *query_item) = {

-:211: WARNING: line over 80 characters
#211: FILE: include/uapi/drm/i915_drm.h:379:
+#define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)

-:219: CHECK: Please don't use multiple blank lines
#219: FILE: include/uapi/drm/i915_drm.h:1620:
 
+

total: 0 errors, 4 warnings, 2 checks, 180 lines checked
23eb4ded07cd drm/i915: expose rcs topology through query uAPI
-:24: WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#24: 
v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)

-:26: WARNING: 'writting' may be misspelled - perhaps 'writing'?
#26: 
v4: factorize query item writting (Tvrtko)

-:82: WARNING: line over 80 characters
#82: FILE: drivers/gpu/drm/i915/i915_query.c:54:
+	total_length = sizeof(topo_info) + slice_length + subslice_length + eu_length;

total: 0 errors, 3 warnings, 0 checks, 131 lines checked

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: expose RCS topology to userspace
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
                   ` (6 preceding siblings ...)
  2018-02-15 12:11 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: expose RCS topology to userspace Patchwork
@ 2018-02-15 12:13 ` Patchwork
  2018-02-15 12:27 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-02-15 12:13 UTC (permalink / raw)
  To: Lionel Landwerlin; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/38356/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: store all subslice masks
Okay!

Commit: drm/i915/debugfs: reuse max slice/subslices already stored in sseu
-
+drivers/gpu/drm/i915/i915_debugfs.c:4292:29: warning: Variable length array is used.
+drivers/gpu/drm/i915/i915_debugfs.c:4293:22: warning: Variable length array is used.
+drivers/gpu/drm/i915/i915_debugfs.c:4347:29: warning: Variable length array is used.
+drivers/gpu/drm/i915/i915_debugfs.c:4348:22: warning: Variable length array is used.

Commit: drm/i915/debugfs: add rcs topology entry
Okay!

Commit: drm/i915: add rcs topology to error state
Okay!

Commit: drm/i915: add query uAPI
+drivers/gpu/drm/i915/i915_query.c:32:5: warning: symbol 'i915_query_ioctl' was not declared. Should it be static?

Commit: drm/i915: expose rcs topology through query uAPI
-O:drivers/gpu/drm/i915/i915_query.c:32:5: warning: symbol 'i915_query_ioctl' was not declared. Should it be static?
+drivers/gpu/drm/i915/i915_query.c:103:5: warning: symbol 'i915_query_ioctl' was not declared. Should it be static?


_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: expose RCS topology to userspace
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
                   ` (7 preceding siblings ...)
  2018-02-15 12:13 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-02-15 12:27 ` Patchwork
  2018-02-15 19:28 ` ✗ Fi.CI.IGT: failure " Patchwork
  2018-02-21 11:33 ` [PATCH v13 0/6] " Chris Wilson
  10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-02-15 12:27 UTC (permalink / raw)
  To: Lionel Landwerlin; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/38356/
State : success

== Summary ==

Series 38356v1 drm/i915: expose RCS topology to userspace
https://patchwork.freedesktop.org/api/1.0/series/38356/revisions/1/mbox/

Test kms_chamelium:
        Subgroup dp-edid-read:
                pass       -> FAIL       (fi-kbl-7500u) fdo#102505

fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:427s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:426s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:375s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:492s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:289s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:478s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:488s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:467s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:455s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:569s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:417s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:281s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:509s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:397s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:411s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:464s
fi-kbl-7500u     total:288  pass:262  dwarn:1   dfail:0   fail:1   skip:24  time:454s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:499s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:500s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:588s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:429s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:506s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:524s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:491s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:486s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:418s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:441s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:526s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:398s
Blacklisted hosts:
fi-glk-dsi       total:117  pass:104  dwarn:0   dfail:0   fail:0   skip:12 
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s

bd16af128e78b302b3034fa85626cd15dcf5f038 drm-tip: 2018y-02m-15d-00h-22m-40s UTC integration manifest
23eb4ded07cd drm/i915: expose rcs topology through query uAPI
63c93eac311d drm/i915: add query uAPI
e23c14155944 drm/i915: add rcs topology to error state
0b54af63ab85 drm/i915/debugfs: add rcs topology entry
64190a6df1db drm/i915/debugfs: reuse max slice/subslices already stored in sseu
b98af10ebabc drm/i915: store all subslice masks

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8048/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: expose RCS topology to userspace
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
                   ` (8 preceding siblings ...)
  2018-02-15 12:27 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-02-15 19:28 ` Patchwork
  2018-02-21 11:33 ` [PATCH v13 0/6] " Chris Wilson
  10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2018-02-15 19:28 UTC (permalink / raw)
  To: Lionel Landwerlin; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: expose RCS topology to userspace
URL   : https://patchwork.freedesktop.org/series/38356/
State : failure

== Summary ==

Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-pri-indfb-multidraw:
                pass       -> FAIL       (shard-snb) fdo#103167
        Subgroup fbc-rgb101010-draw-pwrite:
                pass       -> FAIL       (shard-apl)
Test pm_sseu:
        Subgroup full-enable:
                pass       -> FAIL       (shard-apl) fdo#104651
Test perf:
        Subgroup enable-disable:
                fail       -> PASS       (shard-apl) fdo#103715
        Subgroup oa-exponents:
                pass       -> FAIL       (shard-apl) fdo#102254
Test gem_eio:
        Subgroup in-flight-suspend:
                pass       -> FAIL       (shard-hsw) fdo#104676
        Subgroup in-flight:
                pass       -> DMESG-WARN (shard-snb) fdo#104058
Test kms_flip:
        Subgroup plain-flip-fb-recreate:
                pass       -> FAIL       (shard-hsw) fdo#100368
Test kms_cursor_crc:
        Subgroup cursor-256x256-suspend:
                pass       -> SKIP       (shard-snb) fdo#103375
        Subgroup cursor-128x128-suspend:
                pass       -> INCOMPLETE (shard-hsw) fdo#103540

fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#104651 https://bugs.freedesktop.org/show_bug.cgi?id=104651
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540

shard-apl        total:3342 pass:1726 dwarn:1   dfail:0   fail:22  skip:1592 time:13785s
shard-hsw        total:3388 pass:1741 dwarn:1   dfail:0   fail:12  skip:1632 time:13928s
shard-snb        total:3427 pass:1345 dwarn:2   dfail:0   fail:11  skip:2069 time:7510s
Blacklisted hosts:
shard-kbl        total:3427 pass:1884 dwarn:24  dfail:0   fail:22  skip:1497 time:10979s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8048/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v13 6/6] drm/i915: expose rcs topology through query uAPI
  2018-02-15 12:02 ` [PATCH v13 6/6] drm/i915: expose rcs topology through " Lionel Landwerlin
@ 2018-02-16 12:28   ` Joonas Lahtinen
  2018-02-16 12:35     ` Lionel Landwerlin
  2018-02-20 11:05   ` Tvrtko Ursulin
  1 sibling, 1 reply; 17+ messages in thread
From: Joonas Lahtinen @ 2018-02-16 12:28 UTC (permalink / raw)
  To: Lionel Landwerlin, intel-gfx

Quoting Lionel Landwerlin (2018-02-15 14:02:02)
> With the introduction of asymmetric slices in CNL, we cannot rely on
> the previous SUBSLICE_MASK getparam to tell userspace what subslices
> are available. Here we introduce a more detailed way of querying the
> Gen's GPU topology that doesn't aggregate numbers.
> 
> This is essential for monitoring parts of the GPU with the OA unit,
> because counters need to be normalized to the number of
> EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
> not gives us sufficient information.
> 
> As a bonus we can draw representations of the GPU :
> 
>         https://imgur.com/a/vuqpa
> 
> v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
>     Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
>     Add uapi macros to read data from *_info structs (Tvrtko)
> 
> v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)
> 
> v4: factorize query item writting (Tvrtko)
>     tweak uapi struct/define names (Tvrtko)
> 
> v5: Replace ALIGN() macro (Chris)
> 
> v6: Updated uapi comments (Tvrtko)
>     Moved flags != 0 checks into vfuncs (Tvrtko)
> 
> v7: Use access_ok() before copying anything, to avoid overflows (Chris)
>     Switch BUG_ON() to GEM_WARN_ON() (Tvrtko)
> 
> v8: Tweak uapi comments style to match the coding style (Lionel)
> 
> v9: Fix error in comment about computation of enabled subslice (Tvrtko)
> 
> v10: Fix/update comments in uAPI (Sagar)
> 
> v11: Drop drm_i915_query_(slice|subslice|eu)_info in favor of a single
>      drm_i915_query_topology_info (Joonas)
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

<SNIP>

> +++ b/include/uapi/drm/i915_drm.h
> @@ -1620,6 +1620,7 @@ struct drm_i915_perf_oa_config {
>  
>  struct drm_i915_query_item {
>         __u64 query_id;
> +#define DRM_I915_QUERY_TOPOLOGY_INFO    0x01

Just a number should be sufficient? Hex would indicate a mask.

> +/*
> + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
> + *
> + * data: contains the 3 pieces of information :
> + *
> + * - the slice mask with one bit per slice telling whether a slice is
> + *   available. The availability of slice X can be queried with the following
> + *   formula :
> + *
> + *           (data[X / 8] >> (X % 8)) & 1
> + *
> + * - the subslice mask for each slice with one bit per subslice telling
> + *   whether a subslice is available. The availability of subslice Y in slice
> + *   X can be queried with the following formula :
> + *
> + *           (data[subslice_offset +
> + *                 X * DIV_ROUND_UP(max_subslices, 8) +
> + *                 Y / 8] >> (Y % 8)) & 1
> + *
> + * - the EU mask for each subslice in each slice with one bit per EU telling
> + *   whether an EU is available. The availability of EU Z in subslice Y in
> + *   slice X can be queried with the following formula :
> + *
> + *           (data[eu_offset +
> + *                 X * max_subslices * DIV_ROUND_UP(max_eus_per_subslice, 8) +
> + *                 Y * DIV_ROUND_UP(max_eus_per_subslice, 8) +
> + *                 Z / 8] >> (Z % 8)) & 1

I'm still contemplating if providing *_stride to make this more straightofrward
would be a good or bad thing. The cases would become:

data[X / 8] & BIT(X % 8)

data[subslice_offset + X * subslice_stride + Y/8] & BIT(Y % 8)

data[eu_offset + (X * max_subslices + Y) * eu_stride + Z/8] & BIT(Z % 8)

I think I'm heavily leaning towards that, as it comes with the option
that we increase eu_stride two-fold to report more information per EU
(or subslice for that matter).

Thoughts?

Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v13 6/6] drm/i915: expose rcs topology through query uAPI
  2018-02-16 12:28   ` Joonas Lahtinen
@ 2018-02-16 12:35     ` Lionel Landwerlin
  0 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2018-02-16 12:35 UTC (permalink / raw)
  To: Joonas Lahtinen, intel-gfx

On 16/02/18 12:28, Joonas Lahtinen wrote:
> Quoting Lionel Landwerlin (2018-02-15 14:02:02)
>> With the introduction of asymmetric slices in CNL, we cannot rely on
>> the previous SUBSLICE_MASK getparam to tell userspace what subslices
>> are available. Here we introduce a more detailed way of querying the
>> Gen's GPU topology that doesn't aggregate numbers.
>>
>> This is essential for monitoring parts of the GPU with the OA unit,
>> because counters need to be normalized to the number of
>> EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
>> not gives us sufficient information.
>>
>> As a bonus we can draw representations of the GPU :
>>
>>          https://imgur.com/a/vuqpa
>>
>> v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
>>      Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
>>      Add uapi macros to read data from *_info structs (Tvrtko)
>>
>> v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)
>>
>> v4: factorize query item writting (Tvrtko)
>>      tweak uapi struct/define names (Tvrtko)
>>
>> v5: Replace ALIGN() macro (Chris)
>>
>> v6: Updated uapi comments (Tvrtko)
>>      Moved flags != 0 checks into vfuncs (Tvrtko)
>>
>> v7: Use access_ok() before copying anything, to avoid overflows (Chris)
>>      Switch BUG_ON() to GEM_WARN_ON() (Tvrtko)
>>
>> v8: Tweak uapi comments style to match the coding style (Lionel)
>>
>> v9: Fix error in comment about computation of enabled subslice (Tvrtko)
>>
>> v10: Fix/update comments in uAPI (Sagar)
>>
>> v11: Drop drm_i915_query_(slice|subslice|eu)_info in favor of a single
>>       drm_i915_query_topology_info (Joonas)
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> <SNIP>
>
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -1620,6 +1620,7 @@ struct drm_i915_perf_oa_config {
>>   
>>   struct drm_i915_query_item {
>>          __u64 query_id;
>> +#define DRM_I915_QUERY_TOPOLOGY_INFO    0x01
> Just a number should be sufficient? Hex would indicate a mask.
>
>> +/*
>> + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
>> + *
>> + * data: contains the 3 pieces of information :
>> + *
>> + * - the slice mask with one bit per slice telling whether a slice is
>> + *   available. The availability of slice X can be queried with the following
>> + *   formula :
>> + *
>> + *           (data[X / 8] >> (X % 8)) & 1
>> + *
>> + * - the subslice mask for each slice with one bit per subslice telling
>> + *   whether a subslice is available. The availability of subslice Y in slice
>> + *   X can be queried with the following formula :
>> + *
>> + *           (data[subslice_offset +
>> + *                 X * DIV_ROUND_UP(max_subslices, 8) +
>> + *                 Y / 8] >> (Y % 8)) & 1
>> + *
>> + * - the EU mask for each subslice in each slice with one bit per EU telling
>> + *   whether an EU is available. The availability of EU Z in subslice Y in
>> + *   slice X can be queried with the following formula :
>> + *
>> + *           (data[eu_offset +
>> + *                 X * max_subslices * DIV_ROUND_UP(max_eus_per_subslice, 8) +
>> + *                 Y * DIV_ROUND_UP(max_eus_per_subslice, 8) +
>> + *                 Z / 8] >> (Z % 8)) & 1
> I'm still contemplating if providing *_stride to make this more straightofrward
> would be a good or bad thing. The cases would become:
>
> data[X / 8] & BIT(X % 8)
>
> data[subslice_offset + X * subslice_stride + Y/8] & BIT(Y % 8)
>
> data[eu_offset + (X * max_subslices + Y) * eu_stride + Z/8] & BIT(Z % 8)
>
> I think I'm heavily leaning towards that, as it comes with the option
> that we increase eu_stride two-fold to report more information per EU
> (or subslice for that matter).

I'm not sure adding other types of information interleaved with 
availability mask is good thing. Sounds pretty annoying to parse/test.
I'd much rather adding new structs.

Regarding stride fields, I'm okay either way.

Thanks!

-
Lionel

>
> Thoughts?
>
> Regards, Joonas
>

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v13 5/6] drm/i915: add query uAPI
  2018-02-15 12:02 ` [PATCH v13 5/6] drm/i915: add query uAPI Lionel Landwerlin
@ 2018-02-20 10:58   ` Tvrtko Ursulin
  0 siblings, 0 replies; 17+ messages in thread
From: Tvrtko Ursulin @ 2018-02-20 10:58 UTC (permalink / raw)
  To: Lionel Landwerlin, intel-gfx; +Cc: joonas.lahtinen


On 15/02/2018 12:02, Lionel Landwerlin wrote:
> There are a number of information that are readable from hardware
> registers and that we would like to make accessible to userspace. One
> particular example is the topology of the execution units (how are
> execution units grouped in subslices and slices and also which ones
> have been fused off for die recovery).
> 
> At the moment the GET_PARAM ioctl covers some basic needs, but
> generally is only able to return a single value for each defined
> parameter. This is a bit problematic with topology descriptions which
> are array/maps of available units.
> 
> This change introduces a new ioctl that can deal with requests to fill
> structures of potentially variable lengths. The user is expected fill
> a query with length fields set at 0 on the first call, the kernel then
> sets the length fields to the their expected values. A second call to
> the kernel with length fields at their expected values will trigger a
> copy of the data to the pointed memory locations.
> 
> The scope of this uAPI is only to provide information to userspace,
> not to allow configuration of the device.
> 
> v2: Simplify dispatcher code iteration (Tvrtko)
>      Tweak uapi drm_i915_query_item structure (Tvrtko)
> 
> v3: Rename pad fields into flags (Chris)
>      Return error on flags field != 0 (Chris)
>      Only copy length back to userspace in drm_i915_query_item (Chris)
> 
> v4: Use array of functions instead of switch (Chris)
> 
> v5: More comments in uapi (Tvrtko)
>      Return query item errors in length field (All)
> 
> v6: Tweak uapi comments style to match the coding style (Lionel)
> 
> v7: Add i915_query.h (Joonas)
> 
> v8: (Lionel) Change the behavior of the item iterator to report
>      invalid queries into the query item rather than stopping the
>      iteration. This enables userspace applications to query newer
>      items on older kernels and only have failure on the items that are
>      not supported.
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile     |  1 +
>   drivers/gpu/drm/i915/i915_drv.c   |  2 ++
>   drivers/gpu/drm/i915/i915_query.c | 67 +++++++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/i915_query.h | 33 +++++++++++++++++++
>   include/uapi/drm/i915_drm.h       | 41 ++++++++++++++++++++++++
>   5 files changed, 144 insertions(+)
>   create mode 100644 drivers/gpu/drm/i915/i915_query.c
>   create mode 100644 drivers/gpu/drm/i915/i915_query.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index f55cc028b2eb..e8e25bb3af81 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -70,6 +70,7 @@ i915-y += i915_cmd_parser.o \
>   	  i915_gem_timeline.o \
>   	  i915_gem_userptr.o \
>   	  i915_gemfs.o \
> +	  i915_query.o \
>   	  i915_trace_points.o \
>   	  i915_vma.o \
>   	  intel_breadcrumbs.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 47c9f5a7e6c4..18350620cd06 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -49,6 +49,7 @@
>   #include "i915_drv.h"
>   #include "i915_trace.h"
>   #include "i915_pmu.h"
> +#include "i915_query.h"
>   #include "i915_vgpu.h"
>   #include "intel_drv.h"
>   #include "intel_uc.h"
> @@ -2836,6 +2837,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
>   	DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
>   	DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
>   	DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
> +	DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
>   };
>   
>   static struct drm_driver driver = {
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> new file mode 100644
> index 000000000000..92ce3e24588e
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -0,0 +1,67 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "i915_drv.h"
> +#include <uapi/drm/i915_drm.h>
> +
> +static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
> +					struct drm_i915_query_item *query_item) = {
> +};
> +
> +int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_query *args = data;
> +	struct drm_i915_query_item __user *user_item_ptr =
> +		u64_to_user_ptr(args->items_ptr);
> +	u32 i;
> +
> +	if (args->flags != 0)
> +		return -EINVAL;
> +
> +	for (i = 0; i < args->num_items; i++, user_item_ptr++) {
> +		struct drm_i915_query_item item;
> +		u64 func_idx;
> +		int ret;
> +
> +		if (copy_from_user(&item, user_item_ptr, sizeof(item)))
> +			return -EFAULT;
> +
> +		if (item.query_id == 0)
> +			return -EINVAL;
> +
> +		func_idx = item.query_id - 1;
> +
> +		if (func_idx < ARRAY_SIZE(i915_query_funcs))
> +			ret = i915_query_funcs[func_idx](dev_priv, &item);
> +		else
> +			ret = -EINVAL;
> +
> +		/* Only write the length back to userspace if they differ. */
> +		if (ret != item.length && put_user(ret, &user_item_ptr->length))
> +			return -EFAULT;
> +	}
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/i915_query.h b/drivers/gpu/drm/i915/i915_query.h
> new file mode 100644
> index 000000000000..4550e8f21459
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/i915_query.h
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef _I915_QUERY_H_
> +#define _I915_QUERY_H_
> +
> +struct drm_device;
> +struct drm_file;
> +
> +int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
> +
> +#endif
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 29fa48e4755d..7fd980176f25 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -318,6 +318,7 @@ typedef struct _drm_i915_sarea {
>   #define DRM_I915_PERF_OPEN		0x36
>   #define DRM_I915_PERF_ADD_CONFIG	0x37
>   #define DRM_I915_PERF_REMOVE_CONFIG	0x38
> +#define DRM_I915_QUERY			0x39
>   
>   #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
>   #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
> @@ -375,6 +376,7 @@ typedef struct _drm_i915_sarea {
>   #define DRM_IOCTL_I915_PERF_OPEN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
>   #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
>   #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
> +#define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
>   
>   /* Allow drivers to submit batchbuffers directly to hardware, relying
>    * on the security mechanisms provided by hardware.
> @@ -1615,6 +1617,45 @@ struct drm_i915_perf_oa_config {
>   	__u64 flex_regs_ptr;
>   };
>   
> +
> +struct drm_i915_query_item {
> +	__u64 query_id;
> +
> +	/*
> +	 * When set to zero by userspace, this is filled with the size of the
> +	 * data to be written at the data_ptr pointer. The kernel set this
> +	 * value to a negative value to signal an error on a particular query
> +	 * item.
> +	 */
> +	__s32 length;
> +
> +	/*
> +	 * Unused for now.
> +	 */
> +	__u32 flags;
> +
> +	/*
> +	 * Data will be written at the location pointed by data_ptr when the
> +	 * value of length matches the length of the data to be written by the
> +	 * kernel.
> +	 */
> +	__u64 data_ptr;
> +};
> +
> +struct drm_i915_query {
> +	__u32 num_items;
> +
> +	/*
> +	 * Unused for now.
> +	 */
> +	__u32 flags;
> +
> +	/*
> +	 * This point to an array of num_items drm_i915_query_item structures.
> +	 */
> +	__u64 items_ptr;
> +};
> +
>   #if defined(__cplusplus)
>   }
>   #endif
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v13 6/6] drm/i915: expose rcs topology through query uAPI
  2018-02-15 12:02 ` [PATCH v13 6/6] drm/i915: expose rcs topology through " Lionel Landwerlin
  2018-02-16 12:28   ` Joonas Lahtinen
@ 2018-02-20 11:05   ` Tvrtko Ursulin
  2018-02-20 11:16     ` Lionel Landwerlin
  1 sibling, 1 reply; 17+ messages in thread
From: Tvrtko Ursulin @ 2018-02-20 11:05 UTC (permalink / raw)
  To: Lionel Landwerlin, intel-gfx; +Cc: joonas.lahtinen


On 15/02/2018 12:02, Lionel Landwerlin wrote:
> With the introduction of asymmetric slices in CNL, we cannot rely on
> the previous SUBSLICE_MASK getparam to tell userspace what subslices
> are available. Here we introduce a more detailed way of querying the
> Gen's GPU topology that doesn't aggregate numbers.
> 
> This is essential for monitoring parts of the GPU with the OA unit,
> because counters need to be normalized to the number of
> EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
> not gives us sufficient information.
> 
> As a bonus we can draw representations of the GPU :
> 
>          https://imgur.com/a/vuqpa
> 
> v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
>      Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko)
>      Add uapi macros to read data from *_info structs (Tvrtko)
> 
> v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko)
> 
> v4: factorize query item writting (Tvrtko)
>      tweak uapi struct/define names (Tvrtko)
> 
> v5: Replace ALIGN() macro (Chris)
> 
> v6: Updated uapi comments (Tvrtko)
>      Moved flags != 0 checks into vfuncs (Tvrtko)
> 
> v7: Use access_ok() before copying anything, to avoid overflows (Chris)
>      Switch BUG_ON() to GEM_WARN_ON() (Tvrtko)
> 
> v8: Tweak uapi comments style to match the coding style (Lionel)
> 
> v9: Fix error in comment about computation of enabled subslice (Tvrtko)
> 
> v10: Fix/update comments in uAPI (Sagar)
> 
> v11: Drop drm_i915_query_(slice|subslice|eu)_info in favor of a single
>       drm_i915_query_topology_info (Joonas)
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_query.c | 71 +++++++++++++++++++++++++++++++++++++++
>   include/uapi/drm/i915_drm.h       | 40 ++++++++++++++++++++++
>   2 files changed, 111 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 92ce3e24588e..828f1ba19248 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -25,8 +25,79 @@
>   #include "i915_drv.h"
>   #include <uapi/drm/i915_drm.h>
>   
> +static int query_topology_info(struct drm_i915_private *dev_priv,
> +			       struct drm_i915_query_item *query_item)
> +{
> +	const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
> +	struct drm_i915_query_topology_info topo_info;
> +	u32 slice_length, subslice_length, eu_length, total_length;
> +
> +	if (query_item->flags != 0)
> +		return -EINVAL;
> +
> +	if (sseu->max_slices == 0)
> +		return -ENODEV;
> +
> +	/*
> +	 * If we ever change the internal slice mask data type, we'll need to
> +	 * update this function.
> +	 */
> +	BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
> +
> +	slice_length = sizeof(sseu->slice_mask);
> +	subslice_length = sseu->max_slices *
> +		DIV_ROUND_UP(sseu->max_subslices,
> +			     sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE);
> +	eu_length = sseu->max_slices * sseu->max_subslices *
> +		DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
> +
> +	total_length = sizeof(topo_info) + slice_length + subslice_length + eu_length;
> +
> +	if (query_item->length == 0)
> +		return total_length;
> +
> +	if (query_item->length < total_length)
> +		return -EINVAL;
> +
> +	if (!access_ok(VERIFY_WRITE, u64_to_user_ptr(query_item->data_ptr),
> +		       total_length))
> +		return -EFAULT;
> +
> +	memset(&topo_info, 0, sizeof(topo_info));
> +	topo_info.max_slices = sseu->max_slices;
> +	topo_info.max_subslices = sseu->max_subslices;
> +	topo_info.max_eus_per_subslice = sseu->max_eus_per_subslice;
> +
> +	topo_info.subslice_offset = slice_length;
> +	topo_info.eu_offset = slice_length + subslice_length;
> +
> +	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
> +			   &topo_info, sizeof(topo_info)))
> +		return -EFAULT;
> +
> +	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> +					   sizeof(topo_info)),
> +			   &sseu->slice_mask, slice_length))
> +		return -EFAULT;
> +
> +	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> +					   sizeof(topo_info) +
> +					   slice_length),
> +			   sseu->subslice_mask, subslice_length))
> +		return -EFAULT;
> +
> +	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr +
> +					   sizeof(topo_info) +
> +					   slice_length + subslice_length),
> +			   sseu->eu_mask, eu_length))
> +		return -EFAULT;
> +
> +	return total_length;
> +}
> +
>   static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
>   					struct drm_i915_query_item *query_item) = {
> +	query_topology_info,
>   };
>   
>   int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 7fd980176f25..9d5c4caf5a6d 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1620,6 +1620,7 @@ struct drm_i915_perf_oa_config {
>   
>   struct drm_i915_query_item {
>   	__u64 query_id;
> +#define DRM_I915_QUERY_TOPOLOGY_INFO    0x01
>   
>   	/*
>   	 * When set to zero by userspace, this is filled with the size of the
> @@ -1656,6 +1657,45 @@ struct drm_i915_query {
>   	__u64 items_ptr;
>   };
>   
> +/*
> + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
> + *
> + * data: contains the 3 pieces of information :
> + *
> + * - the slice mask with one bit per slice telling whether a slice is
> + *   available. The availability of slice X can be queried with the following
> + *   formula :
> + *
> + *           (data[X / 8] >> (X % 8)) & 1
> + *
> + * - the subslice mask for each slice with one bit per subslice telling
> + *   whether a subslice is available. The availability of subslice Y in slice
> + *   X can be queried with the following formula :
> + *
> + *           (data[subslice_offset +
> + *                 X * DIV_ROUND_UP(max_subslices, 8) +
> + *                 Y / 8] >> (Y % 8)) & 1
> + *
> + * - the EU mask for each subslice in each slice with one bit per EU telling
> + *   whether an EU is available. The availability of EU Z in subslice Y in
> + *   slice X can be queried with the following formula :
> + *
> + *           (data[eu_offset +
> + *                 X * max_subslices * DIV_ROUND_UP(max_eus_per_subslice, 8) +
> + *                 Y * DIV_ROUND_UP(max_eus_per_subslice, 8) +
> + *                 Z / 8] >> (Z % 8)) & 1
> + */
> +struct drm_i915_query_topology_info {
> +	__u16 max_slices;
> +	__u16 max_subslices;
> +	__u16 max_eus_per_subslice;

I'd add __u16 pad here.

> +
> +	__u16 subslice_offset;
> +	__u16 eu_offset;
> +

And __u16 pad2[2] here.

Or alternatively only __u15 pad[3] here to align to 64-bit. Whichever 
version looks better to you.

> +	__u8 data[];
> +};
> +
>   #if defined(__cplusplus)
>   }
>   #endif
> 

Otherwise I did not do a full review but can say that one query is fine 
by me.

Regards,

Tvrtko

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v13 6/6] drm/i915: expose rcs topology through query uAPI
  2018-02-20 11:05   ` Tvrtko Ursulin
@ 2018-02-20 11:16     ` Lionel Landwerlin
  0 siblings, 0 replies; 17+ messages in thread
From: Lionel Landwerlin @ 2018-02-20 11:16 UTC (permalink / raw)
  To: Tvrtko Ursulin, intel-gfx; +Cc: joonas.lahtinen

On 20/02/18 11:05, Tvrtko Ursulin wrote:
>
> On 15/02/2018 12:02, Lionel Landwerlin wrote:
>> With the introduction of asymmetric slices in CNL, we cannot rely on
>> the previous SUBSLICE_MASK getparam to tell userspace what subslices
>> are available. Here we introduce a more detailed way of querying the
>> Gen's GPU topology that doesn't aggregate numbers.
>>
>> This is essential for monitoring parts of the GPU with the OA unit,
>> because counters need to be normalized to the number of
>> EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do
>> not gives us sufficient information.
>>
>> As a bonus we can draw representations of the GPU :
>>
>>          https://imgur.com/a/vuqpa
>>
>> v2: Rename uapi struct s/_mask/_info/ (Tvrtko)
>>      Report max_slice/subslice/eus_per_subslice rather than strides 
>> (Tvrtko)
>>      Add uapi macros to read data from *_info structs (Tvrtko)
>>
>> v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom 
>> shifts (Tvrtko)
>>
>> v4: factorize query item writting (Tvrtko)
>>      tweak uapi struct/define names (Tvrtko)
>>
>> v5: Replace ALIGN() macro (Chris)
>>
>> v6: Updated uapi comments (Tvrtko)
>>      Moved flags != 0 checks into vfuncs (Tvrtko)
>>
>> v7: Use access_ok() before copying anything, to avoid overflows (Chris)
>>      Switch BUG_ON() to GEM_WARN_ON() (Tvrtko)
>>
>> v8: Tweak uapi comments style to match the coding style (Lionel)
>>
>> v9: Fix error in comment about computation of enabled subslice (Tvrtko)
>>
>> v10: Fix/update comments in uAPI (Sagar)
>>
>> v11: Drop drm_i915_query_(slice|subslice|eu)_info in favor of a single
>>       drm_i915_query_topology_info (Joonas)
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_query.c | 71 
>> +++++++++++++++++++++++++++++++++++++++
>>   include/uapi/drm/i915_drm.h       | 40 ++++++++++++++++++++++
>>   2 files changed, 111 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_query.c 
>> b/drivers/gpu/drm/i915/i915_query.c
>> index 92ce3e24588e..828f1ba19248 100644
>> --- a/drivers/gpu/drm/i915/i915_query.c
>> +++ b/drivers/gpu/drm/i915/i915_query.c
>> @@ -25,8 +25,79 @@
>>   #include "i915_drv.h"
>>   #include <uapi/drm/i915_drm.h>
>>   +static int query_topology_info(struct drm_i915_private *dev_priv,
>> +                   struct drm_i915_query_item *query_item)
>> +{
>> +    const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu;
>> +    struct drm_i915_query_topology_info topo_info;
>> +    u32 slice_length, subslice_length, eu_length, total_length;
>> +
>> +    if (query_item->flags != 0)
>> +        return -EINVAL;
>> +
>> +    if (sseu->max_slices == 0)
>> +        return -ENODEV;
>> +
>> +    /*
>> +     * If we ever change the internal slice mask data type, we'll 
>> need to
>> +     * update this function.
>> +     */
>> +    BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
>> +
>> +    slice_length = sizeof(sseu->slice_mask);
>> +    subslice_length = sseu->max_slices *
>> +        DIV_ROUND_UP(sseu->max_subslices,
>> +                 sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE);
>> +    eu_length = sseu->max_slices * sseu->max_subslices *
>> +        DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE);
>> +
>> +    total_length = sizeof(topo_info) + slice_length + 
>> subslice_length + eu_length;
>> +
>> +    if (query_item->length == 0)
>> +        return total_length;
>> +
>> +    if (query_item->length < total_length)
>> +        return -EINVAL;
>> +
>> +    if (!access_ok(VERIFY_WRITE, u64_to_user_ptr(query_item->data_ptr),
>> +               total_length))
>> +        return -EFAULT;
>> +
>> +    memset(&topo_info, 0, sizeof(topo_info));
>> +    topo_info.max_slices = sseu->max_slices;
>> +    topo_info.max_subslices = sseu->max_subslices;
>> +    topo_info.max_eus_per_subslice = sseu->max_eus_per_subslice;
>> +
>> +    topo_info.subslice_offset = slice_length;
>> +    topo_info.eu_offset = slice_length + subslice_length;
>> +
>> +    if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
>> +               &topo_info, sizeof(topo_info)))
>> +        return -EFAULT;
>> +
>> +    if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr +
>> +                       sizeof(topo_info)),
>> +               &sseu->slice_mask, slice_length))
>> +        return -EFAULT;
>> +
>> +    if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr +
>> +                       sizeof(topo_info) +
>> +                       slice_length),
>> +               sseu->subslice_mask, subslice_length))
>> +        return -EFAULT;
>> +
>> +    if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr +
>> +                       sizeof(topo_info) +
>> +                       slice_length + subslice_length),
>> +               sseu->eu_mask, eu_length))
>> +        return -EFAULT;
>> +
>> +    return total_length;
>> +}
>> +
>>   static int (* const i915_query_funcs[])(struct drm_i915_private 
>> *dev_priv,
>>                       struct drm_i915_query_item *query_item) = {
>> +    query_topology_info,
>>   };
>>     int i915_query_ioctl(struct drm_device *dev, void *data, struct 
>> drm_file *file)
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index 7fd980176f25..9d5c4caf5a6d 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -1620,6 +1620,7 @@ struct drm_i915_perf_oa_config {
>>     struct drm_i915_query_item {
>>       __u64 query_id;
>> +#define DRM_I915_QUERY_TOPOLOGY_INFO    0x01
>>         /*
>>        * When set to zero by userspace, this is filled with the size 
>> of the
>> @@ -1656,6 +1657,45 @@ struct drm_i915_query {
>>       __u64 items_ptr;
>>   };
>>   +/*
>> + * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
>> + *
>> + * data: contains the 3 pieces of information :
>> + *
>> + * - the slice mask with one bit per slice telling whether a slice is
>> + *   available. The availability of slice X can be queried with the 
>> following
>> + *   formula :
>> + *
>> + *           (data[X / 8] >> (X % 8)) & 1
>> + *
>> + * - the subslice mask for each slice with one bit per subslice telling
>> + *   whether a subslice is available. The availability of subslice Y 
>> in slice
>> + *   X can be queried with the following formula :
>> + *
>> + *           (data[subslice_offset +
>> + *                 X * DIV_ROUND_UP(max_subslices, 8) +
>> + *                 Y / 8] >> (Y % 8)) & 1
>> + *
>> + * - the EU mask for each subslice in each slice with one bit per EU 
>> telling
>> + *   whether an EU is available. The availability of EU Z in 
>> subslice Y in
>> + *   slice X can be queried with the following formula :
>> + *
>> + *           (data[eu_offset +
>> + *                 X * max_subslices * 
>> DIV_ROUND_UP(max_eus_per_subslice, 8) +
>> + *                 Y * DIV_ROUND_UP(max_eus_per_subslice, 8) +
>> + *                 Z / 8] >> (Z % 8)) & 1
>> + */
>> +struct drm_i915_query_topology_info {
>> +    __u16 max_slices;
>> +    __u16 max_subslices;
>> +    __u16 max_eus_per_subslice;
>
> I'd add __u16 pad here.

Sure. Joonas also emitted the idea of have a flag to change the meaning 
of data, so will add that too.

>
>> +
>> +    __u16 subslice_offset;
>> +    __u16 eu_offset;
>> +
>
> And __u16 pad2[2] here.
>
> Or alternatively only __u15 pad[3] here to align to 64-bit. Whichever 
> version looks better to you.

Okay, I thought because the following with u8 it wouldn't matter, but sure.

>
>> +    __u8 data[];
>> +};
>> +
>>   #if defined(__cplusplus)
>>   }
>>   #endif
>>
>
> Otherwise I did not do a full review but can say that one query is 
> fine by me.

Thanks!

>
> Regards,
>
> Tvrtko
>
>

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^ permalink raw reply	[flat|nested] 17+ messages in thread
* Re: [PATCH v13 0/6] drm/i915: expose RCS topology to userspace
  2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
                   ` (9 preceding siblings ...)
  2018-02-15 19:28 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-02-21 11:33 ` Chris Wilson
  10 siblings, 0 replies; 17+ messages in thread
From: Chris Wilson @ 2018-02-21 11:33 UTC (permalink / raw)
  To: Lionel Landwerlin, intel-gfx; +Cc: joonas.lahtinen

Quoting Lionel Landwerlin (2018-02-15 12:01:56)
> Hi all,
> 
> After some discussion with Joonas we agreed on changing some of the
> rcs topology structs in the uAPI. It now uses a single struct instead
> of 3.
> 
> I've also changed the bit the query uAPI to make it more sensible to
> userspace (please see comment in patch 5).
> 
> Therefore dropping the Rb on patches 5 & 6.
> 
> Cheers,
> 
> Lionel Landwerlin (6):
>   drm/i915: store all subslice masks
>   drm/i915/debugfs: reuse max slice/subslices already stored in sseu
>   drm/i915/debugfs: add rcs topology entry
>   drm/i915: add rcs topology to error state
>   drm/i915: add query uAPI
>   drm/i915: expose rcs topology through query uAPI

Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply	[flat|nested] 17+ messages in thread
end of thread, other threads:[~2018-02-21 11:33 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-15 12:01 [PATCH v13 0/6] drm/i915: expose RCS topology to userspace Lionel Landwerlin
2018-02-15 12:01 ` [PATCH v13 1/6] drm/i915: store all subslice masks Lionel Landwerlin
2018-02-15 12:01 ` [PATCH v13 2/6] drm/i915/debugfs: reuse max slice/subslices already stored in sseu Lionel Landwerlin
2018-02-15 12:01 ` [PATCH v13 3/6] drm/i915/debugfs: add rcs topology entry Lionel Landwerlin
2018-02-15 12:02 ` [PATCH v13 4/6] drm/i915: add rcs topology to error state Lionel Landwerlin
2018-02-15 12:02 ` [PATCH v13 5/6] drm/i915: add query uAPI Lionel Landwerlin
2018-02-20 10:58   ` Tvrtko Ursulin
2018-02-15 12:02 ` [PATCH v13 6/6] drm/i915: expose rcs topology through " Lionel Landwerlin
2018-02-16 12:28   ` Joonas Lahtinen
2018-02-16 12:35     ` Lionel Landwerlin
2018-02-20 11:05   ` Tvrtko Ursulin
2018-02-20 11:16     ` Lionel Landwerlin
2018-02-15 12:11 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: expose RCS topology to userspace Patchwork
2018-02-15 12:13 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-02-15 12:27 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-15 19:28 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-02-21 11:33 ` [PATCH v13 0/6] " Chris Wilson

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