* [PATCH 0/5] soc: renesas: dd symbols for R-Car Gen3 register offsets
@ 2018-02-12 15:44 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Simon Horman
Add and use symbols for Gen3 register offsets to improve readability.
This has no functional change.
Based on renesas-devel-20180212-v4.16-rc1.
Simon Horman (5):
soc: renesas: Add symbols for R-Car Gen3 register offsets
soc: renesas: Use symbols for register offsets for R-Car H3 power
areas
soc: renesas: Use symbols for register offsets for R-Car M3-W power
areas
soc: renesas: Use symbols for register offsets for R-Car V3M power
areas
soc: renesas: Use symbols for register offsets for R-Car D3 power
areas
drivers/soc/renesas/r8a7795-sysc.c | 76 +++++++++++++++++++++----------------
drivers/soc/renesas/r8a7796-sysc.c | 56 +++++++++++++++------------
drivers/soc/renesas/r8a77970-sysc.c | 39 +++++++++++--------
drivers/soc/renesas/r8a77995-sysc.c | 11 +++---
drivers/soc/renesas/rcar-sysc.h | 19 ++++++++++
5 files changed, 125 insertions(+), 76 deletions(-)
--
2.11.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 0/5] soc: renesas: dd symbols for R-Car Gen3 register offsets
@ 2018-02-12 15:44 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-arm-kernel
Add and use symbols for Gen3 register offsets to improve readability.
This has no functional change.
Based on renesas-devel-20180212-v4.16-rc1.
Simon Horman (5):
soc: renesas: Add symbols for R-Car Gen3 register offsets
soc: renesas: Use symbols for register offsets for R-Car H3 power
areas
soc: renesas: Use symbols for register offsets for R-Car M3-W power
areas
soc: renesas: Use symbols for register offsets for R-Car V3M power
areas
soc: renesas: Use symbols for register offsets for R-Car D3 power
areas
drivers/soc/renesas/r8a7795-sysc.c | 76 +++++++++++++++++++++----------------
drivers/soc/renesas/r8a7796-sysc.c | 56 +++++++++++++++------------
drivers/soc/renesas/r8a77970-sysc.c | 39 +++++++++++--------
drivers/soc/renesas/r8a77995-sysc.c | 11 +++---
drivers/soc/renesas/rcar-sysc.h | 19 ++++++++++
5 files changed, 125 insertions(+), 76 deletions(-)
--
2.11.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] soc: renesas: Add symbols for R-Car Gen3 register offsets
2018-02-12 15:44 ` Simon Horman
@ 2018-02-12 15:44 ` Simon Horman
-1 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Simon Horman
Add symbols for Gen3 register offsets.
These may be used to improve readability of users of these offsets.
This does not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/rcar-sysc.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index 9d9daf9eb91b..c6041e29fbcb 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -24,6 +24,25 @@
#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
+/*
+ * R-Car Gen3 register offsets
+ */
+
+#define RCAR_GEN3_SYSCSR 0
+#define RCAR_GEN3_PWRSR0 0x80
+#define RCAR_GEN3_PWRSR2 0x100
+#define RCAR_GEN3_PWRSR3 0x140
+#define RCAR_GEN3_PWRSR4 0x180
+#define RCAR_GEN3_PWRSR5 0x1c0
+#define RCAR_GEN3_PWRSR6 0x200
+#define RCAR_GEN3_PWRSR7 0x240
+#define RCAR_GEN3_PWRSR8 0x340
+#define RCAR_GEN3_PWRSR9 0x380
+#define RCAR_GEN3_PWRSR10 0x3c0
+#define RCAR_GEN3_PWRSR11 0x400
+#define RCAR_GEN3_PWRSR12 0x2c0
+#define RCAR_GEN3_PWRSR13 0x300
+#define RCAR_GEN3_PWRSR14 0x280
/*
* Description of a Power Area
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 1/5] soc: renesas: Add symbols for R-Car Gen3 register offsets
@ 2018-02-12 15:44 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-arm-kernel
Add symbols for Gen3 register offsets.
These may be used to improve readability of users of these offsets.
This does not introduce any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/rcar-sysc.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
index 9d9daf9eb91b..c6041e29fbcb 100644
--- a/drivers/soc/renesas/rcar-sysc.h
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -24,6 +24,25 @@
#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
+/*
+ * R-Car Gen3 register offsets
+ */
+
+#define RCAR_GEN3_SYSCSR 0
+#define RCAR_GEN3_PWRSR0 0x80
+#define RCAR_GEN3_PWRSR2 0x100
+#define RCAR_GEN3_PWRSR3 0x140
+#define RCAR_GEN3_PWRSR4 0x180
+#define RCAR_GEN3_PWRSR5 0x1c0
+#define RCAR_GEN3_PWRSR6 0x200
+#define RCAR_GEN3_PWRSR7 0x240
+#define RCAR_GEN3_PWRSR8 0x340
+#define RCAR_GEN3_PWRSR9 0x380
+#define RCAR_GEN3_PWRSR10 0x3c0
+#define RCAR_GEN3_PWRSR11 0x400
+#define RCAR_GEN3_PWRSR12 0x2c0
+#define RCAR_GEN3_PWRSR13 0x300
+#define RCAR_GEN3_PWRSR14 0x280
/*
* Description of a Power Area
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/5] soc: renesas: Use symbols for register offsets for R-Car H3 power areas
2018-02-12 15:44 ` Simon Horman
@ 2018-02-12 15:44 ` Simon Horman
-1 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Simon Horman
Use symbols rather for register offsets for R-Car H3 power areas
to improve readability.
This does not have any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/r8a7795-sysc.c | 76 ++++++++++++++++++++++----------------
1 file changed, 44 insertions(+), 32 deletions(-)
diff --git a/drivers/soc/renesas/r8a7795-sysc.c b/drivers/soc/renesas/r8a7795-sysc.c
index 7412666187b3..0c8440741b58 100644
--- a/drivers/soc/renesas/r8a7795-sysc.c
+++ b/drivers/soc/renesas/r8a7795-sysc.c
@@ -17,39 +17,51 @@
#include "rcar-sysc.h"
static struct rcar_sysc_area r8a7795_areas[] __initdata = {
- { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
- { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
- PD_SCU },
- { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
- PD_SCU },
- { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON },
- { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON },
- { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON },
+ { "always-on", RCAR_GEN3_SYSCSR, 0, R8A7795_PD_ALWAYS_ON,
+ -1, PD_ALWAYS_ON },
+ { "ca57-scu", RCAR_GEN3_PWRSR5, 0, R8A7795_PD_CA57_SCU,
+ R8A7795_PD_ALWAYS_ON, PD_SCU },
+ { "ca57-cpu0", RCAR_GEN3_PWRSR0, 0, R8A7795_PD_CA57_CPU0,
+ R8A7795_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca57-cpu1", RCAR_GEN3_PWRSR0, 1, R8A7795_PD_CA57_CPU1,
+ R8A7795_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca57-cpu2", RCAR_GEN3_PWRSR0, 2, R8A7795_PD_CA57_CPU2,
+ R8A7795_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca57-cpu3", RCAR_GEN3_PWRSR0, 3, R8A7795_PD_CA57_CPU3,
+ R8A7795_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca53-scu", RCAR_GEN3_PWRSR3, 0, R8A7795_PD_CA53_SCU,
+ R8A7795_PD_ALWAYS_ON, PD_SCU },
+ { "ca53-cpu0", RCAR_GEN3_PWRSR6, 0, R8A7795_PD_CA53_CPU0,
+ R8A7795_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu1", RCAR_GEN3_PWRSR6, 1, R8A7795_PD_CA53_CPU1,
+ R8A7795_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu2", RCAR_GEN3_PWRSR6, 2, R8A7795_PD_CA53_CPU2,
+ R8A7795_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu3", RCAR_GEN3_PWRSR6, 3, R8A7795_PD_CA53_CPU3,
+ R8A7795_PD_CA53_SCU, PD_CPU_NOCR },
+ { "a3vp", RCAR_GEN3_PWRSR8, 0, R8A7795_PD_A3VP,
+ R8A7795_PD_ALWAYS_ON },
+ { "cr7", RCAR_GEN3_PWRSR7, 0, R8A7795_PD_CR7,
+ R8A7795_PD_ALWAYS_ON },
+ { "a3vc", RCAR_GEN3_PWRSR9, 0, R8A7795_PD_A3VC,
+ R8A7795_PD_ALWAYS_ON },
/* A2VC0 exists on ES1.x only */
- { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
- { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
- { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
- { "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
- { "3dg-c", 0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
- { "3dg-d", 0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
- { "3dg-e", 0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
- { "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON },
+ { "a2vc0", RCAR_GEN3_PWRSR10, 0, R8A7795_PD_A2VC0,
+ R8A7795_PD_A3VC },
+ { "a2vc1", RCAR_GEN3_PWRSR10, 1, R8A7795_PD_A2VC1,
+ R8A7795_PD_A3VC },
+ { "3dg-a", RCAR_GEN3_PWRSR2, 0, R8A7795_PD_3DG_A,
+ R8A7795_PD_ALWAYS_ON },
+ { "3dg-b", RCAR_GEN3_PWRSR2, 1, R8A7795_PD_3DG_B,
+ R8A7795_PD_3DG_A },
+ { "3dg-c", RCAR_GEN3_PWRSR2, 2, R8A7795_PD_3DG_C,
+ R8A7795_PD_3DG_B },
+ { "3dg-d", RCAR_GEN3_PWRSR2, 3, R8A7795_PD_3DG_D,
+ R8A7795_PD_3DG_C },
+ { "3dg-e", RCAR_GEN3_PWRSR2, 4, R8A7795_PD_3DG_E,
+ R8A7795_PD_3DG_D },
+ { "a3ir", RCAR_GEN3_PWRSR4, 0, R8A7795_PD_A3IR,
+ R8A7795_PD_ALWAYS_ON },
};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/5] soc: renesas: Use symbols for register offsets for R-Car H3 power areas
@ 2018-02-12 15:44 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-arm-kernel
Use symbols rather for register offsets for R-Car H3 power areas
to improve readability.
This does not have any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/r8a7795-sysc.c | 76 ++++++++++++++++++++++----------------
1 file changed, 44 insertions(+), 32 deletions(-)
diff --git a/drivers/soc/renesas/r8a7795-sysc.c b/drivers/soc/renesas/r8a7795-sysc.c
index 7412666187b3..0c8440741b58 100644
--- a/drivers/soc/renesas/r8a7795-sysc.c
+++ b/drivers/soc/renesas/r8a7795-sysc.c
@@ -17,39 +17,51 @@
#include "rcar-sysc.h"
static struct rcar_sysc_area r8a7795_areas[] __initdata = {
- { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
- { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
- PD_SCU },
- { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
- PD_SCU },
- { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON },
- { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON },
- { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON },
+ { "always-on", RCAR_GEN3_SYSCSR, 0, R8A7795_PD_ALWAYS_ON,
+ -1, PD_ALWAYS_ON },
+ { "ca57-scu", RCAR_GEN3_PWRSR5, 0, R8A7795_PD_CA57_SCU,
+ R8A7795_PD_ALWAYS_ON, PD_SCU },
+ { "ca57-cpu0", RCAR_GEN3_PWRSR0, 0, R8A7795_PD_CA57_CPU0,
+ R8A7795_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca57-cpu1", RCAR_GEN3_PWRSR0, 1, R8A7795_PD_CA57_CPU1,
+ R8A7795_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca57-cpu2", RCAR_GEN3_PWRSR0, 2, R8A7795_PD_CA57_CPU2,
+ R8A7795_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca57-cpu3", RCAR_GEN3_PWRSR0, 3, R8A7795_PD_CA57_CPU3,
+ R8A7795_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca53-scu", RCAR_GEN3_PWRSR3, 0, R8A7795_PD_CA53_SCU,
+ R8A7795_PD_ALWAYS_ON, PD_SCU },
+ { "ca53-cpu0", RCAR_GEN3_PWRSR6, 0, R8A7795_PD_CA53_CPU0,
+ R8A7795_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu1", RCAR_GEN3_PWRSR6, 1, R8A7795_PD_CA53_CPU1,
+ R8A7795_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu2", RCAR_GEN3_PWRSR6, 2, R8A7795_PD_CA53_CPU2,
+ R8A7795_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu3", RCAR_GEN3_PWRSR6, 3, R8A7795_PD_CA53_CPU3,
+ R8A7795_PD_CA53_SCU, PD_CPU_NOCR },
+ { "a3vp", RCAR_GEN3_PWRSR8, 0, R8A7795_PD_A3VP,
+ R8A7795_PD_ALWAYS_ON },
+ { "cr7", RCAR_GEN3_PWRSR7, 0, R8A7795_PD_CR7,
+ R8A7795_PD_ALWAYS_ON },
+ { "a3vc", RCAR_GEN3_PWRSR9, 0, R8A7795_PD_A3VC,
+ R8A7795_PD_ALWAYS_ON },
/* A2VC0 exists on ES1.x only */
- { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
- { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
- { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
- { "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
- { "3dg-c", 0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
- { "3dg-d", 0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
- { "3dg-e", 0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
- { "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON },
+ { "a2vc0", RCAR_GEN3_PWRSR10, 0, R8A7795_PD_A2VC0,
+ R8A7795_PD_A3VC },
+ { "a2vc1", RCAR_GEN3_PWRSR10, 1, R8A7795_PD_A2VC1,
+ R8A7795_PD_A3VC },
+ { "3dg-a", RCAR_GEN3_PWRSR2, 0, R8A7795_PD_3DG_A,
+ R8A7795_PD_ALWAYS_ON },
+ { "3dg-b", RCAR_GEN3_PWRSR2, 1, R8A7795_PD_3DG_B,
+ R8A7795_PD_3DG_A },
+ { "3dg-c", RCAR_GEN3_PWRSR2, 2, R8A7795_PD_3DG_C,
+ R8A7795_PD_3DG_B },
+ { "3dg-d", RCAR_GEN3_PWRSR2, 3, R8A7795_PD_3DG_D,
+ R8A7795_PD_3DG_C },
+ { "3dg-e", RCAR_GEN3_PWRSR2, 4, R8A7795_PD_3DG_E,
+ R8A7795_PD_3DG_D },
+ { "a3ir", RCAR_GEN3_PWRSR4, 0, R8A7795_PD_A3IR,
+ R8A7795_PD_ALWAYS_ON },
};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/5] soc: renesas: Use symbols for register offsets for R-Car M3-W power areas
2018-02-12 15:44 ` Simon Horman
@ 2018-02-12 15:44 ` Simon Horman
-1 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Simon Horman
Use symbols rather for register offsets for R-Car M3-W power areas
to improve readability.
This does not have any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/r8a7796-sysc.c | 56 ++++++++++++++++++++++----------------
1 file changed, 32 insertions(+), 24 deletions(-)
diff --git a/drivers/soc/renesas/r8a7796-sysc.c b/drivers/soc/renesas/r8a7796-sysc.c
index f700c842b9e1..beea0ee0d85e 100644
--- a/drivers/soc/renesas/r8a7796-sysc.c
+++ b/drivers/soc/renesas/r8a7796-sysc.c
@@ -16,30 +16,38 @@
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a7796_areas[] __initconst = {
- { "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
- { "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON,
- PD_SCU },
- { "ca57-cpu0", 0x80, 0, R8A7796_PD_CA57_CPU0, R8A7796_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca57-cpu1", 0x80, 1, R8A7796_PD_CA57_CPU1, R8A7796_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca53-scu", 0x140, 0, R8A7796_PD_CA53_SCU, R8A7796_PD_ALWAYS_ON,
- PD_SCU },
- { "ca53-cpu0", 0x200, 0, R8A7796_PD_CA53_CPU0, R8A7796_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu1", 0x200, 1, R8A7796_PD_CA53_CPU1, R8A7796_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu2", 0x200, 2, R8A7796_PD_CA53_CPU2, R8A7796_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu3", 0x200, 3, R8A7796_PD_CA53_CPU3, R8A7796_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "cr7", 0x240, 0, R8A7796_PD_CR7, R8A7796_PD_ALWAYS_ON },
- { "a3vc", 0x380, 0, R8A7796_PD_A3VC, R8A7796_PD_ALWAYS_ON },
- { "a2vc0", 0x3c0, 0, R8A7796_PD_A2VC0, R8A7796_PD_A3VC },
- { "a2vc1", 0x3c0, 1, R8A7796_PD_A2VC1, R8A7796_PD_A3VC },
- { "3dg-a", 0x100, 0, R8A7796_PD_3DG_A, R8A7796_PD_ALWAYS_ON },
- { "3dg-b", 0x100, 1, R8A7796_PD_3DG_B, R8A7796_PD_3DG_A },
- { "a3ir", 0x180, 0, R8A7796_PD_A3IR, R8A7796_PD_ALWAYS_ON },
+ { "always-on", RCAR_GEN3_SYSCSR, 0, R8A7796_PD_ALWAYS_ON,
+ -1, PD_ALWAYS_ON },
+ { "ca57-scu", RCAR_GEN3_PWRSR5, 0, R8A7796_PD_CA57_SCU,
+ R8A7796_PD_ALWAYS_ON, PD_SCU },
+ { "ca57-cpu0", RCAR_GEN3_PWRSR0, 0, R8A7796_PD_CA57_CPU0,
+ R8A7796_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca57-cpu1", RCAR_GEN3_PWRSR0, 1, R8A7796_PD_CA57_CPU1,
+ R8A7796_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca53-scu", RCAR_GEN3_PWRSR3, 0, R8A7796_PD_CA53_SCU,
+ R8A7796_PD_ALWAYS_ON, PD_SCU },
+ { "ca53-cpu0", RCAR_GEN3_PWRSR6, 0, R8A7796_PD_CA53_CPU0,
+ R8A7796_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu1", RCAR_GEN3_PWRSR6, 1, R8A7796_PD_CA53_CPU1,
+ R8A7796_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu2", RCAR_GEN3_PWRSR6, 2, R8A7796_PD_CA53_CPU2,
+ R8A7796_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu3", RCAR_GEN3_PWRSR6, 3, R8A7796_PD_CA53_CPU3,
+ R8A7796_PD_CA53_SCU, PD_CPU_NOCR },
+ { "cr7", RCAR_GEN3_PWRSR7, 0, R8A7796_PD_CR7,
+ R8A7796_PD_ALWAYS_ON },
+ { "a3vc", RCAR_GEN3_PWRSR9, 0, R8A7796_PD_A3VC,
+ R8A7796_PD_ALWAYS_ON },
+ { "a2vc0", RCAR_GEN3_PWRSR10, 0, R8A7796_PD_A2VC0,
+ R8A7796_PD_A3VC },
+ { "a2vc1", RCAR_GEN3_PWRSR10, 1, R8A7796_PD_A2VC1,
+ R8A7796_PD_A3VC },
+ { "3dg-a", RCAR_GEN3_PWRSR2, 0, R8A7796_PD_3DG_A,
+ R8A7796_PD_ALWAYS_ON },
+ { "3dg-b", RCAR_GEN3_PWRSR2, 1, R8A7796_PD_3DG_B,
+ R8A7796_PD_3DG_A },
+ { "a3ir", RCAR_GEN3_PWRSR4, 0, R8A7796_PD_A3IR,
+ R8A7796_PD_ALWAYS_ON },
};
const struct rcar_sysc_info r8a7796_sysc_info __initconst = {
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/5] soc: renesas: Use symbols for register offsets for R-Car M3-W power areas
@ 2018-02-12 15:44 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-arm-kernel
Use symbols rather for register offsets for R-Car M3-W power areas
to improve readability.
This does not have any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/r8a7796-sysc.c | 56 ++++++++++++++++++++++----------------
1 file changed, 32 insertions(+), 24 deletions(-)
diff --git a/drivers/soc/renesas/r8a7796-sysc.c b/drivers/soc/renesas/r8a7796-sysc.c
index f700c842b9e1..beea0ee0d85e 100644
--- a/drivers/soc/renesas/r8a7796-sysc.c
+++ b/drivers/soc/renesas/r8a7796-sysc.c
@@ -16,30 +16,38 @@
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a7796_areas[] __initconst = {
- { "always-on", 0, 0, R8A7796_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
- { "ca57-scu", 0x1c0, 0, R8A7796_PD_CA57_SCU, R8A7796_PD_ALWAYS_ON,
- PD_SCU },
- { "ca57-cpu0", 0x80, 0, R8A7796_PD_CA57_CPU0, R8A7796_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca57-cpu1", 0x80, 1, R8A7796_PD_CA57_CPU1, R8A7796_PD_CA57_SCU,
- PD_CPU_NOCR },
- { "ca53-scu", 0x140, 0, R8A7796_PD_CA53_SCU, R8A7796_PD_ALWAYS_ON,
- PD_SCU },
- { "ca53-cpu0", 0x200, 0, R8A7796_PD_CA53_CPU0, R8A7796_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu1", 0x200, 1, R8A7796_PD_CA53_CPU1, R8A7796_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu2", 0x200, 2, R8A7796_PD_CA53_CPU2, R8A7796_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu3", 0x200, 3, R8A7796_PD_CA53_CPU3, R8A7796_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "cr7", 0x240, 0, R8A7796_PD_CR7, R8A7796_PD_ALWAYS_ON },
- { "a3vc", 0x380, 0, R8A7796_PD_A3VC, R8A7796_PD_ALWAYS_ON },
- { "a2vc0", 0x3c0, 0, R8A7796_PD_A2VC0, R8A7796_PD_A3VC },
- { "a2vc1", 0x3c0, 1, R8A7796_PD_A2VC1, R8A7796_PD_A3VC },
- { "3dg-a", 0x100, 0, R8A7796_PD_3DG_A, R8A7796_PD_ALWAYS_ON },
- { "3dg-b", 0x100, 1, R8A7796_PD_3DG_B, R8A7796_PD_3DG_A },
- { "a3ir", 0x180, 0, R8A7796_PD_A3IR, R8A7796_PD_ALWAYS_ON },
+ { "always-on", RCAR_GEN3_SYSCSR, 0, R8A7796_PD_ALWAYS_ON,
+ -1, PD_ALWAYS_ON },
+ { "ca57-scu", RCAR_GEN3_PWRSR5, 0, R8A7796_PD_CA57_SCU,
+ R8A7796_PD_ALWAYS_ON, PD_SCU },
+ { "ca57-cpu0", RCAR_GEN3_PWRSR0, 0, R8A7796_PD_CA57_CPU0,
+ R8A7796_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca57-cpu1", RCAR_GEN3_PWRSR0, 1, R8A7796_PD_CA57_CPU1,
+ R8A7796_PD_CA57_SCU, PD_CPU_NOCR },
+ { "ca53-scu", RCAR_GEN3_PWRSR3, 0, R8A7796_PD_CA53_SCU,
+ R8A7796_PD_ALWAYS_ON, PD_SCU },
+ { "ca53-cpu0", RCAR_GEN3_PWRSR6, 0, R8A7796_PD_CA53_CPU0,
+ R8A7796_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu1", RCAR_GEN3_PWRSR6, 1, R8A7796_PD_CA53_CPU1,
+ R8A7796_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu2", RCAR_GEN3_PWRSR6, 2, R8A7796_PD_CA53_CPU2,
+ R8A7796_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu3", RCAR_GEN3_PWRSR6, 3, R8A7796_PD_CA53_CPU3,
+ R8A7796_PD_CA53_SCU, PD_CPU_NOCR },
+ { "cr7", RCAR_GEN3_PWRSR7, 0, R8A7796_PD_CR7,
+ R8A7796_PD_ALWAYS_ON },
+ { "a3vc", RCAR_GEN3_PWRSR9, 0, R8A7796_PD_A3VC,
+ R8A7796_PD_ALWAYS_ON },
+ { "a2vc0", RCAR_GEN3_PWRSR10, 0, R8A7796_PD_A2VC0,
+ R8A7796_PD_A3VC },
+ { "a2vc1", RCAR_GEN3_PWRSR10, 1, R8A7796_PD_A2VC1,
+ R8A7796_PD_A3VC },
+ { "3dg-a", RCAR_GEN3_PWRSR2, 0, R8A7796_PD_3DG_A,
+ R8A7796_PD_ALWAYS_ON },
+ { "3dg-b", RCAR_GEN3_PWRSR2, 1, R8A7796_PD_3DG_B,
+ R8A7796_PD_3DG_A },
+ { "a3ir", RCAR_GEN3_PWRSR4, 0, R8A7796_PD_A3IR,
+ R8A7796_PD_ALWAYS_ON },
};
const struct rcar_sysc_info r8a7796_sysc_info __initconst = {
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/5] soc: renesas: Use symbols for register offsets for R-Car V3M power areas
2018-02-12 15:44 ` Simon Horman
@ 2018-02-12 15:44 ` Simon Horman
-1 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Simon Horman
Use symbols rather for register offsets for R-Car V3M power areas
to improve readability.
Also line-wrap at 80 columns for consistency with R-Car H3 and M3-W
implementations.
This does not have any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/r8a77970-sysc.c | 39 +++++++++++++++++++++++--------------
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/drivers/soc/renesas/r8a77970-sysc.c b/drivers/soc/renesas/r8a77970-sysc.c
index 8c614164718e..a21066bd5ba7 100644
--- a/drivers/soc/renesas/r8a77970-sysc.c
+++ b/drivers/soc/renesas/r8a77970-sysc.c
@@ -16,21 +16,30 @@
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a77970_areas[] __initconst = {
- { "always-on", 0, 0, R8A77970_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
- { "ca53-scu", 0x140, 0, R8A77970_PD_CA53_SCU, R8A77970_PD_ALWAYS_ON,
- PD_SCU },
- { "ca53-cpu0", 0x200, 0, R8A77970_PD_CA53_CPU0, R8A77970_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu1", 0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "cr7", 0x240, 0, R8A77970_PD_CR7, R8A77970_PD_ALWAYS_ON },
- { "a3ir", 0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON },
- { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_ALWAYS_ON },
- { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A2IR0 },
- { "a2ir2", 0x400, 2, R8A77970_PD_A2IR2, R8A77970_PD_A2IR0 },
- { "a2ir3", 0x400, 3, R8A77970_PD_A2IR3, R8A77970_PD_A2IR0 },
- { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_ALWAYS_ON },
- { "a2sc1", 0x400, 5, R8A77970_PD_A2SC1, R8A77970_PD_A2SC0 },
+ { "always-on", RCAR_GEN3_SYSCSR, 0, R8A77970_PD_ALWAYS_ON,
+ -1, PD_ALWAYS_ON },
+ { "ca53-scu", RCAR_GEN3_PWRSR3, 0, R8A77970_PD_CA53_SCU,
+ R8A77970_PD_ALWAYS_ON, PD_SCU },
+ { "ca53-cpu0", RCAR_GEN3_PWRSR6, 0, R8A77970_PD_CA53_CPU0,
+ R8A77970_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu1", RCAR_GEN3_PWRSR6, 1, R8A77970_PD_CA53_CPU1,
+ R8A77970_PD_CA53_SCU, PD_CPU_NOCR },
+ { "cr7", RCAR_GEN3_PWRSR7, 0, R8A77970_PD_CR7,
+ R8A77970_PD_ALWAYS_ON },
+ { "a3ir", RCAR_GEN3_PWRSR4, 0, R8A77970_PD_A3IR,
+ R8A77970_PD_ALWAYS_ON },
+ { "a2ir0", RCAR_GEN3_PWRSR11, 0, R8A77970_PD_A2IR0,
+ R8A77970_PD_ALWAYS_ON },
+ { "a2ir1", RCAR_GEN3_PWRSR11, 1, R8A77970_PD_A2IR1,
+ R8A77970_PD_A2IR0 },
+ { "a2ir2", RCAR_GEN3_PWRSR11, 2, R8A77970_PD_A2IR2,
+ R8A77970_PD_A2IR0 },
+ { "a2ir3", RCAR_GEN3_PWRSR11, 3, R8A77970_PD_A2IR3,
+ R8A77970_PD_A2IR0 },
+ { "a2sc0", RCAR_GEN3_PWRSR11, 4, R8A77970_PD_A2SC0,
+ R8A77970_PD_ALWAYS_ON },
+ { "a2sc1", RCAR_GEN3_PWRSR11, 5, R8A77970_PD_A2SC1,
+ R8A77970_PD_A2SC0 },
};
const struct rcar_sysc_info r8a77970_sysc_info __initconst = {
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/5] soc: renesas: Use symbols for register offsets for R-Car V3M power areas
@ 2018-02-12 15:44 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-arm-kernel
Use symbols rather for register offsets for R-Car V3M power areas
to improve readability.
Also line-wrap at 80 columns for consistency with R-Car H3 and M3-W
implementations.
This does not have any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/r8a77970-sysc.c | 39 +++++++++++++++++++++++--------------
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/drivers/soc/renesas/r8a77970-sysc.c b/drivers/soc/renesas/r8a77970-sysc.c
index 8c614164718e..a21066bd5ba7 100644
--- a/drivers/soc/renesas/r8a77970-sysc.c
+++ b/drivers/soc/renesas/r8a77970-sysc.c
@@ -16,21 +16,30 @@
#include "rcar-sysc.h"
static const struct rcar_sysc_area r8a77970_areas[] __initconst = {
- { "always-on", 0, 0, R8A77970_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
- { "ca53-scu", 0x140, 0, R8A77970_PD_CA53_SCU, R8A77970_PD_ALWAYS_ON,
- PD_SCU },
- { "ca53-cpu0", 0x200, 0, R8A77970_PD_CA53_CPU0, R8A77970_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "ca53-cpu1", 0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU,
- PD_CPU_NOCR },
- { "cr7", 0x240, 0, R8A77970_PD_CR7, R8A77970_PD_ALWAYS_ON },
- { "a3ir", 0x180, 0, R8A77970_PD_A3IR, R8A77970_PD_ALWAYS_ON },
- { "a2ir0", 0x400, 0, R8A77970_PD_A2IR0, R8A77970_PD_ALWAYS_ON },
- { "a2ir1", 0x400, 1, R8A77970_PD_A2IR1, R8A77970_PD_A2IR0 },
- { "a2ir2", 0x400, 2, R8A77970_PD_A2IR2, R8A77970_PD_A2IR0 },
- { "a2ir3", 0x400, 3, R8A77970_PD_A2IR3, R8A77970_PD_A2IR0 },
- { "a2sc0", 0x400, 4, R8A77970_PD_A2SC0, R8A77970_PD_ALWAYS_ON },
- { "a2sc1", 0x400, 5, R8A77970_PD_A2SC1, R8A77970_PD_A2SC0 },
+ { "always-on", RCAR_GEN3_SYSCSR, 0, R8A77970_PD_ALWAYS_ON,
+ -1, PD_ALWAYS_ON },
+ { "ca53-scu", RCAR_GEN3_PWRSR3, 0, R8A77970_PD_CA53_SCU,
+ R8A77970_PD_ALWAYS_ON, PD_SCU },
+ { "ca53-cpu0", RCAR_GEN3_PWRSR6, 0, R8A77970_PD_CA53_CPU0,
+ R8A77970_PD_CA53_SCU, PD_CPU_NOCR },
+ { "ca53-cpu1", RCAR_GEN3_PWRSR6, 1, R8A77970_PD_CA53_CPU1,
+ R8A77970_PD_CA53_SCU, PD_CPU_NOCR },
+ { "cr7", RCAR_GEN3_PWRSR7, 0, R8A77970_PD_CR7,
+ R8A77970_PD_ALWAYS_ON },
+ { "a3ir", RCAR_GEN3_PWRSR4, 0, R8A77970_PD_A3IR,
+ R8A77970_PD_ALWAYS_ON },
+ { "a2ir0", RCAR_GEN3_PWRSR11, 0, R8A77970_PD_A2IR0,
+ R8A77970_PD_ALWAYS_ON },
+ { "a2ir1", RCAR_GEN3_PWRSR11, 1, R8A77970_PD_A2IR1,
+ R8A77970_PD_A2IR0 },
+ { "a2ir2", RCAR_GEN3_PWRSR11, 2, R8A77970_PD_A2IR2,
+ R8A77970_PD_A2IR0 },
+ { "a2ir3", RCAR_GEN3_PWRSR11, 3, R8A77970_PD_A2IR3,
+ R8A77970_PD_A2IR0 },
+ { "a2sc0", RCAR_GEN3_PWRSR11, 4, R8A77970_PD_A2SC0,
+ R8A77970_PD_ALWAYS_ON },
+ { "a2sc1", RCAR_GEN3_PWRSR11, 5, R8A77970_PD_A2SC1,
+ R8A77970_PD_A2SC0 },
};
const struct rcar_sysc_info r8a77970_sysc_info __initconst = {
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/5] soc: renesas: Use symbols for register offsets for R-Car D3 power areas
2018-02-12 15:44 ` Simon Horman
@ 2018-02-12 15:44 ` Simon Horman
-1 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Simon Horman
Use symbols rather for register offsets for R-Car D3 power areas
to improve readability.
Also line-wrap at 80 columns for consistency with R-Car H3 and M3-W
implementations.
This does not have any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/r8a77995-sysc.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/renesas/r8a77995-sysc.c b/drivers/soc/renesas/r8a77995-sysc.c
index f718429cab02..45355a5cca34 100644
--- a/drivers/soc/renesas/r8a77995-sysc.c
+++ b/drivers/soc/renesas/r8a77995-sysc.c
@@ -17,11 +17,12 @@
#include "rcar-sysc.h"
static struct rcar_sysc_area r8a77995_areas[] __initdata = {
- { "always-on", 0, 0, R8A77995_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
- { "ca53-scu", 0x140, 0, R8A77995_PD_CA53_SCU, R8A77995_PD_ALWAYS_ON,
- PD_SCU },
- { "ca53-cpu0", 0x200, 0, R8A77995_PD_CA53_CPU0, R8A77995_PD_CA53_SCU,
- PD_CPU_NOCR },
+ { "always-on", RCAR_GEN3_SYSCSR, 0, R8A77995_PD_ALWAYS_ON,
+ -1, PD_ALWAYS_ON },
+ { "ca53-scu", RCAR_GEN3_PWRSR3, 0, R8A77995_PD_CA53_SCU,
+ R8A77995_PD_ALWAYS_ON, PD_SCU },
+ { "ca53-cpu0", RCAR_GEN3_PWRSR6, 0, R8A77995_PD_CA53_CPU0,
+ R8A77995_PD_CA53_SCU, PD_CPU_NOCR },
};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/5] soc: renesas: Use symbols for register offsets for R-Car D3 power areas
@ 2018-02-12 15:44 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-12 15:44 UTC (permalink / raw)
To: linux-arm-kernel
Use symbols rather for register offsets for R-Car D3 power areas
to improve readability.
Also line-wrap at 80 columns for consistency with R-Car H3 and M3-W
implementations.
This does not have any functional change.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/r8a77995-sysc.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/renesas/r8a77995-sysc.c b/drivers/soc/renesas/r8a77995-sysc.c
index f718429cab02..45355a5cca34 100644
--- a/drivers/soc/renesas/r8a77995-sysc.c
+++ b/drivers/soc/renesas/r8a77995-sysc.c
@@ -17,11 +17,12 @@
#include "rcar-sysc.h"
static struct rcar_sysc_area r8a77995_areas[] __initdata = {
- { "always-on", 0, 0, R8A77995_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
- { "ca53-scu", 0x140, 0, R8A77995_PD_CA53_SCU, R8A77995_PD_ALWAYS_ON,
- PD_SCU },
- { "ca53-cpu0", 0x200, 0, R8A77995_PD_CA53_CPU0, R8A77995_PD_CA53_SCU,
- PD_CPU_NOCR },
+ { "always-on", RCAR_GEN3_SYSCSR, 0, R8A77995_PD_ALWAYS_ON,
+ -1, PD_ALWAYS_ON },
+ { "ca53-scu", RCAR_GEN3_PWRSR3, 0, R8A77995_PD_CA53_SCU,
+ R8A77995_PD_ALWAYS_ON, PD_SCU },
+ { "ca53-cpu0", RCAR_GEN3_PWRSR6, 0, R8A77995_PD_CA53_CPU0,
+ R8A77995_PD_CA53_SCU, PD_CPU_NOCR },
};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 1/5] soc: renesas: Add symbols for R-Car Gen3 register offsets
2018-02-12 15:44 ` Simon Horman
@ 2018-02-14 10:25 ` Geert Uytterhoeven
-1 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2018-02-14 10:25 UTC (permalink / raw)
To: Simon Horman; +Cc: Linux-Renesas, linux-arm-kernel, Magnus Damm
Hi Simon,
On Mon, Feb 12, 2018 at 4:44 PM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Add symbols for Gen3 register offsets.
> These may be used to improve readability of users of these offsets.
>
> This does not introduce any functional change.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Thanks for your patch!
> --- a/drivers/soc/renesas/rcar-sysc.h
> +++ b/drivers/soc/renesas/rcar-sysc.h
> @@ -24,6 +24,25 @@
> #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
> #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
>
> +/*
> + * R-Car Gen3 register offsets
> + */
> +
> +#define RCAR_GEN3_SYSCSR 0
Please drop this. The "always-on" domains use 0 to indicate "no register
block", not as a reference to the SYSCSR register.
> +#define RCAR_GEN3_PWRSR0 0x80
> +#define RCAR_GEN3_PWRSR2 0x100
> +#define RCAR_GEN3_PWRSR3 0x140
> +#define RCAR_GEN3_PWRSR4 0x180
> +#define RCAR_GEN3_PWRSR5 0x1c0
> +#define RCAR_GEN3_PWRSR6 0x200
> +#define RCAR_GEN3_PWRSR7 0x240
> +#define RCAR_GEN3_PWRSR8 0x340
> +#define RCAR_GEN3_PWRSR9 0x380
> +#define RCAR_GEN3_PWRSR10 0x3c0
> +#define RCAR_GEN3_PWRSR11 0x400
> +#define RCAR_GEN3_PWRSR12 0x2c0
> +#define RCAR_GEN3_PWRSR13 0x300
> +#define RCAR_GEN3_PWRSR14 0x280
What about
#define RCAR_GEN3_PWRSR(n) (0x80 + (n) * 0x40)
instead?
Bummer, they have a hole between 0x240 and 0x340, which they filled later :-(
So I don't know how stable the PWRSRx indices are...
For R-Car H1 and Gen2 you can use the following, though:
#define RCAR_H1_PWRSR(n) (0x40 + (n) * 0x40)
#define RCAR_GEN2_PWRSR(n) (0x40 + (n) * 0x40)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] soc: renesas: Add symbols for R-Car Gen3 register offsets
@ 2018-02-14 10:25 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2018-02-14 10:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon,
On Mon, Feb 12, 2018 at 4:44 PM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Add symbols for Gen3 register offsets.
> These may be used to improve readability of users of these offsets.
>
> This does not introduce any functional change.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Thanks for your patch!
> --- a/drivers/soc/renesas/rcar-sysc.h
> +++ b/drivers/soc/renesas/rcar-sysc.h
> @@ -24,6 +24,25 @@
> #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
> #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
>
> +/*
> + * R-Car Gen3 register offsets
> + */
> +
> +#define RCAR_GEN3_SYSCSR 0
Please drop this. The "always-on" domains use 0 to indicate "no register
block", not as a reference to the SYSCSR register.
> +#define RCAR_GEN3_PWRSR0 0x80
> +#define RCAR_GEN3_PWRSR2 0x100
> +#define RCAR_GEN3_PWRSR3 0x140
> +#define RCAR_GEN3_PWRSR4 0x180
> +#define RCAR_GEN3_PWRSR5 0x1c0
> +#define RCAR_GEN3_PWRSR6 0x200
> +#define RCAR_GEN3_PWRSR7 0x240
> +#define RCAR_GEN3_PWRSR8 0x340
> +#define RCAR_GEN3_PWRSR9 0x380
> +#define RCAR_GEN3_PWRSR10 0x3c0
> +#define RCAR_GEN3_PWRSR11 0x400
> +#define RCAR_GEN3_PWRSR12 0x2c0
> +#define RCAR_GEN3_PWRSR13 0x300
> +#define RCAR_GEN3_PWRSR14 0x280
What about
#define RCAR_GEN3_PWRSR(n) (0x80 + (n) * 0x40)
instead?
Bummer, they have a hole between 0x240 and 0x340, which they filled later :-(
So I don't know how stable the PWRSRx indices are...
For R-Car H1 and Gen2 you can use the following, though:
#define RCAR_H1_PWRSR(n) (0x40 + (n) * 0x40)
#define RCAR_GEN2_PWRSR(n) (0x40 + (n) * 0x40)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/5] soc: renesas: Add symbols for R-Car Gen3 register offsets
2018-02-14 10:25 ` Geert Uytterhoeven
@ 2018-02-15 15:02 ` Simon Horman
-1 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-15 15:02 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linux-Renesas, linux-arm-kernel, Magnus Damm
On Wed, Feb 14, 2018 at 11:25:19AM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Mon, Feb 12, 2018 at 4:44 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Add symbols for Gen3 register offsets.
> > These may be used to improve readability of users of these offsets.
> >
> > This does not introduce any functional change.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Thanks for your patch!
>
> > --- a/drivers/soc/renesas/rcar-sysc.h
> > +++ b/drivers/soc/renesas/rcar-sysc.h
> > @@ -24,6 +24,25 @@
> > #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
> > #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
> >
> > +/*
> > + * R-Car Gen3 register offsets
> > + */
> > +
> > +#define RCAR_GEN3_SYSCSR 0
>
> Please drop this. The "always-on" domains use 0 to indicate "no register
> block", not as a reference to the SYSCSR register.
Ok, understood.
Could I tempt you with RCAR_SYSC_ALWAYS_ON ?
> > +#define RCAR_GEN3_PWRSR0 0x80
> > +#define RCAR_GEN3_PWRSR2 0x100
> > +#define RCAR_GEN3_PWRSR3 0x140
> > +#define RCAR_GEN3_PWRSR4 0x180
> > +#define RCAR_GEN3_PWRSR5 0x1c0
> > +#define RCAR_GEN3_PWRSR6 0x200
> > +#define RCAR_GEN3_PWRSR7 0x240
> > +#define RCAR_GEN3_PWRSR8 0x340
> > +#define RCAR_GEN3_PWRSR9 0x380
> > +#define RCAR_GEN3_PWRSR10 0x3c0
> > +#define RCAR_GEN3_PWRSR11 0x400
> > +#define RCAR_GEN3_PWRSR12 0x2c0
> > +#define RCAR_GEN3_PWRSR13 0x300
> > +#define RCAR_GEN3_PWRSR14 0x280
>
> What about
>
> #define RCAR_GEN3_PWRSR(n) (0x80 + (n) * 0x40)
>
> instead?
> Bummer, they have a hole between 0x240 and 0x340, which they filled later :-(
> So I don't know how stable the PWRSRx indices are...
Ok, would you rather use the approach I provided or wait?
>
> For R-Car H1 and Gen2 you can use the following, though:
>
> #define RCAR_H1_PWRSR(n) (0x40 + (n) * 0x40)
> #define RCAR_GEN2_PWRSR(n) (0x40 + (n) * 0x40)
Thanks, got it.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] soc: renesas: Add symbols for R-Car Gen3 register offsets
@ 2018-02-15 15:02 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-02-15 15:02 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Feb 14, 2018 at 11:25:19AM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Mon, Feb 12, 2018 at 4:44 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Add symbols for Gen3 register offsets.
> > These may be used to improve readability of users of these offsets.
> >
> > This does not introduce any functional change.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Thanks for your patch!
>
> > --- a/drivers/soc/renesas/rcar-sysc.h
> > +++ b/drivers/soc/renesas/rcar-sysc.h
> > @@ -24,6 +24,25 @@
> > #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
> > #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
> >
> > +/*
> > + * R-Car Gen3 register offsets
> > + */
> > +
> > +#define RCAR_GEN3_SYSCSR 0
>
> Please drop this. The "always-on" domains use 0 to indicate "no register
> block", not as a reference to the SYSCSR register.
Ok, understood.
Could I tempt you with RCAR_SYSC_ALWAYS_ON ?
> > +#define RCAR_GEN3_PWRSR0 0x80
> > +#define RCAR_GEN3_PWRSR2 0x100
> > +#define RCAR_GEN3_PWRSR3 0x140
> > +#define RCAR_GEN3_PWRSR4 0x180
> > +#define RCAR_GEN3_PWRSR5 0x1c0
> > +#define RCAR_GEN3_PWRSR6 0x200
> > +#define RCAR_GEN3_PWRSR7 0x240
> > +#define RCAR_GEN3_PWRSR8 0x340
> > +#define RCAR_GEN3_PWRSR9 0x380
> > +#define RCAR_GEN3_PWRSR10 0x3c0
> > +#define RCAR_GEN3_PWRSR11 0x400
> > +#define RCAR_GEN3_PWRSR12 0x2c0
> > +#define RCAR_GEN3_PWRSR13 0x300
> > +#define RCAR_GEN3_PWRSR14 0x280
>
> What about
>
> #define RCAR_GEN3_PWRSR(n) (0x80 + (n) * 0x40)
>
> instead?
> Bummer, they have a hole between 0x240 and 0x340, which they filled later :-(
> So I don't know how stable the PWRSRx indices are...
Ok, would you rather use the approach I provided or wait?
>
> For R-Car H1 and Gen2 you can use the following, though:
>
> #define RCAR_H1_PWRSR(n) (0x40 + (n) * 0x40)
> #define RCAR_GEN2_PWRSR(n) (0x40 + (n) * 0x40)
Thanks, got it.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/5] soc: renesas: Add symbols for R-Car Gen3 register offsets
2018-02-15 15:02 ` Simon Horman
@ 2018-02-16 8:52 ` Geert Uytterhoeven
-1 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2018-02-16 8:52 UTC (permalink / raw)
To: Simon Horman, Jacopo Mondi, Sergei Shtylyov
Cc: Linux-Renesas, linux-arm-kernel, Magnus Damm
Hi Simon,
On Thu, Feb 15, 2018 at 4:02 PM, Simon Horman <horms@verge.net.au> wrote:
> On Wed, Feb 14, 2018 at 11:25:19AM +0100, Geert Uytterhoeven wrote:
>> On Mon, Feb 12, 2018 at 4:44 PM, Simon Horman
>> <horms+renesas@verge.net.au> wrote:
>> > Add symbols for Gen3 register offsets.
>> > These may be used to improve readability of users of these offsets.
>> >
>> > This does not introduce any functional change.
>> >
>> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>>
>> Thanks for your patch!
>>
>> > --- a/drivers/soc/renesas/rcar-sysc.h
>> > +++ b/drivers/soc/renesas/rcar-sysc.h
>> > @@ -24,6 +24,25 @@
>> > #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
>> > #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
>> >
>> > +/*
>> > + * R-Car Gen3 register offsets
>> > + */
>> > +
>> > +#define RCAR_GEN3_SYSCSR 0
>>
>> Please drop this. The "always-on" domains use 0 to indicate "no register
>> block", not as a reference to the SYSCSR register.
>
> Ok, understood.
>
> Could I tempt you with RCAR_SYSC_ALWAYS_ON ?
IMHO that obfuscates what's going on, while 0 is a clear indicator.
>> > +#define RCAR_GEN3_PWRSR0 0x80
>> > +#define RCAR_GEN3_PWRSR2 0x100
>> > +#define RCAR_GEN3_PWRSR3 0x140
>> > +#define RCAR_GEN3_PWRSR4 0x180
>> > +#define RCAR_GEN3_PWRSR5 0x1c0
>> > +#define RCAR_GEN3_PWRSR6 0x200
>> > +#define RCAR_GEN3_PWRSR7 0x240
>> > +#define RCAR_GEN3_PWRSR8 0x340
>> > +#define RCAR_GEN3_PWRSR9 0x380
>> > +#define RCAR_GEN3_PWRSR10 0x3c0
>> > +#define RCAR_GEN3_PWRSR11 0x400
>> > +#define RCAR_GEN3_PWRSR12 0x2c0
>> > +#define RCAR_GEN3_PWRSR13 0x300
>> > +#define RCAR_GEN3_PWRSR14 0x280
>>
>> What about
>>
>> #define RCAR_GEN3_PWRSR(n) (0x80 + (n) * 0x40)
>>
>> instead?
>> Bummer, they have a hole between 0x240 and 0x340, which they filled later :-(
>> So I don't know how stable the PWRSRx indices are...
>
> Ok, would you rather use the approach I provided or wait?
Your approach is fine, due to the non-contiguous numbering.
Although I still have mixed feelings, as I usually look at the actual
base offsets,
not register abbreviations, when adding/reviewing support for new SoCs.
I may be biased, though.
Jacopo/Sergei: You were the last persons adding a new SYSC driver.
Do you have any opinion?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/5] soc: renesas: Add symbols for R-Car Gen3 register offsets
@ 2018-02-16 8:52 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2018-02-16 8:52 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon,
On Thu, Feb 15, 2018 at 4:02 PM, Simon Horman <horms@verge.net.au> wrote:
> On Wed, Feb 14, 2018 at 11:25:19AM +0100, Geert Uytterhoeven wrote:
>> On Mon, Feb 12, 2018 at 4:44 PM, Simon Horman
>> <horms+renesas@verge.net.au> wrote:
>> > Add symbols for Gen3 register offsets.
>> > These may be used to improve readability of users of these offsets.
>> >
>> > This does not introduce any functional change.
>> >
>> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>>
>> Thanks for your patch!
>>
>> > --- a/drivers/soc/renesas/rcar-sysc.h
>> > +++ b/drivers/soc/renesas/rcar-sysc.h
>> > @@ -24,6 +24,25 @@
>> > #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
>> > #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
>> >
>> > +/*
>> > + * R-Car Gen3 register offsets
>> > + */
>> > +
>> > +#define RCAR_GEN3_SYSCSR 0
>>
>> Please drop this. The "always-on" domains use 0 to indicate "no register
>> block", not as a reference to the SYSCSR register.
>
> Ok, understood.
>
> Could I tempt you with RCAR_SYSC_ALWAYS_ON ?
IMHO that obfuscates what's going on, while 0 is a clear indicator.
>> > +#define RCAR_GEN3_PWRSR0 0x80
>> > +#define RCAR_GEN3_PWRSR2 0x100
>> > +#define RCAR_GEN3_PWRSR3 0x140
>> > +#define RCAR_GEN3_PWRSR4 0x180
>> > +#define RCAR_GEN3_PWRSR5 0x1c0
>> > +#define RCAR_GEN3_PWRSR6 0x200
>> > +#define RCAR_GEN3_PWRSR7 0x240
>> > +#define RCAR_GEN3_PWRSR8 0x340
>> > +#define RCAR_GEN3_PWRSR9 0x380
>> > +#define RCAR_GEN3_PWRSR10 0x3c0
>> > +#define RCAR_GEN3_PWRSR11 0x400
>> > +#define RCAR_GEN3_PWRSR12 0x2c0
>> > +#define RCAR_GEN3_PWRSR13 0x300
>> > +#define RCAR_GEN3_PWRSR14 0x280
>>
>> What about
>>
>> #define RCAR_GEN3_PWRSR(n) (0x80 + (n) * 0x40)
>>
>> instead?
>> Bummer, they have a hole between 0x240 and 0x340, which they filled later :-(
>> So I don't know how stable the PWRSRx indices are...
>
> Ok, would you rather use the approach I provided or wait?
Your approach is fine, due to the non-contiguous numbering.
Although I still have mixed feelings, as I usually look at the actual
base offsets,
not register abbreviations, when adding/reviewing support for new SoCs.
I may be biased, though.
Jacopo/Sergei: You were the last persons adding a new SYSC driver.
Do you have any opinion?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-02-16 8:52 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-12 15:44 [PATCH 0/5] soc: renesas: dd symbols for R-Car Gen3 register offsets Simon Horman
2018-02-12 15:44 ` Simon Horman
2018-02-12 15:44 ` [PATCH 1/5] soc: renesas: Add " Simon Horman
2018-02-12 15:44 ` Simon Horman
2018-02-14 10:25 ` Geert Uytterhoeven
2018-02-14 10:25 ` Geert Uytterhoeven
2018-02-15 15:02 ` Simon Horman
2018-02-15 15:02 ` Simon Horman
2018-02-16 8:52 ` Geert Uytterhoeven
2018-02-16 8:52 ` Geert Uytterhoeven
2018-02-12 15:44 ` [PATCH 2/5] soc: renesas: Use symbols for register offsets for R-Car H3 power areas Simon Horman
2018-02-12 15:44 ` Simon Horman
2018-02-12 15:44 ` [PATCH 3/5] soc: renesas: Use symbols for register offsets for R-Car M3-W " Simon Horman
2018-02-12 15:44 ` Simon Horman
2018-02-12 15:44 ` [PATCH 4/5] soc: renesas: Use symbols for register offsets for R-Car V3M " Simon Horman
2018-02-12 15:44 ` Simon Horman
2018-02-12 15:44 ` [PATCH 5/5] soc: renesas: Use symbols for register offsets for R-Car D3 " Simon Horman
2018-02-12 15:44 ` Simon Horman
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