* [PATCH 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
@ 2018-02-23 14:10 Michal Wajdeczko
2018-02-23 14:10 ` [PATCH 2/2] HAX: Enable GuC for CI Michal Wajdeczko
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Michal Wajdeczko @ 2018-02-23 14:10 UTC (permalink / raw)
To: intel-gfx
We want to use higher level 'uc' functions as the main entry points to
the GuC/HuC code to hide some details and keep code layered.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.c | 6 +++---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
drivers/gpu/drm/i915/intel_guc.c | 42 +++++++++++++------------------------
drivers/gpu/drm/i915/intel_guc.h | 4 ++--
drivers/gpu/drm/i915/intel_uc.c | 45 ++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_uc.h | 2 ++
6 files changed, 68 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aaa861b..d61b51c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2575,7 +2575,7 @@ static int intel_runtime_suspend(struct device *kdev)
*/
i915_gem_runtime_suspend(dev_priv);
- intel_guc_suspend(dev_priv);
+ intel_uc_suspend(dev_priv);
intel_runtime_pm_disable_interrupts(dev_priv);
@@ -2597,7 +2597,7 @@ static int intel_runtime_suspend(struct device *kdev)
intel_runtime_pm_enable_interrupts(dev_priv);
- intel_guc_resume(dev_priv);
+ intel_uc_resume(dev_priv);
i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
@@ -2683,7 +2683,7 @@ static int intel_runtime_resume(struct device *kdev)
intel_runtime_pm_enable_interrupts(dev_priv);
- intel_guc_resume(dev_priv);
+ intel_uc_resume(dev_priv);
/*
* No point of rolling back things in case of an error, as the best
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 14c855b..ef6aff8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4919,7 +4919,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
mutex_unlock(&dev->struct_mutex);
- intel_guc_suspend(dev_priv);
+ intel_uc_suspend(dev_priv);
cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(&dev_priv->gt.retire_work);
@@ -4986,7 +4986,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
if (i915_gem_init_hw(i915))
goto err_wedged;
- intel_guc_resume(i915);
+ intel_uc_resume(i915);
/* Always reload a context for powersaving. */
if (i915_gem_switch_to_kernel_context(i915))
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 21140cc..6ca6b9a 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -403,22 +403,15 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
/**
* intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv: i915 device private
+ * @guc: the guc
*/
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
+int intel_guc_suspend(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- gen9_disable_guc_interrupts(dev_priv);
-
- data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
- /* any value greater than GUC_POWER_D0 */
- data[1] = GUC_POWER_D1;
- data[2] = guc_ggtt_offset(guc->shared_data);
+ u32 data[] = {
+ INTEL_GUC_ACTION_ENTER_S_STATE,
+ GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
+ guc_ggtt_offset(guc->shared_data)
+ };
return intel_guc_send(guc, data, ARRAY_SIZE(data));
}
@@ -448,22 +441,15 @@ int intel_guc_reset_engine(struct intel_guc *guc,
/**
* intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv: i915 device private
+ * @guc: the guc
*/
-int intel_guc_resume(struct drm_i915_private *dev_priv)
+int intel_guc_resume(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- if (i915_modparams.guc_log_level)
- gen9_enable_guc_interrupts(dev_priv);
-
- data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
- data[1] = GUC_POWER_D0;
- data[2] = guc_ggtt_offset(guc->shared_data);
+ u32 data[] = {
+ INTEL_GUC_ACTION_EXIT_S_STATE,
+ GUC_POWER_D0,
+ guc_ggtt_offset(guc->shared_data)
+ };
return intel_guc_send(guc, data, ARRAY_SIZE(data));
}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 52856a9..b9424ac 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -127,8 +127,8 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
-int intel_guc_suspend(struct drm_i915_private *dev_priv);
-int intel_guc_resume(struct drm_i915_private *dev_priv);
+int intel_guc_suspend(struct intel_guc *guc);
+int intel_guc_resume(struct intel_guc *guc);
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9f1bac6..a821f7a 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -445,3 +445,48 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
if (USES_GUC_SUBMISSION(dev_priv))
gen9_disable_guc_interrupts(dev_priv);
}
+
+int intel_uc_suspend(struct drm_i915_private *i915)
+{
+ struct intel_guc *guc = &i915->guc;
+ int err;
+
+ if (!USES_GUC(i915))
+ return 0;
+
+ if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ return 0;
+
+ err = intel_guc_suspend(guc);
+ if (err) {
+ DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
+ return err;
+ }
+
+ gen9_disable_guc_interrupts(i915);
+
+ return 0;
+}
+
+int intel_uc_resume(struct drm_i915_private *i915)
+{
+ struct intel_guc *guc = &i915->guc;
+ int err;
+
+ if (!USES_GUC(i915))
+ return 0;
+
+ if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ return 0;
+
+ if (i915_modparams.guc_log_level)
+ gen9_enable_guc_interrupts(i915);
+
+ err = intel_guc_resume(guc);
+ if (err) {
+ DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
+ return err;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index f2984e0..f76d51d 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -39,6 +39,8 @@
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
int intel_uc_init(struct drm_i915_private *dev_priv);
void intel_uc_fini(struct drm_i915_private *dev_priv);
+int intel_uc_suspend(struct drm_i915_private *dev_priv);
+int intel_uc_resume(struct drm_i915_private *dev_priv);
static inline bool intel_uc_is_using_guc(void)
{
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] HAX: Enable GuC for CI
2018-02-23 14:10 [PATCH 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Michal Wajdeczko
@ 2018-02-23 14:10 ` Michal Wajdeczko
2018-02-23 14:59 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: Michal Wajdeczko @ 2018-02-23 14:10 UTC (permalink / raw)
To: intel-gfx
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..3deae1e 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, 0) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index a821f7a..0e72e60 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
enable_guc |= ENABLE_GUC_LOAD_HUC;
/* Any platform specific fine-tuning can be done here */
+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+ enable_guc = 0;
return enable_guc;
}
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
2018-02-23 14:10 [PATCH 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Michal Wajdeczko
2018-02-23 14:10 ` [PATCH 2/2] HAX: Enable GuC for CI Michal Wajdeczko
@ 2018-02-23 14:59 ` Patchwork
2018-02-23 16:11 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-02-26 6:58 ` [PATCH 1/2] " Sagar Arun Kamble
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2018-02-23 14:59 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
URL : https://patchwork.freedesktop.org/series/38867/
State : success
== Summary ==
Series 38867v1 series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
https://patchwork.freedesktop.org/api/1.0/series/38867/revisions/1/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass -> FAIL (fi-skl-6700k2) fdo#104108
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:415s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:422s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:376s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:487s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:480s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:483s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:466s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:453s
fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:390s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:564s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:414s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:291s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:506s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:386s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:406s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:452s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:448s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:488s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:449s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:488s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:586s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:429s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:498s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:519s
fi-skl-6700k2 total:288 pass:263 dwarn:0 dfail:0 fail:1 skip:24 time:472s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:466s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:405s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:426s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:520s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:389s
562dc33a969ded94e63f6fd1d76eb42d344052fb drm-tip: 2018y-02m-23d-09h-04m-20s UTC integration manifest
bad5f6e76de7 HAX: Enable GuC for CI
05ec834cb9c7 drm/i915/uc: Introduce intel_uc_suspend|resume
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8143/issues.html
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
2018-02-23 14:10 [PATCH 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Michal Wajdeczko
2018-02-23 14:10 ` [PATCH 2/2] HAX: Enable GuC for CI Michal Wajdeczko
2018-02-23 14:59 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Patchwork
@ 2018-02-23 16:11 ` Patchwork
2018-02-26 6:58 ` [PATCH 1/2] " Sagar Arun Kamble
3 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2018-02-23 16:11 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
URL : https://patchwork.freedesktop.org/series/38867/
State : failure
== Summary ==
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
incomplete -> PASS (shard-hsw) fdo#103540
Test gem_exec_schedule:
Subgroup smoketest-render:
pass -> FAIL (shard-apl)
Subgroup smoketest-all:
pass -> FAIL (shard-apl)
Test drv_selftest:
Subgroup live_guc:
pass -> DMESG-WARN (shard-apl)
Test drv_missed_irq:
pass -> SKIP (shard-apl)
Test kms_flip:
Subgroup 2x-modeset-vs-vblank-race-interruptible:
fail -> PASS (shard-hsw) fdo#103060 +1
Test drv_suspend:
Subgroup debugfs-reader:
pass -> SKIP (shard-snb) fdo#102365
pass -> SKIP (shard-hsw)
Test kms_chv_cursor_fail:
Subgroup pipe-b-256x256-left-edge:
pass -> DMESG-WARN (shard-snb) fdo#105185
Test gem_exec_suspend:
Subgroup basic-s3-devices:
pass -> INCOMPLETE (shard-apl)
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass -> FAIL (shard-apl)
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
shard-apl total:3334 pass:1749 dwarn:2 dfail:0 fail:19 skip:1561 time:11975s
shard-hsw total:3465 pass:1767 dwarn:1 dfail:0 fail:2 skip:1694 time:11670s
shard-snb total:3465 pass:1355 dwarn:2 dfail:0 fail:3 skip:2105 time:6607s
Blacklisted hosts:
shard-kbl total:3400 pass:1901 dwarn:2 dfail:1 fail:29 skip:1465 time:9367s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8143/shards.html
_______________________________________________
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
2018-02-23 14:10 [PATCH 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Michal Wajdeczko
` (2 preceding siblings ...)
2018-02-23 16:11 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-02-26 6:58 ` Sagar Arun Kamble
2018-02-26 12:33 ` Michal Wajdeczko
3 siblings, 1 reply; 12+ messages in thread
From: Sagar Arun Kamble @ 2018-02-26 6:58 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 2/23/2018 7:40 PM, Michal Wajdeczko wrote:
> We want to use higher level 'uc' functions as the main entry points to
> the GuC/HuC code to hide some details and keep code layered.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Couple of queries:
Need to add to commit message that ordering of disable_guc_interrupts
and suspend is now changed as needed
for CTB. right?
Please find below another query.
> ---
<snip>
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -445,3 +445,48 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
> if (USES_GUC_SUBMISSION(dev_priv))
> gen9_disable_guc_interrupts(dev_priv);
> }
> +
> +int intel_uc_suspend(struct drm_i915_private *i915)
> +{
> + struct intel_guc *guc = &i915->guc;
> + int err;
> +
> + if (!USES_GUC(i915))
> + return 0;
> +
> + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
Assume this will get replaced by intel_uc_fw_is_loaded from other patch
under review?
> + return 0;
> +
> + err = intel_guc_suspend(guc);
> + if (err) {
> + DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
> + return err;
> + }
> +
> + gen9_disable_guc_interrupts(i915);
> +
> + return 0;
> +}
> +
> +int intel_uc_resume(struct drm_i915_private *i915)
> +{
> + struct intel_guc *guc = &i915->guc;
> + int err;
> +
> + if (!USES_GUC(i915))
> + return 0;
> +
> + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
> + return 0;
> +
> + if (i915_modparams.guc_log_level)
> + gen9_enable_guc_interrupts(i915);
> +
> + err = intel_guc_resume(guc);
> + if (err) {
> + DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
> + return err;
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index f2984e0..f76d51d 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -39,6 +39,8 @@
> void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
> int intel_uc_init(struct drm_i915_private *dev_priv);
> void intel_uc_fini(struct drm_i915_private *dev_priv);
> +int intel_uc_suspend(struct drm_i915_private *dev_priv);
> +int intel_uc_resume(struct drm_i915_private *dev_priv);
>
> static inline bool intel_uc_is_using_guc(void)
> {
--
Thanks,
Sagar
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume
2018-02-26 6:58 ` [PATCH 1/2] " Sagar Arun Kamble
@ 2018-02-26 12:33 ` Michal Wajdeczko
0 siblings, 0 replies; 12+ messages in thread
From: Michal Wajdeczko @ 2018-02-26 12:33 UTC (permalink / raw)
To: intel-gfx, Sagar Arun Kamble
On Mon, 26 Feb 2018 07:58:49 +0100, Sagar Arun Kamble
<sagar.a.kamble@intel.com> wrote:
>
>
> On 2/23/2018 7:40 PM, Michal Wajdeczko wrote:
>> We want to use higher level 'uc' functions as the main entry points to
>> the GuC/HuC code to hide some details and keep code layered.
>>
>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>
> Couple of queries:
> Need to add to commit message that ordering of disable_guc_interrupts
> and suspend is now changed as needed
> for CTB. right?
Correct, I'll send v2 with updated commit message
> Please find below another query.
>> ---
> <snip>
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -445,3 +445,48 @@ void intel_uc_fini_hw(struct drm_i915_private
>> *dev_priv)
>> if (USES_GUC_SUBMISSION(dev_priv))
>> gen9_disable_guc_interrupts(dev_priv);
>> }
>> +
>> +int intel_uc_suspend(struct drm_i915_private *i915)
>> +{
>> + struct intel_guc *guc = &i915->guc;
>> + int err;
>> +
>> + if (!USES_GUC(i915))
>> + return 0;
>> +
>> + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
> Assume this will get replaced by intel_uc_fw_is_loaded from other patch
> under review?
That's correct too.
>> + return 0;
>> +
>> + err = intel_guc_suspend(guc);
>> + if (err) {
>> + DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
>> + return err;
>> + }
>> +
>> + gen9_disable_guc_interrupts(i915);
>> +
>> + return 0;
>> +}
>> +
>> +int intel_uc_resume(struct drm_i915_private *i915)
>> +{
>> + struct intel_guc *guc = &i915->guc;
>> + int err;
>> +
>> + if (!USES_GUC(i915))
>> + return 0;
>> +
>> + if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>> + return 0;
>> +
>> + if (i915_modparams.guc_log_level)
>> + gen9_enable_guc_interrupts(i915);
>> +
>> + err = intel_guc_resume(guc);
>> + if (err) {
>> + DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
>> + return err;
>> + }
>> +
>> + return 0;
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_uc.h
>> b/drivers/gpu/drm/i915/intel_uc.h
>> index f2984e0..f76d51d 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.h
>> +++ b/drivers/gpu/drm/i915/intel_uc.h
>> @@ -39,6 +39,8 @@
>> void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
>> int intel_uc_init(struct drm_i915_private *dev_priv);
>> void intel_uc_fini(struct drm_i915_private *dev_priv);
>> +int intel_uc_suspend(struct drm_i915_private *dev_priv);
>> +int intel_uc_resume(struct drm_i915_private *dev_priv);
>> static inline bool intel_uc_is_using_guc(void)
>> {
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/2] HAX enable GuC for CI
2018-10-16 9:42 [PATCH 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
@ 2018-10-16 9:42 ` Michal Wajdeczko
0 siblings, 0 replies; 12+ messages in thread
From: Michal Wajdeczko @ 2018-10-16 9:42 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
1.9.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] HAX enable GuC for CI
2018-10-16 8:59 [PATCH 1/2] drm/i915/guc: Fix Gen9 GuC loading workarounds Michal Wajdeczko
@ 2018-10-16 8:59 ` Michal Wajdeczko
0 siblings, 0 replies; 12+ messages in thread
From: Michal Wajdeczko @ 2018-10-16 8:59 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c51..c681537 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
1.9.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] HAX enable GuC for CI
2018-10-15 22:10 [PATCH 1/2] drm/i915/guc: fix GuC suspend/resume Daniele Ceraolo Spurio
@ 2018-10-15 22:10 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 12+ messages in thread
From: Daniele Ceraolo Spurio @ 2018-10-15 22:10 UTC (permalink / raw)
To: intel-gfx
From: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 7e56c516c815..c681537bcb92 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -45,7 +45,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
2.19.0
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] HAX enable GuC for CI
2018-07-12 14:07 [PATCH 1/2] drm/i915: Keep local modparams copy for mock selftests Jakub Bartmiński
@ 2018-07-12 14:07 ` Jakub Bartmiński
0 siblings, 0 replies; 12+ messages in thread
From: Jakub Bartmiński @ 2018-07-12 14:07 UTC (permalink / raw)
To: intel-gfx
From: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index aebe0469ddaa..3e4e128237ac 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
2.17.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] HAX enable guc for CI
2018-03-20 23:18 [PATCH 1/2] drm/i915: Add code to accept valid locked WOPCM register values Jackie Li
@ 2018-03-20 23:18 ` Jackie Li
0 siblings, 0 replies; 12+ messages in thread
From: Jackie Li @ 2018-03-20 23:18 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Jackie Li <yaodong.li@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index c963603..53037b5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
2.7.4
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] HAX: enable GuC for CI
2018-02-23 9:04 [PATCH 1/2] drm/i915/preemption: Allow preemption between submission ports Chris Wilson
@ 2018-02-23 9:04 ` Chris Wilson
0 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2018-02-23 9:04 UTC (permalink / raw)
To: intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9d0ff4..3deae1e22974 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, 0) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9f1bac6398fb..b48056fb769d 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
enable_guc |= ENABLE_GUC_LOAD_HUC;
/* Any platform specific fine-tuning can be done here */
+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+ enable_guc = 0;
return enable_guc;
}
--
2.16.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2018-10-16 9:42 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-23 14:10 [PATCH 1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Michal Wajdeczko
2018-02-23 14:10 ` [PATCH 2/2] HAX: Enable GuC for CI Michal Wajdeczko
2018-02-23 14:59 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/uc: Introduce intel_uc_suspend|resume Patchwork
2018-02-23 16:11 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-02-26 6:58 ` [PATCH 1/2] " Sagar Arun Kamble
2018-02-26 12:33 ` Michal Wajdeczko
-- strict thread matches above, loose matches on Subject: below --
2018-10-16 9:42 [PATCH 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
2018-10-16 9:42 ` [PATCH 2/2] HAX enable GuC for CI Michal Wajdeczko
2018-10-16 8:59 [PATCH 1/2] drm/i915/guc: Fix Gen9 GuC loading workarounds Michal Wajdeczko
2018-10-16 8:59 ` [PATCH 2/2] HAX enable GuC for CI Michal Wajdeczko
2018-10-15 22:10 [PATCH 1/2] drm/i915/guc: fix GuC suspend/resume Daniele Ceraolo Spurio
2018-10-15 22:10 ` [PATCH 2/2] HAX enable GuC for CI Daniele Ceraolo Spurio
2018-07-12 14:07 [PATCH 1/2] drm/i915: Keep local modparams copy for mock selftests Jakub Bartmiński
2018-07-12 14:07 ` [PATCH 2/2] HAX enable GuC for CI Jakub Bartmiński
2018-03-20 23:18 [PATCH 1/2] drm/i915: Add code to accept valid locked WOPCM register values Jackie Li
2018-03-20 23:18 ` [PATCH 2/2] HAX enable guc for CI Jackie Li
2018-02-23 9:04 [PATCH 1/2] drm/i915/preemption: Allow preemption between submission ports Chris Wilson
2018-02-23 9:04 ` [PATCH 2/2] HAX: enable GuC for CI Chris Wilson
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