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From: Jernej Skrabec <jernej.skrabec@siol.net>
To: maxime.ripard@free-electrons.com, wens@csie.org,
	airlied@linux.ie, robh+dt@kernel.org, mark.rutland@arm.com,
	mturquette@baylibre.com, sboyd@kernel.org
Cc: jernej.skrabec@siol.net, dri-devel@lists.freedesktop.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-sunxi@googlegroups.com
Subject: [PATCH v2 02/16] clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
Date: Tue, 27 Feb 2018 23:26:47 +0100	[thread overview]
Message-ID: <20180227222701.9716-3-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20180227222701.9716-1-jernej.skrabec@siol.net>

Although user manuals for H3 and H5 SoCs state that minimal rate
supported by video PLL is around 30 MHz, it seems that in reality
minimal rate is around 192 MHz.

Experiments showed that any rate below 96 MHz doesn't produce any video
output at all. Even at this frequency, stable output depends on right
factors. For example, when N = 4 and M = 1, output is stable and when N
= 8 and M = 2, it's not.

BSP clock driver suggest that minimum stable frequency is 192 MHz. That
would also be in line with A64 SoC, which has similar periphery.

Set minimal video PLL rate for H3/H5 to 192 MHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 29bc0566b776..b9f39078c0b2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -69,17 +69,18 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
 				       BIT(28),	/* lock */
 				       CLK_SET_RATE_UNGATE);
 
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
-					"osc24M", 0x0010,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video",
+					    "osc24M", 0x0010,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
 					"osc24M", 0x0018,
-- 
2.16.2

WARNING: multiple messages have this Message-ID (diff)
From: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org,
	wens-jdAy2FN1RRM@public.gmane.org,
	airlied-cv59FeDIM0c@public.gmane.org,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
	sboyd-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Cc: jernej.skrabec-gGgVlfcn5nU@public.gmane.org,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org
Subject: [PATCH v2 02/16] clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
Date: Tue, 27 Feb 2018 23:26:47 +0100	[thread overview]
Message-ID: <20180227222701.9716-3-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20180227222701.9716-1-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>

Although user manuals for H3 and H5 SoCs state that minimal rate
supported by video PLL is around 30 MHz, it seems that in reality
minimal rate is around 192 MHz.

Experiments showed that any rate below 96 MHz doesn't produce any video
output at all. Even at this frequency, stable output depends on right
factors. For example, when N = 4 and M = 1, output is stable and when N
= 8 and M = 2, it's not.

BSP clock driver suggest that minimum stable frequency is 192 MHz. That
would also be in line with A64 SoC, which has similar periphery.

Set minimal video PLL rate for H3/H5 to 192 MHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 29bc0566b776..b9f39078c0b2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -69,17 +69,18 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
 				       BIT(28),	/* lock */
 				       CLK_SET_RATE_UNGATE);
 
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
-					"osc24M", 0x0010,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video",
+					    "osc24M", 0x0010,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
 					"osc24M", 0x0018,
-- 
2.16.2

WARNING: multiple messages have this Message-ID (diff)
From: jernej.skrabec@siol.net (Jernej Skrabec)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 02/16] clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
Date: Tue, 27 Feb 2018 23:26:47 +0100	[thread overview]
Message-ID: <20180227222701.9716-3-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20180227222701.9716-1-jernej.skrabec@siol.net>

Although user manuals for H3 and H5 SoCs state that minimal rate
supported by video PLL is around 30 MHz, it seems that in reality
minimal rate is around 192 MHz.

Experiments showed that any rate below 96 MHz doesn't produce any video
output at all. Even at this frequency, stable output depends on right
factors. For example, when N = 4 and M = 1, output is stable and when N
= 8 and M = 2, it's not.

BSP clock driver suggest that minimum stable frequency is 192 MHz. That
would also be in line with A64 SoC, which has similar periphery.

Set minimal video PLL rate for H3/H5 to 192 MHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 29bc0566b776..b9f39078c0b2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -69,17 +69,18 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
 				       BIT(28),	/* lock */
 				       CLK_SET_RATE_UNGATE);
 
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
-					"osc24M", 0x0010,
-					8, 7,		/* N */
-					0, 4,		/* M */
-					BIT(24),	/* frac enable */
-					BIT(25),	/* frac select */
-					270000000,	/* frac rate 0 */
-					297000000,	/* frac rate 1 */
-					BIT(31),	/* gate */
-					BIT(28),	/* lock */
-					CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video",
+					    "osc24M", 0x0010,
+					    192000000,	/* Minimum rate */
+					    8, 7,	/* N */
+					    0, 4,	/* M */
+					    BIT(24),	/* frac enable */
+					    BIT(25),	/* frac select */
+					    270000000,	/* frac rate 0 */
+					    297000000,	/* frac rate 1 */
+					    BIT(31),	/* gate */
+					    BIT(28),	/* lock */
+					    CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
 					"osc24M", 0x0018,
-- 
2.16.2

  parent reply	other threads:[~2018-02-27 22:27 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-27 22:26 [PATCH v2 00/16] Implement H3/H5 HDMI driver Jernej Skrabec
2018-02-27 22:26 ` Jernej Skrabec
2018-02-27 22:26 ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 01/16] clk: sunxi-ng: Add check for minimal rate to NM PLLs Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-28  7:34   ` Maxime Ripard
2018-02-28  7:34     ` Maxime Ripard
2018-02-28  7:34     ` Maxime Ripard
2018-02-28 21:55     ` Jernej Škrabec
2018-02-28 21:55       ` Jernej Škrabec
2018-02-28 21:55       ` Jernej Škrabec
2018-02-27 22:26 ` Jernej Skrabec [this message]
2018-02-27 22:26   ` [PATCH v2 02/16] clk: sunxi-ng: h3: h5: Add minimal rate for video PLL Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 03/16] clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 04/16] clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 05/16] dt-bindings: display: sun4i-drm: Add compatibles for H3 HDMI pipeline Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 06/16] drm/sun4i: Don't process LVDS if TCON doesn't support it Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-28  7:36   ` Maxime Ripard
2018-02-28  7:36     ` Maxime Ripard
2018-02-28  7:36     ` Maxime Ripard
2018-02-28 21:43     ` Jernej Škrabec
2018-02-28 21:43       ` Jernej Škrabec
2018-03-02  8:12       ` Maxime Ripard
2018-03-02  8:12         ` Maxime Ripard
2018-03-02  8:12         ` Maxime Ripard
2018-02-27 22:26 ` [PATCH v2 07/16] drm/sun4i: Add support for H3 display engine Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 08/16] drm/sun4i: Add support for H3 mixer 0 Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 09/16] drm/sun4i: Fix polarity configuration for DW HDMI PHY Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 10/16] drm/sun4i: Add support for variants to " Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 11/16] drm/sun4i: Move and expand DW HDMI PHY register macros Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 12/16] drm/sun4i: Add support for H3 HDMI PHY variant Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 13/16] drm/sun4i: Allow building on arm64 Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26 ` [PATCH v2 14/16] ARM: dts: sunxi: h3/h5: Add HDMI pipeline Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:26   ` Jernej Skrabec
2018-02-27 22:27 ` [PATCH v2 15/16] ARM: dts: sun8i: h3: Enable HDMI output on H3 boards Jernej Skrabec
2018-02-27 22:27   ` Jernej Skrabec
2018-02-27 22:27   ` Jernej Skrabec
2018-02-27 22:27 ` [PATCH v2 16/16] ARM64: dts: sun50i: h5: Enable HDMI output on H5 boards Jernej Skrabec
2018-02-27 22:27   ` Jernej Skrabec
2018-02-27 22:27   ` Jernej Skrabec
2018-02-28 21:23 ` [PATCH v2 00/16] Implement H3/H5 HDMI driver Jernej Škrabec
2018-02-28 21:23   ` Jernej Škrabec
2018-02-28 21:23   ` Jernej Škrabec
2018-03-01  8:23   ` Maxime Ripard
2018-03-01  8:23     ` Maxime Ripard
2018-03-01  8:23     ` Maxime Ripard

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