* [CI 1/2] drm/i915/icl: Prepare for more rings @ 2018-02-28 10:11 Mika Kuoppala 2018-02-28 10:11 ` [CI 2/2] drm/i915/icl: Interrupt handling Mika Kuoppala ` (3 more replies) 0 siblings, 4 replies; 6+ messages in thread From: Mika Kuoppala @ 2018-02-28 10:11 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Gen11 will add more VCS and VECS rings so prepare the infrastructure to support that. Bspec: 7021 v2: Rebase. v3: Rebase. v4: Rebase. v5: Rebase. v6: - Update for POR changes. (Daniele Ceraolo Spurio) - Add provisional guc engine ids - to be checked and confirmed. v7: - Rebased. - Added the new ring masks. - Added the new HW ids. v8: - Introduce I915_MAX_VCS/VECS to avoid magic numbers (Michal) v9: increase MAX_ENGINE_INSTANCE to 3 Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Oscar Mateo <oscar.mateo@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_gem.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 5 ++++- drivers/gpu/drm/i915/intel_device_info.c | 3 +++ drivers/gpu/drm/i915/intel_device_info.h | 4 +++- drivers/gpu/drm/i915/intel_ringbuffer.h | 9 ++++++++- 6 files changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7bbec5546d12..10c9e5e619ab 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2746,6 +2746,9 @@ intel_info(const struct drm_i915_private *dev_priv) #define BLT_RING ENGINE_MASK(BCS) #define VEBOX_RING ENGINE_MASK(VECS) #define BSD2_RING ENGINE_MASK(VCS2) +#define BSD3_RING ENGINE_MASK(VCS3) +#define BSD4_RING ENGINE_MASK(VCS4) +#define VEBOX2_RING ENGINE_MASK(VECS2) #define ALL_ENGINES (~0) #define HAS_ENGINE(dev_priv, id) \ diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h index d9f0709973d1..f54c4ff74ded 100644 --- a/drivers/gpu/drm/i915/i915_gem.h +++ b/drivers/gpu/drm/i915/i915_gem.h @@ -57,6 +57,6 @@ #define GEM_TRACE(...) do { } while (0) #endif -#define I915_NUM_ENGINES 5 +#define I915_NUM_ENGINES 8 #endif /* __I915_GEM_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eea5b2c537d4..95a2e51ecbb0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -178,6 +178,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define BCS_HW 2 #define VECS_HW 3 #define VCS2_HW 4 +#define VCS3_HW 6 +#define VCS4_HW 7 +#define VECS2_HW 12 /* Engine class */ @@ -188,7 +191,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OTHER_CLASS 4 #define MAX_ENGINE_CLASS 4 -#define MAX_ENGINE_INSTANCE 1 +#define MAX_ENGINE_INSTANCE 3 /* PCI config space */ diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 1c780cc4cd48..cadc5f81ed72 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -542,6 +542,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info) info->num_scalers[PIPE_C] = 1; } + BUILD_BUG_ON(I915_NUM_ENGINES > + sizeof(intel_ring_mask_t) * BITS_PER_BYTE); + /* * Skylake and Broxton currently don't expose the topmost plane as its * use is exclusive with the legacy cursor and we only want to expose diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 8904ad87bf37..ab5bfd305477 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -125,6 +125,8 @@ struct sseu_dev_info { u8 has_eu_pg:1; }; +typedef u8 intel_ring_mask_t; + struct intel_device_info { u16 device_id; u16 gen_mask; @@ -132,7 +134,7 @@ struct intel_device_info { u8 gen; u8 gt; /* GT number, 0 if undefined */ u8 num_rings; - u8 ring_mask; /* Rings supported by the HW */ + intel_ring_mask_t ring_mask; /* Rings supported by the HW */ enum intel_platform platform; u32 platform_mask; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index bbacf4d0f4cb..90e4380cbdd5 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -160,6 +160,9 @@ struct i915_ctx_workarounds { struct i915_request; +#define I915_MAX_VCS 4 +#define I915_MAX_VECS 2 + /* * Engine IDs definitions. * Keep instances of the same type engine together. @@ -169,8 +172,12 @@ enum intel_engine_id { BCS, VCS, VCS2, + VCS3, + VCS4, #define _VCS(n) (VCS + (n)) - VECS + VECS, + VECS2 +#define _VECS(n) (VECS + (n)) }; struct i915_priolist { -- 2.14.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [CI 2/2] drm/i915/icl: Interrupt handling 2018-02-28 10:11 [CI 1/2] drm/i915/icl: Prepare for more rings Mika Kuoppala @ 2018-02-28 10:11 ` Mika Kuoppala 2018-02-28 11:33 ` ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings Patchwork ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Mika Kuoppala @ 2018-02-28 10:11 UTC (permalink / raw) To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi v2: Rebase. v3: * Remove DPF, it has been removed from SKL+. * Fix -internal rebase wrt. execlists interrupt handling. v4: Rebase. v5: * Updated for POR changes. (Daniele Ceraolo Spurio) * Merged with irq handling fixes by Daniele Ceraolo Spurio: * Simplify the code by using gen8_cs_irq_handler. * Fix interrupt handling for the upstream kernel. v6: * Remove early bringup debug messages (Tvrtko) * Add NB about arbitrary spin wait timeout (Tvrtko) v7 (from Paulo): * Don't try to write RO bits to registers. * Don't check for PCH types that don't exist. PCH interrupts are not here yet. v9: * squashed in selector and shared register handling (Daniele) * skip writing of irq if data is not valid (Daniele) * use time_after32 (Chris) * use I915_MAX_VCS and I915_MAX_VECS (Daniele) * remove fake pm interrupt handling for later patch (Mika) v10: * Direct processing of banks. clear banks early (Chris) * remove poll on valid bit, only clear valid bit (Mika) * use raw accessors, better naming (Chris) v11: * adapt to raw_reg_[read|write] * bring back polling the valid bit (Daniele) v12: * continue if unset intr_dw (Daniele) * comment the usage of gen8_de_irq_handler bits (Daniele) Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 235 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_pm.c | 7 +- 2 files changed, 241 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 0a7ed990a8d1..ce16003ef048 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) if (READ_ONCE(rps->interrupts_enabled)) return; + if (WARN_ON_ONCE(IS_GEN11(dev_priv))) + return; + spin_lock_irq(&dev_priv->irq_lock); WARN_ON_ONCE(rps->pm_iir); WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) if (!READ_ONCE(rps->interrupts_enabled)) return; + if (WARN_ON_ONCE(IS_GEN11(dev_priv))) + return; + spin_lock_irq(&dev_priv->irq_lock); rps->interrupts_enabled = false; @@ -2755,6 +2761,156 @@ static void __fini_wedge(struct wedge_me *w) (W)->i915; \ __fini_wedge((W))) +static __always_inline void +gen11_cs_irq_handler(struct intel_engine_cs * const engine, const u32 iir) +{ + gen8_cs_irq_handler(engine, iir, 0); +} + +static void +gen11_gt_engine_irq_handler(struct drm_i915_private * const i915, + const unsigned int bank, + const unsigned int engine_n, + const u16 iir) +{ + struct intel_engine_cs ** const engine = i915->engine; + + switch (bank) { + case 0: + switch (engine_n) { + + case GEN11_RCS0: + return gen11_cs_irq_handler(engine[RCS], iir); + + case GEN11_BCS: + return gen11_cs_irq_handler(engine[BCS], iir); + } + case 1: + switch (engine_n) { + + case GEN11_VCS(0): + return gen11_cs_irq_handler(engine[_VCS(0)], iir); + case GEN11_VCS(1): + return gen11_cs_irq_handler(engine[_VCS(1)], iir); + case GEN11_VCS(2): + return gen11_cs_irq_handler(engine[_VCS(2)], iir); + case GEN11_VCS(3): + return gen11_cs_irq_handler(engine[_VCS(3)], iir); + + case GEN11_VECS(0): + return gen11_cs_irq_handler(engine[_VECS(0)], iir); + case GEN11_VECS(1): + return gen11_cs_irq_handler(engine[_VECS(1)], iir); + } + } +} + +static u32 +gen11_gt_engine_intr(struct drm_i915_private * const i915, + const unsigned int bank, const unsigned int bit) +{ + void __iomem * const regs = i915->regs; + u32 timeout_ts; + u32 ident; + + raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); + + /* + * NB: Specs do not specify how long to spin wait, + * so we do ~100us as an educated guess. + */ + timeout_ts = (local_clock() >> 10) + 100; + do { + ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank)); + } while (!(ident & GEN11_INTR_DATA_VALID) && + !time_after32(local_clock() >> 10, timeout_ts)); + + if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) { + DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n", + bank, bit, ident); + return 0; + } + + raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank), + GEN11_INTR_DATA_VALID); + + return ident & GEN11_INTR_ENGINE_MASK; +} + +static void +gen11_gt_irq_handler(struct drm_i915_private * const i915, + const u32 master_ctl) +{ + void __iomem * const regs = i915->regs; + unsigned int bank; + + for (bank = 0; bank < 2; bank++) { + unsigned long intr_dw; + unsigned int bit; + + if (!(master_ctl & GEN11_GT_DW_IRQ(bank))) + continue; + + intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); + + if (unlikely(!intr_dw)) { + DRM_ERROR("GT_INTR_DW%u blank!\n", bank); + continue; + } + + for_each_set_bit(bit, &intr_dw, 32) { + const u16 iir = gen11_gt_engine_intr(i915, bank, bit); + + if (unlikely(!iir)) + continue; + + gen11_gt_engine_irq_handler(i915, bank, bit, iir); + } + + /* Clear must be after shared has been served for engine */ + raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw); + } +} + +static irqreturn_t gen11_irq_handler(int irq, void *arg) +{ + struct drm_i915_private * const i915 = to_i915(arg); + void __iomem * const regs = i915->regs; + u32 master_ctl; + + if (!intel_irqs_enabled(i915)) + return IRQ_NONE; + + master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); + master_ctl &= ~GEN11_MASTER_IRQ; + if (!master_ctl) + return IRQ_NONE; + + /* Disable interrupts. */ + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); + + /* Find, clear, then process each source of interrupt. */ + gen11_gt_irq_handler(i915, master_ctl); + + /* IRQs are synced during runtime_suspend, we don't require a wakeref */ + if (master_ctl & GEN11_DISPLAY_IRQ) { + const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); + + disable_rpm_wakeref_asserts(i915); + /* + * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ + * for the display related bits. + */ + gen8_de_irq_handler(i915, disp_ctl); + enable_rpm_wakeref_asserts(i915); + } + + /* Acknowledge and enable interrupts. */ + raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl); + + return IRQ_HANDLED; +} + /** * i915_reset_device - do process context error handling work * @dev_priv: i915 device private @@ -3180,6 +3336,42 @@ static void gen8_irq_reset(struct drm_device *dev) ibx_irq_reset(dev_priv); } +static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) +{ + /* Disable RCS, BCS, VCS and VECS class engines. */ + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0); + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0); + + /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0); + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0); + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0); + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0); + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0); +} + +static void gen11_irq_reset(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int pipe; + + I915_WRITE(GEN11_GFX_MSTR_IRQ, 0); + POSTING_READ(GEN11_GFX_MSTR_IRQ); + + gen11_gt_irq_reset(dev_priv); + + I915_WRITE(GEN11_DISPLAY_INT_CTL, 0); + + for_each_pipe(dev_priv, pipe) + if (intel_display_power_is_enabled(dev_priv, + POWER_DOMAIN_PIPE(pipe))) + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); + + GEN3_IRQ_RESET(GEN8_DE_PORT_); + GEN3_IRQ_RESET(GEN8_DE_MISC_); + GEN3_IRQ_RESET(GEN8_PCU_); +} + void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u8 pipe_mask) { @@ -3677,6 +3869,41 @@ static int gen8_irq_postinstall(struct drm_device *dev) return 0; } +static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv) +{ + const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT; + + BUILD_BUG_ON(irqs & 0xffff0000); + + /* Enable RCS, BCS, VCS and VECS class interrupts. */ + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs); + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs); + + /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16)); + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16)); + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16)); + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16)); + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16)); + + dev_priv->pm_imr = 0xffffffff; /* TODO */ +} + +static int gen11_irq_postinstall(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + gen11_gt_irq_postinstall(dev_priv); + gen8_de_irq_postinstall(dev_priv); + + I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); + + I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); + POSTING_READ(GEN11_GFX_MSTR_IRQ); + + return 0; +} + static int cherryview_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); @@ -4125,6 +4352,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->enable_vblank = i965_enable_vblank; dev->driver->disable_vblank = i965_disable_vblank; dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; + } else if (INTEL_GEN(dev_priv) >= 11) { + dev->driver->irq_handler = gen11_irq_handler; + dev->driver->irq_preinstall = gen11_irq_reset; + dev->driver->irq_postinstall = gen11_irq_postinstall; + dev->driver->irq_uninstall = gen11_irq_reset; + dev->driver->enable_vblank = gen8_enable_vblank; + dev->driver->disable_vblank = gen8_disable_vblank; + dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; } else if (INTEL_GEN(dev_priv) >= 8) { dev->driver->irq_handler = gen8_irq_handler; dev->driver->irq_preinstall = gen8_irq_reset; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3c1499687d13..3e60279f18b1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8026,7 +8026,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */ intel_disable_gt_powersave(dev_priv); - gen6_reset_rps_interrupts(dev_priv); + if (INTEL_GEN(dev_priv) < 11) + gen6_reset_rps_interrupts(dev_priv); + else + WARN_ON_ONCE(1); } static inline void intel_disable_llc_pstate(struct drm_i915_private *i915) @@ -8139,6 +8142,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv) cherryview_enable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { valleyview_enable_rps(dev_priv); + } else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) { + /* TODO */ } else if (INTEL_GEN(dev_priv) >= 9) { gen9_enable_rps(dev_priv); } else if (IS_BROADWELL(dev_priv)) { -- 2.14.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings 2018-02-28 10:11 [CI 1/2] drm/i915/icl: Prepare for more rings Mika Kuoppala 2018-02-28 10:11 ` [CI 2/2] drm/i915/icl: Interrupt handling Mika Kuoppala @ 2018-02-28 11:33 ` Patchwork 2018-02-28 13:02 ` Mika Kuoppala 2018-03-01 10:40 ` ✓ Fi.CI.BAT: success " Patchwork 2018-03-01 14:50 ` ✗ Fi.CI.IGT: warning " Patchwork 3 siblings, 1 reply; 6+ messages in thread From: Patchwork @ 2018-02-28 11:33 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx == Series Details == Series: series starting with [CI,1/2] drm/i915/icl: Prepare for more rings URL : https://patchwork.freedesktop.org/series/39102/ State : warning == Summary == Series 39102v1 series starting with [CI,1/2] drm/i915/icl: Prepare for more rings https://patchwork.freedesktop.org/api/1.0/series/39102/revisions/1/mbox/ ---- Possible new issues: Test drv_module_reload: Subgroup basic-no-display: pass -> DMESG-WARN (fi-cfl-8700k) ---- Known issues: Test debugfs_test: Subgroup read_all_entries: pass -> INCOMPLETE (fi-snb-2520m) fdo#103713 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:416s fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:421s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:372s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:480s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:283s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:482s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:479s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:463s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:455s fi-cfl-8700k total:288 pass:259 dwarn:1 dfail:0 fail:0 skip:28 time:392s fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:561s fi-cnl-y3 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:583s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:413s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:284s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:509s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:387s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:414s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:458s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:411s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:449s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:484s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:443s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:493s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:581s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:435s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:506s fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:519s fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:485s fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:406s fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0 fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:389s 9a02ae14ae024bdbb268333cddccbaf01d8f02ef drm-tip: 2018y-02m-28d-10h-13m-18s UTC integration manifest a4fe8c3a60ee drm/i915/icl: Interrupt handling a28809c1ee8d drm/i915/icl: Prepare for more rings == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8185/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings 2018-02-28 11:33 ` ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings Patchwork @ 2018-02-28 13:02 ` Mika Kuoppala 0 siblings, 0 replies; 6+ messages in thread From: Mika Kuoppala @ 2018-02-28 13:02 UTC (permalink / raw) To: Patchwork; +Cc: intel-gfx Patchwork <patchwork@emeril.freedesktop.org> writes: > == Series Details == > > Series: series starting with [CI,1/2] drm/i915/icl: Prepare for more rings > URL : https://patchwork.freedesktop.org/series/39102/ > State : warning > > == Summary == > > Series 39102v1 series starting with [CI,1/2] drm/i915/icl: Prepare for more rings > https://patchwork.freedesktop.org/api/1.0/series/39102/revisions/1/mbox/ > > ---- Possible new issues: > > Test drv_module_reload: > Subgroup basic-no-display: > pass -> DMESG-WARN (fi-cfl-8700k) https://bugs.freedesktop.org/show_bug.cgi?id=91883 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings 2018-02-28 10:11 [CI 1/2] drm/i915/icl: Prepare for more rings Mika Kuoppala 2018-02-28 10:11 ` [CI 2/2] drm/i915/icl: Interrupt handling Mika Kuoppala 2018-02-28 11:33 ` ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings Patchwork @ 2018-03-01 10:40 ` Patchwork 2018-03-01 14:50 ` ✗ Fi.CI.IGT: warning " Patchwork 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-03-01 10:40 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx == Series Details == Series: series starting with [CI,1/2] drm/i915/icl: Prepare for more rings URL : https://patchwork.freedesktop.org/series/39102/ State : success == Summary == Series 39102v1 series starting with [CI,1/2] drm/i915/icl: Prepare for more rings https://patchwork.freedesktop.org/api/1.0/series/39102/revisions/1/mbox/ ---- Known issues: Test debugfs_test: Subgroup read_all_entries: incomplete -> PASS (fi-snb-2520m) fdo#103713 Test prime_vgem: Subgroup basic-fence-flip: fail -> PASS (fi-ilk-650) fdo#104008 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:417s fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:423s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:372s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:488s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:278s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:476s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:477s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:465s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:452s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:397s fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:564s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:413s fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:291s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:507s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:385s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:412s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:446s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:410s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:453s fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:488s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:447s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:497s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:581s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:420s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:501s fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:516s fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:491s fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:469s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:406s fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:426s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:521s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:390s 4f93bc69c016e696a7ea97c6f894d9bab8a905d8 drm-tip: 2018y-03m-01d-09h-30m-35s UTC integration manifest 7c05e1f55596 drm/i915/icl: Interrupt handling 9fb6e26f81ee drm/i915/icl: Prepare for more rings == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8194/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.IGT: warning for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings 2018-02-28 10:11 [CI 1/2] drm/i915/icl: Prepare for more rings Mika Kuoppala ` (2 preceding siblings ...) 2018-03-01 10:40 ` ✓ Fi.CI.BAT: success " Patchwork @ 2018-03-01 14:50 ` Patchwork 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-03-01 14:50 UTC (permalink / raw) To: Mika Kuoppala; +Cc: intel-gfx == Series Details == Series: series starting with [CI,1/2] drm/i915/icl: Prepare for more rings URL : https://patchwork.freedesktop.org/series/39102/ State : warning == Summary == ---- Possible new issues: Test kms_frontbuffer_tracking: Subgroup fbc-2p-primscrn-shrfb-pgflip-blt: pass -> SKIP (shard-hsw) ---- Known issues: Test gem_eio: Subgroup in-flight-contexts: incomplete -> PASS (shard-apl) fdo#104945 Test kms_chv_cursor_fail: Subgroup pipe-b-256x256-left-edge: pass -> DMESG-WARN (shard-snb) fdo#105185 +2 Test kms_cursor_crc: Subgroup cursor-64x64-suspend: pass -> INCOMPLETE (shard-hsw) fdo#103540 Test kms_flip: Subgroup 2x-flip-vs-expired-vblank: pass -> FAIL (shard-hsw) fdo#102887 Subgroup 2x-modeset-vs-vblank-race-interruptible: pass -> FAIL (shard-hsw) fdo#103060 Subgroup 2x-wf_vblank-ts-check: pass -> FAIL (shard-hsw) fdo#100368 +1 Test kms_frontbuffer_tracking: Subgroup fbc-1p-primscrn-pri-shrfb-draw-pwrite: pass -> DMESG-FAIL (shard-apl) fdo#101623 Subgroup fbc-1p-primscrn-spr-indfb-draw-render: pass -> FAIL (shard-apl) fdo#103167 +1 Test perf: Subgroup oa-exponents: pass -> INCOMPLETE (shard-apl) fdo#102254 fdo#104945 https://bugs.freedesktop.org/show_bug.cgi?id=104945 fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254 shard-apl total:3447 pass:1809 dwarn:1 dfail:1 fail:9 skip:1626 time:11959s shard-hsw total:3382 pass:1723 dwarn:1 dfail:0 fail:5 skip:1651 time:11205s shard-snb total:3460 pass:1357 dwarn:3 dfail:0 fail:1 skip:2099 time:6674s Blacklisted hosts: shard-kbl total:3383 pass:1906 dwarn:1 dfail:0 fail:7 skip:1467 time:8941s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8194/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-03-01 14:50 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-02-28 10:11 [CI 1/2] drm/i915/icl: Prepare for more rings Mika Kuoppala 2018-02-28 10:11 ` [CI 2/2] drm/i915/icl: Interrupt handling Mika Kuoppala 2018-02-28 11:33 ` ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings Patchwork 2018-02-28 13:02 ` Mika Kuoppala 2018-03-01 10:40 ` ✓ Fi.CI.BAT: success " Patchwork 2018-03-01 14:50 ` ✗ Fi.CI.IGT: warning " Patchwork
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.