* [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers
@ 2018-03-02 9:56 Ville Syrjala
2018-03-02 11:22 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ville Syrjala @ 2018-03-02 9:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
AFAIK CHV was supposed to have HBR2 originally, but in the end the feature
was dropped. We still have some code leftovers from those early days.
Eliminate them.
The extra bit for the training pattern seems to be dead in the hardware.
I can set it (in fact I can set almost any reserved bit in the
registers) but it doesn't seem to interfere with the operation of the
hardware. Either that or I'm very lucky that my displays complete link
training with the incorrect pattern being sent out.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 --
drivers/gpu/drm/i915/intel_dp.c | 20 ++++----------------
2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 95a2e51ecbb0..f3efc242df2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5250,8 +5250,6 @@ enum {
#define DP_LINK_TRAIN_OFF (3 << 28)
#define DP_LINK_TRAIN_MASK (3 << 28)
#define DP_LINK_TRAIN_SHIFT 28
-#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
-#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
/* CPT Link training mode */
#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index aba2f45819d8..df1772044208 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -92,8 +92,6 @@ static const struct dp_link_dpll chv_dpll[] = {
{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
{ 270000, /* m2_int = 27, m2_fraction = 0 */
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
- { 540000, /* m2_int = 27, m2_fraction = 0 */
- { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};
/**
@@ -2908,10 +2906,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
}
} else {
- if (IS_CHERRYVIEW(dev_priv))
- *DP &= ~DP_LINK_TRAIN_MASK_CHV;
- else
- *DP &= ~DP_LINK_TRAIN_MASK;
+ *DP &= ~DP_LINK_TRAIN_MASK;
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
case DP_TRAINING_PATTERN_DISABLE:
@@ -2924,12 +2919,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
*DP |= DP_LINK_TRAIN_PAT_2;
break;
case DP_TRAINING_PATTERN_3:
- if (IS_CHERRYVIEW(dev_priv)) {
- *DP |= DP_LINK_TRAIN_PAT_3_CHV;
- } else {
- DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
- *DP |= DP_LINK_TRAIN_PAT_2;
- }
+ DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
+ *DP |= DP_LINK_TRAIN_PAT_2;
break;
}
}
@@ -3668,10 +3659,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
DP &= ~DP_LINK_TRAIN_MASK_CPT;
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
} else {
- if (IS_CHERRYVIEW(dev_priv))
- DP &= ~DP_LINK_TRAIN_MASK_CHV;
- else
- DP &= ~DP_LINK_TRAIN_MASK;
+ DP &= ~DP_LINK_TRAIN_MASK;
DP |= DP_LINK_TRAIN_PAT_IDLE;
}
I915_WRITE(intel_dp->output_reg, DP);
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Kill the remaining CHV HBR2 leftovers
2018-03-02 9:56 [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers Ville Syrjala
@ 2018-03-02 11:22 ` Patchwork
2018-03-02 13:22 ` ✓ Fi.CI.IGT: " Patchwork
2018-03-07 21:41 ` [PATCH] " Pandiyan, Dhinakaran
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-03-02 11:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Kill the remaining CHV HBR2 leftovers
URL : https://patchwork.freedesktop.org/series/39260/
State : success
== Summary ==
Series 39260v1 drm/i915: Kill the remaining CHV HBR2 leftovers
https://patchwork.freedesktop.org/api/1.0/series/39260/revisions/1/mbox/
---- Known issues:
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test prime_vgem:
Subgroup basic-fence-flip:
fail -> PASS (fi-byt-n2820) fdo#104008
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:414s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:423s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:370s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:481s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:277s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:480s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:462s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:453s
fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:393s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:567s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:415s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:289s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:506s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:384s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:413s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:443s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:413s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:450s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:489s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:452s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:494s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:581s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:423s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:499s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:516s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:489s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:466s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:406s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:429s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:519s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:386s
Blacklisted hosts:
fi-cfl-u total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:490s
fi-bxt-dsi failed to collect. IGT log at Patchwork_8208/fi-bxt-dsi/run0.log
b2e10fd5e8b2cd72b0e1eba46c1221dc3d4b70bc drm-tip: 2018y-03m-02d-09h-36m-59s UTC integration manifest
bd80036a0d46 drm/i915: Kill the remaining CHV HBR2 leftovers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8208/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Kill the remaining CHV HBR2 leftovers
2018-03-02 9:56 [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers Ville Syrjala
2018-03-02 11:22 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-03-02 13:22 ` Patchwork
2018-03-07 21:41 ` [PATCH] " Pandiyan, Dhinakaran
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-03-02 13:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Kill the remaining CHV HBR2 leftovers
URL : https://patchwork.freedesktop.org/series/39260/
State : success
== Summary ==
---- Possible new issues:
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
skip -> PASS (shard-snb)
---- Known issues:
Test kms_chv_cursor_fail:
Subgroup pipe-b-128x128-right-edge:
pass -> DMESG-WARN (shard-snb) fdo#105185 +4
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
pass -> DMESG-WARN (shard-snb) fdo#102365
Test kms_sysfs_edid_timing:
warn -> PASS (shard-apl) fdo#100047
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
shard-apl total:3442 pass:1810 dwarn:1 dfail:0 fail:7 skip:1623 time:12114s
shard-hsw total:3366 pass:1727 dwarn:1 dfail:0 fail:1 skip:1636 time:11477s
shard-snb total:3463 pass:1358 dwarn:5 dfail:0 fail:1 skip:2099 time:7024s
Blacklisted hosts:
shard-kbl total:3445 pass:1927 dwarn:1 dfail:0 fail:7 skip:1509 time:9675s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8208/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers
2018-03-02 9:56 [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers Ville Syrjala
2018-03-02 11:22 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-03-02 13:22 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-03-07 21:41 ` Pandiyan, Dhinakaran
2018-03-08 12:58 ` Ville Syrjälä
2 siblings, 1 reply; 6+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-03-07 21:41 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Fri, 2018-03-02 at 11:56 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> AFAIK CHV was supposed to have HBR2 originally, but in the end the feature
> was dropped. We still have some code leftovers from those early days.
> Eliminate them.
>
Not much in the spec about HBR2 other than the support for TP3. Since we
don't support HBR2 on CHV, removing the unused TPS3 bits looks correct.
> The extra bit for the training pattern seems to be dead in the hardware.
> I can set it (in fact I can set almost any reserved bit in the
> registers) but it doesn't seem to interfere with the operation of the
> hardware. Either that or I'm very lucky that my displays complete link
> training with the incorrect pattern being sent out.
>
I don't think I follow this, are you saying there's no need to clear the
TPS3 bit? Isn't it better to have the mask include 1 << 14, so that
_intel_dp_set_link_train() clears the bit?
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 --
> drivers/gpu/drm/i915/intel_dp.c | 20 ++++----------------
> 2 files changed, 4 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 95a2e51ecbb0..f3efc242df2d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5250,8 +5250,6 @@ enum {
> #define DP_LINK_TRAIN_OFF (3 << 28)
> #define DP_LINK_TRAIN_MASK (3 << 28)
> #define DP_LINK_TRAIN_SHIFT 28
> -#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
> -#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
>
> /* CPT Link training mode */
> #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index aba2f45819d8..df1772044208 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -92,8 +92,6 @@ static const struct dp_link_dpll chv_dpll[] = {
> { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
> { 270000, /* m2_int = 27, m2_fraction = 0 */
> { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
> - { 540000, /* m2_int = 27, m2_fraction = 0 */
> - { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> };
>
> /**
> @@ -2908,10 +2906,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> }
>
> } else {
> - if (IS_CHERRYVIEW(dev_priv))
> - *DP &= ~DP_LINK_TRAIN_MASK_CHV;
> - else
> - *DP &= ~DP_LINK_TRAIN_MASK;
> + *DP &= ~DP_LINK_TRAIN_MASK;
>
> switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> case DP_TRAINING_PATTERN_DISABLE:
> @@ -2924,12 +2919,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> *DP |= DP_LINK_TRAIN_PAT_2;
> break;
> case DP_TRAINING_PATTERN_3:
> - if (IS_CHERRYVIEW(dev_priv)) {
> - *DP |= DP_LINK_TRAIN_PAT_3_CHV;
> - } else {
> - DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
> - *DP |= DP_LINK_TRAIN_PAT_2;
> - }
> + DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
> + *DP |= DP_LINK_TRAIN_PAT_2;
> break;
> }
> }
> @@ -3668,10 +3659,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> DP &= ~DP_LINK_TRAIN_MASK_CPT;
> DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> } else {
> - if (IS_CHERRYVIEW(dev_priv))
> - DP &= ~DP_LINK_TRAIN_MASK_CHV;
> - else
> - DP &= ~DP_LINK_TRAIN_MASK;
> + DP &= ~DP_LINK_TRAIN_MASK;
> DP |= DP_LINK_TRAIN_PAT_IDLE;
> }
> I915_WRITE(intel_dp->output_reg, DP);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers
2018-03-07 21:41 ` [PATCH] " Pandiyan, Dhinakaran
@ 2018-03-08 12:58 ` Ville Syrjälä
2018-03-08 17:35 ` Pandiyan, Dhinakaran
0 siblings, 1 reply; 6+ messages in thread
From: Ville Syrjälä @ 2018-03-08 12:58 UTC (permalink / raw)
To: Pandiyan, Dhinakaran; +Cc: intel-gfx
On Wed, Mar 07, 2018 at 09:41:06PM +0000, Pandiyan, Dhinakaran wrote:
>
>
>
> On Fri, 2018-03-02 at 11:56 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > AFAIK CHV was supposed to have HBR2 originally, but in the end the feature
> > was dropped. We still have some code leftovers from those early days.
> > Eliminate them.
> >
>
> Not much in the spec about HBR2 other than the support for TP3. Since we
> don't support HBR2 on CHV, removing the unused TPS3 bits looks correct.
>
>
>
> > The extra bit for the training pattern seems to be dead in the hardware.
> > I can set it (in fact I can set almost any reserved bit in the
> > registers) but it doesn't seem to interfere with the operation of the
> > hardware. Either that or I'm very lucky that my displays complete link
> > training with the incorrect pattern being sent out.
> >
>
> I don't think I follow this, are you saying there's no need to clear the
> TPS3 bit? Isn't it better to have the mask include 1 << 14, so that
> _intel_dp_set_link_train() clears the bit?
I'm saying the bit doesn't actually seem to exist in hardware. In fact
most of my specs don't list it either. Looks like only the "K0" specs
have it.
>
>
>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 --
> > drivers/gpu/drm/i915/intel_dp.c | 20 ++++----------------
> > 2 files changed, 4 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 95a2e51ecbb0..f3efc242df2d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5250,8 +5250,6 @@ enum {
> > #define DP_LINK_TRAIN_OFF (3 << 28)
> > #define DP_LINK_TRAIN_MASK (3 << 28)
> > #define DP_LINK_TRAIN_SHIFT 28
> > -#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
> > -#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
> >
> > /* CPT Link training mode */
> > #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index aba2f45819d8..df1772044208 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -92,8 +92,6 @@ static const struct dp_link_dpll chv_dpll[] = {
> > { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
> > { 270000, /* m2_int = 27, m2_fraction = 0 */
> > { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
> > - { 540000, /* m2_int = 27, m2_fraction = 0 */
> > - { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> > };
> >
> > /**
> > @@ -2908,10 +2906,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> > }
> >
> > } else {
> > - if (IS_CHERRYVIEW(dev_priv))
> > - *DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > - else
> > - *DP &= ~DP_LINK_TRAIN_MASK;
> > + *DP &= ~DP_LINK_TRAIN_MASK;
> >
> > switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> > case DP_TRAINING_PATTERN_DISABLE:
> > @@ -2924,12 +2919,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> > *DP |= DP_LINK_TRAIN_PAT_2;
> > break;
> > case DP_TRAINING_PATTERN_3:
> > - if (IS_CHERRYVIEW(dev_priv)) {
> > - *DP |= DP_LINK_TRAIN_PAT_3_CHV;
> > - } else {
> > - DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
> > - *DP |= DP_LINK_TRAIN_PAT_2;
> > - }
> > + DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
> > + *DP |= DP_LINK_TRAIN_PAT_2;
> > break;
> > }
> > }
> > @@ -3668,10 +3659,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> > DP &= ~DP_LINK_TRAIN_MASK_CPT;
> > DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> > } else {
> > - if (IS_CHERRYVIEW(dev_priv))
> > - DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > - else
> > - DP &= ~DP_LINK_TRAIN_MASK;
> > + DP &= ~DP_LINK_TRAIN_MASK;
> > DP |= DP_LINK_TRAIN_PAT_IDLE;
> > }
> > I915_WRITE(intel_dp->output_reg, DP);
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers
2018-03-08 12:58 ` Ville Syrjälä
@ 2018-03-08 17:35 ` Pandiyan, Dhinakaran
0 siblings, 0 replies; 6+ messages in thread
From: Pandiyan, Dhinakaran @ 2018-03-08 17:35 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Thu, 2018-03-08 at 14:58 +0200, Ville Syrjälä wrote:
> On Wed, Mar 07, 2018 at 09:41:06PM +0000, Pandiyan, Dhinakaran wrote:
> >
> >
> >
> > On Fri, 2018-03-02 at 11:56 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > AFAIK CHV was supposed to have HBR2 originally, but in the end the feature
> > > was dropped. We still have some code leftovers from those early days.
> > > Eliminate them.
> > >
> >
> > Not much in the spec about HBR2 other than the support for TP3. Since we
> > don't support HBR2 on CHV, removing the unused TPS3 bits looks correct.
> >
> >
> >
> > > The extra bit for the training pattern seems to be dead in the hardware.
> > > I can set it (in fact I can set almost any reserved bit in the
> > > registers) but it doesn't seem to interfere with the operation of the
> > > hardware. Either that or I'm very lucky that my displays complete link
> > > training with the incorrect pattern being sent out.
> > >
> >
> > I don't think I follow this, are you saying there's no need to clear the
> > TPS3 bit? Isn't it better to have the mask include 1 << 14, so that
> > _intel_dp_set_link_train() clears the bit?
>
> I'm saying the bit doesn't actually seem to exist in hardware. In fact
> most of my specs don't list it either. Looks like only the "K0" specs
> have it.
>
Thanks for clarifying.
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> >
> >
> >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 2 --
> > > drivers/gpu/drm/i915/intel_dp.c | 20 ++++----------------
> > > 2 files changed, 4 insertions(+), 18 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 95a2e51ecbb0..f3efc242df2d 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -5250,8 +5250,6 @@ enum {
> > > #define DP_LINK_TRAIN_OFF (3 << 28)
> > > #define DP_LINK_TRAIN_MASK (3 << 28)
> > > #define DP_LINK_TRAIN_SHIFT 28
> > > -#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
> > > -#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
> > >
> > > /* CPT Link training mode */
> > > #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index aba2f45819d8..df1772044208 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -92,8 +92,6 @@ static const struct dp_link_dpll chv_dpll[] = {
> > > { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
> > > { 270000, /* m2_int = 27, m2_fraction = 0 */
> > > { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
> > > - { 540000, /* m2_int = 27, m2_fraction = 0 */
> > > - { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> > > };
> > >
> > > /**
> > > @@ -2908,10 +2906,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> > > }
> > >
> > > } else {
> > > - if (IS_CHERRYVIEW(dev_priv))
> > > - *DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > - else
> > > - *DP &= ~DP_LINK_TRAIN_MASK;
> > > + *DP &= ~DP_LINK_TRAIN_MASK;
> > >
> > > switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> > > case DP_TRAINING_PATTERN_DISABLE:
> > > @@ -2924,12 +2919,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> > > *DP |= DP_LINK_TRAIN_PAT_2;
> > > break;
> > > case DP_TRAINING_PATTERN_3:
> > > - if (IS_CHERRYVIEW(dev_priv)) {
> > > - *DP |= DP_LINK_TRAIN_PAT_3_CHV;
> > > - } else {
> > > - DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
> > > - *DP |= DP_LINK_TRAIN_PAT_2;
> > > - }
> > > + DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
> > > + *DP |= DP_LINK_TRAIN_PAT_2;
> > > break;
> > > }
> > > }
> > > @@ -3668,10 +3659,7 @@ intel_dp_link_down(struct intel_encoder *encoder,
> > > DP &= ~DP_LINK_TRAIN_MASK_CPT;
> > > DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> > > } else {
> > > - if (IS_CHERRYVIEW(dev_priv))
> > > - DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > - else
> > > - DP &= ~DP_LINK_TRAIN_MASK;
> > > + DP &= ~DP_LINK_TRAIN_MASK;
> > > DP |= DP_LINK_TRAIN_PAT_IDLE;
> > > }
> > > I915_WRITE(intel_dp->output_reg, DP);
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-03-08 17:35 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-02 9:56 [PATCH] drm/i915: Kill the remaining CHV HBR2 leftovers Ville Syrjala
2018-03-02 11:22 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-03-02 13:22 ` ✓ Fi.CI.IGT: " Patchwork
2018-03-07 21:41 ` [PATCH] " Pandiyan, Dhinakaran
2018-03-08 12:58 ` Ville Syrjälä
2018-03-08 17:35 ` Pandiyan, Dhinakaran
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