* [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64
@ 2018-03-06 12:08 Sandipan Das
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 1/3] ppc64.risu: Add missing byte and dword loads Sandipan Das
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Sandipan Das @ 2018-03-06 12:08 UTC (permalink / raw)
To: peter.maydell, joserz; +Cc: nikunj, naveen.n.rao, qemu-devel
The first patch adds the patterns for the missing byte and
doubleword load instructions. The second patch fixes mismatches
encountered when using the load quadword instruction. The last
patch fixes a minor typo in the floating-point register prefix
shown when dumping the register values.
Changelog:
v2 -> Added a cover letter as requested by Peter.
Sandipan Das (3):
ppc64.risu: Add missing byte and dword loads
ppc64.risu: Fix pattern for load qword
risu_reginfo_ppc64.c: Fix register name prefix
ppc64.risu | 29 +++++++++++++++++++++++++++--
risu_reginfo_ppc64.c | 4 ++--
2 files changed, 29 insertions(+), 4 deletions(-)
--
2.14.3
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH risu v2 1/3] ppc64.risu: Add missing byte and dword loads
2018-03-06 12:08 [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64 Sandipan Das
@ 2018-03-06 12:08 ` Sandipan Das
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 2/3] ppc64.risu: Fix pattern for load qword Sandipan Das
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Sandipan Das @ 2018-03-06 12:08 UTC (permalink / raw)
To: peter.maydell, joserz; +Cc: nikunj, naveen.n.rao, qemu-devel
The patterns for the following instructions are added:
* Load Byte and Zero (lbz)
* Load Byte and Zero with Update (lbzu)
* Load Byte and Zero Indexed (lbzx)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Doubleword (ld)
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---
ppc64.risu | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/ppc64.risu b/ppc64.risu
index e2fd4f6..13b95ac 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -887,6 +887,31 @@ FTSQRT PPC64LE 111111 bf:3 0000000 frb:5 00101000000
ISEL PPC64LE 011111 rt:5 ra:5 rb:5 bc:5 011110 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
+# format:D book:I page:48 v:P1 lbz Load Byte & Zero
+LBZ PPC64LE 100010 rt:5 ra:5 imm:16 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 32752; } \
+!memory { reg_plus_imm($ra, $imm); }
+
+# format:D book:I page:48 v:P1 lbzu Load Byte & Zero with Update
+LBZU PPC64LE 100011 rt:5 ra:5 imm:16 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 32752; } \
+!memory { reg_plus_imm($ra, $imm); }
+
+# format:X book:I page:49 v:P1 lbzux Load Byte & Zero with Update Indexed
+LBZUX PPC64LE 011111 rt:5 ra:5 rb:5 00011101110 \
+!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
+!memory { reg_plus_reg($ra, $rb); }
+
+# format:X book:I page:49 v:P1 lbzx Load Byte & Zero Indexed
+LBZX PPC64LE 011111 rt:5 ra:5 rb:5 00010101110 \
+!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
+!memory { reg_plus_reg($ra, $rb); }
+
+# format:DS book:I page:53 PPC ld Load Dword
+LD PPC64LE 111010 rt:5 ra:5 imm:14 00 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 8176; } \
+!memory { reg_plus_imm($ra, $imm << 2); }
+
# format:X book:I page:62 v2.06 ldbrx Load Dword Byte-Reverse Indexed
LDBRX PPC64LE 011111 rt:5 ra:5 rb:5 10000101000 \
!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
--
2.14.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH risu v2 2/3] ppc64.risu: Fix pattern for load qword
2018-03-06 12:08 [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64 Sandipan Das
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 1/3] ppc64.risu: Add missing byte and dword loads Sandipan Das
@ 2018-03-06 12:08 ` Sandipan Das
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 3/3] risu_reginfo_ppc64.c: Fix register name prefix Sandipan Das
2018-03-06 13:05 ` [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64 Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Sandipan Das @ 2018-03-06 12:08 UTC (permalink / raw)
To: peter.maydell, joserz; +Cc: nikunj, naveen.n.rao, qemu-devel
The pattern for the Load Quadword (lq) instruction is fixed.
If rtp is 0 or 12, the instruction will overwrite r0, r1 or
r12, r13 respectively. However, r1 is the stack frame pointer
and r13 is the thread pointer. So, overwriting them can cause
a crash. This is avoided by putting a constraint to prevent
rtp from being 0 or 12.
For a given effective address (ea), this instruction loads
two dwords from ea and ea+8. However, if ea is the start
address of the current stack frame, then the value of the
back chain dword from the previous stack frame, which is at
ea+8, is loaded on to one of the registers. This can cause
a mismatch as the addresses may vary across the master and
the apprentice instances. This is avoided by always adding
8 to the offset used for calculating the ea.
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---
ppc64.risu | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/ppc64.risu b/ppc64.risu
index 13b95ac..2018103 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -1050,8 +1050,8 @@ LHZX PPC64LE 011111 rt:5 ra:5 rb:5 01000101110 \
# format:DQ book:I page:59 v2.03 lq Load Qword
LQ PPC64LE 111000 rtp:5 ra:5 imm:12 0000 \
-!constraints { $rtp % 2 == 0 && $ra != 1 && $ra != 13 && $ra != 0 && $ra != $rtp && $imm <= 2032; } \
-!memory { reg_plus_imm($ra, $imm << 4); }
+!constraints { $rtp % 2 == 0 && $rtp != 0 && $rtp != 12 && $ra != 1 && $ra != 13 && $ra != 0 && $ra != $rtp && $imm <= 2032; } \
+!memory { reg_plus_imm($ra, ($imm << 4) + 8); }
# format:X book:I page:65 v:P1 lswi Load String Word Immediate
LSWI PPC64LE 011111 rt:5 ra:5 rb:5 10010101010 \
--
2.14.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH risu v2 3/3] risu_reginfo_ppc64.c: Fix register name prefix
2018-03-06 12:08 [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64 Sandipan Das
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 1/3] ppc64.risu: Add missing byte and dword loads Sandipan Das
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 2/3] ppc64.risu: Fix pattern for load qword Sandipan Das
@ 2018-03-06 12:08 ` Sandipan Das
2018-03-06 13:05 ` [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64 Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Sandipan Das @ 2018-03-06 12:08 UTC (permalink / raw)
To: peter.maydell, joserz; +Cc: nikunj, naveen.n.rao, qemu-devel
Use 'f' instead of 'r' as the prefix when dumping the values
of floating-point registers.
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---
risu_reginfo_ppc64.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c
index eb9c12b..5f33648 100644
--- a/risu_reginfo_ppc64.c
+++ b/risu_reginfo_ppc64.c
@@ -122,7 +122,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f)
fprintf(f, "\tdscr : %16lx\n\n", ri->gregs[44]);
for (i = 0; i < 16; i++) {
- fprintf(f, "\tf%2d: %.4f\tr%2d: %.4f\n", i, ri->fpregs[i],
+ fprintf(f, "\tf%2d: %.4f\tf%2d: %.4f\n", i, ri->fpregs[i],
i + 16, ri->fpregs[i + 16]);
}
fprintf(f, "\tfpscr: %f\n\n", ri->fpregs[32]);
@@ -167,7 +167,7 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f)
}
if (m->fpregs[i] != a->fpregs[i]) {
- fprintf(f, "Mismatch: Register r%d\n", i);
+ fprintf(f, "Mismatch: Register f%d\n", i);
fprintf(f, "m: [%f] != a: [%f]\n", m->fpregs[i], a->fpregs[i]);
}
}
--
2.14.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64
2018-03-06 12:08 [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64 Sandipan Das
` (2 preceding siblings ...)
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 3/3] risu_reginfo_ppc64.c: Fix register name prefix Sandipan Das
@ 2018-03-06 13:05 ` Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2018-03-06 13:05 UTC (permalink / raw)
To: Sandipan Das
Cc: Jose Ricardo Ziviani, Nikunj A Dadhania, naveen.n.rao, QEMU Developers
On 6 March 2018 at 12:08, Sandipan Das <sandipan@linux.vnet.ibm.com> wrote:
> The first patch adds the patterns for the missing byte and
> doubleword load instructions. The second patch fixes mismatches
> encountered when using the load quadword instruction. The last
> patch fixes a minor typo in the floating-point register prefix
> shown when dumping the register values.
>
> Changelog:
> v2 -> Added a cover letter as requested by Peter.
>
> Sandipan Das (3):
> ppc64.risu: Add missing byte and dword loads
> ppc64.risu: Fix pattern for load qword
> risu_reginfo_ppc64.c: Fix register name prefix
>
> ppc64.risu | 29 +++++++++++++++++++++++++++--
> risu_reginfo_ppc64.c | 4 ++--
> 2 files changed, 29 insertions(+), 4 deletions(-)
Thanks; I've applied these to risu master.
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-03-06 13:06 UTC | newest]
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2018-03-06 12:08 [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64 Sandipan Das
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 1/3] ppc64.risu: Add missing byte and dword loads Sandipan Das
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 2/3] ppc64.risu: Fix pattern for load qword Sandipan Das
2018-03-06 12:08 ` [Qemu-devel] [PATCH risu v2 3/3] risu_reginfo_ppc64.c: Fix register name prefix Sandipan Das
2018-03-06 13:05 ` [Qemu-devel] [PATCH risu v2 0/3] Miscellaneous fixes for powerpc64 Peter Maydell
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