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* [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers
@ 2018-03-07 13:36 Aneesh Kumar K.V
  2018-03-07 13:36 ` [PATCH 2/2] powerpc/mm/keys: Update documentation in key fault handling Aneesh Kumar K.V
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Aneesh Kumar K.V @ 2018-03-07 13:36 UTC (permalink / raw)
  To: benh, paulus, mpe, linuxram; +Cc: linuxppc-dev, Aneesh Kumar K.V

Memory keys are supported only with hash translation mode. Instead of #ifdef in
generic code move the key related pte bits to respective headers

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/book3s/64/hash-4k.h  |  7 +++++++
 arch/powerpc/include/asm/book3s/64/hash-64k.h |  7 +++++++
 arch/powerpc/include/asm/book3s/64/pgtable.h  | 19 -------------------
 3 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index fc3dc6a93939..4103bfc7c223 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -33,6 +33,13 @@
 #define H_PAGE_THP_HUGE 0x0
 #define H_PAGE_COMBO	0x0
 
+/* memory key bits, only 8 keys supported */
+#define H_PTE_PKEY_BIT0	0
+#define H_PTE_PKEY_BIT1	0
+#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
+#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
+#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
+
 /* 8 bytes per each pte entry */
 #define H_PTE_FRAG_SIZE_SHIFT  (H_PTE_INDEX_SIZE + 3)
 #define H_PTE_FRAG_NR	(PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index e53728ff29a0..bb880c97b87d 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -16,6 +16,13 @@
 #define H_PAGE_BUSY	_RPAGE_RPN44     /* software: PTE & hash are busy */
 #define H_PAGE_HASHPTE	_RPAGE_RPN43	/* PTE has associated HPTE */
 
+/* memory key bits. */
+#define H_PTE_PKEY_BIT0	_RPAGE_RSV1
+#define H_PTE_PKEY_BIT1	_RPAGE_RSV2
+#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
+#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
+#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
+
 /*
  * We need to differentiate between explicit huge page and THP huge
  * page, since THP huge page also need to track real subpage details
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 973199bd4654..c233915abb68 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -60,25 +60,6 @@
 /* Max physical address bit as per radix table */
 #define _RPAGE_PA_MAX		57
 
-#ifdef CONFIG_PPC_MEM_KEYS
-#ifdef CONFIG_PPC_64K_PAGES
-#define H_PTE_PKEY_BIT0	_RPAGE_RSV1
-#define H_PTE_PKEY_BIT1	_RPAGE_RSV2
-#else /* CONFIG_PPC_64K_PAGES */
-#define H_PTE_PKEY_BIT0	0 /* _RPAGE_RSV1 is not available */
-#define H_PTE_PKEY_BIT1	0 /* _RPAGE_RSV2 is not available */
-#endif /* CONFIG_PPC_64K_PAGES */
-#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
-#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
-#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
-#else /*  CONFIG_PPC_MEM_KEYS */
-#define H_PTE_PKEY_BIT0	0
-#define H_PTE_PKEY_BIT1	0
-#define H_PTE_PKEY_BIT2	0
-#define H_PTE_PKEY_BIT3	0
-#define H_PTE_PKEY_BIT4	0
-#endif /*  CONFIG_PPC_MEM_KEYS */
-
 /*
  * Max physical address bit we will use for now.
  *
-- 
2.14.3

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/2] powerpc/mm/keys: Update documentation in key fault handling
  2018-03-07 13:36 [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers Aneesh Kumar K.V
@ 2018-03-07 13:36 ` Aneesh Kumar K.V
  2018-04-04 14:39   ` [2/2] " Michael Ellerman
  2018-03-07 20:28 ` [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers Ram Pai
  2018-03-31 14:03 ` [1/2] " Michael Ellerman
  2 siblings, 1 reply; 6+ messages in thread
From: Aneesh Kumar K.V @ 2018-03-07 13:36 UTC (permalink / raw)
  To: benh, paulus, mpe, linuxram; +Cc: linuxppc-dev, Aneesh Kumar K.V

No functionality change in this patch. Adds more code comments. We also remove
an unnecessary pkey check after we check for pkey error in this patch.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/mm/fault.c | 28 ++++++++++++----------------
 arch/powerpc/mm/pkeys.c | 11 ++++-------
 2 files changed, 16 insertions(+), 23 deletions(-)

diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 866446cf2d9a..c01d627e687a 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -297,7 +297,12 @@ static bool access_error(bool is_write, bool is_exec,
 
 	if (unlikely(!(vma->vm_flags & (VM_READ | VM_EXEC | VM_WRITE))))
 		return true;
-
+	/*
+	 * We should ideally do the vma pkey access check here. But in the
+	 * fault path, handle_mm_fault() also does the same check. To avoid
+	 * these multiple checks, we skip it here and handle access error due
+	 * to pkeys later.
+	 */
 	return false;
 }
 
@@ -518,25 +523,16 @@ static int __do_page_fault(struct pt_regs *regs, unsigned long address,
 
 #ifdef CONFIG_PPC_MEM_KEYS
 	/*
-	 * if the HPTE is not hashed, hardware will not detect
-	 * a key fault. Lets check if we failed because of a
-	 * software detected key fault.
+	 * we skipped checking for access error due to key earlier.
+	 * Check that using handle_mm_fault error return.
 	 */
 	if (unlikely(fault & VM_FAULT_SIGSEGV) &&
-		!arch_vma_access_permitted(vma, flags & FAULT_FLAG_WRITE,
-			is_exec, 0)) {
-		/*
-		 * The PGD-PDT...PMD-PTE tree may not have been fully setup.
-		 * Hence we cannot walk the tree to locate the PTE, to locate
-		 * the key. Hence let's use vma_pkey() to get the key; instead
-		 * of get_mm_addr_key().
-		 */
+		!arch_vma_access_permitted(vma, is_write, is_exec, 0)) {
+
 		int pkey = vma_pkey(vma);
 
-		if (likely(pkey)) {
-			up_read(&mm->mmap_sem);
-			return bad_key_fault_exception(regs, address, pkey);
-		}
+		up_read(&mm->mmap_sem);
+		return bad_key_fault_exception(regs, address, pkey);
 	}
 #endif /* CONFIG_PPC_MEM_KEYS */
 
diff --git a/arch/powerpc/mm/pkeys.c b/arch/powerpc/mm/pkeys.c
index ba71c5481f42..56d33056a559 100644
--- a/arch/powerpc/mm/pkeys.c
+++ b/arch/powerpc/mm/pkeys.c
@@ -119,18 +119,15 @@ int pkey_initialize(void)
 #else
 	os_reserved = 0;
 #endif
+	initial_allocation_mask = ~0x0;
+	pkey_amr_uamor_mask = ~0x0ul;
+	pkey_iamr_mask = ~0x0ul;
 	/*
-	 * Bits are in LE format. NOTE: 1, 0 are reserved.
+	 * key 0, 1 are reserved.
 	 * key 0 is the default key, which allows read/write/execute.
 	 * key 1 is recommended not to be used. PowerISA(3.0) page 1015,
 	 * programming note.
 	 */
-	initial_allocation_mask = ~0x0;
-
-	/* register mask is in BE format */
-	pkey_amr_uamor_mask = ~0x0ul;
-	pkey_iamr_mask = ~0x0ul;
-
 	for (i = 2; i < (pkeys_total - os_reserved); i++) {
 		initial_allocation_mask &= ~(0x1 << i);
 		pkey_amr_uamor_mask &= ~(0x3ul << pkeyshift(i));
-- 
2.14.3

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers
  2018-03-07 13:36 [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers Aneesh Kumar K.V
  2018-03-07 13:36 ` [PATCH 2/2] powerpc/mm/keys: Update documentation in key fault handling Aneesh Kumar K.V
@ 2018-03-07 20:28 ` Ram Pai
  2018-03-08  2:28   ` Aneesh Kumar K.V
  2018-03-31 14:03 ` [1/2] " Michael Ellerman
  2 siblings, 1 reply; 6+ messages in thread
From: Ram Pai @ 2018-03-07 20:28 UTC (permalink / raw)
  To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev

On Wed, Mar 07, 2018 at 07:06:44PM +0530, Aneesh Kumar K.V wrote:
> Memory keys are supported only with hash translation mode. Instead of #ifdef in
> generic code move the key related pte bits to respective headers
> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
>  arch/powerpc/include/asm/book3s/64/hash-4k.h  |  7 +++++++
>  arch/powerpc/include/asm/book3s/64/hash-64k.h |  7 +++++++
>  arch/powerpc/include/asm/book3s/64/pgtable.h  | 19 -------------------
>  3 files changed, 14 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
> index fc3dc6a93939..4103bfc7c223 100644
> --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
> +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
> @@ -33,6 +33,13 @@
>  #define H_PAGE_THP_HUGE 0x0
>  #define H_PAGE_COMBO	0x0
> 
> +/* memory key bits, only 8 keys supported */
> +#define H_PTE_PKEY_BIT0	0
> +#define H_PTE_PKEY_BIT1	0
> +#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
> +#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
> +#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
> +


If CONFIG_PPC_MEM_KEYS is not defined, all of them have to be 0.  How is
that handled here? 

>  /* 8 bytes per each pte entry */
>  #define H_PTE_FRAG_SIZE_SHIFT  (H_PTE_INDEX_SIZE + 3)
>  #define H_PTE_FRAG_NR	(PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
> diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
> index e53728ff29a0..bb880c97b87d 100644
> --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
> +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
> @@ -16,6 +16,13 @@
>  #define H_PAGE_BUSY	_RPAGE_RPN44     /* software: PTE & hash are busy */
>  #define H_PAGE_HASHPTE	_RPAGE_RPN43	/* PTE has associated HPTE */
> 
> +/* memory key bits. */
> +#define H_PTE_PKEY_BIT0	_RPAGE_RSV1
> +#define H_PTE_PKEY_BIT1	_RPAGE_RSV2
> +#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
> +#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
> +#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
> +

same comment as above.

RP

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers
  2018-03-07 20:28 ` [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers Ram Pai
@ 2018-03-08  2:28   ` Aneesh Kumar K.V
  0 siblings, 0 replies; 6+ messages in thread
From: Aneesh Kumar K.V @ 2018-03-08  2:28 UTC (permalink / raw)
  To: Ram Pai; +Cc: benh, paulus, mpe, linuxppc-dev

On 03/08/2018 01:58 AM, Ram Pai wrote:
> On Wed, Mar 07, 2018 at 07:06:44PM +0530, Aneesh Kumar K.V wrote:
>> Memory keys are supported only with hash translation mode. Instead of #ifdef in
>> generic code move the key related pte bits to respective headers
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>>   arch/powerpc/include/asm/book3s/64/hash-4k.h  |  7 +++++++
>>   arch/powerpc/include/asm/book3s/64/hash-64k.h |  7 +++++++
>>   arch/powerpc/include/asm/book3s/64/pgtable.h  | 19 -------------------
>>   3 files changed, 14 insertions(+), 19 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
>> index fc3dc6a93939..4103bfc7c223 100644
>> --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
>> +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
>> @@ -33,6 +33,13 @@
>>   #define H_PAGE_THP_HUGE 0x0
>>   #define H_PAGE_COMBO	0x0
>>
>> +/* memory key bits, only 8 keys supported */
>> +#define H_PTE_PKEY_BIT0	0
>> +#define H_PTE_PKEY_BIT1	0
>> +#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
>> +#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
>> +#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
>> +
> 
> 
> If CONFIG_PPC_MEM_KEYS is not defined, all of them have to be 0.  How is
> that handled here?

why? conditional defines of pte bits always results in error, like we 
check for an overloaded key bit in some code path and taking wrong action.

> 
>>   /* 8 bytes per each pte entry */
>>   #define H_PTE_FRAG_SIZE_SHIFT  (H_PTE_INDEX_SIZE + 3)
>>   #define H_PTE_FRAG_NR	(PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
>> diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
>> index e53728ff29a0..bb880c97b87d 100644
>> --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
>> +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
>> @@ -16,6 +16,13 @@
>>   #define H_PAGE_BUSY	_RPAGE_RPN44     /* software: PTE & hash are busy */
>>   #define H_PAGE_HASHPTE	_RPAGE_RPN43	/* PTE has associated HPTE */
>>
>> +/* memory key bits. */
>> +#define H_PTE_PKEY_BIT0	_RPAGE_RSV1
>> +#define H_PTE_PKEY_BIT1	_RPAGE_RSV2
>> +#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
>> +#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
>> +#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
>> +
> 
> same comment as above.
> 

-aneesh

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [1/2] powerpc/mm/keys: Move pte bits to correct headers
  2018-03-07 13:36 [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers Aneesh Kumar K.V
  2018-03-07 13:36 ` [PATCH 2/2] powerpc/mm/keys: Update documentation in key fault handling Aneesh Kumar K.V
  2018-03-07 20:28 ` [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers Ram Pai
@ 2018-03-31 14:03 ` Michael Ellerman
  2 siblings, 0 replies; 6+ messages in thread
From: Michael Ellerman @ 2018-03-31 14:03 UTC (permalink / raw)
  To: Aneesh Kumar K.V, benh, paulus, linuxram; +Cc: linuxppc-dev, Aneesh Kumar K.V

On Wed, 2018-03-07 at 13:36:44 UTC, "Aneesh Kumar K.V" wrote:
> Memory keys are supported only with hash translation mode. Instead of #ifdef in
> generic code move the key related pte bits to respective headers
> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/1a2f778970c81273c121be160fb661

cheers

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [2/2] powerpc/mm/keys: Update documentation in key fault handling
  2018-03-07 13:36 ` [PATCH 2/2] powerpc/mm/keys: Update documentation in key fault handling Aneesh Kumar K.V
@ 2018-04-04 14:39   ` Michael Ellerman
  0 siblings, 0 replies; 6+ messages in thread
From: Michael Ellerman @ 2018-04-04 14:39 UTC (permalink / raw)
  To: Aneesh Kumar K.V, benh, paulus, linuxram; +Cc: linuxppc-dev, Aneesh Kumar K.V

On Wed, 2018-03-07 at 13:36:45 UTC, "Aneesh Kumar K.V" wrote:
> No functionality change in this patch. Adds more code comments. We also remove
> an unnecessary pkey check after we check for pkey error in this patch.
> 
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/f2ed480fa4d7f95b190279722690df

cheers

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-04-04 14:39 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-07 13:36 [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers Aneesh Kumar K.V
2018-03-07 13:36 ` [PATCH 2/2] powerpc/mm/keys: Update documentation in key fault handling Aneesh Kumar K.V
2018-04-04 14:39   ` [2/2] " Michael Ellerman
2018-03-07 20:28 ` [PATCH 1/2] powerpc/mm/keys: Move pte bits to correct headers Ram Pai
2018-03-08  2:28   ` Aneesh Kumar K.V
2018-03-31 14:03 ` [1/2] " Michael Ellerman

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