From: Christoph Hellwig <hch@infradead.org> To: Mikulas Patocka <mpatocka@redhat.com> Cc: Mike Snitzer <msnitzer@redhat.com>, dm-devel@redhat.com, "Alasdair G. Kergon" <agk@redhat.com>, linux-nvdimm@lists.01.org Subject: Re: [dm-devel] [PATCH] dm-writecache Date: Thu, 8 Mar 2018 06:51:53 -0800 [thread overview] Message-ID: <20180308145153.GB23262@infradead.org> (raw) In-Reply-To: <alpine.LRH.2.02.1803080824210.2819@file01.intranet.prod.int.rdu2.redhat.com> > --- /dev/null 1970-01-01 00:00:00.000000000 +0000 > +++ linux-2.6/drivers/md/dm-writecache.c 2018-03-08 14:23:31.059999000 +0100 > @@ -0,0 +1,2417 @@ > +#include <linux/device-mapper.h> missing copyright statement, or for those new-fashioned SPDX statement. > +#define WRITEBACK_FUA true no business having this around. > +#ifndef bio_set_dev > +#define bio_set_dev(bio, dev) ((bio)->bi_bdev = (dev)) > +#endif > +#ifndef timer_setup > +#define timer_setup(t, c, f) setup_timer(t, c, (unsigned long)(t)) > +#endif no business in mainline. > +/* > + * On X86, non-temporal stores are more efficient than cache flushing. > + * On ARM64, cache flushing is more efficient. > + */ > +#if defined(CONFIG_X86_64) > +#define NT_STORE(dest, src) \ > +do { \ > + typeof(src) val = (src); \ > + memcpy_flushcache(&(dest), &val, sizeof(src)); \ > +} while (0) > +#define COMMIT_FLUSHED() wmb() > +#else > +#define NT_STORE(dest, src) WRITE_ONCE(dest, src) > +#define FLUSH_RANGE dax_flush > +#define COMMIT_FLUSHED() do { } while (0) > +#endif Please use proper APIs for this, this has no business in a driver. And that's it for now. This is clearly not submission ready, and I should got back to my backlog of other things. _______________________________________________ Linux-nvdimm mailing list Linux-nvdimm@lists.01.org https://lists.01.org/mailman/listinfo/linux-nvdimm
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org> To: Mikulas Patocka <mpatocka-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> Cc: Mike Snitzer <msnitzer-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>, dm-devel-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, "Alasdair G. Kergon" <agk-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>, linux-nvdimm-hn68Rpc1hR1g9hUCZPvPmw@public.gmane.org Subject: Re: [dm-devel] [PATCH] dm-writecache Date: Thu, 8 Mar 2018 06:51:53 -0800 [thread overview] Message-ID: <20180308145153.GB23262@infradead.org> (raw) In-Reply-To: <alpine.LRH.2.02.1803080824210.2819-Hpncn10jQN4oNljnaZt3ZvA+iT7yCHsGwRM8/txMwJMAicBL8TP8PQ@public.gmane.org> > --- /dev/null 1970-01-01 00:00:00.000000000 +0000 > +++ linux-2.6/drivers/md/dm-writecache.c 2018-03-08 14:23:31.059999000 +0100 > @@ -0,0 +1,2417 @@ > +#include <linux/device-mapper.h> missing copyright statement, or for those new-fashioned SPDX statement. > +#define WRITEBACK_FUA true no business having this around. > +#ifndef bio_set_dev > +#define bio_set_dev(bio, dev) ((bio)->bi_bdev = (dev)) > +#endif > +#ifndef timer_setup > +#define timer_setup(t, c, f) setup_timer(t, c, (unsigned long)(t)) > +#endif no business in mainline. > +/* > + * On X86, non-temporal stores are more efficient than cache flushing. > + * On ARM64, cache flushing is more efficient. > + */ > +#if defined(CONFIG_X86_64) > +#define NT_STORE(dest, src) \ > +do { \ > + typeof(src) val = (src); \ > + memcpy_flushcache(&(dest), &val, sizeof(src)); \ > +} while (0) > +#define COMMIT_FLUSHED() wmb() > +#else > +#define NT_STORE(dest, src) WRITE_ONCE(dest, src) > +#define FLUSH_RANGE dax_flush > +#define COMMIT_FLUSHED() do { } while (0) > +#endif Please use proper APIs for this, this has no business in a driver. And that's it for now. This is clearly not submission ready, and I should got back to my backlog of other things.
next prev parent reply other threads:[~2018-03-08 14:45 UTC|newest] Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-08 13:25 [PATCH] dm-writecache Mikulas Patocka 2018-03-08 14:51 ` Christoph Hellwig [this message] 2018-03-08 14:51 ` [dm-devel] " Christoph Hellwig 2018-03-08 17:08 ` Dan Williams 2018-03-08 17:08 ` Dan Williams 2018-03-12 7:48 ` Christoph Hellwig 2018-03-12 7:48 ` Christoph Hellwig 2018-03-12 12:15 ` Mikulas Patocka 2018-03-12 12:15 ` Mikulas Patocka 2018-05-18 15:44 ` dm-writecache Mike Snitzer 2018-05-18 15:44 ` dm-writecache Mike Snitzer 2018-05-18 15:54 ` dm-writecache Dan Williams 2018-05-18 15:54 ` dm-writecache Dan Williams 2018-05-18 20:12 ` dm-writecache Mikulas Patocka 2018-05-18 20:12 ` dm-writecache Mikulas Patocka 2018-05-18 20:14 ` dm-writecache Dan Williams 2018-05-18 20:14 ` dm-writecache Dan Williams 2018-05-18 22:00 ` dm-writecache Mikulas Patocka 2018-05-18 22:00 ` dm-writecache Mikulas Patocka 2018-05-18 22:10 ` dm-writecache Dan Williams 2018-05-18 22:10 ` dm-writecache Dan Williams 2018-03-09 3:26 ` [dm-devel] [PATCH] dm-writecache Mikulas Patocka 2018-03-09 3:26 ` Mikulas Patocka 2018-03-12 7:50 ` Christoph Hellwig 2018-03-12 7:50 ` Christoph Hellwig 2018-03-12 12:12 ` Mikulas Patocka 2018-03-12 12:12 ` Mikulas Patocka
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