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* [PATCH 0/3] CNL port refactoring
@ 2018-03-09 12:58 Mahesh Kumar
  2018-03-09 12:58 ` [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar
                   ` (4 more replies)
  0 siblings, 5 replies; 10+ messages in thread
From: Mahesh Kumar @ 2018-03-09 12:58 UTC (permalink / raw)
  To: intel-gfx; +Cc: rodrigo.vivi

This series fixes CNL PORT_TX_DW5/7_LNO_D register address.
This series also introduces macros to get register address of
CNL_PORT_TX registers instead of defining for each DW instance.

changes since V1:
 completely kill _MMIO_PORT6 macro

Mahesh Kumar (3):
  drm/i915/cnl; Add macro to get PORT_TX register
  drm/i915/cnl: Replace PORT_TX register macros with new ones
  drm/i915/cnl: Kill _MMIO_PORT6 macro

 drivers/gpu/drm/i915/i915_reg.h | 147 ++++++++++++----------------------------
 1 file changed, 44 insertions(+), 103 deletions(-)

-- 
2.14.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register
  2018-03-09 12:58 [PATCH 0/3] CNL port refactoring Mahesh Kumar
@ 2018-03-09 12:58 ` Mahesh Kumar
  2018-03-09 19:55   ` Rodrigo Vivi
  2018-03-09 12:58 ` [PATCH 2/3] drm/i915/cnl: Replace PORT_TX register macros with new ones Mahesh Kumar
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 10+ messages in thread
From: Mahesh Kumar @ 2018-03-09 12:58 UTC (permalink / raw)
  To: intel-gfx; +Cc: rodrigo.vivi

This patch creates a new macro to get PORT_TX register for any given DW.
This will remove the need of defining register address for each port & DW.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e6a8c0ee7df1..30ef3513dc6f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1964,6 +1964,34 @@ enum i915_power_well_id {
 						    _CNL_PORT_PCS_DW1_LN0_F)
 #define   COMMON_KEEPER_EN		(1 << 26)
 
+/* CNL Port TX registers */
+#define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
+#define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
+#define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
+#define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
+#define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
+#define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
+#define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
+#define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
+#define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
+#define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
+#define CNL_PORT_TX_DW_GRP(port, dw)	(_PICK((port), \
+					       _CNL_PORT_TX_AE_GRP_OFFSET, \
+					       _CNL_PORT_TX_B_GRP_OFFSET, \
+					       _CNL_PORT_TX_B_GRP_OFFSET, \
+					       _CNL_PORT_TX_D_GRP_OFFSET, \
+					       _CNL_PORT_TX_AE_GRP_OFFSET, \
+					       _CNL_PORT_TX_F_GRP_OFFSET) + \
+					       4*(dw))
+#define CNL_PORT_TX_DW_LN0(port, dw)	(_PICK((port), \
+					       _CNL_PORT_TX_AE_LN0_OFFSET, \
+					       _CNL_PORT_TX_B_LN0_OFFSET, \
+					       _CNL_PORT_TX_B_LN0_OFFSET, \
+					       _CNL_PORT_TX_D_LN0_OFFSET, \
+					       _CNL_PORT_TX_AE_LN0_OFFSET, \
+					       _CNL_PORT_TX_F_LN0_OFFSET) + \
+					       4*(dw))
+
 #define _CNL_PORT_TX_DW2_GRP_AE		0x162348
 #define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
 #define _CNL_PORT_TX_DW2_GRP_C		0x162B48
-- 
2.14.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/i915/cnl: Replace PORT_TX register macros with new ones
  2018-03-09 12:58 [PATCH 0/3] CNL port refactoring Mahesh Kumar
  2018-03-09 12:58 ` [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar
@ 2018-03-09 12:58 ` Mahesh Kumar
  2018-03-09 12:58 ` [PATCH 3/3] drm/i915/cnl: Kill _MMIO_PORT6 macro Mahesh Kumar
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 10+ messages in thread
From: Mahesh Kumar @ 2018-03-09 12:58 UTC (permalink / raw)
  To: intel-gfx; +Cc: rodrigo.vivi

This patch replaces CNL_PORT_TX register macros with new macros defined
in previous patch.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 107 +++++-----------------------------------
 1 file changed, 11 insertions(+), 96 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 30ef3513dc6f..7987a3f85d04 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1992,30 +1992,8 @@ enum i915_power_well_id {
 					       _CNL_PORT_TX_F_LN0_OFFSET) + \
 					       4*(dw))
 
-#define _CNL_PORT_TX_DW2_GRP_AE		0x162348
-#define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
-#define _CNL_PORT_TX_DW2_GRP_C		0x162B48
-#define _CNL_PORT_TX_DW2_GRP_D		0x162BC8
-#define _CNL_PORT_TX_DW2_GRP_F		0x162A48
-#define _CNL_PORT_TX_DW2_LN0_AE		0x162448
-#define _CNL_PORT_TX_DW2_LN0_B		0x162648
-#define _CNL_PORT_TX_DW2_LN0_C		0x162C48
-#define _CNL_PORT_TX_DW2_LN0_D		0x162E48
-#define _CNL_PORT_TX_DW2_LN0_F		0x162848
-#define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
-						    _CNL_PORT_TX_DW2_GRP_AE, \
-						    _CNL_PORT_TX_DW2_GRP_B, \
-						    _CNL_PORT_TX_DW2_GRP_C, \
-						    _CNL_PORT_TX_DW2_GRP_D, \
-						    _CNL_PORT_TX_DW2_GRP_AE, \
-						    _CNL_PORT_TX_DW2_GRP_F)
-#define CNL_PORT_TX_DW2_LN0(port)	_MMIO_PORT6(port, \
-						    _CNL_PORT_TX_DW2_LN0_AE, \
-						    _CNL_PORT_TX_DW2_LN0_B, \
-						    _CNL_PORT_TX_DW2_LN0_C, \
-						    _CNL_PORT_TX_DW2_LN0_D, \
-						    _CNL_PORT_TX_DW2_LN0_AE, \
-						    _CNL_PORT_TX_DW2_LN0_F)
+#define CNL_PORT_TX_DW2_GRP(port)	_MMIO(CNL_PORT_TX_DW_GRP((port), 2))
+#define CNL_PORT_TX_DW2_LN0(port)	_MMIO(CNL_PORT_TX_DW_LN0((port), 2))
 #define   SWING_SEL_UPPER(x)		((x >> 3) << 15)
 #define   SWING_SEL_UPPER_MASK		(1 << 15)
 #define   SWING_SEL_LOWER(x)		((x & 0x7) << 11)
@@ -2023,32 +2001,13 @@ enum i915_power_well_id {
 #define   RCOMP_SCALAR(x)		((x) << 0)
 #define   RCOMP_SCALAR_MASK		(0xFF << 0)
 
-#define _CNL_PORT_TX_DW4_GRP_AE		0x162350
-#define _CNL_PORT_TX_DW4_GRP_B		0x1623D0
-#define _CNL_PORT_TX_DW4_GRP_C		0x162B50
-#define _CNL_PORT_TX_DW4_GRP_D		0x162BD0
-#define _CNL_PORT_TX_DW4_GRP_F		0x162A50
 #define _CNL_PORT_TX_DW4_LN0_AE		0x162450
 #define _CNL_PORT_TX_DW4_LN1_AE		0x1624D0
-#define _CNL_PORT_TX_DW4_LN0_B		0x162650
-#define _CNL_PORT_TX_DW4_LN0_C		0x162C50
-#define _CNL_PORT_TX_DW4_LN0_D		0x162E50
-#define _CNL_PORT_TX_DW4_LN0_F		0x162850
-#define CNL_PORT_TX_DW4_GRP(port)       _MMIO_PORT6(port, \
-						    _CNL_PORT_TX_DW4_GRP_AE, \
-						    _CNL_PORT_TX_DW4_GRP_B, \
-						    _CNL_PORT_TX_DW4_GRP_C, \
-						    _CNL_PORT_TX_DW4_GRP_D, \
-						    _CNL_PORT_TX_DW4_GRP_AE, \
-						    _CNL_PORT_TX_DW4_GRP_F)
-#define CNL_PORT_TX_DW4_LN(port, ln)       _MMIO_PORT6_LN(port, ln,	\
-						    _CNL_PORT_TX_DW4_LN0_AE, \
-						    _CNL_PORT_TX_DW4_LN1_AE, \
-						    _CNL_PORT_TX_DW4_LN0_B, \
-						    _CNL_PORT_TX_DW4_LN0_C, \
-						    _CNL_PORT_TX_DW4_LN0_D, \
-						    _CNL_PORT_TX_DW4_LN0_AE, \
-						    _CNL_PORT_TX_DW4_LN0_F)
+#define CNL_PORT_TX_DW4_GRP(port)	_MMIO(CNL_PORT_TX_DW_GRP((port), 4))
+#define CNL_PORT_TX_DW4_LN0(port)	_MMIO(CNL_PORT_TX_DW_LN0((port), 4))
+#define CNL_PORT_TX_DW4_LN(port, ln)   _MMIO(CNL_PORT_TX_DW_LN0((port), 4) + \
+					     (ln * (_CNL_PORT_TX_DW4_LN1_AE - \
+						    _CNL_PORT_TX_DW4_LN0_AE)))
 #define   LOADGEN_SELECT		(1 << 31)
 #define   POST_CURSOR_1(x)		((x) << 12)
 #define   POST_CURSOR_1_MASK		(0x3F << 12)
@@ -2057,30 +2016,8 @@ enum i915_power_well_id {
 #define   CURSOR_COEFF(x)		((x) << 0)
 #define   CURSOR_COEFF_MASK		(0x3F << 0)
 
-#define _CNL_PORT_TX_DW5_GRP_AE		0x162354
-#define _CNL_PORT_TX_DW5_GRP_B		0x1623D4
-#define _CNL_PORT_TX_DW5_GRP_C		0x162B54
-#define _CNL_PORT_TX_DW5_GRP_D		0x162BD4
-#define _CNL_PORT_TX_DW5_GRP_F		0x162A54
-#define _CNL_PORT_TX_DW5_LN0_AE		0x162454
-#define _CNL_PORT_TX_DW5_LN0_B		0x162654
-#define _CNL_PORT_TX_DW5_LN0_C		0x162C54
-#define _CNL_PORT_TX_DW5_LN0_D		0x162E54
-#define _CNL_PORT_TX_DW5_LN0_F		0x162854
-#define CNL_PORT_TX_DW5_GRP(port)	_MMIO_PORT6(port, \
-						    _CNL_PORT_TX_DW5_GRP_AE, \
-						    _CNL_PORT_TX_DW5_GRP_B, \
-						    _CNL_PORT_TX_DW5_GRP_C, \
-						    _CNL_PORT_TX_DW5_GRP_D, \
-						    _CNL_PORT_TX_DW5_GRP_AE, \
-						    _CNL_PORT_TX_DW5_GRP_F)
-#define CNL_PORT_TX_DW5_LN0(port)	_MMIO_PORT6(port, \
-						    _CNL_PORT_TX_DW5_LN0_AE, \
-						    _CNL_PORT_TX_DW5_LN0_B, \
-						    _CNL_PORT_TX_DW5_LN0_C, \
-						    _CNL_PORT_TX_DW5_LN0_D, \
-						    _CNL_PORT_TX_DW5_LN0_AE, \
-						    _CNL_PORT_TX_DW5_LN0_F)
+#define CNL_PORT_TX_DW5_GRP(port)	_MMIO(CNL_PORT_TX_DW_GRP((port), 5))
+#define CNL_PORT_TX_DW5_LN0(port)	_MMIO(CNL_PORT_TX_DW_LN0((port), 5))
 #define   TX_TRAINING_EN		(1 << 31)
 #define   TAP3_DISABLE			(1 << 29)
 #define   SCALING_MODE_SEL(x)		((x) << 18)
@@ -2088,30 +2025,8 @@ enum i915_power_well_id {
 #define   RTERM_SELECT(x)		((x) << 3)
 #define   RTERM_SELECT_MASK		(0x7 << 3)
 
-#define _CNL_PORT_TX_DW7_GRP_AE		0x16235C
-#define _CNL_PORT_TX_DW7_GRP_B		0x1623DC
-#define _CNL_PORT_TX_DW7_GRP_C		0x162B5C
-#define _CNL_PORT_TX_DW7_GRP_D		0x162BDC
-#define _CNL_PORT_TX_DW7_GRP_F		0x162A5C
-#define _CNL_PORT_TX_DW7_LN0_AE		0x16245C
-#define _CNL_PORT_TX_DW7_LN0_B		0x16265C
-#define _CNL_PORT_TX_DW7_LN0_C		0x162C5C
-#define _CNL_PORT_TX_DW7_LN0_D		0x162E5C
-#define _CNL_PORT_TX_DW7_LN0_F		0x16285C
-#define CNL_PORT_TX_DW7_GRP(port)	_MMIO_PORT6(port, \
-						    _CNL_PORT_TX_DW7_GRP_AE, \
-						    _CNL_PORT_TX_DW7_GRP_B, \
-						    _CNL_PORT_TX_DW7_GRP_C, \
-						    _CNL_PORT_TX_DW7_GRP_D, \
-						    _CNL_PORT_TX_DW7_GRP_AE, \
-						    _CNL_PORT_TX_DW7_GRP_F)
-#define CNL_PORT_TX_DW7_LN0(port)	_MMIO_PORT6(port, \
-						    _CNL_PORT_TX_DW7_LN0_AE, \
-						    _CNL_PORT_TX_DW7_LN0_B, \
-						    _CNL_PORT_TX_DW7_LN0_C, \
-						    _CNL_PORT_TX_DW7_LN0_D, \
-						    _CNL_PORT_TX_DW7_LN0_AE, \
-						    _CNL_PORT_TX_DW7_LN0_F)
+#define CNL_PORT_TX_DW7_GRP(port)	_MMIO(CNL_PORT_TX_DW_GRP((port), 7))
+#define CNL_PORT_TX_DW7_LN0(port)	_MMIO(CNL_PORT_TX_DW_LN0((port), 7))
 #define   N_SCALAR(x)			((x) << 24)
 #define   N_SCALAR_MASK			(0x7F << 24)
 
-- 
2.14.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH 3/3] drm/i915/cnl: Kill _MMIO_PORT6 macro
  2018-03-09 12:58 [PATCH 0/3] CNL port refactoring Mahesh Kumar
  2018-03-09 12:58 ` [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar
  2018-03-09 12:58 ` [PATCH 2/3] drm/i915/cnl: Replace PORT_TX register macros with new ones Mahesh Kumar
@ 2018-03-09 12:58 ` Mahesh Kumar
  2018-03-09 19:56   ` Rodrigo Vivi
  2018-03-09 14:02 ` ✓ Fi.CI.BAT: success for CNL port refactoring (rev2) Patchwork
  2018-03-09 17:31 ` ✓ Fi.CI.IGT: " Patchwork
  4 siblings, 1 reply; 10+ messages in thread
From: Mahesh Kumar @ 2018-03-09 12:58 UTC (permalink / raw)
  To: intel-gfx; +Cc: rodrigo.vivi

This patch replaces use of remaining _MMIO_PORT6 macro and removes the
macro.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7987a3f85d04..37742d774ba0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -153,9 +153,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
 #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
-#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
-#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)			\
-	_MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
 
@@ -1948,20 +1945,21 @@ enum i915_power_well_id {
 #define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
 #define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
 #define _CNL_PORT_PCS_DW1_LN0_F		0x162804
-#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
+#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO(_PICK(port, \
 						    _CNL_PORT_PCS_DW1_GRP_AE, \
 						    _CNL_PORT_PCS_DW1_GRP_B, \
 						    _CNL_PORT_PCS_DW1_GRP_C, \
 						    _CNL_PORT_PCS_DW1_GRP_D, \
 						    _CNL_PORT_PCS_DW1_GRP_AE, \
-						    _CNL_PORT_PCS_DW1_GRP_F)
-#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_PCS_DW1_GRP_F))
+
+#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
 						    _CNL_PORT_PCS_DW1_LN0_AE, \
 						    _CNL_PORT_PCS_DW1_LN0_B, \
 						    _CNL_PORT_PCS_DW1_LN0_C, \
 						    _CNL_PORT_PCS_DW1_LN0_D, \
 						    _CNL_PORT_PCS_DW1_LN0_AE, \
-						    _CNL_PORT_PCS_DW1_LN0_F)
+						    _CNL_PORT_PCS_DW1_LN0_F))
 #define   COMMON_KEEPER_EN		(1 << 26)
 
 /* CNL Port TX registers */
-- 
2.14.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for CNL port refactoring (rev2)
  2018-03-09 12:58 [PATCH 0/3] CNL port refactoring Mahesh Kumar
                   ` (2 preceding siblings ...)
  2018-03-09 12:58 ` [PATCH 3/3] drm/i915/cnl: Kill _MMIO_PORT6 macro Mahesh Kumar
@ 2018-03-09 14:02 ` Patchwork
  2018-03-09 17:31 ` ✓ Fi.CI.IGT: " Patchwork
  4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2018-03-09 14:02 UTC (permalink / raw)
  To: Mahesh Kumar; +Cc: intel-gfx

== Series Details ==

Series: CNL port refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/38334/
State : success

== Summary ==

Series 38334v2 CNL port refactoring
https://patchwork.freedesktop.org/api/1.0/series/38334/revisions/2/mbox/

---- Known issues:

Test kms_frontbuffer_tracking:
        Subgroup basic:
                fail       -> PASS       (fi-cnl-y3) fdo#103167
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                dmesg-warn -> PASS       (fi-skl-6700k2) fdo#103191

fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:422s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:426s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:372s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:509s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:280s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:489s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:500s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:487s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:475s
fi-cfl-8700k     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:407s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:576s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:581s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:415s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:291s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:514s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:404s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:419s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:453s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:423s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:469s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:463s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:510s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:590s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:429s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:523s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:534s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:497s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:488s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:420s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:514s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:395s
Blacklisted hosts:
fi-cnl-drrs      total:288  pass:257  dwarn:3   dfail:0   fail:0   skip:19  time:519s

074e834cb3cccf697895a7dc471d324c2309a610 drm-tip: 2018y-03m-09d-10h-30m-56s UTC integration manifest
d271c009a148 drm/i915/cnl: Kill _MMIO_PORT6 macro
5a42fe815c97 drm/i915/cnl: Replace PORT_TX register macros with new ones
08448452816c drm/i915/cnl; Add macro to get PORT_TX register

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8290/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for CNL port refactoring (rev2)
  2018-03-09 12:58 [PATCH 0/3] CNL port refactoring Mahesh Kumar
                   ` (3 preceding siblings ...)
  2018-03-09 14:02 ` ✓ Fi.CI.BAT: success for CNL port refactoring (rev2) Patchwork
@ 2018-03-09 17:31 ` Patchwork
  4 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2018-03-09 17:31 UTC (permalink / raw)
  To: Mahesh Kumar; +Cc: intel-gfx

== Series Details ==

Series: CNL port refactoring (rev2)
URL   : https://patchwork.freedesktop.org/series/38334/
State : success

== Summary ==

---- Known issues:

Test gem_eio:
        Subgroup in-flight-external:
                pass       -> INCOMPLETE (shard-apl) fdo#105341
Test kms_cursor_crc:
        Subgroup cursor-256x256-suspend:
                incomplete -> PASS       (shard-hsw) fdo#103375
Test kms_frontbuffer_tracking:
        Subgroup fbc-suspend:
                pass       -> FAIL       (shard-apl) fdo#101623
Test kms_setmode:
        Subgroup basic:
                fail       -> PASS       (shard-hsw) fdo#99912
Test kms_vblank:
        Subgroup pipe-a-ts-continuation-dpms-suspend:
                incomplete -> PASS       (shard-hsw) fdo#103540
Test perf:
        Subgroup blocking:
                pass       -> FAIL       (shard-hsw) fdo#102252

fdo#105341 https://bugs.freedesktop.org/show_bug.cgi?id=105341
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apl        total:3381 pass:1778 dwarn:1   dfail:0   fail:9   skip:1591 time:11749s
shard-hsw        total:3467 pass:1773 dwarn:1   dfail:0   fail:1   skip:1691 time:11736s
shard-snb        total:3467 pass:1363 dwarn:1   dfail:0   fail:2   skip:2101 time:6959s
Blacklisted hosts:
shard-kbl        total:3390 pass:1905 dwarn:1   dfail:0   fail:9   skip:1473 time:8543s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8290/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register
  2018-03-09 12:58 ` [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar
@ 2018-03-09 19:55   ` Rodrigo Vivi
  2018-03-09 20:51     ` Lucas De Marchi
  0 siblings, 1 reply; 10+ messages in thread
From: Rodrigo Vivi @ 2018-03-09 19:55 UTC (permalink / raw)
  To: Mahesh Kumar; +Cc: intel-gfx

On Fri, Mar 09, 2018 at 06:28:56PM +0530, Mahesh Kumar wrote:
> This patch creates a new macro to get PORT_TX register for any given DW.
> This will remove the need of defining register address for each port & DW.

please squash patches 1 and 2. I had to open both simultaneously to review it
what indicates that they should be 1 patch.

> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e6a8c0ee7df1..30ef3513dc6f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1964,6 +1964,34 @@ enum i915_power_well_id {
>  						    _CNL_PORT_PCS_DW1_LN0_F)
>  #define   COMMON_KEEPER_EN		(1 << 26)
>  
> +/* CNL Port TX registers */
> +#define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
> +#define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
> +#define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
> +#define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
> +#define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
> +#define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
> +#define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
> +#define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
> +#define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
> +#define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
> +#define CNL_PORT_TX_DW_GRP(port, dw)	(_PICK((port), \
> +					       _CNL_PORT_TX_AE_GRP_OFFSET, \
> +					       _CNL_PORT_TX_B_GRP_OFFSET, \
> +					       _CNL_PORT_TX_B_GRP_OFFSET, \
> +					       _CNL_PORT_TX_D_GRP_OFFSET, \
> +					       _CNL_PORT_TX_AE_GRP_OFFSET, \
> +					       _CNL_PORT_TX_F_GRP_OFFSET) + \
> +					       4*(dw))

the math is right. I'm glad someone could see some logic on all these
numbers. I with we had a basic offset and math for all the port registers, but...

> +#define CNL_PORT_TX_DW_LN0(port, dw)	(_PICK((port), \

who converts the offset to MMIO reg now?

> +					       _CNL_PORT_TX_AE_LN0_OFFSET, \
> +					       _CNL_PORT_TX_B_LN0_OFFSET, \
> +					       _CNL_PORT_TX_B_LN0_OFFSET, \
> +					       _CNL_PORT_TX_D_LN0_OFFSET, \
> +					       _CNL_PORT_TX_AE_LN0_OFFSET, \
> +					       _CNL_PORT_TX_F_LN0_OFFSET) + \
> +					       4*(dw))
> +
>  #define _CNL_PORT_TX_DW2_GRP_AE		0x162348
>  #define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
>  #define _CNL_PORT_TX_DW2_GRP_C		0x162B48
> -- 
> 2.14.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] drm/i915/cnl: Kill _MMIO_PORT6 macro
  2018-03-09 12:58 ` [PATCH 3/3] drm/i915/cnl: Kill _MMIO_PORT6 macro Mahesh Kumar
@ 2018-03-09 19:56   ` Rodrigo Vivi
  0 siblings, 0 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2018-03-09 19:56 UTC (permalink / raw)
  To: Mahesh Kumar; +Cc: intel-gfx

On Fri, Mar 09, 2018 at 06:28:58PM +0530, Mahesh Kumar wrote:
> This patch replaces use of remaining _MMIO_PORT6 macro and removes the
> macro.

Thanks... I hope that we don't need to bring it back for the ICL patches...

> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7987a3f85d04..37742d774ba0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -153,9 +153,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
>  #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
>  #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
> -#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
> -#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)			\
> -	_MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
>  #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
>  #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>  
> @@ -1948,20 +1945,21 @@ enum i915_power_well_id {
>  #define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
>  #define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
>  #define _CNL_PORT_PCS_DW1_LN0_F		0x162804
> -#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
> +#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO(_PICK(port, \
>  						    _CNL_PORT_PCS_DW1_GRP_AE, \
>  						    _CNL_PORT_PCS_DW1_GRP_B, \
>  						    _CNL_PORT_PCS_DW1_GRP_C, \
>  						    _CNL_PORT_PCS_DW1_GRP_D, \
>  						    _CNL_PORT_PCS_DW1_GRP_AE, \
> -						    _CNL_PORT_PCS_DW1_GRP_F)
> -#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_PCS_DW1_GRP_F))
> +
> +#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
>  						    _CNL_PORT_PCS_DW1_LN0_AE, \
>  						    _CNL_PORT_PCS_DW1_LN0_B, \
>  						    _CNL_PORT_PCS_DW1_LN0_C, \
>  						    _CNL_PORT_PCS_DW1_LN0_D, \
>  						    _CNL_PORT_PCS_DW1_LN0_AE, \
> -						    _CNL_PORT_PCS_DW1_LN0_F)
> +						    _CNL_PORT_PCS_DW1_LN0_F))
>  #define   COMMON_KEEPER_EN		(1 << 26)
>  
>  /* CNL Port TX registers */
> -- 
> 2.14.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register
  2018-03-09 19:55   ` Rodrigo Vivi
@ 2018-03-09 20:51     ` Lucas De Marchi
  2018-03-12  7:01       ` Kumar, Mahesh
  0 siblings, 1 reply; 10+ messages in thread
From: Lucas De Marchi @ 2018-03-09 20:51 UTC (permalink / raw)
  To: Rodrigo Vivi; +Cc: intel-gfx

On Fri, Mar 09, 2018 at 11:55:47AM -0800, Rodrigo Vivi wrote:
> On Fri, Mar 09, 2018 at 06:28:56PM +0530, Mahesh Kumar wrote:
> > This patch creates a new macro to get PORT_TX register for any given DW.
> > This will remove the need of defining register address for each port & DW.
> 
> please squash patches 1 and 2. I had to open both simultaneously to review it
> what indicates that they should be 1 patch.
> 
> > 
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
> >  1 file changed, 28 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e6a8c0ee7df1..30ef3513dc6f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1964,6 +1964,34 @@ enum i915_power_well_id {
> >  						    _CNL_PORT_PCS_DW1_LN0_F)
> >  #define   COMMON_KEEPER_EN		(1 << 26)
> >  
> > +/* CNL Port TX registers */
> > +#define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
> > +#define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
> > +#define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
> > +#define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
> > +#define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
> > +#define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
> > +#define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
> > +#define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
> > +#define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
> > +#define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
> > +#define CNL_PORT_TX_DW_GRP(port, dw)	(_PICK((port), \
> > +					       _CNL_PORT_TX_AE_GRP_OFFSET, \
> > +					       _CNL_PORT_TX_B_GRP_OFFSET, \
> > +					       _CNL_PORT_TX_B_GRP_OFFSET, \
> > +					       _CNL_PORT_TX_D_GRP_OFFSET, \
> > +					       _CNL_PORT_TX_AE_GRP_OFFSET, \
> > +					       _CNL_PORT_TX_F_GRP_OFFSET) + \
> > +					       4*(dw))
> 
> the math is right. I'm glad someone could see some logic on all these
> numbers. I with we had a basic offset and math for all the port registers, but...
> 
> > +#define CNL_PORT_TX_DW_LN0(port, dw)	(_PICK((port), \
> 
> who converts the offset to MMIO reg now?

I don't think this is supposed to be used outside the header is it?
I think it should have a underscore, because otherwise it's confusing
that CNL_PORT_TX_DW_LN0 returns an offsed and CNL_PORT_TX_DW[0-5]_LN0
return an mmio reg.

And if it's used elsewhere, maybe append _OFFSET to the macro?

Lucas De Marchi

> 
> > +					       _CNL_PORT_TX_AE_LN0_OFFSET, \
> > +					       _CNL_PORT_TX_B_LN0_OFFSET, \
> > +					       _CNL_PORT_TX_B_LN0_OFFSET, \
> > +					       _CNL_PORT_TX_D_LN0_OFFSET, \
> > +					       _CNL_PORT_TX_AE_LN0_OFFSET, \
> > +					       _CNL_PORT_TX_F_LN0_OFFSET) + \
> > +					       4*(dw))
> > +
> >  #define _CNL_PORT_TX_DW2_GRP_AE		0x162348
> >  #define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
> >  #define _CNL_PORT_TX_DW2_GRP_C		0x162B48
> > -- 
> > 2.14.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register
  2018-03-09 20:51     ` Lucas De Marchi
@ 2018-03-12  7:01       ` Kumar, Mahesh
  0 siblings, 0 replies; 10+ messages in thread
From: Kumar, Mahesh @ 2018-03-12  7:01 UTC (permalink / raw)
  To: Lucas De Marchi, Rodrigo Vivi; +Cc: intel-gfx

Hi,


On 3/10/2018 2:21 AM, Lucas De Marchi wrote:
> On Fri, Mar 09, 2018 at 11:55:47AM -0800, Rodrigo Vivi wrote:
>> On Fri, Mar 09, 2018 at 06:28:56PM +0530, Mahesh Kumar wrote:
>>> This patch creates a new macro to get PORT_TX register for any given DW.
>>> This will remove the need of defining register address for each port & DW.
>> please squash patches 1 and 2. I had to open both simultaneously to review it
>> what indicates that they should be 1 patch.
ok, will merge.
>>
>>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
>>>   1 file changed, 28 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index e6a8c0ee7df1..30ef3513dc6f 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -1964,6 +1964,34 @@ enum i915_power_well_id {
>>>   						    _CNL_PORT_PCS_DW1_LN0_F)
>>>   #define   COMMON_KEEPER_EN		(1 << 26)
>>>   
>>> +/* CNL Port TX registers */
>>> +#define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
>>> +#define _CNL_PORT_TX_B_GRP_OFFSET		0x1623C0
>>> +#define _CNL_PORT_TX_C_GRP_OFFSET		0x162B40
>>> +#define _CNL_PORT_TX_D_GRP_OFFSET		0x162BC0
>>> +#define _CNL_PORT_TX_F_GRP_OFFSET		0x162A40
>>> +#define _CNL_PORT_TX_AE_LN0_OFFSET		0x162440
>>> +#define _CNL_PORT_TX_B_LN0_OFFSET		0x162640
>>> +#define _CNL_PORT_TX_C_LN0_OFFSET		0x162C40
>>> +#define _CNL_PORT_TX_D_LN0_OFFSET		0x162E40
>>> +#define _CNL_PORT_TX_F_LN0_OFFSET		0x162840
>>> +#define CNL_PORT_TX_DW_GRP(port, dw)	(_PICK((port), \
>>> +					       _CNL_PORT_TX_AE_GRP_OFFSET, \
>>> +					       _CNL_PORT_TX_B_GRP_OFFSET, \
>>> +					       _CNL_PORT_TX_B_GRP_OFFSET, \
>>> +					       _CNL_PORT_TX_D_GRP_OFFSET, \
>>> +					       _CNL_PORT_TX_AE_GRP_OFFSET, \
>>> +					       _CNL_PORT_TX_F_GRP_OFFSET) + \
>>> +					       4*(dw))
>> the math is right. I'm glad someone could see some logic on all these
>> numbers. I with we had a basic offset and math for all the port registers, but...
>>
>>> +#define CNL_PORT_TX_DW_LN0(port, dw)	(_PICK((port), \
>> who converts the offset to MMIO reg now?
caller of this macro converts it to MMIO reg
> I don't think this is supposed to be used outside the header is it?
> I think it should have a underscore, because otherwise it's confusing
> that CNL_PORT_TX_DW_LN0 returns an offsed and CNL_PORT_TX_DW[0-5]_LN0
> return an mmio reg.
hmm, agree, will add underscore to the macros.
>
> And if it's used elsewhere, maybe append _OFFSET to the macro?
this isn't intended to be used outside of header file.
-Mahesh
>
> Lucas De Marchi
>
>>> +					       _CNL_PORT_TX_AE_LN0_OFFSET, \
>>> +					       _CNL_PORT_TX_B_LN0_OFFSET, \
>>> +					       _CNL_PORT_TX_B_LN0_OFFSET, \
>>> +					       _CNL_PORT_TX_D_LN0_OFFSET, \
>>> +					       _CNL_PORT_TX_AE_LN0_OFFSET, \
>>> +					       _CNL_PORT_TX_F_LN0_OFFSET) + \
>>> +					       4*(dw))
>>> +
>>>   #define _CNL_PORT_TX_DW2_GRP_AE		0x162348
>>>   #define _CNL_PORT_TX_DW2_GRP_B		0x1623C8
>>>   #define _CNL_PORT_TX_DW2_GRP_C		0x162B48
>>> -- 
>>> 2.14.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-03-12  7:01 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-09 12:58 [PATCH 0/3] CNL port refactoring Mahesh Kumar
2018-03-09 12:58 ` [PATCH 1/3] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar
2018-03-09 19:55   ` Rodrigo Vivi
2018-03-09 20:51     ` Lucas De Marchi
2018-03-12  7:01       ` Kumar, Mahesh
2018-03-09 12:58 ` [PATCH 2/3] drm/i915/cnl: Replace PORT_TX register macros with new ones Mahesh Kumar
2018-03-09 12:58 ` [PATCH 3/3] drm/i915/cnl: Kill _MMIO_PORT6 macro Mahesh Kumar
2018-03-09 19:56   ` Rodrigo Vivi
2018-03-09 14:02 ` ✓ Fi.CI.BAT: success for CNL port refactoring (rev2) Patchwork
2018-03-09 17:31 ` ✓ Fi.CI.IGT: " Patchwork

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