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From: Andre Przywara <andre.przywara@linaro.org>
To: Stefano Stabellini <sstabellini@kernel.org>,
	Julien Grall <julien.grall@arm.com>
Cc: xen-devel@lists.xenproject.org
Subject: [PATCH 17/17] ARM: GICv2: fix GICH_V2_LR definitions
Date: Fri,  9 Mar 2018 15:11:33 +0000	[thread overview]
Message-ID: <20180309151133.31371-18-andre.przywara@linaro.org> (raw)
In-Reply-To: <20180309151133.31371-1-andre.przywara@linaro.org>

The bit definition for the CPUID mask in the GICv2 LR register was
wrong, fortunately the current implementation does not use that bit.
Fix it up (it's starting at bit 10, not bit 9) and clean up some
nearby definitions on the way.
This will be used by the new VGIC shortly.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
---
 xen/arch/arm/gic-v2.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index fa9afc2be8..f16e17c1a3 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -57,10 +57,11 @@
 #define GICH_V2_LR_HW_MASK         0x1
 #define GICH_V2_LR_GRP_SHIFT       30
 #define GICH_V2_LR_GRP_MASK        0x1
-#define GICH_V2_LR_MAINTENANCE_IRQ (1<<19)
-#define GICH_V2_LR_GRP1            (1<<30)
-#define GICH_V2_LR_HW              (1<<31)
-#define GICH_V2_LR_CPUID_SHIFT     9
+#define GICH_V2_LR_MAINTENANCE_IRQ (1U << 19)
+#define GICH_V2_LR_GRP1            (1U << 30)
+#define GICH_V2_LR_HW              (1U << GICH_V2_LR_HW_SHIFT)
+#define GICH_V2_LR_CPUID_SHIFT     10
+#define GICH_V2_LR_CPUID_MASK      0x7
 #define GICH_V2_VTR_NRLRGS         0x3f
 
 #define GICH_V2_VMCR_PRIORITY_MASK   0x1f
-- 
2.14.1


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  parent reply	other threads:[~2018-03-09 15:12 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-09 15:11 [PATCH 00/17] ARM: vGIC: prepare for splitting the vGIC code Andre Przywara
2018-03-09 15:11 ` [PATCH 01/17] ARM: vGICv3: clarify on GUEST_GICV3_RDIST_REGIONS symbol Andre Przywara
2018-03-09 15:11 ` [PATCH 02/17] ARM: GICv3: use hardware GICv3 redistributor values for Dom0 Andre Przywara
2018-03-09 15:11 ` [PATCH 03/17] ARM: vGICv3: always use architected redist stride Andre Przywara
2018-03-12 11:08   ` Julien Grall
2018-03-09 15:11 ` [PATCH 04/17] ARM: vGICv3: remove rdist_stride from VGIC structure Andre Przywara
2018-03-09 15:11 ` [PATCH 05/17] ARM: VGIC: rename gic_inject() and gic_clear_lrs() Andre Przywara
2018-03-09 15:11 ` [PATCH 06/17] ARM: VGIC: Move gic_remove_from_lr_pending() prototype Andre Przywara
2018-03-09 15:11 ` [PATCH 07/17] ARM: VGIC: Adjust domain_max_vcpus() to be VGIC specific Andre Przywara
2018-03-12 11:09   ` Julien Grall
2018-03-09 15:11 ` [PATCH 08/17] ARM: VGIC: rename gic_event_needs_delivery() Andre Przywara
2018-03-12 11:10   ` Julien Grall
2018-03-09 15:11 ` [PATCH 09/17] ARM: VGIC: change to level-IRQ compatible IRQ injection interface Andre Przywara
2018-03-12 11:29   ` Julien Grall
2018-03-09 15:11 ` [PATCH 10/17] ARM: VGIC: carve out struct vgic_cpu and struct vgic_dist Andre Przywara
2018-03-09 15:11 ` [PATCH 11/17] ARM: VGIC: reorder prototypes in vgic.h Andre Przywara
2018-03-09 15:11 ` [PATCH 12/17] ARM: VGIC: Introduce gic_get_nr_lrs() Andre Przywara
2018-03-09 15:11 ` [PATCH 13/17] ARM: GICv3: rename HYP interface definitions to use ICH_ prefix Andre Przywara
2018-03-09 15:11 ` [PATCH 14/17] ARM: Implement vcpu_kick() Andre Przywara
2018-03-12 11:41   ` Julien Grall
2018-03-09 15:11 ` [PATCH 15/17] ARM: GICv2: introduce gicv2_poke_irq() Andre Przywara
2018-03-09 15:11 ` [PATCH 16/17] ARM: GICv3: poke_irq: make RWP optional Andre Przywara
2018-03-09 15:11 ` Andre Przywara [this message]
2018-03-12 12:08 ` [PATCH 00/17] ARM: vGIC: prepare for splitting the vGIC code Julien Grall

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