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From: Andre Przywara <andre.przywara@linaro.org>
To: Stefano Stabellini <sstabellini@kernel.org>,
	Julien Grall <julien.grall@arm.com>
Cc: xen-devel@lists.xenproject.org
Subject: [PATCH 07/17] ARM: VGIC: Adjust domain_max_vcpus() to be VGIC specific
Date: Fri,  9 Mar 2018 15:11:23 +0000	[thread overview]
Message-ID: <20180309151133.31371-8-andre.przywara@linaro.org> (raw)
In-Reply-To: <20180309151133.31371-1-andre.przywara@linaro.org>

domain_max_vcpus(), which is used by generic Xen code, returns the
maximum number of VCPUs for a domain, which on ARM is mostly limited by
the VGIC model emulated (a (v)GICv2 can only handle 8 CPUs).
Our current implementation lives in arch/arm/domain.c, but reaches into
VGIC internal data structures.
Move the actual functionality into vgic.c, and provide a shim in
domain.h, to keep this VGIC internal.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
---
Changelog:
- rename helper function and wrap in domain.h

 xen/arch/arm/domain.c        | 14 --------------
 xen/arch/arm/vgic.c          | 14 ++++++++++++++
 xen/include/asm-arm/domain.h |  6 +++++-
 xen/include/asm-arm/vgic.h   |  2 ++
 4 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 8de4c0a343..6b902fa30f 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -967,20 +967,6 @@ void vcpu_block_unless_event_pending(struct vcpu *v)
         vcpu_unblock(current);
 }
 
-unsigned int domain_max_vcpus(const struct domain *d)
-{
-    /*
-     * Since evtchn_init would call domain_max_vcpus for poll_mask
-     * allocation when the vgic_ops haven't been initialised yet,
-     * we return MAX_VIRT_CPUS if d->arch.vgic.handler is null.
-     */
-    if ( !d->arch.vgic.handler )
-        return MAX_VIRT_CPUS;
-    else
-        return min_t(unsigned int, MAX_VIRT_CPUS,
-                     d->arch.vgic.handler->max_vcpus);
-}
-
 /*
  * Local variables:
  * mode: C
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 34269bcf27..fa00c21a69 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -665,6 +665,20 @@ void vgic_free_virq(struct domain *d, unsigned int virq)
     clear_bit(virq, d->arch.vgic.allocated_irqs);
 }
 
+unsigned int vgic_max_vcpus(const struct domain *d)
+{
+    /*
+     * Since evtchn_init would call domain_max_vcpus for poll_mask
+     * allocation when the vgic_ops haven't been initialised yet,
+     * we return MAX_VIRT_CPUS if d->arch.vgic.handler is null.
+     */
+    if ( !d->arch.vgic.handler )
+        return MAX_VIRT_CPUS;
+    else
+        return min_t(unsigned int, MAX_VIRT_CPUS,
+                     d->arch.vgic.handler->max_vcpus);
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index c6aa5cf389..e730e07fcf 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -289,7 +289,11 @@ void vcpu_show_execution_state(struct vcpu *);
 void vcpu_show_registers(const struct vcpu *);
 void vcpu_switch_to_aarch64_mode(struct vcpu *);
 
-unsigned int domain_max_vcpus(const struct domain *);
+/* On ARM, the number of VCPUs is limited by the type of GIC emulated. */
+static inline unsigned int domain_max_vcpus(const struct domain *d)
+{
+    return vgic_max_vcpus(d);
+}
 
 /*
  * Due to the restriction of GICv3, the number of vCPUs in AFF0 is
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index d03298e12c..afb4776ad4 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -254,6 +254,8 @@ static inline int vgic_allocate_spi(struct domain *d)
 
 extern void vgic_free_virq(struct domain *d, unsigned int virq);
 
+unsigned int vgic_max_vcpus(const struct domain *d);
+
 void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
                       paddr_t vbase, uint32_t aliased_offset);
 
-- 
2.14.1


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  parent reply	other threads:[~2018-03-09 15:11 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-09 15:11 [PATCH 00/17] ARM: vGIC: prepare for splitting the vGIC code Andre Przywara
2018-03-09 15:11 ` [PATCH 01/17] ARM: vGICv3: clarify on GUEST_GICV3_RDIST_REGIONS symbol Andre Przywara
2018-03-09 15:11 ` [PATCH 02/17] ARM: GICv3: use hardware GICv3 redistributor values for Dom0 Andre Przywara
2018-03-09 15:11 ` [PATCH 03/17] ARM: vGICv3: always use architected redist stride Andre Przywara
2018-03-12 11:08   ` Julien Grall
2018-03-09 15:11 ` [PATCH 04/17] ARM: vGICv3: remove rdist_stride from VGIC structure Andre Przywara
2018-03-09 15:11 ` [PATCH 05/17] ARM: VGIC: rename gic_inject() and gic_clear_lrs() Andre Przywara
2018-03-09 15:11 ` [PATCH 06/17] ARM: VGIC: Move gic_remove_from_lr_pending() prototype Andre Przywara
2018-03-09 15:11 ` Andre Przywara [this message]
2018-03-12 11:09   ` [PATCH 07/17] ARM: VGIC: Adjust domain_max_vcpus() to be VGIC specific Julien Grall
2018-03-09 15:11 ` [PATCH 08/17] ARM: VGIC: rename gic_event_needs_delivery() Andre Przywara
2018-03-12 11:10   ` Julien Grall
2018-03-09 15:11 ` [PATCH 09/17] ARM: VGIC: change to level-IRQ compatible IRQ injection interface Andre Przywara
2018-03-12 11:29   ` Julien Grall
2018-03-09 15:11 ` [PATCH 10/17] ARM: VGIC: carve out struct vgic_cpu and struct vgic_dist Andre Przywara
2018-03-09 15:11 ` [PATCH 11/17] ARM: VGIC: reorder prototypes in vgic.h Andre Przywara
2018-03-09 15:11 ` [PATCH 12/17] ARM: VGIC: Introduce gic_get_nr_lrs() Andre Przywara
2018-03-09 15:11 ` [PATCH 13/17] ARM: GICv3: rename HYP interface definitions to use ICH_ prefix Andre Przywara
2018-03-09 15:11 ` [PATCH 14/17] ARM: Implement vcpu_kick() Andre Przywara
2018-03-12 11:41   ` Julien Grall
2018-03-09 15:11 ` [PATCH 15/17] ARM: GICv2: introduce gicv2_poke_irq() Andre Przywara
2018-03-09 15:11 ` [PATCH 16/17] ARM: GICv3: poke_irq: make RWP optional Andre Przywara
2018-03-09 15:11 ` [PATCH 17/17] ARM: GICv2: fix GICH_V2_LR definitions Andre Przywara
2018-03-12 12:08 ` [PATCH 00/17] ARM: vGIC: prepare for splitting the vGIC code Julien Grall

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