* [CI 1/4] drm/i915/guc: Tidy guc_log_control
@ 2018-03-09 16:40 Chris Wilson
2018-03-09 16:40 ` [CI 2/4] drm/i915/guc: Create common entry points for log register/unregister Chris Wilson
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Chris Wilson @ 2018-03-09 16:40 UTC (permalink / raw)
To: intel-gfx
From: Michał Winiarski <michal.winiarski@intel.com>
We plan to decouple log runtime (mapping + relay) from verbosity control.
Let's tidy the code now to reduce the churn in the following patches.
v2: Tidy macros, keep debug messages, use helper var for enable,
correct typo (Michał)
Fix incorrect input validaction (Sagar)
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180308154707.21716-1-michal.winiarski@intel.com
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 ++---
drivers/gpu/drm/i915/intel_guc_log.c | 80 +++++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_guc_log.h | 3 +-
3 files changed, 53 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 34d12522a1da..c4cc8fef11a0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2499,13 +2499,10 @@ static int i915_guc_log_control_get(void *data, u64 *val)
{
struct drm_i915_private *dev_priv = data;
- if (!HAS_GUC(dev_priv))
+ if (!USES_GUC(dev_priv))
return -ENODEV;
- if (!dev_priv->guc.log.vma)
- return -EINVAL;
-
- *val = i915_modparams.guc_log_level;
+ *val = intel_guc_log_control_get(&dev_priv->guc);
return 0;
}
@@ -2514,10 +2511,10 @@ static int i915_guc_log_control_set(void *data, u64 val)
{
struct drm_i915_private *dev_priv = data;
- if (!HAS_GUC(dev_priv))
+ if (!USES_GUC(dev_priv))
return -ENODEV;
- return intel_guc_log_control(&dev_priv->guc, val);
+ return intel_guc_log_control_set(&dev_priv->guc, val);
}
DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index c0c2e7d1c7d7..7e59fb07b06b 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -659,51 +659,63 @@ void intel_guc_log_destroy(struct intel_guc *guc)
i915_vma_unpin_and_release(&guc->log.vma);
}
-int intel_guc_log_control(struct intel_guc *guc, u64 control_val)
+int intel_guc_log_control_get(struct intel_guc *guc)
+{
+ GEM_BUG_ON(!guc->log.vma);
+ GEM_BUG_ON(i915_modparams.guc_log_level < 0);
+
+ return i915_modparams.guc_log_level;
+}
+
+#define GUC_LOG_LEVEL_DISABLED 0
+#define LOG_LEVEL_TO_ENABLED(x) ((x) > 0)
+#define LOG_LEVEL_TO_VERBOSITY(x) ({ \
+ typeof(x) _x = (x); \
+ LOG_LEVEL_TO_ENABLED(_x) ? _x - 1 : 0; \
+})
+#define VERBOSITY_TO_LOG_LEVEL(x) ((x) + 1)
+int intel_guc_log_control_set(struct intel_guc *guc, u64 val)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- bool enable_logging = control_val > 0;
- u32 verbosity;
+ bool enabled = LOG_LEVEL_TO_ENABLED(val);
int ret;
- if (!guc->log.vma)
- return -ENODEV;
+ BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN != 0);
+ GEM_BUG_ON(!guc->log.vma);
+ GEM_BUG_ON(i915_modparams.guc_log_level < 0);
- BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN);
- if (control_val > 1 + GUC_LOG_VERBOSITY_MAX)
+ /*
+ * GuC is recognizing log levels starting from 0 to max, we're using 0
+ * as indication that logging should be disabled.
+ */
+ if (val < GUC_LOG_LEVEL_DISABLED ||
+ val > VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX))
return -EINVAL;
- /* This combination doesn't make sense & won't have any effect */
- if (!enable_logging && !i915_modparams.guc_log_level)
- return 0;
+ mutex_lock(&dev_priv->drm.struct_mutex);
- verbosity = enable_logging ? control_val - 1 : 0;
+ if (i915_modparams.guc_log_level == val) {
+ ret = 0;
+ goto out_unlock;
+ }
- ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
- if (ret)
- return ret;
intel_runtime_pm_get(dev_priv);
- ret = guc_log_control(guc, enable_logging, verbosity);
+ ret = guc_log_control(guc, enabled, LOG_LEVEL_TO_VERBOSITY(val));
intel_runtime_pm_put(dev_priv);
- mutex_unlock(&dev_priv->drm.struct_mutex);
-
- if (ret < 0) {
- DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
- return ret;
+ if (ret) {
+ DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
+ goto out_unlock;
}
- if (enable_logging) {
- i915_modparams.guc_log_level = 1 + verbosity;
+ i915_modparams.guc_log_level = val;
- /*
- * If log was disabled at boot time, then the relay channel file
- * wouldn't have been created by now and interrupts also would
- * not have been enabled. Try again now, just in case.
- */
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+
+ if (enabled && !guc_log_has_runtime(guc)) {
ret = guc_log_late_setup(guc);
- if (ret < 0) {
+ if (ret) {
DRM_DEBUG_DRIVER("GuC log late setup failed %d\n", ret);
- return ret;
+ goto out;
}
/* GuC logging is currently the only user of Guc2Host interrupts */
@@ -712,7 +724,7 @@ int intel_guc_log_control(struct intel_guc *guc, u64 control_val)
gen9_enable_guc_interrupts(dev_priv);
intel_runtime_pm_put(dev_priv);
mutex_unlock(&dev_priv->drm.struct_mutex);
- } else {
+ } else if (!enabled && guc_log_has_runtime(guc)) {
/*
* Once logging is disabled, GuC won't generate logs & send an
* interrupt. But there could be some data in the log buffer
@@ -720,11 +732,13 @@ int intel_guc_log_control(struct intel_guc *guc, u64 control_val)
* buffer state and then collect the left over logs.
*/
guc_flush_logs(guc);
-
- /* As logging is disabled, update log level to reflect that */
- i915_modparams.guc_log_level = 0;
}
+ return 0;
+
+out_unlock:
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+out:
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_guc_log.h b/drivers/gpu/drm/i915/intel_guc_log.h
index dab0e949567a..141ce9ca22ce 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/intel_guc_log.h
@@ -64,7 +64,8 @@ void intel_guc_log_destroy(struct intel_guc *guc);
void intel_guc_log_init_early(struct intel_guc *guc);
int intel_guc_log_relay_create(struct intel_guc *guc);
void intel_guc_log_relay_destroy(struct intel_guc *guc);
-int intel_guc_log_control(struct intel_guc *guc, u64 control_val);
+int intel_guc_log_control_get(struct intel_guc *guc);
+int intel_guc_log_control_set(struct intel_guc *guc, u64 control_val);
void i915_guc_log_register(struct drm_i915_private *dev_priv);
void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
--
2.16.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [CI 2/4] drm/i915/guc: Create common entry points for log register/unregister
2018-03-09 16:40 [CI 1/4] drm/i915/guc: Tidy guc_log_control Chris Wilson
@ 2018-03-09 16:40 ` Chris Wilson
2018-03-09 16:40 ` [CI 3/4] drm/i915/guc: Move GuC notification handling to separate function Chris Wilson
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2018-03-09 16:40 UTC (permalink / raw)
To: intel-gfx
From: Michał Winiarski <michal.winiarski@intel.com>
We have many functions responsible for allocating different parts of
GuC log runtime called from multiple places. Let's stick with keeping
everything in guc_log_register instead.
v2: Use more generic intel_uc_register name, keep using "misc" suffix (Michał)
s/dev_priv/i915 (Sagar)
Make guc_log_relay_* static (sparse)
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180308154707.21716-2-michal.winiarski@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/intel_guc_log.c | 156 ++++++++++++++---------------------
drivers/gpu/drm/i915/intel_guc_log.h | 6 +-
drivers/gpu/drm/i915/intel_uc.c | 41 +++++----
drivers/gpu/drm/i915/intel_uc.h | 2 +
5 files changed, 95 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d7c4de45644d..987c6770d1a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1238,9 +1238,11 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
/* Reveal our presence to userspace */
if (drm_dev_register(dev, 0) == 0) {
i915_debugfs_register(dev_priv);
- i915_guc_log_register(dev_priv);
i915_setup_sysfs(dev_priv);
+ /* Depends on debugfs having been initialized */
+ intel_uc_register(dev_priv);
+
/* Depends on sysfs having been initialized */
i915_perf_register(dev_priv);
} else
@@ -1298,7 +1300,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv)
i915_pmu_unregister(dev_priv);
i915_teardown_sysfs(dev_priv);
- i915_guc_log_unregister(dev_priv);
+ intel_uc_unregister(dev_priv);
drm_dev_unregister(&dev_priv->drm);
i915_gem_shrinker_unregister(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 7e59fb07b06b..90b395f34808 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -443,7 +443,7 @@ void intel_guc_log_init_early(struct intel_guc *guc)
INIT_WORK(&guc->log.runtime.flush_work, capture_logs_work);
}
-int intel_guc_log_relay_create(struct intel_guc *guc)
+static int guc_log_relay_create(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct rchan *guc_log_relay_chan;
@@ -496,7 +496,7 @@ int intel_guc_log_relay_create(struct intel_guc *guc)
return ret;
}
-void intel_guc_log_relay_destroy(struct intel_guc *guc)
+static void guc_log_relay_destroy(struct intel_guc *guc)
{
mutex_lock(&guc->log.runtime.relay_lock);
@@ -514,49 +514,6 @@ void intel_guc_log_relay_destroy(struct intel_guc *guc)
mutex_unlock(&guc->log.runtime.relay_lock);
}
-static int guc_log_late_setup(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- int ret;
-
- if (!guc_log_has_runtime(guc)) {
- /*
- * If log was disabled at boot time, then setup needed to handle
- * log buffer flush interrupts would not have been done yet, so
- * do that now.
- */
- ret = intel_guc_log_relay_create(guc);
- if (ret)
- goto err;
-
- mutex_lock(&dev_priv->drm.struct_mutex);
- intel_runtime_pm_get(dev_priv);
- ret = guc_log_runtime_create(guc);
- intel_runtime_pm_put(dev_priv);
- mutex_unlock(&dev_priv->drm.struct_mutex);
-
- if (ret)
- goto err_relay;
- }
-
- ret = guc_log_relay_file_create(guc);
- if (ret)
- goto err_runtime;
-
- return 0;
-
-err_runtime:
- mutex_lock(&dev_priv->drm.struct_mutex);
- guc_log_runtime_destroy(guc);
- mutex_unlock(&dev_priv->drm.struct_mutex);
-err_relay:
- intel_guc_log_relay_destroy(guc);
-err:
- /* logging will remain off */
- i915_modparams.guc_log_level = 0;
- return ret;
-}
-
static void guc_log_capture_logs(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -576,16 +533,6 @@ static void guc_flush_logs(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
- if (!USES_GUC_SUBMISSION(dev_priv) || !i915_modparams.guc_log_level)
- return;
-
- /* First disable the interrupts, will be renabled afterwards */
- mutex_lock(&dev_priv->drm.struct_mutex);
- intel_runtime_pm_get(dev_priv);
- gen9_disable_guc_interrupts(dev_priv);
- intel_runtime_pm_put(dev_priv);
- mutex_unlock(&dev_priv->drm.struct_mutex);
-
/*
* Before initiating the forceful flush, wait for any pending/ongoing
* flush to complete otherwise forceful flush may not actually happen.
@@ -628,12 +575,6 @@ int intel_guc_log_create(struct intel_guc *guc)
guc->log.vma = vma;
- if (i915_modparams.guc_log_level) {
- ret = guc_log_runtime_create(guc);
- if (ret < 0)
- goto err_vma;
- }
-
/* each allocated unit is a page */
flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
(GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
@@ -645,8 +586,6 @@ int intel_guc_log_create(struct intel_guc *guc)
return 0;
-err_vma:
- i915_vma_unpin_and_release(&guc->log.vma);
err:
/* logging will be off */
i915_modparams.guc_log_level = 0;
@@ -712,26 +651,14 @@ int intel_guc_log_control_set(struct intel_guc *guc, u64 val)
mutex_unlock(&dev_priv->drm.struct_mutex);
if (enabled && !guc_log_has_runtime(guc)) {
- ret = guc_log_late_setup(guc);
+ ret = intel_guc_log_register(guc);
if (ret) {
- DRM_DEBUG_DRIVER("GuC log late setup failed %d\n", ret);
+ /* logging will remain off */
+ i915_modparams.guc_log_level = 0;
goto out;
}
-
- /* GuC logging is currently the only user of Guc2Host interrupts */
- mutex_lock(&dev_priv->drm.struct_mutex);
- intel_runtime_pm_get(dev_priv);
- gen9_enable_guc_interrupts(dev_priv);
- intel_runtime_pm_put(dev_priv);
- mutex_unlock(&dev_priv->drm.struct_mutex);
} else if (!enabled && guc_log_has_runtime(guc)) {
- /*
- * Once logging is disabled, GuC won't generate logs & send an
- * interrupt. But there could be some data in the log buffer
- * which is yet to be captured. So request GuC to update the log
- * buffer state and then collect the left over logs.
- */
- guc_flush_logs(guc);
+ intel_guc_log_unregister(guc);
}
return 0;
@@ -742,29 +669,72 @@ int intel_guc_log_control_set(struct intel_guc *guc, u64 val)
return ret;
}
-void i915_guc_log_register(struct drm_i915_private *dev_priv)
+int intel_guc_log_register(struct intel_guc *guc)
{
- if (!USES_GUC_SUBMISSION(dev_priv) || !i915_modparams.guc_log_level)
- return;
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+ int ret;
+
+ GEM_BUG_ON(guc_log_has_runtime(guc));
+
+ /*
+ * If log was disabled at boot time, then setup needed to handle
+ * log buffer flush interrupts would not have been done yet, so
+ * do that now.
+ */
+ ret = guc_log_relay_create(guc);
+ if (ret)
+ goto err;
+
+ mutex_lock(&i915->drm.struct_mutex);
+ ret = guc_log_runtime_create(guc);
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ if (ret)
+ goto err_relay;
+
+ ret = guc_log_relay_file_create(guc);
+ if (ret)
+ goto err_runtime;
+
+ /* GuC logging is currently the only user of Guc2Host interrupts */
+ mutex_lock(&i915->drm.struct_mutex);
+ intel_runtime_pm_get(i915);
+ gen9_enable_guc_interrupts(i915);
+ intel_runtime_pm_put(i915);
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ return 0;
- guc_log_late_setup(&dev_priv->guc);
+err_runtime:
+ mutex_lock(&i915->drm.struct_mutex);
+ guc_log_runtime_destroy(guc);
+ mutex_unlock(&i915->drm.struct_mutex);
+err_relay:
+ guc_log_relay_destroy(guc);
+err:
+ return ret;
}
-void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
+void intel_guc_log_unregister(struct intel_guc *guc)
{
- struct intel_guc *guc = &dev_priv->guc;
+ struct drm_i915_private *i915 = guc_to_i915(guc);
- if (!USES_GUC_SUBMISSION(dev_priv))
- return;
+ /*
+ * Once logging is disabled, GuC won't generate logs & send an
+ * interrupt. But there could be some data in the log buffer
+ * which is yet to be captured. So request GuC to update the log
+ * buffer state and then collect the left over logs.
+ */
+ guc_flush_logs(guc);
- mutex_lock(&dev_priv->drm.struct_mutex);
+ mutex_lock(&i915->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
- intel_runtime_pm_get(dev_priv);
- gen9_disable_guc_interrupts(dev_priv);
- intel_runtime_pm_put(dev_priv);
+ intel_runtime_pm_get(i915);
+ gen9_disable_guc_interrupts(i915);
+ intel_runtime_pm_put(i915);
guc_log_runtime_destroy(guc);
- mutex_unlock(&dev_priv->drm.struct_mutex);
+ mutex_unlock(&i915->drm.struct_mutex);
- intel_guc_log_relay_destroy(guc);
+ guc_log_relay_destroy(guc);
}
diff --git a/drivers/gpu/drm/i915/intel_guc_log.h b/drivers/gpu/drm/i915/intel_guc_log.h
index 141ce9ca22ce..09dd2ef1933d 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.h
+++ b/drivers/gpu/drm/i915/intel_guc_log.h
@@ -62,11 +62,9 @@ struct intel_guc_log {
int intel_guc_log_create(struct intel_guc *guc);
void intel_guc_log_destroy(struct intel_guc *guc);
void intel_guc_log_init_early(struct intel_guc *guc);
-int intel_guc_log_relay_create(struct intel_guc *guc);
-void intel_guc_log_relay_destroy(struct intel_guc *guc);
int intel_guc_log_control_get(struct intel_guc *guc);
int intel_guc_log_control_set(struct intel_guc *guc, u64 control_val);
-void i915_guc_log_register(struct drm_i915_private *dev_priv);
-void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
+int intel_guc_log_register(struct intel_guc *guc);
+void intel_guc_log_unregister(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index e5bf0d37bf43..1c1a00df010b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -219,6 +219,28 @@ static void guc_free_load_err_log(struct intel_guc *guc)
i915_gem_object_put(guc->load_err_log);
}
+int intel_uc_register(struct drm_i915_private *i915)
+{
+ int ret = 0;
+
+ if (!USES_GUC(i915))
+ return 0;
+
+ if (i915_modparams.guc_log_level)
+ ret = intel_guc_log_register(&i915->guc);
+
+ return ret;
+}
+
+void intel_uc_unregister(struct drm_i915_private *i915)
+{
+ if (!USES_GUC(i915))
+ return;
+
+ if (i915_modparams.guc_log_level)
+ intel_guc_log_unregister(&i915->guc);
+}
+
static int guc_enable_communication(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -249,23 +271,10 @@ int intel_uc_init_misc(struct drm_i915_private *dev_priv)
return 0;
ret = intel_guc_init_wq(guc);
- if (ret) {
- DRM_ERROR("Couldn't allocate workqueues for GuC\n");
- goto err;
- }
-
- ret = intel_guc_log_relay_create(guc);
- if (ret) {
- DRM_ERROR("Couldn't allocate relay for GuC log\n");
- goto err_relay;
- }
+ if (ret)
+ return ret;
return 0;
-
-err_relay:
- intel_guc_fini_wq(guc);
-err:
- return ret;
}
void intel_uc_fini_misc(struct drm_i915_private *dev_priv)
@@ -276,8 +285,6 @@ void intel_uc_fini_misc(struct drm_i915_private *dev_priv)
return;
intel_guc_fini_wq(guc);
-
- intel_guc_log_relay_destroy(guc);
}
int intel_uc_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index f76d51d1ce70..d6af984cd789 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -31,6 +31,8 @@
void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
void intel_uc_init_early(struct drm_i915_private *dev_priv);
void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
+int intel_uc_register(struct drm_i915_private *dev_priv);
+void intel_uc_unregister(struct drm_i915_private *dev_priv);
void intel_uc_init_fw(struct drm_i915_private *dev_priv);
void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
int intel_uc_init_misc(struct drm_i915_private *dev_priv);
--
2.16.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [CI 3/4] drm/i915/guc: Move GuC notification handling to separate function
2018-03-09 16:40 [CI 1/4] drm/i915/guc: Tidy guc_log_control Chris Wilson
2018-03-09 16:40 ` [CI 2/4] drm/i915/guc: Create common entry points for log register/unregister Chris Wilson
@ 2018-03-09 16:40 ` Chris Wilson
2018-03-09 16:40 ` [CI 4/4] HAX: Enable GuC for CI Chris Wilson
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2018-03-09 16:40 UTC (permalink / raw)
To: intel-gfx
From: Michal Wajdeczko <michal.wajdeczko@intel.com>
To allow future code reuse. While here, fix comment style.
v2: Notifications are a separate thing - rename the handler (Sagar)
Suggested-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180308154707.21716-3-michal.winiarski@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 33 ++-------------------------------
drivers/gpu/drm/i915/intel_guc.c | 37 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_guc.h | 1 +
3 files changed, 40 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c8c29d8ecbab..828f3104488c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1766,37 +1766,8 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
{
- if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
- /* Sample the log buffer flush related bits & clear them out now
- * itself from the message identity register to minimize the
- * probability of losing a flush interrupt, when there are back
- * to back flush interrupts.
- * There can be a new flush interrupt, for different log buffer
- * type (like for ISR), whilst Host is handling one (for DPC).
- * Since same bit is used in message register for ISR & DPC, it
- * could happen that GuC sets the bit for 2nd interrupt but Host
- * clears out the bit on handling the 1st interrupt.
- */
- u32 msg, flush;
-
- msg = I915_READ(SOFT_SCRATCH(15));
- flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
- INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
- if (flush) {
- /* Clear the message bits that are handled */
- I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
-
- /* Handle flush interrupt in bottom half */
- queue_work(dev_priv->guc.log.runtime.flush_wq,
- &dev_priv->guc.log.runtime.flush_work);
-
- dev_priv->guc.log.flush_interrupt_count++;
- } else {
- /* Not clearing of unhandled event bits won't result in
- * re-triggering of the interrupt.
- */
- }
- }
+ if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
+ intel_guc_to_host_event_handler(&dev_priv->guc);
}
static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index ff08ea0ebf49..25f92291fd40 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -364,6 +364,43 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
return ret;
}
+void intel_guc_to_host_event_handler(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ u32 msg, flush;
+
+ /*
+ * Sample the log buffer flush related bits & clear them out now
+ * itself from the message identity register to minimize the
+ * probability of losing a flush interrupt, when there are back
+ * to back flush interrupts.
+ * There can be a new flush interrupt, for different log buffer
+ * type (like for ISR), whilst Host is handling one (for DPC).
+ * Since same bit is used in message register for ISR & DPC, it
+ * could happen that GuC sets the bit for 2nd interrupt but Host
+ * clears out the bit on handling the 1st interrupt.
+ */
+
+ msg = I915_READ(SOFT_SCRATCH(15));
+ flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
+ INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
+ if (flush) {
+ /* Clear the message bits that are handled */
+ I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
+
+ /* Handle flush interrupt in bottom half */
+ queue_work(guc->log.runtime.flush_wq,
+ &guc->log.runtime.flush_work);
+
+ guc->log.flush_interrupt_count++;
+ } else {
+ /*
+ * Not clearing of unhandled event bits won't result in
+ * re-triggering of the interrupt.
+ */
+ }
+}
+
int intel_guc_sample_forcewake(struct intel_guc *guc)
{
struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index b9424ac644ac..6d5aebe55039 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -125,6 +125,7 @@ int intel_guc_init(struct intel_guc *guc);
void intel_guc_fini(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
+void intel_guc_to_host_event_handler(struct intel_guc *guc);
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
int intel_guc_suspend(struct intel_guc *guc);
--
2.16.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [CI 4/4] HAX: Enable GuC for CI
2018-03-09 16:40 [CI 1/4] drm/i915/guc: Tidy guc_log_control Chris Wilson
2018-03-09 16:40 ` [CI 2/4] drm/i915/guc: Create common entry points for log register/unregister Chris Wilson
2018-03-09 16:40 ` [CI 3/4] drm/i915/guc: Move GuC notification handling to separate function Chris Wilson
@ 2018-03-09 16:40 ` Chris Wilson
2018-03-09 17:39 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control Patchwork
2018-03-09 22:48 ` ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2018-03-09 16:40 UTC (permalink / raw)
To: intel-gfx
From: Michal Wajdeczko <michal.wajdeczko@intel.com>
v2: except running with HYPERVISOR
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9d0ff4..3deae1e22974 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, 0) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1c1a00df010b..cfa21f6058a5 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
enable_guc |= ENABLE_GUC_LOAD_HUC;
/* Any platform specific fine-tuning can be done here */
+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+ enable_guc = 0;
return enable_guc;
}
--
2.16.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
2018-03-09 16:40 [CI 1/4] drm/i915/guc: Tidy guc_log_control Chris Wilson
` (2 preceding siblings ...)
2018-03-09 16:40 ` [CI 4/4] HAX: Enable GuC for CI Chris Wilson
@ 2018-03-09 17:39 ` Patchwork
2018-03-09 22:48 ` ✗ Fi.CI.IGT: failure " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2018-03-09 17:39 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
URL : https://patchwork.freedesktop.org/series/39710/
State : success
== Summary ==
Series 39710v1 series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
https://patchwork.freedesktop.org/api/1.0/series/39710/revisions/1/mbox/
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass -> DMESG-WARN (fi-cnl-y3) fdo#104951
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:421s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:425s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:370s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:501s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:277s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:490s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:493s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:482s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:468s
fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:403s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:581s
fi-cnl-y3 total:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:585s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:409s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:290s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:517s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:397s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:414s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:454s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:417s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:466s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:460s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:510s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:582s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:430s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:521s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:534s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:496s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:483s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:422s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:428s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:519s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:391s
Blacklisted hosts:
fi-cfl-u total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:508s
fi-cnl-drrs total:288 pass:257 dwarn:3 dfail:0 fail:0 skip:19 time:512s
2e2ef5a5221a7469ecd72c68ed15dd8b94e2e0c6 drm-tip: 2018y-03m-09d-14h-28m-10s UTC integration manifest
59dcd0fe0c8f HAX: Enable GuC for CI
d4bc41a8a9d6 drm/i915/guc: Move GuC notification handling to separate function
9ab68c44f5e7 drm/i915/guc: Create common entry points for log register/unregister
e0ff1976b21c drm/i915/guc: Tidy guc_log_control
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8295/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
2018-03-09 16:40 [CI 1/4] drm/i915/guc: Tidy guc_log_control Chris Wilson
` (3 preceding siblings ...)
2018-03-09 17:39 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control Patchwork
@ 2018-03-09 22:48 ` Patchwork
2018-03-10 11:07 ` Michał Winiarski
4 siblings, 1 reply; 8+ messages in thread
From: Patchwork @ 2018-03-09 22:48 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
URL : https://patchwork.freedesktop.org/series/39710/
State : failure
== Summary ==
---- Possible new issues:
Test drv_missed_irq:
pass -> SKIP (shard-apl)
Test drv_selftest:
Subgroup live_guc:
pass -> DMESG-WARN (shard-apl)
Test gem_exec_capture:
Subgroup capture-vebox:
pass -> FAIL (shard-apl)
Test perf:
Subgroup gen8-unprivileged-single-ctx-counters:
pass -> FAIL (shard-apl)
---- Known issues:
Test gem_eio:
Subgroup in-flight-contexts:
incomplete -> PASS (shard-apl) fdo#105341 +1
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
pass -> FAIL (shard-hsw) fdo#102887
Subgroup plain-flip-ts-check-interruptible:
fail -> PASS (shard-hsw) fdo#100368 +1
Test kms_plane_multiple:
Subgroup atomic-pipe-c-tiling-y:
pass -> FAIL (shard-apl) fdo#103166
fdo#105341 https://bugs.freedesktop.org/show_bug.cgi?id=105341
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
shard-apl total:3262 pass:1716 dwarn:2 dfail:0 fail:17 skip:1524 time:11509s
shard-hsw total:3467 pass:1770 dwarn:1 dfail:0 fail:3 skip:1692 time:11547s
shard-snb total:3467 pass:1365 dwarn:1 dfail:0 fail:1 skip:2100 time:6868s
Blacklisted hosts:
shard-kbl total:3168 pass:1779 dwarn:2 dfail:1 fail:18 skip:1364 time:8065s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8295/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
2018-03-09 22:48 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-03-10 11:07 ` Michał Winiarski
2018-03-10 11:24 ` Chris Wilson
0 siblings, 1 reply; 8+ messages in thread
From: Michał Winiarski @ 2018-03-10 11:07 UTC (permalink / raw)
To: intel-gfx
On Fri, Mar 09, 2018 at 10:48:29PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
> URL : https://patchwork.freedesktop.org/series/39710/
> State : failure
>
> == Summary ==
>
> ---- Possible new issues:
>
> Test drv_missed_irq:
> pass -> SKIP (shard-apl)
> Test drv_selftest:
> Subgroup live_guc:
> pass -> DMESG-WARN (shard-apl)
> Test gem_exec_capture:
> Subgroup capture-vebox:
> pass -> FAIL (shard-apl)
> Test perf:
> Subgroup gen8-unprivileged-single-ctx-counters:
> pass -> FAIL (shard-apl)
Note that drv_missed_irq, drv_selftest and perf are also failing without this
series (probably a good time to take a closer look at that).
I'm not sure what happened on gem_exec_capture (works for me):
[ 59.708020] [drm:error_state_write [i915]] Resetting error state
[ 59.708508] [IGT] gem_exec_capture: starting subtest capture-vebox
[ 59.718849] [drm] GPU HANG: ecode 9:0:0xfff7fffe, reason: Manually set
wedged engine mask = ffffffffffffffff, action: reset
[ 59.719421] i915 0000:00:02.0: Resetting vecs0 after gpu hang
[ 59.720276] [drm:i915_gem_reset_engine [i915]] resetting vecs0 to restart
from tail of request 0x1
[ 59.721008] [drm:i915_reset_device [i915]] resetting chip
[ 59.721226] i915 0000:00:02.0: Resetting chip after gpu hang
[ 59.721575] i915 0000:00:02.0: GPU recovery failed
-Michał
>
> ---- Known issues:
>
> Test gem_eio:
> Subgroup in-flight-contexts:
> incomplete -> PASS (shard-apl) fdo#105341 +1
> Test kms_flip:
> Subgroup 2x-flip-vs-expired-vblank:
> pass -> FAIL (shard-hsw) fdo#102887
> Subgroup plain-flip-ts-check-interruptible:
> fail -> PASS (shard-hsw) fdo#100368 +1
> Test kms_plane_multiple:
> Subgroup atomic-pipe-c-tiling-y:
> pass -> FAIL (shard-apl) fdo#103166
>
> fdo#105341 https://bugs.freedesktop.org/show_bug.cgi?id=105341
> fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
> fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
> fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
>
> shard-apl total:3262 pass:1716 dwarn:2 dfail:0 fail:17 skip:1524 time:11509s
> shard-hsw total:3467 pass:1770 dwarn:1 dfail:0 fail:3 skip:1692 time:11547s
> shard-snb total:3467 pass:1365 dwarn:1 dfail:0 fail:1 skip:2100 time:6868s
> Blacklisted hosts:
> shard-kbl total:3168 pass:1779 dwarn:2 dfail:1 fail:18 skip:1364 time:8065s
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8295/shards.html
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control
2018-03-10 11:07 ` Michał Winiarski
@ 2018-03-10 11:24 ` Chris Wilson
0 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2018-03-10 11:24 UTC (permalink / raw)
To: Michał Winiarski, intel-gfx
Quoting Michał Winiarski (2018-03-10 11:07:03)
> [ 59.708020] [drm:error_state_write [i915]] Resetting error state
> [ 59.708508] [IGT] gem_exec_capture: starting subtest capture-vebox
> [ 59.718849] [drm] GPU HANG: ecode 9:0:0xfff7fffe, reason: Manually set
> wedged engine mask = ffffffffffffffff, action: reset
> [ 59.719421] i915 0000:00:02.0: Resetting vecs0 after gpu hang
> [ 59.720276] [drm:i915_gem_reset_engine [i915]] resetting vecs0 to restart
> from tail of request 0x1
> [ 59.721008] [drm:i915_reset_device [i915]] resetting chip
> [ 59.721226] i915 0000:00:02.0: Resetting chip after gpu hang
> [ 59.721575] i915 0000:00:02.0: GPU recovery failed
Full device reset doesn't handle being called from a failed per-engine
reset. Whoops. It doesn't look there's any reason for it to have failed
per-engine reset either,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 828f3104488c..44eef355e12c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2985,6 +2985,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
*/
intel_runtime_pm_get(dev_priv);
+ engine_mask &= INTEL_INFO(dev_priv)->ring_mask;
i915_capture_error_state(dev_priv, engine_mask, error_msg);
i915_clear_error_registers(dev_priv);
should fix the immediate problem; but there's no reason afaict for this
to vary between test runs. As to how to properly ignore left-over state
from per-engine reset when doing the full-reset fallback... ugh.
-Chris
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^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-03-10 11:24 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-09 16:40 [CI 1/4] drm/i915/guc: Tidy guc_log_control Chris Wilson
2018-03-09 16:40 ` [CI 2/4] drm/i915/guc: Create common entry points for log register/unregister Chris Wilson
2018-03-09 16:40 ` [CI 3/4] drm/i915/guc: Move GuC notification handling to separate function Chris Wilson
2018-03-09 16:40 ` [CI 4/4] HAX: Enable GuC for CI Chris Wilson
2018-03-09 17:39 ` ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/guc: Tidy guc_log_control Patchwork
2018-03-09 22:48 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-03-10 11:07 ` Michał Winiarski
2018-03-10 11:24 ` Chris Wilson
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