All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v3 0/3] drm/i915/uc: Sanitize uC
@ 2018-03-12 13:03 Michal Wajdeczko
  2018-03-12 13:03 ` [PATCH v3 1/3] drm/i915/uc: Sanitize uC options early Michal Wajdeczko
                   ` (4 more replies)
  0 siblings, 5 replies; 9+ messages in thread
From: Michal Wajdeczko @ 2018-03-12 13:03 UTC (permalink / raw)
  To: intel-gfx

Attempt to sanitize uC for better alignment with rest of GEM driver.

v2: cover reset path and sanitize uc before gem
v3: drop now redundant disable_communication in uc_init_hw

Michal Wajdeczko (3):
  drm/i915/uc: Sanitize uC options early
  drm/i915/uc: Sanitize uC together with GEM
  HAX: Enable GuC for CI

 drivers/gpu/drm/i915/i915_drv.c    |  2 --
 drivers/gpu/drm/i915/i915_gem.c    |  2 ++
 drivers/gpu/drm/i915/i915_params.h |  2 +-
 drivers/gpu/drm/i915/intel_guc.h   |  6 ++++++
 drivers/gpu/drm/i915/intel_huc.h   |  6 ++++++
 drivers/gpu/drm/i915/intel_uc.c    | 27 ++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_uc.h    |  2 +-
 drivers/gpu/drm/i915/intel_uc_fw.h |  6 ++++++
 8 files changed, 46 insertions(+), 7 deletions(-)

-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH v3 1/3] drm/i915/uc: Sanitize uC options early
  2018-03-12 13:03 [PATCH v3 0/3] drm/i915/uc: Sanitize uC Michal Wajdeczko
@ 2018-03-12 13:03 ` Michal Wajdeczko
  2018-03-12 13:03 ` [PATCH v3 2/3] drm/i915/uc: Sanitize uC together with GEM Michal Wajdeczko
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 9+ messages in thread
From: Michal Wajdeczko @ 2018-03-12 13:03 UTC (permalink / raw)
  To: intel-gfx

We are sanitizing uC related modparams together with other driver
modparams in intel_sanitize_options called from i915_driver_init_hw,
but this is too late for us as we will want to use USES_GUC/USES_HUC
macros at earlier stage. Since our sanitizing does not require any
MMIO access, we can do it in intel_uc_init_early right after we resolve
firmware names.

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.c | 2 --
 drivers/gpu/drm/i915/intel_uc.c | 6 ++++--
 drivers/gpu/drm/i915/intel_uc.h | 1 -
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 987c677..0126b22 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1074,8 +1074,6 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 					    i915_modparams.enable_ppgtt);
 	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
 
-	intel_uc_sanitize_options(dev_priv);
-
 	intel_gvt_sanitize_options(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 1c1a00d..6dec6d6 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -83,7 +83,7 @@ static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
 }
 
 /**
- * intel_uc_sanitize_options - sanitize uC related modparam options
+ * sanitize_options_early - sanitize uC related modparam options
  * @dev_priv: device private
  *
  * In case of "enable_guc" option this function will attempt to modify
@@ -99,7 +99,7 @@ static int __get_default_guc_log_level(struct drm_i915_private *dev_priv)
  * unless GuC is enabled on given platform and the driver is compiled with
  * debug config when this modparam will default to "enable(1..4)".
  */
-void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
+static void sanitize_options_early(struct drm_i915_private *dev_priv)
 {
 	struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
 	struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
@@ -163,6 +163,8 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv)
 {
 	intel_guc_init_early(&dev_priv->guc);
 	intel_huc_init_early(&dev_priv->huc);
+
+	sanitize_options_early(dev_priv);
 }
 
 void intel_uc_init_fw(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index d6af984..49b5b2f 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -28,7 +28,6 @@
 #include "intel_huc.h"
 #include "i915_params.h"
 
-void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
 void intel_uc_init_early(struct drm_i915_private *dev_priv);
 void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
 int intel_uc_register(struct drm_i915_private *dev_priv);
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH v3 2/3] drm/i915/uc: Sanitize uC together with GEM
  2018-03-12 13:03 [PATCH v3 0/3] drm/i915/uc: Sanitize uC Michal Wajdeczko
  2018-03-12 13:03 ` [PATCH v3 1/3] drm/i915/uc: Sanitize uC options early Michal Wajdeczko
@ 2018-03-12 13:03 ` Michal Wajdeczko
  2018-03-12 13:03 ` [PATCH v3 3/3] HAX: Enable GuC for CI Michal Wajdeczko
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 9+ messages in thread
From: Michal Wajdeczko @ 2018-03-12 13:03 UTC (permalink / raw)
  To: intel-gfx

Instead of dancing around uC on reset/suspend/resume scenarios,
explicitly sanitize uC when we sanitize GEM to force uC reload
and start from known beginning.

v2: don't forget about reset path (Daniele)
    sanitize uc before gem initiated full reset (Daniele)
v3: drop redundant disable_communication in init_hw (Daniele)

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c    |  2 ++
 drivers/gpu/drm/i915/intel_guc.h   |  6 ++++++
 drivers/gpu/drm/i915/intel_huc.h   |  6 ++++++
 drivers/gpu/drm/i915/intel_uc.c    | 19 ++++++++++++++++++-
 drivers/gpu/drm/i915/intel_uc.h    |  1 +
 drivers/gpu/drm/i915/intel_uc_fw.h |  6 ++++++
 6 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e58b741..05b0724 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2998,6 +2998,7 @@ int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
 	}
 
 	i915_gem_revoke_fences(dev_priv);
+	intel_uc_sanitize(dev_priv);
 
 	return err;
 }
@@ -4978,6 +4979,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 	 * machines is a good idea, we don't - just in case it leaves the
 	 * machine in an unusable condition.
 	 */
+	intel_uc_sanitize(dev_priv);
 	i915_gem_sanitize(dev_priv);
 
 	intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 6d5aebe..d878160 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -133,4 +133,10 @@ static inline u32 guc_ggtt_offset(struct i915_vma *vma)
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
 
+static inline int intel_guc_sanitize(struct intel_guc *guc)
+{
+	intel_uc_fw_sanitize(&guc->fw);
+	return 0;
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 5d6e804..b185850 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -38,4 +38,10 @@ struct intel_huc {
 void intel_huc_init_early(struct intel_huc *huc);
 int intel_huc_auth(struct intel_huc *huc);
 
+static inline int intel_huc_sanitize(struct intel_huc *huc)
+{
+	intel_uc_fw_sanitize(&huc->fw);
+	return 0;
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 6dec6d6..9d5ffd7 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -334,6 +334,24 @@ void intel_uc_fini(struct drm_i915_private *dev_priv)
 	intel_guc_fini(guc);
 }
 
+void intel_uc_sanitize(struct drm_i915_private *i915)
+{
+	struct intel_guc *guc = &i915->guc;
+	struct intel_huc *huc = &i915->huc;
+
+	if (!USES_GUC(i915))
+		return;
+
+	GEM_BUG_ON(!HAS_GUC(i915));
+
+	guc_disable_communication(guc);
+
+	intel_huc_sanitize(huc);
+	intel_guc_sanitize(guc);
+
+	__intel_uc_reset_hw(i915);
+}
+
 int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
@@ -345,7 +363,6 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 
 	GEM_BUG_ON(!HAS_GUC(dev_priv));
 
-	guc_disable_communication(guc);
 	gen9_reset_guc_interrupts(dev_priv);
 
 	/* init WOPCM */
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 49b5b2f..0a2b413 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -36,6 +36,7 @@
 void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
 int intel_uc_init_misc(struct drm_i915_private *dev_priv);
 void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
+void intel_uc_sanitize(struct drm_i915_private *dev_priv);
 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
 int intel_uc_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
index d5fd460..2601521 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -115,6 +115,12 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)
 	return uc_fw->path != NULL;
 }
 
+static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw)
+{
+	if (uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS)
+		uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
+}
+
 void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
 		       struct intel_uc_fw *uc_fw);
 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH v3 3/3] HAX: Enable GuC for CI
  2018-03-12 13:03 [PATCH v3 0/3] drm/i915/uc: Sanitize uC Michal Wajdeczko
  2018-03-12 13:03 ` [PATCH v3 1/3] drm/i915/uc: Sanitize uC options early Michal Wajdeczko
  2018-03-12 13:03 ` [PATCH v3 2/3] drm/i915/uc: Sanitize uC together with GEM Michal Wajdeczko
@ 2018-03-12 13:03 ` Michal Wajdeczko
  2018-03-12 14:49 ` ✓ Fi.CI.BAT: success for drm/i915/uc: Sanitize uC (rev3) Patchwork
  2018-03-12 19:24 ` ✗ Fi.CI.IGT: failure " Patchwork
  4 siblings, 0 replies; 9+ messages in thread
From: Michal Wajdeczko @ 2018-03-12 13:03 UTC (permalink / raw)
  To: intel-gfx

v2: except running with HYPERVISOR

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 drivers/gpu/drm/i915/intel_uc.c    | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 430f5f9..3deae1e 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, -1) \
 	param(int, guc_log_level, 0) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9d5ffd7..c0d89b9 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -63,6 +63,8 @@ static int __get_platform_enable_guc(struct drm_i915_private *dev_priv)
 		enable_guc |= ENABLE_GUC_LOAD_HUC;
 
 	/* Any platform specific fine-tuning can be done here */
+	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
+		enable_guc = 0;
 
 	return enable_guc;
 }
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/uc: Sanitize uC (rev3)
  2018-03-12 13:03 [PATCH v3 0/3] drm/i915/uc: Sanitize uC Michal Wajdeczko
                   ` (2 preceding siblings ...)
  2018-03-12 13:03 ` [PATCH v3 3/3] HAX: Enable GuC for CI Michal Wajdeczko
@ 2018-03-12 14:49 ` Patchwork
  2018-03-12 19:24 ` ✗ Fi.CI.IGT: failure " Patchwork
  4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-03-12 14:49 UTC (permalink / raw)
  To: Michal Wajdeczko; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/uc: Sanitize uC (rev3)
URL   : https://patchwork.freedesktop.org/series/39634/
State : success

== Summary ==

Series 39634v3 drm/i915/uc: Sanitize uC
https://patchwork.freedesktop.org/api/1.0/series/39634/revisions/3/mbox/

---- Known issues:

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                fail       -> PASS       (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                pass       -> DMESG-WARN (fi-cnl-y3) fdo#104951

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:432s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:433s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:382s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:527s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:299s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:508s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:508s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:509s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:496s
fi-cfl-8700k     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:413s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:584s
fi-cnl-y3        total:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  time:592s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:419s
fi-gdg-551       total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 time:314s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:531s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:401s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:421s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:474s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:427s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:472s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:466s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:513s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:639s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:440s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:533s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:538s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:502s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:487s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:429s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:444s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:530s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:400s
Blacklisted hosts:
fi-cnl-drrs      total:288  pass:0    dwarn:0   dfail:0   fail:0   skip:0   time:3s

1bf8f00fed0b78f5d286304deb1f1526b10aeaca drm-tip: 2018y-03m-12d-11h-28m-33s UTC integration manifest
390c0688ad48 HAX: Enable GuC for CI
7181e0ab37c6 drm/i915/uc: Sanitize uC together with GEM
90dfc0bcd1dc drm/i915/uc: Sanitize uC options early

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8304/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/uc: Sanitize uC (rev3)
  2018-03-12 13:03 [PATCH v3 0/3] drm/i915/uc: Sanitize uC Michal Wajdeczko
                   ` (3 preceding siblings ...)
  2018-03-12 14:49 ` ✓ Fi.CI.BAT: success for drm/i915/uc: Sanitize uC (rev3) Patchwork
@ 2018-03-12 19:24 ` Patchwork
  2018-03-12 22:07   ` Chris Wilson
  4 siblings, 1 reply; 9+ messages in thread
From: Patchwork @ 2018-03-12 19:24 UTC (permalink / raw)
  To: Michal Wajdeczko; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/uc: Sanitize uC (rev3)
URL   : https://patchwork.freedesktop.org/series/39634/
State : failure

== Summary ==

---- Possible new issues:

Test drv_missed_irq:
                pass       -> SKIP       (shard-apl)
Test drv_selftest:
        Subgroup live_guc:
                pass       -> DMESG-WARN (shard-apl)
Test perf:
        Subgroup gen8-unprivileged-single-ctx-counters:
                pass       -> FAIL       (shard-apl)

---- Known issues:

Test gem_eio:
        Subgroup in-flight-external:
                pass       -> INCOMPLETE (shard-apl) fdo#105341 +1
Test kms_flip:
        Subgroup flip-vs-panning-vs-hang:
                pass       -> DMESG-WARN (shard-snb) fdo#103821
Test pm_lpsp:
        Subgroup screens-disabled:
                fail       -> PASS       (shard-hsw) fdo#104941

fdo#105341 https://bugs.freedesktop.org/show_bug.cgi?id=105341
fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#104941 https://bugs.freedesktop.org/show_bug.cgi?id=104941

shard-apl        total:3391 pass:1774 dwarn:2   dfail:0   fail:10  skip:1601 time:11819s
shard-hsw        total:3467 pass:1773 dwarn:1   dfail:0   fail:1   skip:1691 time:11910s
shard-snb        total:3467 pass:1363 dwarn:2   dfail:0   fail:2   skip:2100 time:7268s
Blacklisted hosts:
shard-kbl        total:3243 pass:1794 dwarn:3   dfail:1   fail:7   skip:1434 time:8685s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8304/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for drm/i915/uc: Sanitize uC (rev3)
  2018-03-12 19:24 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-03-12 22:07   ` Chris Wilson
  0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2018-03-12 22:07 UTC (permalink / raw)
  To: Patchwork, Michal Wajdeczko; +Cc: intel-gfx

Quoting Patchwork (2018-03-12 19:24:08)
> == Series Details ==
> 
> Series: drm/i915/uc: Sanitize uC (rev3)
> URL   : https://patchwork.freedesktop.org/series/39634/
> State : failure
> 
> == Summary ==
> 
> ---- Possible new issues:
> 
> Test drv_missed_irq:
>                 pass       -> SKIP       (shard-apl)
> Test drv_selftest:
>         Subgroup live_guc:
>                 pass       -> DMESG-WARN (shard-apl)
> Test perf:
>         Subgroup gen8-unprivileged-single-ctx-counters:
>                 pass       -> FAIL       (shard-apl)
> 
> ---- Known issues:
> 
> Test gem_eio:
>         Subgroup in-flight-external:
>                 pass       -> INCOMPLETE (shard-apl) fdo#105341 +1
> Test kms_flip:
>         Subgroup flip-vs-panning-vs-hang:
>                 pass       -> DMESG-WARN (shard-snb) fdo#103821
> Test pm_lpsp:
>         Subgroup screens-disabled:
>                 fail       -> PASS       (shard-hsw) fdo#104941

Nothing untoward. Thanks for the patches and review, pushed.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 9+ messages in thread
* [PATCH v3 3/3] HAX enable GuC for CI
  2018-06-28 14:15 [PATCH v3 1/3] drm/i915/guc: Use intel_guc_init_misc to hide GuC internals Michal Wajdeczko
@ 2018-06-28 14:15 ` Michal Wajdeczko
  0 siblings, 0 replies; 9+ messages in thread
From: Michal Wajdeczko @ 2018-06-28 14:15 UTC (permalink / raw)
  To: intel-gfx

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index aebe046..3e4e128 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, -1) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH v3 3/3] HAX: Enable GuC for CI
  2018-03-23 11:19 [PATCH v3 1/3] drm/i915: Reorder early initialization Michal Wajdeczko
@ 2018-03-23 11:19 ` Michal Wajdeczko
  0 siblings, 0 replies; 9+ messages in thread
From: Michal Wajdeczko @ 2018-03-23 11:19 UTC (permalink / raw)
  To: intel-gfx

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index c963603..53037b5 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -47,7 +47,7 @@
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
-	param(int, enable_guc, 0) \
+	param(int, enable_guc, -1) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
 	param(char *, huc_firmware_path, NULL) \
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-06-28 14:15 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-12 13:03 [PATCH v3 0/3] drm/i915/uc: Sanitize uC Michal Wajdeczko
2018-03-12 13:03 ` [PATCH v3 1/3] drm/i915/uc: Sanitize uC options early Michal Wajdeczko
2018-03-12 13:03 ` [PATCH v3 2/3] drm/i915/uc: Sanitize uC together with GEM Michal Wajdeczko
2018-03-12 13:03 ` [PATCH v3 3/3] HAX: Enable GuC for CI Michal Wajdeczko
2018-03-12 14:49 ` ✓ Fi.CI.BAT: success for drm/i915/uc: Sanitize uC (rev3) Patchwork
2018-03-12 19:24 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-03-12 22:07   ` Chris Wilson
2018-03-23 11:19 [PATCH v3 1/3] drm/i915: Reorder early initialization Michal Wajdeczko
2018-03-23 11:19 ` [PATCH v3 3/3] HAX: Enable GuC for CI Michal Wajdeczko
2018-06-28 14:15 [PATCH v3 1/3] drm/i915/guc: Use intel_guc_init_misc to hide GuC internals Michal Wajdeczko
2018-06-28 14:15 ` [PATCH v3 3/3] HAX enable GuC for CI Michal Wajdeczko

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.