* [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc for imx6sll
@ 2018-03-12 9:36 Bai Ping
2018-03-12 9:36 ` [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support " Bai Ping
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Bai Ping @ 2018-03-12 9:36 UTC (permalink / raw)
To: linux-arm-kernel
Add pinctrl binding doc update for imx6sll.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
changes v2-v3:
- add generic config binding
change v3->v4:
- add SION bit define
- fix typo
- move the pin header file to dts patch.
change v4->5:
- drop generic config, use the old fsl pin config style
---
.../bindings/pinctrl/fsl,imx6sll-pinctrl.txt | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt
new file mode 100644
index 0000000..2e897a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt
@@ -0,0 +1,40 @@
+* Freescale i.MX6 SLL IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx6sll-iomuxc"
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
+ input_val> are specified using a PIN_FUNC_ID macro, which can be found in
+ imx6sll-pinfunc.h under device tree source folder. The last integer CONFIG is
+ the pad setting value like pull-up on this pin. Please refer to i.MX6SLL
+ Reference Manual for detailed CONFIG settings.
+
+CONFIG bits definition:
+PAD_CTL_LVE (1 << 22)
+PAD_CTL_HYS (1 << 16)
+PAD_CTL_PUS_100K_DOWN (0 << 14)
+PAD_CTL_PUS_47K_UP (1 << 14)
+PAD_CTL_PUS_100K_UP (2 << 14)
+PAD_CTL_PUS_22K_UP (3 << 14)
+PAD_CTL_PUE (1 << 13)
+PAD_CTL_PKE (1 << 12)
+PAD_CTL_ODE (1 << 11)
+PAD_CTL_SPEED_LOW (0 << 6)
+PAD_CTL_SPEED_MED (1 << 6)
+PAD_CTL_SPEED_HIGH (3 << 6)
+PAD_CTL_DSE_DISABLE (0 << 3)
+PAD_CTL_DSE_260ohm (1 << 3)
+PAD_CTL_DSE_130ohm (2 << 3)
+PAD_CTL_DSE_87ohm (3 << 3)
+PAD_CTL_DSE_65ohm (4 << 3)
+PAD_CTL_DSE_52ohm (5 << 3)
+PAD_CTL_DSE_43ohm (6 << 3)
+PAD_CTL_DSE_37ohm (7 << 3)
+PAD_CTL_SRE_FAST (1 << 0)
+PAD_CTL_SRE_SLOW (0 << 0)
+
+Refer to imx6sll-pinfunc.h in device tree source folder for all available
+imx6sll PIN_FUNC_ID.
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support for imx6sll
2018-03-12 9:36 [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc for imx6sll Bai Ping
@ 2018-03-12 9:36 ` Bai Ping
2018-03-13 0:56 ` Shawn Guo
2018-03-16 10:51 ` A.s. Dong
2018-03-13 0:55 ` [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc " Shawn Guo
2018-03-16 10:38 ` A.s. Dong
2 siblings, 2 replies; 6+ messages in thread
From: Bai Ping @ 2018-03-12 9:36 UTC (permalink / raw)
To: linux-arm-kernel
Add pinctrl driver support for imx6sll.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
---
changes v2->v3
- switch the pinctrl driver to use generic pinconfig based on imx7ulp
changes v3->v4
- remove the unecessary log print
- add SION support
- update the license identifier to SPDX
change v4->v5
- drop generic pin config, use the old fsl pin config
---
arch/arm/mach-imx/Kconfig | 1 +
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx6sll.c | 360 ++++++++++++++++++++++++++++
4 files changed, 369 insertions(+)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx6sll.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 8e3a618..cb010a0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -514,6 +514,7 @@ config SOC_IMX6SL
config SOC_IMX6SLL
bool "i.MX6 SoloLiteLite support"
+ select PINCTRL_IMX6SLL
select SOC_IMX6
help
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 4dbc576..b4886ee 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -82,6 +82,13 @@ config PINCTRL_IMX6SL
help
Say Y here to enable the imx6sl pinctrl driver
+config PINCTRL_IMX6SLL
+ bool "IMX6SL pinctrl driver"
+ depends on SOC_IMX6SLL
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx6sl pinctrl driver
+
config PINCTRL_IMX6SX
bool "IMX6SX pinctrl driver"
depends on SOC_IMX6SX
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 19bb9a5..368be8c 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
+obj-$(CONFIG_PINCTRL_IMX6SLL) += pinctrl-imx6sll.o
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sll.c b/drivers/pinctrl/freescale/pinctrl-imx6sll.c
new file mode 100644
index 0000000..2698375
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sll.c
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP.
+ *
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+enum imx6sll_pads {
+ MX6SLL_PAD_RESERVE0 = 0,
+ MX6SLL_PAD_RESERVE1 = 1,
+ MX6SLL_PAD_RESERVE2 = 2,
+ MX6SLL_PAD_RESERVE3 = 3,
+ MX6SLL_PAD_RESERVE4 = 4,
+ MX6SLL_PAD_WDOG_B = 5,
+ MX6SLL_PAD_REF_CLK_24M = 6,
+ MX6SLL_PAD_REF_CLK_32K = 7,
+ MX6SLL_PAD_PWM1 = 8,
+ MX6SLL_PAD_KEY_COL0 = 9,
+ MX6SLL_PAD_KEY_ROW0 = 10,
+ MX6SLL_PAD_KEY_COL1 = 11,
+ MX6SLL_PAD_KEY_ROW1 = 12,
+ MX6SLL_PAD_KEY_COL2 = 13,
+ MX6SLL_PAD_KEY_ROW2 = 14,
+ MX6SLL_PAD_KEY_COL3 = 15,
+ MX6SLL_PAD_KEY_ROW3 = 16,
+ MX6SLL_PAD_KEY_COL4 = 17,
+ MX6SLL_PAD_KEY_ROW4 = 18,
+ MX6SLL_PAD_KEY_COL5 = 19,
+ MX6SLL_PAD_KEY_ROW5 = 20,
+ MX6SLL_PAD_KEY_COL6 = 21,
+ MX6SLL_PAD_KEY_ROW6 = 22,
+ MX6SLL_PAD_KEY_COL7 = 23,
+ MX6SLL_PAD_KEY_ROW7 = 24,
+ MX6SLL_PAD_EPDC_DATA00 = 25,
+ MX6SLL_PAD_EPDC_DATA01 = 26,
+ MX6SLL_PAD_EPDC_DATA02 = 27,
+ MX6SLL_PAD_EPDC_DATA03 = 28,
+ MX6SLL_PAD_EPDC_DATA04 = 29,
+ MX6SLL_PAD_EPDC_DATA05 = 30,
+ MX6SLL_PAD_EPDC_DATA06 = 31,
+ MX6SLL_PAD_EPDC_DATA07 = 32,
+ MX6SLL_PAD_EPDC_DATA08 = 33,
+ MX6SLL_PAD_EPDC_DATA09 = 34,
+ MX6SLL_PAD_EPDC_DATA10 = 35,
+ MX6SLL_PAD_EPDC_DATA11 = 36,
+ MX6SLL_PAD_EPDC_DATA12 = 37,
+ MX6SLL_PAD_EPDC_DATA13 = 38,
+ MX6SLL_PAD_EPDC_DATA14 = 39,
+ MX6SLL_PAD_EPDC_DATA15 = 40,
+ MX6SLL_PAD_EPDC_SDCLK = 41,
+ MX6SLL_PAD_EPDC_SDLE = 42,
+ MX6SLL_PAD_EPDC_SDOE = 43,
+ MX6SLL_PAD_EPDC_SDSHR = 44,
+ MX6SLL_PAD_EPDC_SDCE0 = 45,
+ MX6SLL_PAD_EPDC_SDCE1 = 46,
+ MX6SLL_PAD_EPDC_SDCE2 = 47,
+ MX6SLL_PAD_EPDC_SDCE3 = 48,
+ MX6SLL_PAD_EPDC_GDCLK = 49,
+ MX6SLL_PAD_EPDC_GDOE = 50,
+ MX6SLL_PAD_EPDC_GDRL = 51,
+ MX6SLL_PAD_EPDC_GDSP = 52,
+ MX6SLL_PAD_EPDC_VCOM0 = 53,
+ MX6SLL_PAD_EPDC_VCOM1 = 54,
+ MX6SLL_PAD_EPDC_BDR0 = 55,
+ MX6SLL_PAD_EPDC_BDR1 = 56,
+ MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
+ MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
+ MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
+ MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
+ MX6SLL_PAD_EPDC_PWR_COM = 61,
+ MX6SLL_PAD_EPDC_PWR_INT = 62,
+ MX6SLL_PAD_EPDC_PWR_STAT = 63,
+ MX6SLL_PAD_EPDC_PWR_WAKE = 64,
+ MX6SLL_PAD_LCD_CLK = 65,
+ MX6SLL_PAD_LCD_ENABLE = 66,
+ MX6SLL_PAD_LCD_HSYNC = 67,
+ MX6SLL_PAD_LCD_VSYNC = 68,
+ MX6SLL_PAD_LCD_RESET = 69,
+ MX6SLL_PAD_LCD_DATA00 = 70,
+ MX6SLL_PAD_LCD_DATA01 = 71,
+ MX6SLL_PAD_LCD_DATA02 = 72,
+ MX6SLL_PAD_LCD_DATA03 = 73,
+ MX6SLL_PAD_LCD_DATA04 = 74,
+ MX6SLL_PAD_LCD_DATA05 = 75,
+ MX6SLL_PAD_LCD_DATA06 = 76,
+ MX6SLL_PAD_LCD_DATA07 = 77,
+ MX6SLL_PAD_LCD_DATA08 = 78,
+ MX6SLL_PAD_LCD_DATA09 = 79,
+ MX6SLL_PAD_LCD_DATA10 = 80,
+ MX6SLL_PAD_LCD_DATA11 = 81,
+ MX6SLL_PAD_LCD_DATA12 = 82,
+ MX6SLL_PAD_LCD_DATA13 = 83,
+ MX6SLL_PAD_LCD_DATA14 = 84,
+ MX6SLL_PAD_LCD_DATA15 = 85,
+ MX6SLL_PAD_LCD_DATA16 = 86,
+ MX6SLL_PAD_LCD_DATA17 = 87,
+ MX6SLL_PAD_LCD_DATA18 = 88,
+ MX6SLL_PAD_LCD_DATA19 = 89,
+ MX6SLL_PAD_LCD_DATA20 = 90,
+ MX6SLL_PAD_LCD_DATA21 = 91,
+ MX6SLL_PAD_LCD_DATA22 = 92,
+ MX6SLL_PAD_LCD_DATA23 = 93,
+ MX6SLL_PAD_AUD_RXFS = 94,
+ MX6SLL_PAD_AUD_RXC = 95,
+ MX6SLL_PAD_AUD_RXD = 96,
+ MX6SLL_PAD_AUD_TXC = 97,
+ MX6SLL_PAD_AUD_TXFS = 98,
+ MX6SLL_PAD_AUD_TXD = 99,
+ MX6SLL_PAD_AUD_MCLK = 100,
+ MX6SLL_PAD_UART1_RXD = 101,
+ MX6SLL_PAD_UART1_TXD = 102,
+ MX6SLL_PAD_I2C1_SCL = 103,
+ MX6SLL_PAD_I2C1_SDA = 104,
+ MX6SLL_PAD_I2C2_SCL = 105,
+ MX6SLL_PAD_I2C2_SDA = 106,
+ MX6SLL_PAD_ECSPI1_SCLK = 107,
+ MX6SLL_PAD_ECSPI1_MOSI = 108,
+ MX6SLL_PAD_ECSPI1_MISO = 109,
+ MX6SLL_PAD_ECSPI1_SS0 = 110,
+ MX6SLL_PAD_ECSPI2_SCLK = 111,
+ MX6SLL_PAD_ECSPI2_MOSI = 112,
+ MX6SLL_PAD_ECSPI2_MISO = 113,
+ MX6SLL_PAD_ECSPI2_SS0 = 114,
+ MX6SLL_PAD_SD1_CLK = 115,
+ MX6SLL_PAD_SD1_CMD = 116,
+ MX6SLL_PAD_SD1_DATA0 = 117,
+ MX6SLL_PAD_SD1_DATA1 = 118,
+ MX6SLL_PAD_SD1_DATA2 = 119,
+ MX6SLL_PAD_SD1_DATA3 = 120,
+ MX6SLL_PAD_SD1_DATA4 = 121,
+ MX6SLL_PAD_SD1_DATA5 = 122,
+ MX6SLL_PAD_SD1_DATA6 = 123,
+ MX6SLL_PAD_SD1_DATA7 = 124,
+ MX6SLL_PAD_SD2_RESET = 125,
+ MX6SLL_PAD_SD2_CLK = 126,
+ MX6SLL_PAD_SD2_CMD = 127,
+ MX6SLL_PAD_SD2_DATA0 = 128,
+ MX6SLL_PAD_SD2_DATA1 = 129,
+ MX6SLL_PAD_SD2_DATA2 = 130,
+ MX6SLL_PAD_SD2_DATA3 = 131,
+ MX6SLL_PAD_SD2_DATA4 = 132,
+ MX6SLL_PAD_SD2_DATA5 = 133,
+ MX6SLL_PAD_SD2_DATA6 = 134,
+ MX6SLL_PAD_SD2_DATA7 = 135,
+ MX6SLL_PAD_SD3_CLK = 136,
+ MX6SLL_PAD_SD3_CMD = 137,
+ MX6SLL_PAD_SD3_DATA0 = 138,
+ MX6SLL_PAD_SD3_DATA1 = 139,
+ MX6SLL_PAD_SD3_DATA2 = 140,
+ MX6SLL_PAD_SD3_DATA3 = 141,
+ MX6SLL_PAD_GPIO4_IO20 = 142,
+ MX6SLL_PAD_GPIO4_IO21 = 143,
+ MX6SLL_PAD_GPIO4_IO19 = 144,
+ MX6SLL_PAD_GPIO4_IO25 = 145,
+ MX6SLL_PAD_GPIO4_IO18 = 146,
+ MX6SLL_PAD_GPIO4_IO24 = 147,
+ MX6SLL_PAD_GPIO4_IO23 = 148,
+ MX6SLL_PAD_GPIO4_IO17 = 149,
+ MX6SLL_PAD_GPIO4_IO22 = 150,
+ MX6SLL_PAD_GPIO4_IO16 = 151,
+ MX6SLL_PAD_GPIO4_IO26 = 152,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
+ IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
+};
+
+static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
+ .pins = imx6sll_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
+ .gpr_compatible = "fsl,imx6sll-iomuxc-gpr",
+};
+
+static const struct of_device_id imx6sll_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
+ { /* sentinel */ }
+};
+
+static int imx6sll_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info);
+}
+
+static struct platform_driver imx6sll_pinctrl_driver = {
+ .driver = {
+ .name = "imx6sll-pinctrl",
+ .of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
+ },
+ .probe = imx6sll_pinctrl_probe,
+};
+
+static int __init imx6sll_pinctrl_init(void)
+{
+ return platform_driver_register(&imx6sll_pinctrl_driver);
+}
+arch_initcall(imx6sll_pinctrl_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc for imx6sll
2018-03-12 9:36 [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc for imx6sll Bai Ping
2018-03-12 9:36 ` [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support " Bai Ping
@ 2018-03-13 0:55 ` Shawn Guo
2018-03-16 10:38 ` A.s. Dong
2 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2018-03-13 0:55 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Mar 12, 2018 at 05:36:55PM +0800, Bai Ping wrote:
> Add pinctrl binding doc update for imx6sll.
>
> Signed-off-by: Bai Ping <ping.bai@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support for imx6sll
2018-03-12 9:36 ` [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support " Bai Ping
@ 2018-03-13 0:56 ` Shawn Guo
2018-03-16 10:51 ` A.s. Dong
1 sibling, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2018-03-13 0:56 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Mar 12, 2018 at 05:36:56PM +0800, Bai Ping wrote:
> Add pinctrl driver support for imx6sll.
>
> Signed-off-by: Bai Ping <ping.bai@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc for imx6sll
2018-03-12 9:36 [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc for imx6sll Bai Ping
2018-03-12 9:36 ` [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support " Bai Ping
2018-03-13 0:55 ` [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc " Shawn Guo
@ 2018-03-16 10:38 ` A.s. Dong
2 siblings, 0 replies; 6+ messages in thread
From: A.s. Dong @ 2018-03-16 10:38 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Jacky Bai
> Sent: Monday, March 12, 2018 5:37 PM
> To: linus.walleij at linaro.org; robh+dt at kernel.org; shawnguo at kernel.org;
> kernel at pengutronix.de
> Cc: Fabio Estevam <fabio.estevam@nxp.com>; linux-arm-
> kernel at lists.infradead.org; A.s. Dong <aisheng.dong@nxp.com>; dl-linux-
> imx <linux-imx@nxp.com>; jacky.baip at gmail.com
> Subject: [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc for imx6sll
>
> Add pinctrl binding doc update for imx6sll.
>
> Signed-off-by: Bai Ping <ping.bai@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Regards
Dong Aisheng
> ---
> changes v2-v3:
> - add generic config binding
>
> change v3->v4:
> - add SION bit define
> - fix typo
> - move the pin header file to dts patch.
>
> change v4->5:
> - drop generic config, use the old fsl pin config style
> ---
> .../bindings/pinctrl/fsl,imx6sll-pinctrl.txt | 40 ++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-
> pinctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt
> new file mode 100644
> index 0000000..2e897a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sll-pinctrl.txt
> @@ -0,0 +1,40 @@
> +* Freescale i.MX6 SLL IOMUX Controller
> +
> +Please refer to fsl,imx-pinctrl.txt in this directory for common
> +binding part and usage.
> +
> +Required properties:
> +- compatible: "fsl,imx6sll-iomuxc"
> +- fsl,pins: each entry consists of 6 integers and represents the mux
> +and config
> + setting for one pin. The first 5 integers <mux_reg conf_reg
> +input_reg mux_val
> + input_val> are specified using a PIN_FUNC_ID macro, which can be
> +found in
> + imx6sll-pinfunc.h under device tree source folder. The last integer
> +CONFIG is
> + the pad setting value like pull-up on this pin. Please refer to
> +i.MX6SLL
> + Reference Manual for detailed CONFIG settings.
> +
> +CONFIG bits definition:
> +PAD_CTL_LVE (1 << 22)
> +PAD_CTL_HYS (1 << 16)
> +PAD_CTL_PUS_100K_DOWN (0 << 14)
> +PAD_CTL_PUS_47K_UP (1 << 14)
> +PAD_CTL_PUS_100K_UP (2 << 14)
> +PAD_CTL_PUS_22K_UP (3 << 14)
> +PAD_CTL_PUE (1 << 13)
> +PAD_CTL_PKE (1 << 12)
> +PAD_CTL_ODE (1 << 11)
> +PAD_CTL_SPEED_LOW (0 << 6)
> +PAD_CTL_SPEED_MED (1 << 6)
> +PAD_CTL_SPEED_HIGH (3 << 6)
> +PAD_CTL_DSE_DISABLE (0 << 3)
> +PAD_CTL_DSE_260ohm (1 << 3)
> +PAD_CTL_DSE_130ohm (2 << 3)
> +PAD_CTL_DSE_87ohm (3 << 3)
> +PAD_CTL_DSE_65ohm (4 << 3)
> +PAD_CTL_DSE_52ohm (5 << 3)
> +PAD_CTL_DSE_43ohm (6 << 3)
> +PAD_CTL_DSE_37ohm (7 << 3)
> +PAD_CTL_SRE_FAST (1 << 0)
> +PAD_CTL_SRE_SLOW (0 << 0)
> +
> +Refer to imx6sll-pinfunc.h in device tree source folder for all
> +available imx6sll PIN_FUNC_ID.
> --
> 1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support for imx6sll
2018-03-12 9:36 ` [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support " Bai Ping
2018-03-13 0:56 ` Shawn Guo
@ 2018-03-16 10:51 ` A.s. Dong
1 sibling, 0 replies; 6+ messages in thread
From: A.s. Dong @ 2018-03-16 10:51 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Jacky Bai
> Sent: Monday, March 12, 2018 5:37 PM
> To: linus.walleij at linaro.org; robh+dt at kernel.org; shawnguo at kernel.org;
> kernel at pengutronix.de
> Cc: Fabio Estevam <fabio.estevam@nxp.com>; linux-arm-
> kernel at lists.infradead.org; A.s. Dong <aisheng.dong@nxp.com>; dl-linux-
> imx <linux-imx@nxp.com>; jacky.baip at gmail.com
> Subject: [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support for imx6sll
>
> Add pinctrl driver support for imx6sll.
>
> Signed-off-by: Bai Ping <ping.bai@nxp.com>
Only a few minor comments.
> ---
> changes v2->v3
> - switch the pinctrl driver to use generic pinconfig based on imx7ulp
>
> changes v3->v4
> - remove the unecessary log print
> - add SION support
> - update the license identifier to SPDX
>
> change v4->v5
> - drop generic pin config, use the old fsl pin config
> ---
> arch/arm/mach-imx/Kconfig | 1 +
> drivers/pinctrl/freescale/Kconfig | 7 +
> drivers/pinctrl/freescale/Makefile | 1 +
> drivers/pinctrl/freescale/pinctrl-imx6sll.c | 360
> ++++++++++++++++++++++++++++
> 4 files changed, 369 insertions(+)
> create mode 100644 drivers/pinctrl/freescale/pinctrl-imx6sll.c
>
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index
> 8e3a618..cb010a0 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -514,6 +514,7 @@ config SOC_IMX6SL
>
> config SOC_IMX6SLL
> bool "i.MX6 SoloLiteLite support"
> + select PINCTRL_IMX6SLL
> select SOC_IMX6
>
> help
> diff --git a/drivers/pinctrl/freescale/Kconfig
> b/drivers/pinctrl/freescale/Kconfig
> index 4dbc576..b4886ee 100644
> --- a/drivers/pinctrl/freescale/Kconfig
> +++ b/drivers/pinctrl/freescale/Kconfig
> @@ -82,6 +82,13 @@ config PINCTRL_IMX6SL
> help
> Say Y here to enable the imx6sl pinctrl driver
>
> +config PINCTRL_IMX6SLL
> + bool "IMX6SL pinctrl driver"
> + depends on SOC_IMX6SLL
> + select PINCTRL_IMX
> + help
> + Say Y here to enable the imx6sl pinctrl driver
s/imx6sl/imx6sll
> +
> config PINCTRL_IMX6SX
> bool "IMX6SX pinctrl driver"
> depends on SOC_IMX6SX
> diff --git a/drivers/pinctrl/freescale/Makefile
> b/drivers/pinctrl/freescale/Makefile
> index 19bb9a5..368be8c 100644
> --- a/drivers/pinctrl/freescale/Makefile
> +++ b/drivers/pinctrl/freescale/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
> obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
> obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
> obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
> +obj-$(CONFIG_PINCTRL_IMX6SLL) += pinctrl-imx6sll.o
> obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
> obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
> obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
> diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sll.c
> b/drivers/pinctrl/freescale/pinctrl-imx6sll.c
> new file mode 100644
> index 0000000..2698375
> --- /dev/null
> +++ b/drivers/pinctrl/freescale/pinctrl-imx6sll.c
> @@ -0,0 +1,360 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017-2018 NXP.
> + *
> + */
> +
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinconf-generic.h> #include
Drop this one
> +<linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-imx.h"
> +
> +enum imx6sll_pads {
> + MX6SLL_PAD_RESERVE0 = 0,
> + MX6SLL_PAD_RESERVE1 = 1,
> + MX6SLL_PAD_RESERVE2 = 2,
> + MX6SLL_PAD_RESERVE3 = 3,
> + MX6SLL_PAD_RESERVE4 = 4,
> + MX6SLL_PAD_WDOG_B = 5,
> + MX6SLL_PAD_REF_CLK_24M = 6,
> + MX6SLL_PAD_REF_CLK_32K = 7,
> + MX6SLL_PAD_PWM1 = 8,
> + MX6SLL_PAD_KEY_COL0 = 9,
> + MX6SLL_PAD_KEY_ROW0 = 10,
> + MX6SLL_PAD_KEY_COL1 = 11,
> + MX6SLL_PAD_KEY_ROW1 = 12,
> + MX6SLL_PAD_KEY_COL2 = 13,
> + MX6SLL_PAD_KEY_ROW2 = 14,
> + MX6SLL_PAD_KEY_COL3 = 15,
> + MX6SLL_PAD_KEY_ROW3 = 16,
> + MX6SLL_PAD_KEY_COL4 = 17,
> + MX6SLL_PAD_KEY_ROW4 = 18,
> + MX6SLL_PAD_KEY_COL5 = 19,
> + MX6SLL_PAD_KEY_ROW5 = 20,
> + MX6SLL_PAD_KEY_COL6 = 21,
> + MX6SLL_PAD_KEY_ROW6 = 22,
> + MX6SLL_PAD_KEY_COL7 = 23,
> + MX6SLL_PAD_KEY_ROW7 = 24,
> + MX6SLL_PAD_EPDC_DATA00 = 25,
> + MX6SLL_PAD_EPDC_DATA01 = 26,
> + MX6SLL_PAD_EPDC_DATA02 = 27,
> + MX6SLL_PAD_EPDC_DATA03 = 28,
> + MX6SLL_PAD_EPDC_DATA04 = 29,
> + MX6SLL_PAD_EPDC_DATA05 = 30,
> + MX6SLL_PAD_EPDC_DATA06 = 31,
> + MX6SLL_PAD_EPDC_DATA07 = 32,
> + MX6SLL_PAD_EPDC_DATA08 = 33,
> + MX6SLL_PAD_EPDC_DATA09 = 34,
> + MX6SLL_PAD_EPDC_DATA10 = 35,
> + MX6SLL_PAD_EPDC_DATA11 = 36,
> + MX6SLL_PAD_EPDC_DATA12 = 37,
> + MX6SLL_PAD_EPDC_DATA13 = 38,
> + MX6SLL_PAD_EPDC_DATA14 = 39,
> + MX6SLL_PAD_EPDC_DATA15 = 40,
> + MX6SLL_PAD_EPDC_SDCLK = 41,
> + MX6SLL_PAD_EPDC_SDLE = 42,
> + MX6SLL_PAD_EPDC_SDOE = 43,
> + MX6SLL_PAD_EPDC_SDSHR = 44,
> + MX6SLL_PAD_EPDC_SDCE0 = 45,
> + MX6SLL_PAD_EPDC_SDCE1 = 46,
> + MX6SLL_PAD_EPDC_SDCE2 = 47,
> + MX6SLL_PAD_EPDC_SDCE3 = 48,
> + MX6SLL_PAD_EPDC_GDCLK = 49,
> + MX6SLL_PAD_EPDC_GDOE = 50,
> + MX6SLL_PAD_EPDC_GDRL = 51,
> + MX6SLL_PAD_EPDC_GDSP = 52,
> + MX6SLL_PAD_EPDC_VCOM0 = 53,
> + MX6SLL_PAD_EPDC_VCOM1 = 54,
> + MX6SLL_PAD_EPDC_BDR0 = 55,
> + MX6SLL_PAD_EPDC_BDR1 = 56,
> + MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
> + MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
> + MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
> + MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
> + MX6SLL_PAD_EPDC_PWR_COM = 61,
> + MX6SLL_PAD_EPDC_PWR_INT = 62,
> + MX6SLL_PAD_EPDC_PWR_STAT = 63,
> + MX6SLL_PAD_EPDC_PWR_WAKE = 64,
> + MX6SLL_PAD_LCD_CLK = 65,
> + MX6SLL_PAD_LCD_ENABLE = 66,
> + MX6SLL_PAD_LCD_HSYNC = 67,
> + MX6SLL_PAD_LCD_VSYNC = 68,
> + MX6SLL_PAD_LCD_RESET = 69,
> + MX6SLL_PAD_LCD_DATA00 = 70,
> + MX6SLL_PAD_LCD_DATA01 = 71,
> + MX6SLL_PAD_LCD_DATA02 = 72,
> + MX6SLL_PAD_LCD_DATA03 = 73,
> + MX6SLL_PAD_LCD_DATA04 = 74,
> + MX6SLL_PAD_LCD_DATA05 = 75,
> + MX6SLL_PAD_LCD_DATA06 = 76,
> + MX6SLL_PAD_LCD_DATA07 = 77,
> + MX6SLL_PAD_LCD_DATA08 = 78,
> + MX6SLL_PAD_LCD_DATA09 = 79,
> + MX6SLL_PAD_LCD_DATA10 = 80,
> + MX6SLL_PAD_LCD_DATA11 = 81,
> + MX6SLL_PAD_LCD_DATA12 = 82,
> + MX6SLL_PAD_LCD_DATA13 = 83,
> + MX6SLL_PAD_LCD_DATA14 = 84,
> + MX6SLL_PAD_LCD_DATA15 = 85,
> + MX6SLL_PAD_LCD_DATA16 = 86,
> + MX6SLL_PAD_LCD_DATA17 = 87,
> + MX6SLL_PAD_LCD_DATA18 = 88,
> + MX6SLL_PAD_LCD_DATA19 = 89,
> + MX6SLL_PAD_LCD_DATA20 = 90,
> + MX6SLL_PAD_LCD_DATA21 = 91,
> + MX6SLL_PAD_LCD_DATA22 = 92,
> + MX6SLL_PAD_LCD_DATA23 = 93,
> + MX6SLL_PAD_AUD_RXFS = 94,
> + MX6SLL_PAD_AUD_RXC = 95,
> + MX6SLL_PAD_AUD_RXD = 96,
> + MX6SLL_PAD_AUD_TXC = 97,
> + MX6SLL_PAD_AUD_TXFS = 98,
> + MX6SLL_PAD_AUD_TXD = 99,
> + MX6SLL_PAD_AUD_MCLK = 100,
> + MX6SLL_PAD_UART1_RXD = 101,
> + MX6SLL_PAD_UART1_TXD = 102,
> + MX6SLL_PAD_I2C1_SCL = 103,
> + MX6SLL_PAD_I2C1_SDA = 104,
> + MX6SLL_PAD_I2C2_SCL = 105,
> + MX6SLL_PAD_I2C2_SDA = 106,
> + MX6SLL_PAD_ECSPI1_SCLK = 107,
> + MX6SLL_PAD_ECSPI1_MOSI = 108,
> + MX6SLL_PAD_ECSPI1_MISO = 109,
> + MX6SLL_PAD_ECSPI1_SS0 = 110,
> + MX6SLL_PAD_ECSPI2_SCLK = 111,
> + MX6SLL_PAD_ECSPI2_MOSI = 112,
> + MX6SLL_PAD_ECSPI2_MISO = 113,
> + MX6SLL_PAD_ECSPI2_SS0 = 114,
> + MX6SLL_PAD_SD1_CLK = 115,
> + MX6SLL_PAD_SD1_CMD = 116,
> + MX6SLL_PAD_SD1_DATA0 = 117,
> + MX6SLL_PAD_SD1_DATA1 = 118,
> + MX6SLL_PAD_SD1_DATA2 = 119,
> + MX6SLL_PAD_SD1_DATA3 = 120,
> + MX6SLL_PAD_SD1_DATA4 = 121,
> + MX6SLL_PAD_SD1_DATA5 = 122,
> + MX6SLL_PAD_SD1_DATA6 = 123,
> + MX6SLL_PAD_SD1_DATA7 = 124,
> + MX6SLL_PAD_SD2_RESET = 125,
> + MX6SLL_PAD_SD2_CLK = 126,
> + MX6SLL_PAD_SD2_CMD = 127,
> + MX6SLL_PAD_SD2_DATA0 = 128,
> + MX6SLL_PAD_SD2_DATA1 = 129,
> + MX6SLL_PAD_SD2_DATA2 = 130,
> + MX6SLL_PAD_SD2_DATA3 = 131,
> + MX6SLL_PAD_SD2_DATA4 = 132,
> + MX6SLL_PAD_SD2_DATA5 = 133,
> + MX6SLL_PAD_SD2_DATA6 = 134,
> + MX6SLL_PAD_SD2_DATA7 = 135,
> + MX6SLL_PAD_SD3_CLK = 136,
> + MX6SLL_PAD_SD3_CMD = 137,
> + MX6SLL_PAD_SD3_DATA0 = 138,
> + MX6SLL_PAD_SD3_DATA1 = 139,
> + MX6SLL_PAD_SD3_DATA2 = 140,
> + MX6SLL_PAD_SD3_DATA3 = 141,
> + MX6SLL_PAD_GPIO4_IO20 = 142,
> + MX6SLL_PAD_GPIO4_IO21 = 143,
> + MX6SLL_PAD_GPIO4_IO19 = 144,
> + MX6SLL_PAD_GPIO4_IO25 = 145,
> + MX6SLL_PAD_GPIO4_IO18 = 146,
> + MX6SLL_PAD_GPIO4_IO24 = 147,
> + MX6SLL_PAD_GPIO4_IO23 = 148,
> + MX6SLL_PAD_GPIO4_IO17 = 149,
> + MX6SLL_PAD_GPIO4_IO22 = 150,
> + MX6SLL_PAD_GPIO4_IO16 = 151,
> + MX6SLL_PAD_GPIO4_IO26 = 152,
> +};
> +
> +/* Pad names for the pinmux subsystem */ static const struct
> +pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
> + IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
> + IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
> +};
> +
> +static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
> + .pins = imx6sll_pinctrl_pads,
> + .npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
> + .gpr_compatible = "fsl,imx6sll-iomuxc-gpr", };
Should we document this somewhere? Probably in another patch before
dts changes.
> +
> +static const struct of_device_id imx6sll_pinctrl_of_match[] = {
> + { .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
> + { /* sentinel */ }
> +};
> +
> +static int imx6sll_pinctrl_probe(struct platform_device *pdev) {
> + return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info); }
> +
> +static struct platform_driver imx6sll_pinctrl_driver = {
> + .driver = {
> + .name = "imx6sll-pinctrl",
> + .of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
.suppress_bind_attrs = true,
> + },
> + .probe = imx6sll_pinctrl_probe,
> +};
> +
> +static int __init imx6sll_pinctrl_init(void) {
> + return platform_driver_register(&imx6sll_pinctrl_driver);
> +}
> +arch_initcall(imx6sll_pinctrl_init);
Otherwise:
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Regards
Dong Aisheng
> --
> 1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-03-16 10:51 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-12 9:36 [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc for imx6sll Bai Ping
2018-03-12 9:36 ` [PATCH v5 2/2] pinctrl: imx: Add pinctrl driver support " Bai Ping
2018-03-13 0:56 ` Shawn Guo
2018-03-16 10:51 ` A.s. Dong
2018-03-13 0:55 ` [PATCH v5 1/2] dt-bindings: imx: update pinctrl doc " Shawn Guo
2018-03-16 10:38 ` A.s. Dong
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