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From: Andre Przywara <andre.przywara@linaro.org>
To: Stefano Stabellini <sstabellini@kernel.org>,
	Julien Grall <julien.grall@arm.com>
Cc: xen-devel@lists.xenproject.org
Subject: [PATCH v2 42/45] ARM: new VGIC: vgic-init: implement vgic_init
Date: Thu, 15 Mar 2018 20:30:47 +0000	[thread overview]
Message-ID: <20180315203050.19791-43-andre.przywara@linaro.org> (raw)
In-Reply-To: <20180315203050.19791-1-andre.przywara@linaro.org>

This patch allocates and initializes the data structures used to model
the vgic distributor and virtual cpu interfaces. At that stage the
number of IRQs and number of virtual CPUs is frozen.
Implement the various functions that the Xen arch code is expecting to
call during domain and VCPU setup to initialize the VGIC.
Their prototypes are already in existing header files.

This is based on Linux commit ad275b8bb1e6, written by Eric Auger.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
---
Changelog v1 ... v2:
- remove stray kvm_ prefix in comment
- use unsigned int
- ROUNDUP number of SPIs
- fix indentation

 xen/arch/arm/vgic/vgic-init.c | 199 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 199 insertions(+)

diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c
index d091c92ed0..d7695d69bf 100644
--- a/xen/arch/arm/vgic/vgic-init.c
+++ b/xen/arch/arm/vgic/vgic-init.c
@@ -15,11 +15,83 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <xen/lib.h>
 #include <xen/sched.h>
 #include <asm/new_vgic.h>
 
 #include "vgic.h"
 
+/*
+ * Initialization rules: there are multiple stages to the vgic
+ * initialization, both for the distributor and the CPU interfaces.  The basic
+ * idea is that even though the VGIC is not functional or not requested from
+ * user space, the critical path of the run loop can still call VGIC functions
+ * that just won't do anything, without them having to check additional
+ * initialization flags to ensure they don't look at uninitialized data
+ * structures.
+ *
+ * Distributor:
+ *
+ * - vgic_early_init(): initialization of static data that doesn't
+ *   depend on any sizing information or emulation type. No allocation
+ *   is allowed there.
+ *
+ * - vgic_init(): allocation and initialization of the generic data
+ *   structures that depend on sizing information (number of CPUs,
+ *   number of interrupts). Also initializes the vcpu specific data
+ *   structures. Can be executed lazily for GICv2.
+ *
+ * CPU Interface:
+ *
+ * - vgic_vcpu_early_init(): initialization of static data that
+ *   doesn't depend on any sizing information or emulation type. No
+ *   allocation is allowed there.
+ */
+
+/**
+ * vgic_vcpu_early_init() - Initialize static VGIC VCPU data structures
+ * @vcpu: The VCPU whose VGIC data structures whould be initialized
+ *
+ * Only do initialization, but do not actually enable the VGIC CPU interface
+ * yet.
+ */
+static void vgic_vcpu_early_init(struct vcpu *vcpu)
+{
+    struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+    unsigned int i;
+
+    INIT_LIST_HEAD(&vgic_cpu->ap_list_head);
+    spin_lock_init(&vgic_cpu->ap_list_lock);
+
+    /*
+     * Enable and configure all SGIs to be edge-triggered and
+     * configure all PPIs as level-triggered.
+     */
+    for ( i = 0; i < VGIC_NR_PRIVATE_IRQS; i++ )
+    {
+        struct vgic_irq *irq = &vgic_cpu->private_irqs[i];
+
+        INIT_LIST_HEAD(&irq->ap_list);
+        spin_lock_init(&irq->irq_lock);
+        irq->intid = i;
+        irq->vcpu = NULL;
+        irq->target_vcpu = vcpu;
+        irq->targets = 1U << vcpu->vcpu_id;
+        atomic_set(&irq->refcount, 0);
+        if ( vgic_irq_is_sgi(i) )
+        {
+            /* SGIs */
+            irq->enabled = 1;
+            irq->config = VGIC_CONFIG_EDGE;
+        }
+        else
+        {
+            /* PPIs */
+            irq->config = VGIC_CONFIG_LEVEL;
+        }
+    }
+}
+
 /* CREATION */
 
 /**
@@ -50,6 +122,133 @@ int domain_vgic_register(struct domain *d, int *mmio_count)
     return 0;
 }
 
+/* INIT/DESTROY */
+
+/**
+ * domain_vgic_init: initialize the dist data structures
+ * @d: domain pointer
+ * @nr_spis: number of SPIs
+ */
+int domain_vgic_init(struct domain *d, unsigned int nr_spis)
+{
+    struct vgic_dist *dist = &d->arch.vgic;
+    unsigned int i;
+    int ret;
+
+    /* Limit the number of virtual SPIs supported to (1020 - 32) = 988  */
+    if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
+        return -EINVAL;
+    nr_spis = ROUNDUP(nr_spis, 32);
+
+    dist->nr_spis = nr_spis;
+    dist->spis = xzalloc_array(struct vgic_irq, nr_spis);
+    if ( !dist->spis )
+        return  -ENOMEM;
+
+    /*
+     * In the following code we do not take the irq struct lock since
+     * no other action on irq structs can happen while the VGIC is
+     * not initialized yet:
+     * If someone wants to inject an interrupt or does a MMIO access, we
+     * require prior initialization in case of a virtual GICv3 or trigger
+     * initialization when using a virtual GICv2.
+     */
+    for ( i = 0; i < nr_spis; i++ )
+    {
+        struct vgic_irq *irq = &dist->spis[i];
+
+        irq->intid = i + VGIC_NR_PRIVATE_IRQS;
+        INIT_LIST_HEAD(&irq->ap_list);
+        spin_lock_init(&irq->irq_lock);
+        irq->vcpu = NULL;
+        irq->target_vcpu = NULL;
+        atomic_set(&irq->refcount, 0);
+        if ( dist->version == GIC_V2 )
+            irq->targets = 0;
+        else
+            irq->mpidr = 0;
+    }
+
+    INIT_LIST_HEAD(&dist->lpi_list_head);
+    spin_lock_init(&dist->lpi_list_lock);
+
+    if ( dist->version == GIC_V2 )
+        ret = vgic_v2_map_resources(d);
+    else
+        ret = -ENXIO;
+
+    if ( ret )
+        return ret;
+
+    /* allocated_irqs() is used by Xen to find available vIRQs */
+    d->arch.vgic.allocated_irqs =
+        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
+    if ( !d->arch.vgic.allocated_irqs )
+        return -ENOMEM;
+
+    /* vIRQ0-15 (SGIs) are reserved */
+    for ( i = 0; i < NR_GIC_SGI; i++ )
+        set_bit(i, d->arch.vgic.allocated_irqs);
+
+    return 0;
+}
+
+/**
+ * vcpu_vgic_init() - Register VCPU-specific KVM iodevs
+ * was: kvm_vgic_vcpu_init()
+ * Xen: adding vgic_vx_enable() call
+ * @vcpu: pointer to the VCPU being created and initialized
+ */
+int vcpu_vgic_init(struct vcpu *vcpu)
+{
+    int ret = 0;
+
+    vgic_vcpu_early_init(vcpu);
+
+    if ( gic_hw_version() == GIC_V2 )
+        vgic_v2_enable(vcpu);
+    else
+        ret = -ENXIO;
+
+    return ret;
+}
+
+void domain_vgic_free(struct domain *d)
+{
+    struct vgic_dist *dist = &d->arch.vgic;
+        int i, ret;
+
+    for ( i = 0; i < dist->nr_spis; i++ )
+    {
+        struct vgic_irq *irq = vgic_get_irq(d, NULL, 32 + i);
+
+        if ( !irq->hw )
+            continue;
+
+        ret = release_guest_irq(d, irq->hwintid);
+        if ( ret )
+            dprintk(XENLOG_G_WARNING,
+                    "d%u: Failed to release virq %u ret = %d\n",
+                    d->domain_id, 32 + i, ret);
+    }
+
+    dist->ready = false;
+    dist->initialized = false;
+
+    xfree(dist->spis);
+    xfree(dist->allocated_irqs);
+    dist->nr_spis = 0;
+}
+
+int vcpu_vgic_free(struct vcpu *vcpu)
+{
+    struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+
+    INIT_LIST_HEAD(&vgic_cpu->ap_list_head);
+
+    return 0;
+}
+
 /*
  * Local variables:
  * mode: C
-- 
2.14.1


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  parent reply	other threads:[~2018-03-15 20:31 UTC|newest]

Thread overview: 106+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-15 20:30 [PATCH v2 00/45] New VGIC(-v2) implementation Andre Przywara
2018-03-15 20:30 ` [PATCH v2 01/45] ARM: VGIC: rename gic_event_needs_delivery() Andre Przywara
2018-03-16 10:58   ` Julien Grall
2018-03-16 21:21   ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 02/45] ARM: Implement vcpu_kick() Andre Przywara
2018-03-16 10:59   ` Julien Grall
2018-03-16 21:23   ` Stefano Stabellini
2018-03-20 10:35   ` Jan Beulich
2018-03-21  4:10     ` Julien Grall
2018-03-21  7:40       ` Jan Beulich
2018-03-15 20:30 ` [PATCH v2 03/45] xen/arm: gic: Fix indentation in gic_update_one_lr Andre Przywara
2018-03-15 20:30 ` [PATCH v2 04/45] xen/arm: vgic: Override the group in lr everytime Andre Przywara
2018-03-16 21:25   ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 05/45] xen/arm: gic: Use bool instead of uint8_t for the hw_status in gic_lr Andre Przywara
2018-03-16 21:25   ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 06/45] xen/arm: gic: Split the field state in gic_lr in 2 fields active and pending Andre Przywara
2018-03-16 21:34   ` Stefano Stabellini
2018-03-16 22:14     ` Julien Grall
2018-03-16 22:52       ` Stefano Stabellini
2018-03-19  9:10         ` Andre Przywara
2018-03-15 20:30 ` [PATCH v2 07/45] xen/arm: GIC: Only set pirq in the LR when hw_status is set Andre Przywara
2018-03-16 21:38   ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 08/45] ARM: GIC: extend LR read/write functions to cover EOI and source Andre Przywara
2018-03-16 21:43   ` Stefano Stabellini
2018-03-15 20:30 ` [PATCH v2 09/45] ARM: GIC: Allow tweaking the active and pending state of an IRQ Andre Przywara
2018-03-16 16:05   ` Andre Przywara
2018-03-19  9:30     ` Julien Grall
2018-03-19 17:54       ` Andre Przywara
2018-03-20  0:57         ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 10/45] ARM: GIC: Allow reading pending state of a hardware IRQ Andre Przywara
2018-03-19 10:04   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 11/45] ARM: timer: Handle level triggered IRQs correctly Andre Przywara
2018-03-19 10:07   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 12/45] ARM: evtchn: " Andre Przywara
2018-03-19 10:54   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 13/45] ARM: vPL011: Use the VGIC's level triggered IRQs handling if available Andre Przywara
2018-03-19 10:59   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 14/45] ARM: new VGIC: Add data structure definitions Andre Przywara
2018-03-19 11:01   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 15/45] ARM: new VGIC: Add acccessor to new struct vgic_irq instance Andre Przywara
2018-03-19 11:04   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 16/45] ARM: new VGIC: Implement virtual IRQ injection Andre Przywara
2018-03-19 12:48   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 17/45] Add list_sort() routine from Linux Andre Przywara
2018-03-16 10:47   ` Jan Beulich
2018-03-15 20:30 ` [PATCH v2 18/45] ARM: new VGIC: Add IRQ sorting Andre Przywara
2018-03-19 12:51   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 19/45] ARM: new VGIC: Add IRQ sync/flush framework Andre Przywara
2018-03-19 14:17   ` Julien Grall
2018-03-19 17:32     ` Andre Przywara
2018-03-15 20:30 ` [PATCH v2 20/45] ARM: new VGIC: Add GICv2 world switch backend Andre Przywara
2018-03-19 14:36   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 21/45] ARM: new VGIC: Implement vgic_vcpu_pending_irq Andre Przywara
2018-03-19  7:55   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 22/45] ARM: new VGIC: Add MMIO handling framework Andre Przywara
2018-03-19  7:59   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 23/45] ARM: new VGIC: Add GICv2 " Andre Przywara
2018-03-15 20:30 ` [PATCH v2 24/45] ARM: new VGIC: Add CTLR, TYPER and IIDR handlers Andre Przywara
2018-03-19  8:13   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 25/45] ARM: new VGIC: Add ENABLE registers handlers Andre Przywara
2018-03-19  8:22   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 26/45] ARM: new VGIC: Add PENDING " Andre Przywara
2018-03-19  8:25   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 27/45] ARM: new VGIC: Add ACTIVE " Andre Przywara
2018-03-19  8:27   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 28/45] ARM: new VGIC: Add PRIORITY " Andre Przywara
2018-03-19  9:40   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 29/45] ARM: new VGIC: Add CONFIG " Andre Przywara
2018-03-15 20:30 ` [PATCH v2 30/45] ARM: new VGIC: Add TARGET " Andre Przywara
2018-03-19  9:44   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 31/45] ARM: new VGIC: Add SGIR register handler Andre Przywara
2018-03-19  9:47   ` Julien Grall
2018-03-19 16:21     ` Andre Przywara
2018-03-15 20:30 ` [PATCH v2 32/45] ARM: new VGIC: Add SGIPENDR register handlers Andre Przywara
2018-03-15 20:30 ` [PATCH v2 33/45] ARM: new VGIC: Handle hardware mapped IRQs Andre Przywara
2018-03-15 20:30 ` [PATCH v2 34/45] ARM: new VGIC: Add event channel IRQ handling Andre Przywara
2018-03-15 20:30 ` [PATCH v2 35/45] ARM: new VGIC: Handle virtual IRQ allocation/reservation Andre Przywara
2018-03-15 20:30 ` [PATCH v2 36/45] ARM: new VGIC: Dump virtual IRQ info Andre Przywara
2018-03-15 20:30 ` [PATCH v2 37/45] ARM: new VGIC: Provide system register emulation stub Andre Przywara
2018-03-15 20:30 ` [PATCH v2 38/45] ARM: new VGIC: Implement arch_move_irqs() Andre Przywara
2018-03-19  9:53   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 39/45] ARM: new VGIC: Add preliminary stub implementation Andre Przywara
2018-03-19  9:54   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 40/45] ARM: new VGIC: vgic-init: register VGIC Andre Przywara
2018-03-20  1:17   ` Julien Grall
2018-03-20 17:11     ` Andre Przywara
2018-03-21  4:29       ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 41/45] ARM: new VGIC: Add vgic_v2_enable Andre Przywara
2018-03-19  9:57   ` Julien Grall
2018-03-15 20:30 ` Andre Przywara [this message]
2018-03-20  3:02   ` [PATCH v2 42/45] ARM: new VGIC: vgic-init: implement vgic_init Julien Grall
2018-03-15 20:30 ` [PATCH v2 43/45] ARM: new VGIC: vgic-init: implement map_resources Andre Przywara
2018-03-20  3:10   ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 44/45] ARM: new VGIC: Allocate two pages for struct vcpu Andre Przywara
2018-03-19 10:00   ` Julien Grall
2018-03-19 10:04     ` Julien Grall
2018-03-15 20:30 ` [PATCH v2 45/45] ARM: VGIC: wire new VGIC(-v2) files into Xen build system Andre Przywara
2018-03-16 10:48   ` Jan Beulich
2018-03-16 11:10     ` Andre Przywara
2018-03-16 11:32       ` Jan Beulich
2018-03-16 15:13         ` Andre Przywara
2018-03-16 15:34           ` Jan Beulich
2018-03-20  3:13   ` Julien Grall
2018-03-20 15:57     ` Andre Przywara
2018-03-20  8:30 ` [PATCH v2 00/45] New VGIC(-v2) implementation Julien Grall
2018-03-20 11:20   ` Andre Przywara

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