* [PATCH 0/8] clk: renesas: Always use readl()/writel()
@ 2018-03-16 13:40 Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 1/8] clk: renesas: div6: " Geert Uytterhoeven
` (9 more replies)
0 siblings, 10 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2018-03-16 13:40 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Hi Mike, Stephen,
On arm32/arm64, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel(), and the generic readl()/writel() should be
used in instead.
Commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use
readl()/writel()") already got rid of them in the R-Car Gen3 clock
driver, but Stephen noticed that a few new users crept in recently.
Hence this series fixes that, and replaces all other uses in the Renesas
clock drivers as a bonus.
I plan to queue these up in clk-renesas-for-v4.17.
Thanks!
Geert Uytterhoeven (8):
clk: renesas: div6: Always use readl()/writel()
clk: renesas: mstp: Always use readl()/writel()
clk: renesas: r8a73a4: Always use readl()/writel()
clk: renesas: r8a7740: Always use readl()/writel()
clk: renesas: rcar-gen2: Always use readl()/writel()
clk: renesas: rza1: Always use readl()/writel()
clk: renesas: sh73a0: Always use readl()/writel()
clk: renesas: rcar-gen3: Always use readl()/writel()
drivers/clk/renesas/clk-div6.c | 22 +++++++++++-----------
drivers/clk/renesas/clk-mstp.c | 4 ++--
drivers/clk/renesas/clk-r8a73a4.c | 11 +++++------
drivers/clk/renesas/clk-r8a7740.c | 8 ++++----
drivers/clk/renesas/clk-rcar-gen2.c | 17 ++++++++---------
drivers/clk/renesas/clk-rz.c | 4 ++--
drivers/clk/renesas/clk-sh73a0.c | 14 +++++++-------
drivers/clk/renesas/rcar-gen3-cpg.c | 14 +++++++-------
8 files changed, 46 insertions(+), 48 deletions(-)
--
2.7.4
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/8] clk: renesas: div6: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
@ 2018-03-16 13:40 ` Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 2/8] clk: renesas: mstp: " Geert Uytterhoeven
` (8 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2018-03-16 13:40 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
On arm32/arm64, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel(). Hence use the generic readl()/writel()
instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/clk-div6.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
index 151336d2ba59e689..9febbf42c3df6979 100644
--- a/drivers/clk/renesas/clk-div6.c
+++ b/drivers/clk/renesas/clk-div6.c
@@ -53,9 +53,9 @@ static int cpg_div6_clock_enable(struct clk_hw *hw)
struct div6_clock *clock = to_div6_clock(hw);
u32 val;
- val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
+ val = (readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
| CPG_DIV6_DIV(clock->div - 1);
- clk_writel(val, clock->reg);
+ writel(val, clock->reg);
return 0;
}
@@ -65,7 +65,7 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
struct div6_clock *clock = to_div6_clock(hw);
u32 val;
- val = clk_readl(clock->reg);
+ val = readl(clock->reg);
val |= CPG_DIV6_CKSTP;
/*
* DIV6 clocks require the divisor field to be non-zero when stopping
@@ -75,14 +75,14 @@ static void cpg_div6_clock_disable(struct clk_hw *hw)
*/
if (!(val & CPG_DIV6_DIV_MASK))
val |= CPG_DIV6_DIV_MASK;
- clk_writel(val, clock->reg);
+ writel(val, clock->reg);
}
static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
{
struct div6_clock *clock = to_div6_clock(hw);
- return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
+ return !(readl(clock->reg) & CPG_DIV6_CKSTP);
}
static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
@@ -122,10 +122,10 @@ static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
clock->div = div;
- val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
+ val = readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
/* Only program the new divisor if the clock isn't stopped. */
if (!(val & CPG_DIV6_CKSTP))
- clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
+ writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
return 0;
}
@@ -139,7 +139,7 @@ static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
if (clock->src_width == 0)
return 0;
- hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
+ hw_index = (readl(clock->reg) >> clock->src_shift) &
(BIT(clock->src_width) - 1);
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
if (clock->parents[i] == hw_index)
@@ -163,8 +163,8 @@ static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
hw_index = clock->parents[index];
- clk_writel((clk_readl(clock->reg) & mask) |
- (hw_index << clock->src_shift), clock->reg);
+ writel((readl(clock->reg) & mask) | (hw_index << clock->src_shift),
+ clock->reg);
return 0;
}
@@ -241,7 +241,7 @@ struct clk * __init cpg_div6_register(const char *name,
* Read the divisor. Disabling the clock overwrites the divisor, so we
* need to cache its value for the enable operation.
*/
- clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
+ clock->div = (readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
switch (num_parents) {
case 1:
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/8] clk: renesas: mstp: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 1/8] clk: renesas: div6: " Geert Uytterhoeven
@ 2018-03-16 13:40 ` Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 3/8] clk: renesas: r8a73a4: " Geert Uytterhoeven
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2018-03-16 13:40 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel(). Hence use the generic readl()/writel()
instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/clk-mstp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index d6a57dc23679711b..2b7e3eb651e3d375 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -64,13 +64,13 @@ struct mstp_clock {
static inline u32 cpg_mstp_read(struct mstp_clock_group *group,
u32 __iomem *reg)
{
- return group->width_8bit ? readb(reg) : clk_readl(reg);
+ return group->width_8bit ? readb(reg) : readl(reg);
}
static inline void cpg_mstp_write(struct mstp_clock_group *group, u32 val,
u32 __iomem *reg)
{
- group->width_8bit ? writeb(val, reg) : clk_writel(val, reg);
+ group->width_8bit ? writeb(val, reg) : writel(val, reg);
}
static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/8] clk: renesas: r8a73a4: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 1/8] clk: renesas: div6: " Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 2/8] clk: renesas: mstp: " Geert Uytterhoeven
@ 2018-03-16 13:40 ` Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 4/8] clk: renesas: r8a7740: " Geert Uytterhoeven
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2018-03-16 13:40 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel(). Hence use the generic readl()/writel()
instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/clk-r8a73a4.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/clk-r8a73a4.c b/drivers/clk/renesas/clk-r8a73a4.c
index 28d204bb659e7879..7b903ce4c9015ad7 100644
--- a/drivers/clk/renesas/clk-r8a73a4.c
+++ b/drivers/clk/renesas/clk-r8a73a4.c
@@ -71,7 +71,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
if (!strcmp(name, "main")) {
- u32 ckscr = clk_readl(cpg->reg + CPG_CKSCR);
+ u32 ckscr = readl(cpg->reg + CPG_CKSCR);
switch ((ckscr >> 28) & 3) {
case 0: /* extal1 */
@@ -95,14 +95,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
* clock implementation and we currently have no need to change
* the multiplier value.
*/
- u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
+ u32 value = readl(cpg->reg + CPG_PLL0CR);
parent_name = "main";
mult = ((value >> 24) & 0x7f) + 1;
if (value & BIT(20))
div = 2;
} else if (!strcmp(name, "pll1")) {
- u32 value = clk_readl(cpg->reg + CPG_PLL1CR);
+ u32 value = readl(cpg->reg + CPG_PLL1CR);
parent_name = "main";
/* XXX: enable bit? */
@@ -125,7 +125,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
default:
return ERR_PTR(-EINVAL);
}
- value = clk_readl(cpg->reg + cr);
+ value = readl(cpg->reg + cr);
switch ((value >> 5) & 7) {
case 0:
parent_name = "main";
@@ -161,8 +161,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
shift = 0;
}
div *= 32;
- mult = 0x20 - ((clk_readl(cpg->reg + CPG_FRQCRC) >> shift)
- & 0x1f);
+ mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
} else {
struct div4_clk *c;
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/8] clk: renesas: r8a7740: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
` (2 preceding siblings ...)
2018-03-16 13:40 ` [PATCH 3/8] clk: renesas: r8a73a4: " Geert Uytterhoeven
@ 2018-03-16 13:40 ` Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 5/8] clk: renesas: rcar-gen2: " Geert Uytterhoeven
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2018-03-16 13:40 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel(). Hence use the generic readl()/writel()
instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/clk-r8a7740.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8a7740.c
index 2f7ce6696b6c0f1d..d074f8e982d0851c 100644
--- a/drivers/clk/renesas/clk-r8a7740.c
+++ b/drivers/clk/renesas/clk-r8a7740.c
@@ -98,20 +98,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
* clock implementation and we currently have no need to change
* the multiplier value.
*/
- u32 value = clk_readl(cpg->reg + CPG_FRQCRC);
+ u32 value = readl(cpg->reg + CPG_FRQCRC);
parent_name = "system";
mult = ((value >> 24) & 0x7f) + 1;
} else if (!strcmp(name, "pllc1")) {
- u32 value = clk_readl(cpg->reg + CPG_FRQCRA);
+ u32 value = readl(cpg->reg + CPG_FRQCRA);
parent_name = "system";
mult = ((value >> 24) & 0x7f) + 1;
div = 2;
} else if (!strcmp(name, "pllc2")) {
- u32 value = clk_readl(cpg->reg + CPG_PLLC2CR);
+ u32 value = readl(cpg->reg + CPG_PLLC2CR);
parent_name = "system";
mult = ((value >> 24) & 0x3f) + 1;
} else if (!strcmp(name, "usb24s")) {
- u32 value = clk_readl(cpg->reg + CPG_USBCKCR);
+ u32 value = readl(cpg->reg + CPG_USBCKCR);
if (value & BIT(7))
/* extal2 */
parent_name = of_clk_get_parent_name(np, 1);
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/8] clk: renesas: rcar-gen2: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
` (3 preceding siblings ...)
2018-03-16 13:40 ` [PATCH 4/8] clk: renesas: r8a7740: " Geert Uytterhoeven
@ 2018-03-16 13:40 ` Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 6/8] clk: renesas: rza1: " Geert Uytterhoeven
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2018-03-16 13:40 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel(). Hence use the generic readl()/writel()
instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/clk-rcar-gen2.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index d14cbe1ca29ac009..ee32a022e6da9548 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -62,8 +62,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
unsigned int mult;
unsigned int val;
- val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
- >> CPG_FRQCRC_ZFC_SHIFT;
+ val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
mult = 32 - val;
return div_u64((u64)parent_rate * mult, 32);
@@ -95,21 +94,21 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
mult = div_u64((u64)rate * 32, parent_rate);
mult = clamp(mult, 1U, 32U);
- if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
+ if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
return -EBUSY;
- val = clk_readl(zclk->reg);
+ val = readl(zclk->reg);
val &= ~CPG_FRQCRC_ZFC_MASK;
val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
- clk_writel(val, zclk->reg);
+ writel(val, zclk->reg);
/*
* Set KICK bit in FRQCRB to update hardware setting and wait for
* clock change completion.
*/
- kick = clk_readl(zclk->kick_reg);
+ kick = readl(zclk->kick_reg);
kick |= CPG_FRQCRB_KICK;
- clk_writel(kick, zclk->kick_reg);
+ writel(kick, zclk->kick_reg);
/*
* Note: There is no HW information about the worst case latency.
@@ -121,7 +120,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
* "super" safe value.
*/
for (i = 1000; i; i--) {
- if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
+ if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
return 0;
cpu_relax();
@@ -332,7 +331,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
mult = config->pll0_mult;
div = 3;
} else {
- u32 value = clk_readl(cpg->reg + CPG_PLL0CR);
+ u32 value = readl(cpg->reg + CPG_PLL0CR);
mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
}
parent_name = "main";
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/8] clk: renesas: rza1: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
` (4 preceding siblings ...)
2018-03-16 13:40 ` [PATCH 5/8] clk: renesas: rcar-gen2: " Geert Uytterhoeven
@ 2018-03-16 13:40 ` Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 7/8] clk: renesas: sh73a0: " Geert Uytterhoeven
` (3 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2018-03-16 13:40 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel(). Hence use the generic readl()/writel()
instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/clk-rz.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c
index 127c58135c8fec76..67dd712aa723c77c 100644
--- a/drivers/clk/renesas/clk-rz.c
+++ b/drivers/clk/renesas/clk-rz.c
@@ -75,9 +75,9 @@ rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *na
* let them run at fixed current speed and implement the details later.
*/
if (strcmp(name, "i") == 0)
- val = (clk_readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
+ val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
else if (strcmp(name, "g") == 0)
- val = clk_readl(cpg->reg + CPG_FRQCR2) & 3;
+ val = readl(cpg->reg + CPG_FRQCR2) & 3;
else
return ERR_PTR(-EINVAL);
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 7/8] clk: renesas: sh73a0: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
` (5 preceding siblings ...)
2018-03-16 13:40 ` [PATCH 6/8] clk: renesas: rza1: " Geert Uytterhoeven
@ 2018-03-16 13:40 ` Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 8/8] clk: renesas: rcar-gen3: " Geert Uytterhoeven
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2018-03-16 13:40 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
On arm32, there is no reason to use the (soon deprecated)
clk_readl()/clk_writel(). Hence use the generic readl()/writel()
instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/clk-sh73a0.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/renesas/clk-sh73a0.c b/drivers/clk/renesas/clk-sh73a0.c
index eea38f6ea77e995d..6cfa6b51904117a5 100644
--- a/drivers/clk/renesas/clk-sh73a0.c
+++ b/drivers/clk/renesas/clk-sh73a0.c
@@ -85,7 +85,7 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
if (!strcmp(name, "main")) {
/* extal1, extal1_div2, extal2, extal2_div2 */
- u32 parent_idx = (clk_readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
+ u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
div = (parent_idx & 1) + 1;
@@ -110,11 +110,11 @@ sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
default:
return ERR_PTR(-EINVAL);
}
- if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
- mult = ((clk_readl(enable_reg) >> 24) & 0x3f) + 1;
+ if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
+ mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
/* handle CFG bit for PLL1 and PLL2 */
if (enable_bit == 1 || enable_bit == 2)
- if (clk_readl(enable_reg) & BIT(20))
+ if (readl(enable_reg) & BIT(20))
mult *= 2;
}
} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
@@ -193,9 +193,9 @@ static void __init sh73a0_cpg_clocks_init(struct device_node *np)
return;
/* Set SDHI clocks to a known state */
- clk_writel(0x108, cpg->reg + CPG_SD0CKCR);
- clk_writel(0x108, cpg->reg + CPG_SD1CKCR);
- clk_writel(0x108, cpg->reg + CPG_SD2CKCR);
+ writel(0x108, cpg->reg + CPG_SD0CKCR);
+ writel(0x108, cpg->reg + CPG_SD1CKCR);
+ writel(0x108, cpg->reg + CPG_SD2CKCR);
for (i = 0; i < num_clks; ++i) {
const char *name;
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 8/8] clk: renesas: rcar-gen3: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
` (6 preceding siblings ...)
2018-03-16 13:40 ` [PATCH 7/8] clk: renesas: sh73a0: " Geert Uytterhoeven
@ 2018-03-16 13:40 ` Geert Uytterhoeven
2018-03-16 16:26 ` Stephen Boyd
2018-03-19 8:53 ` Simon Horman
9 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2018-03-16 13:40 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
The R-Car Gen3 CPG/MSSR driver (again) uses a mix of
clk_readl()/clk_writel() and readl()/writel() to access the clock
registers. Settle on the generic readl()/writel().
Cfr. commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use
readl()/writel()").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/rcar-gen3-cpg.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 0c8fe10d57fe2942..628b63b85d3f09c5 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -93,7 +93,7 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
unsigned int mult;
u32 val;
- val = clk_readl(zclk->reg) & zclk->mask;
+ val = readl(zclk->reg) & zclk->mask;
mult = 32 - (val >> __ffs(zclk->mask));
/* Factor of 2 is for fixed divider */
@@ -125,20 +125,20 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
mult = clamp(mult, 1U, 32U);
- if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
+ if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
return -EBUSY;
- val = clk_readl(zclk->reg) & ~zclk->mask;
+ val = readl(zclk->reg) & ~zclk->mask;
val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
- clk_writel(val, zclk->reg);
+ writel(val, zclk->reg);
/*
* Set KICK bit in FRQCRB to update hardware setting and wait for
* clock change completion.
*/
- kick = clk_readl(zclk->kick_reg);
+ kick = readl(zclk->kick_reg);
kick |= CPG_FRQCRB_KICK;
- clk_writel(kick, zclk->kick_reg);
+ writel(kick, zclk->kick_reg);
/*
* Note: There is no HW information about the worst case latency.
@@ -150,7 +150,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
* "super" safe value.
*/
for (i = 1000; i; i--) {
- if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
+ if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
return 0;
cpu_relax();
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 0/8] clk: renesas: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
@ 2018-03-16 16:26 ` Stephen Boyd
2018-03-16 13:40 ` [PATCH 2/8] clk: renesas: mstp: " Geert Uytterhoeven
` (8 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Stephen Boyd @ 2018-03-16 16:26 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Quoting Geert Uytterhoeven (2018-03-16 06:40:14)
> Hi Mike, Stephen,
>
> On arm32/arm64, there is no reason to use the (soon deprecated)
> clk_readl()/clk_writel(), and the generic readl()/writel() should be
> used in instead.
>
> Commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use
> readl()/writel()") already got rid of them in the R-Car Gen3 clock
> driver, but Stephen noticed that a few new users crept in recently.
>
> Hence this series fixes that, and replaces all other uses in the Renesas
> clock drivers as a bonus.
>
> I plan to queue these up in clk-renesas-for-v4.17.
>
Ok. I'll wait for the PR. Thanks!
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/8] clk: renesas: Always use readl()/writel()
@ 2018-03-16 16:26 ` Stephen Boyd
0 siblings, 0 replies; 12+ messages in thread
From: Stephen Boyd @ 2018-03-16 16:26 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette
Cc: linux-clk, linux-renesas-soc, Geert Uytterhoeven
Quoting Geert Uytterhoeven (2018-03-16 06:40:14)
> Hi Mike, Stephen,
> =
> On arm32/arm64, there is no reason to use the (soon deprecated)
> clk_readl()/clk_writel(), and the generic readl()/writel() should be
> used in instead.
> =
> Commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use
> readl()/writel()") already got rid of them in the R-Car Gen3 clock
> driver, but Stephen noticed that a few new users crept in recently.
> =
> Hence this series fixes that, and replaces all other uses in the Renesas
> clock drivers as a bonus.
> =
> I plan to queue these up in clk-renesas-for-v4.17.
> =
Ok. I'll wait for the PR. Thanks!
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 0/8] clk: renesas: Always use readl()/writel()
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
` (8 preceding siblings ...)
2018-03-16 16:26 ` Stephen Boyd
@ 2018-03-19 8:53 ` Simon Horman
9 siblings, 0 replies; 12+ messages in thread
From: Simon Horman @ 2018-03-19 8:53 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-clk, linux-renesas-soc
On Fri, Mar 16, 2018 at 02:40:14PM +0100, Geert Uytterhoeven wrote:
> Hi Mike, Stephen,
>
> On arm32/arm64, there is no reason to use the (soon deprecated)
> clk_readl()/clk_writel(), and the generic readl()/writel() should be
> used in instead.
>
> Commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use
> readl()/writel()") already got rid of them in the R-Car Gen3 clock
> driver, but Stephen noticed that a few new users crept in recently.
>
> Hence this series fixes that, and replaces all other uses in the Renesas
> clock drivers as a bonus.
>
> I plan to queue these up in clk-renesas-for-v4.17.
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2018-03-19 8:54 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-16 13:40 [PATCH 0/8] clk: renesas: Always use readl()/writel() Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 1/8] clk: renesas: div6: " Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 2/8] clk: renesas: mstp: " Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 3/8] clk: renesas: r8a73a4: " Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 4/8] clk: renesas: r8a7740: " Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 5/8] clk: renesas: rcar-gen2: " Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 6/8] clk: renesas: rza1: " Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 7/8] clk: renesas: sh73a0: " Geert Uytterhoeven
2018-03-16 13:40 ` [PATCH 8/8] clk: renesas: rcar-gen3: " Geert Uytterhoeven
2018-03-16 16:26 ` [PATCH 0/8] clk: renesas: " Stephen Boyd
2018-03-16 16:26 ` Stephen Boyd
2018-03-19 8:53 ` Simon Horman
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