From: Catalin Marinas <catalin.marinas@arm.com> To: Christoph Hellwig <hch@lst.de> Cc: Will Deacon <will.deacon@arm.com>, Robin Murphy <robin.murphy@arm.com>, x86@kernel.org, Tom Lendacky <thomas.lendacky@amd.com>, Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>, linux-kernel@vger.kernel.org, Muli Ben-Yehuda <mulix@mulix.org>, iommu@lists.linux-foundation.org, David Woodhouse <dwmw2@infradead.org> Subject: Re: [PATCH 12/14] dma-direct: handle the memory encryption bit in common code Date: Tue, 20 Mar 2018 16:23:27 +0000 [thread overview] Message-ID: <20180320162327.4cixyuhqc62bfh3n@armageddon.cambridge.arm.com> (raw) In-Reply-To: <20180319194930.GA3255@lst.de> On Mon, Mar 19, 2018 at 08:49:30PM +0100, Christoph Hellwig wrote: > On Mon, Mar 19, 2018 at 06:01:41PM +0000, Catalin Marinas wrote: > > I don't particularly like maintaining an arm64-specific dma-direct.h > > either but arm64 seems to be the only architecture that needs to > > potentially force a bounce when cache_line_size() > ARCH_DMA_MINALIGN > > and the device is non-coherent. > > mips is another likely candidate, see all the recent drama about > dma_get_alignmet(). And I'm also having major discussion about even > exposing the cache line size architecturally for RISC-V, so changes > are high it'll have to deal with this mess sooner or later as they > probably can't agree on a specific cache line size. On Arm, the cache line size varies between 32 and 128 on publicly available hardware (and I wouldn't exclude higher numbers at some point). In addition, the cache line size has a different meaning in the DMA context, we call it "cache writeback granule" on Arm which is greater than or equal the minimum cache line size. So the aim is to have L1_CACHE_BYTES small enough for acceptable performance numbers and ARCH_DMA_MINALIGN the maximum from a correctness perspective (the latter is defined by some larger cache lines in L2/L3). To make things worse, there is no clear definition in the generic kernel on what cache_line_size() means and the default definition returns L1_CACHE_BYTES. On arm64, we define it to the hardware's cache writeback granule (CWG), if available, with a fallback on ARCH_DMA_MINALIGN. The network layer, OTOH, seems to assume that SMP_CACHE_BYTES is sufficient for DMA alignment (L1_CACHE_BYTES in arm64's case). > > As I said above, adding a check in swiotlb.c for > > !is_device_dma_coherent(dev) && (ARCH_DMA_MINALIGN < cache_line_size()) > > feels too architecture specific. > > And what exactly is architecture specific about that? It is a totally > generic concept, which at this point also seems entirely theoretical > based on the previous mail in this thread. The concept may be generic but the kernel macros/functions used here aren't. is_device_dma_coherent() is only defined on arm and arm64. The relation between ARCH_DMA_MINALIGN, L1_CACHE_BYTES and cache_line_size() seems to be pretty ad-hoc. ARCH_DMA_MINALIGN is also only defined for some architectures and, while there is dma_get_cache_alignment() which returns this constant, it doesn't seem to be used much. I'm all for fixing this in a generic way but I think we first need swiotlb.c to become aware of non-cache-coherent DMA devices. -- Catalin
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> To: Christoph Hellwig <hch-jcswGhMUV9g@public.gmane.org> Cc: Tom Lendacky <thomas.lendacky-5C7GfCeVMHo@public.gmane.org>, Konrad Rzeszutek Wilk <konrad.wilk-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>, David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>, x86-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Muli Ben-Yehuda <mulix-BzGcCpaT2IbYtjvyW6yDsg@public.gmane.org>, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Subject: Re: [PATCH 12/14] dma-direct: handle the memory encryption bit in common code Date: Tue, 20 Mar 2018 16:23:27 +0000 [thread overview] Message-ID: <20180320162327.4cixyuhqc62bfh3n@armageddon.cambridge.arm.com> (raw) In-Reply-To: <20180319194930.GA3255-jcswGhMUV9g@public.gmane.org> On Mon, Mar 19, 2018 at 08:49:30PM +0100, Christoph Hellwig wrote: > On Mon, Mar 19, 2018 at 06:01:41PM +0000, Catalin Marinas wrote: > > I don't particularly like maintaining an arm64-specific dma-direct.h > > either but arm64 seems to be the only architecture that needs to > > potentially force a bounce when cache_line_size() > ARCH_DMA_MINALIGN > > and the device is non-coherent. > > mips is another likely candidate, see all the recent drama about > dma_get_alignmet(). And I'm also having major discussion about even > exposing the cache line size architecturally for RISC-V, so changes > are high it'll have to deal with this mess sooner or later as they > probably can't agree on a specific cache line size. On Arm, the cache line size varies between 32 and 128 on publicly available hardware (and I wouldn't exclude higher numbers at some point). In addition, the cache line size has a different meaning in the DMA context, we call it "cache writeback granule" on Arm which is greater than or equal the minimum cache line size. So the aim is to have L1_CACHE_BYTES small enough for acceptable performance numbers and ARCH_DMA_MINALIGN the maximum from a correctness perspective (the latter is defined by some larger cache lines in L2/L3). To make things worse, there is no clear definition in the generic kernel on what cache_line_size() means and the default definition returns L1_CACHE_BYTES. On arm64, we define it to the hardware's cache writeback granule (CWG), if available, with a fallback on ARCH_DMA_MINALIGN. The network layer, OTOH, seems to assume that SMP_CACHE_BYTES is sufficient for DMA alignment (L1_CACHE_BYTES in arm64's case). > > As I said above, adding a check in swiotlb.c for > > !is_device_dma_coherent(dev) && (ARCH_DMA_MINALIGN < cache_line_size()) > > feels too architecture specific. > > And what exactly is architecture specific about that? It is a totally > generic concept, which at this point also seems entirely theoretical > based on the previous mail in this thread. The concept may be generic but the kernel macros/functions used here aren't. is_device_dma_coherent() is only defined on arm and arm64. The relation between ARCH_DMA_MINALIGN, L1_CACHE_BYTES and cache_line_size() seems to be pretty ad-hoc. ARCH_DMA_MINALIGN is also only defined for some architectures and, while there is dma_get_cache_alignment() which returns this constant, it doesn't seem to be used much. I'm all for fixing this in a generic way but I think we first need swiotlb.c to become aware of non-cache-coherent DMA devices. -- Catalin
next prev parent reply other threads:[~2018-03-20 16:23 UTC|newest] Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-03-19 10:38 use generic dma-direct and swiotlb code for x86 V3 Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-19 10:38 ` [PATCH 01/14] x86: remove X86_PPRO_FENCE Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-20 11:04 ` [tip:x86/pti] x86/cpu: Remove the CONFIG_X86_PPRO_FENCE=y quirk tip-bot for Christoph Hellwig 2018-03-20 12:51 ` Peter Zijlstra 2018-03-19 10:38 ` [PATCH 02/14] x86: remove dma_alloc_coherent_mask Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-23 19:48 ` [tip:x86/dma] x86/dma: Remove dma_alloc_coherent_mask() tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 03/14] x86: use dma-direct Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-23 19:49 ` [tip:x86/dma] x86/dma: Use DMA-direct (CONFIG_DMA_DIRECT_OPS=y) tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 04/14] x86: use generic swiotlb_ops Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-23 19:49 ` [tip:x86/dma] x86/dma: Use " tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 05/14] x86/amd_gart: look at coherent_dma_mask instead of GFP_DMA Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-23 19:50 ` [tip:x86/dma] x86/dma/amd_gart: Look at dev->coherent_dma_mask " tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 06/14] x86/amd_gart: use dma_direct_{alloc,free} Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-23 19:50 ` [tip:x86/dma] x86/dma/amd_gart: Use dma_direct_{alloc,free}() tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 07/14] iommu/amd_iommu: use dma_direct_{alloc,free} Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-23 19:51 ` [tip:x86/dma] iommu/amd_iommu: Use CONFIG_DMA_DIRECT_OPS=y and dma_direct_{alloc,free}() tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 08/14] iommu/intel-iommu: cleanup intel_{alloc,free}_coherent Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-23 19:51 ` [tip:x86/dma] iommu/intel-iommu: Enable CONFIG_DMA_DIRECT_OPS=y and clean up intel_{alloc,free}_coherent() tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 09/14] x86: remove dma_alloc_coherent_gfp_flags Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-23 19:52 ` [tip:x86/dma] x86/dma: Remove dma_alloc_coherent_gfp_flags() tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 10/14] set_memory.h: provide set_memory_{en,de}crypted stubs Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-19 14:21 ` Tom Lendacky 2018-03-19 14:21 ` Tom Lendacky 2018-03-23 19:52 ` [tip:x86/dma] set_memory.h: Provide set_memory_{en,de}crypted() stubs tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 11/14] swiotlb: remove swiotlb_set_mem_attributes Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-19 14:41 ` Tom Lendacky 2018-03-19 14:41 ` Tom Lendacky 2018-03-23 19:52 ` [tip:x86/dma] dma/swiotlb: Remove swiotlb_set_mem_attributes() tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 12/14] dma-direct: handle the memory encryption bit in common code Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-19 14:50 ` Tom Lendacky 2018-03-19 14:50 ` Tom Lendacky 2018-03-19 15:19 ` Robin Murphy 2018-03-19 15:19 ` Robin Murphy 2018-03-19 15:24 ` Christoph Hellwig 2018-03-19 15:24 ` Christoph Hellwig 2018-03-19 15:37 ` Robin Murphy 2018-03-19 15:37 ` Robin Murphy 2018-03-19 15:48 ` Will Deacon 2018-03-19 15:48 ` Will Deacon 2018-03-19 16:03 ` Christoph Hellwig 2018-03-19 16:03 ` Christoph Hellwig 2018-03-19 16:55 ` Will Deacon 2018-03-19 16:55 ` Will Deacon 2018-03-19 18:01 ` Catalin Marinas 2018-03-19 18:01 ` Catalin Marinas 2018-03-19 19:49 ` Christoph Hellwig 2018-03-19 19:49 ` Christoph Hellwig 2018-03-20 16:23 ` Catalin Marinas [this message] 2018-03-20 16:23 ` Catalin Marinas 2018-03-23 19:53 ` [tip:x86/dma] dma/direct: Handle " tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 13/14] dma-direct: handle force decryption for dma coherent buffers " Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-19 14:51 ` Tom Lendacky 2018-03-19 14:51 ` Tom Lendacky 2018-03-23 19:53 ` [tip:x86/dma] dma/direct: Handle force decryption for DMA " tip-bot for Christoph Hellwig 2018-03-19 10:38 ` [PATCH 14/14] swiotlb: remove swiotlb_{alloc,free}_coherent Christoph Hellwig 2018-03-19 10:38 ` Christoph Hellwig 2018-03-23 19:54 ` [tip:x86/dma] dma/swiotlb: Remove swiotlb_{alloc,free}_coherent() tip-bot for Christoph Hellwig 2018-03-19 14:00 ` use generic dma-direct and swiotlb code for x86 V3 Tom Lendacky 2018-03-19 14:00 ` Tom Lendacky 2018-03-19 14:56 ` Thomas Gleixner 2018-03-19 14:56 ` Thomas Gleixner 2018-03-19 15:27 ` Konrad Rzeszutek Wilk 2018-03-19 15:27 ` Konrad Rzeszutek Wilk 2018-03-19 15:28 ` Christoph Hellwig 2018-03-20 8:37 ` Ingo Molnar 2018-03-20 8:37 ` Ingo Molnar 2018-03-20 8:44 ` Christoph Hellwig 2018-03-20 8:44 ` Christoph Hellwig 2018-03-20 9:03 ` Ingo Molnar 2018-03-20 9:03 ` Ingo Molnar [not found] ` <20180320090351.2qnwcsauhodrqxdj-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2018-03-20 11:25 ` Konrad Rzeszutek Wilk 2018-03-20 15:16 ` Christoph Hellwig 2018-03-20 15:16 ` Christoph Hellwig 2018-03-21 14:32 ` Konrad Rzeszutek Wilk 2018-03-21 14:32 ` Konrad Rzeszutek Wilk -- strict thread matches above, loose matches on Subject: below -- 2018-03-14 17:51 use generic dma-direct and swiotlb code for x86 V2 Christoph Hellwig 2018-03-14 17:52 ` [PATCH 12/14] dma-direct: handle the memory encryption bit in common code Christoph Hellwig 2018-03-14 17:52 ` Christoph Hellwig
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20180320162327.4cixyuhqc62bfh3n@armageddon.cambridge.arm.com \ --to=catalin.marinas@arm.com \ --cc=dwmw2@infradead.org \ --cc=hch@lst.de \ --cc=iommu@lists.linux-foundation.org \ --cc=konrad.wilk@oracle.com \ --cc=linux-kernel@vger.kernel.org \ --cc=mulix@mulix.org \ --cc=robin.murphy@arm.com \ --cc=thomas.lendacky@amd.com \ --cc=will.deacon@arm.com \ --cc=x86@kernel.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.