[PATCH v2 0/7] drm/i915: move dpll_info inside intel_shared_dpll

[PATCH v2 0/7] drm/i915: move dpll_info inside intel_shared_dpll

[Lucas De Marchi]

v2:
- Make dpll_info a pointer inside intel_shared_dpll
- Add a patch to reorder dpll_info members

Lucas De Marchi (7):
  drm/i915: move dpll_info to header
  drm/i915: add dpll_info inside intel_shared_dpll
  drm/i915: use funcs from intel_shared_dpll.info
  drm/i915: use name from intel_shared_dpll.info
  drm/i915: use id from intel_shared_dpll.info
  drm/i915: use flags from dpll_info embedded in intel_shared_dpll
  drm/i915: reorder dpll_info members

 drivers/gpu/drm/i915/i915_debugfs.c   |   3 +-
 drivers/gpu/drm/i915/intel_ddi.c      |   8 +-
 drivers/gpu/drm/i915/intel_display.c  |  25 ++--
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 253 ++++++++++++++++++----------------
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  56 ++++----
 5 files changed, 184 insertions(+), 161 deletions(-)

-- 
2.14.3

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[PATCH v2 1/7] drm/i915: move dpll_info to header

[Lucas De Marchi]

This will allow the struct to be embedded in intel_shared_dpll.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  7 -------
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 10 ++++++++++
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 51c5ae4e9116..52d6e731c3e9 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1877,13 +1877,6 @@ static void intel_ddi_pll_init(struct drm_device *dev)
 	}
 }
 
-struct dpll_info {
-	const char *name;
-	const int id;
-	const struct intel_shared_dpll_funcs *funcs;
-	uint32_t flags;
-};
-
 struct intel_dpll_mgr {
 	const struct dpll_info *dpll_info;
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index f24ccf443d25..e99d6385478a 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -205,6 +205,16 @@ struct intel_shared_dpll_funcs {
 			     struct intel_dpll_hw_state *hw_state);
 };
 
+/**
+ * struct dpll_info - display PLL platform specific info
+ */
+struct dpll_info {
+	const char *name;
+	const int id;
+	const struct intel_shared_dpll_funcs *funcs;
+	uint32_t flags;
+};
+
 /**
  * struct intel_shared_dpll - display PLL with tracked state and users
  */
-- 
2.14.3

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[PATCH v2 2/7] drm/i915: add dpll_info inside intel_shared_dpll

[Lucas De Marchi]

This way we can stop copying fields from dpll_info to intel_shared_dpll
one by one. The migration of each field will come on separate patches.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 1 +
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 52d6e731c3e9..30a9ac5322fe 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2410,6 +2410,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
 
 	for (i = 0; dpll_info[i].id >= 0; i++) {
 		WARN_ON(i != dpll_info[i].id);
+		dev_priv->shared_dplls[i].info = &dpll_info[i];
 
 		dev_priv->shared_dplls[i].id = dpll_info[i].id;
 		dev_priv->shared_dplls[i].name = dpll_info[i].name;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index e99d6385478a..bd2d3652cec4 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -253,6 +253,11 @@ struct intel_shared_dpll {
 	 */
 	struct intel_shared_dpll_funcs funcs;
 
+	/**
+	 * @info: platform specific info
+	 */
+	const struct dpll_info *info;
+
 #define INTEL_DPLL_ALWAYS_ON	(1 << 0)
 	/**
 	 * @flags:
-- 
2.14.3

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[PATCH v2 3/7] drm/i915: use funcs from intel_shared_dpll.info

[Lucas De Marchi]

Replace all users of pll->funcs.* to use
pll->info->funcs->*. The extra indirection here is not on any critical
path and we can leave all const data together.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c  | 16 ++++++++--------
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  9 ++++-----
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  8 +++-----
 3 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3e7ab75e1b41..9e355671f8b0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8768,8 +8768,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 			intel_get_shared_dpll_by_id(dev_priv, pll_id);
 		pll = pipe_config->shared_dpll;
 
-		WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
-						 &pipe_config->dpll_hw_state));
+		WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
+						&pipe_config->dpll_hw_state));
 
 		tmp = pipe_config->dpll_hw_state.dpll;
 		pipe_config->pixel_multiplier =
@@ -9245,8 +9245,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
 
 	pll = pipe_config->shared_dpll;
 	if (pll) {
-		WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
-						 &pipe_config->dpll_hw_state));
+		WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
+						&pipe_config->dpll_hw_state));
 	}
 
 	/*
@@ -11647,7 +11647,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
 
 	DRM_DEBUG_KMS("%s\n", pll->name);
 
-	active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
+	active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
 
 	if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
 		I915_STATE_WARN(!pll->on && pll->active_mask,
@@ -15123,8 +15123,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
 
-		pll->on = pll->funcs.get_hw_state(dev_priv, pll,
-						  &pll->state.hw_state);
+		pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
+							&pll->state.hw_state);
 		pll->state.crtc_mask = 0;
 		for_each_intel_crtc(dev, crtc) {
 			struct intel_crtc_state *crtc_state =
@@ -15313,7 +15313,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 
 		DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
 
-		pll->funcs.disable(dev_priv, pll);
+		pll->info->funcs->disable(dev_priv, pll);
 		pll->on = false;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 30a9ac5322fe..24d9aa180e0c 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -118,7 +118,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 	if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
 		return;
 
-	cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state);
+	cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
 	I915_STATE_WARN(cur_state != state,
 	     "%s assertion failure (expected %s, current %s)\n",
 			pll->name, onoff(state), onoff(cur_state));
@@ -147,7 +147,7 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
 		WARN_ON(pll->on);
 		assert_shared_dpll_disabled(dev_priv, pll);
 
-		pll->funcs.prepare(dev_priv, pll);
+		pll->info->funcs->prepare(dev_priv, pll);
 	}
 	mutex_unlock(&dev_priv->dpll_lock);
 }
@@ -190,7 +190,7 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
 	WARN_ON(pll->on);
 
 	DRM_DEBUG_KMS("enabling %s\n", pll->name);
-	pll->funcs.enable(dev_priv, pll);
+	pll->info->funcs->enable(dev_priv, pll);
 	pll->on = true;
 
 out:
@@ -232,7 +232,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
 		goto out;
 
 	DRM_DEBUG_KMS("disabling %s\n", pll->name);
-	pll->funcs.disable(dev_priv, pll);
+	pll->info->funcs->disable(dev_priv, pll);
 	pll->on = false;
 
 out:
@@ -2414,7 +2414,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
 
 		dev_priv->shared_dplls[i].id = dpll_info[i].id;
 		dev_priv->shared_dplls[i].name = dpll_info[i].name;
-		dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs;
 		dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index bd2d3652cec4..f49382207a0a 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -211,6 +211,9 @@ struct intel_shared_dpll_funcs {
 struct dpll_info {
 	const char *name;
 	const int id;
+	/**
+	 * @funcs: platform specific hooks
+	 */
 	const struct intel_shared_dpll_funcs *funcs;
 	uint32_t flags;
 };
@@ -248,11 +251,6 @@ struct intel_shared_dpll {
 	 */
 	enum intel_dpll_id id;
 
-	/**
-	 * @funcs: platform specific hooks
-	 */
-	struct intel_shared_dpll_funcs funcs;
-
 	/**
 	 * @info: platform specific info
 	 */
-- 
2.14.3

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[PATCH v2 4/7] drm/i915: use name from intel_shared_dpll.info

[Lucas De Marchi]

Replace all users of pll->name to use pll->info->name.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c   |  3 ++-
 drivers/gpu/drm/i915/intel_display.c  |  7 ++++---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 26 ++++++++++++++------------
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  8 +++-----
 4 files changed, 23 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7816cd53100a..057fe12124d8 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3285,7 +3285,8 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
 
-		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
+		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
+			   pll->id);
 		seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
 			   pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
 		seq_printf(m, " tracked hardware state:\n");
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9e355671f8b0..e55f962a3a0b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11645,7 +11645,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
 
 	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
 
-	DRM_DEBUG_KMS("%s\n", pll->name);
+	DRM_DEBUG_KMS("%s\n", pll->info->name);
 
 	active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
 
@@ -15137,7 +15137,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 		pll->active_mask = pll->state.crtc_mask;
 
 		DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
-			      pll->name, pll->state.crtc_mask, pll->on);
+			      pll->info->name, pll->state.crtc_mask, pll->on);
 	}
 
 	for_each_intel_encoder(dev, encoder) {
@@ -15311,7 +15311,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 		if (!pll->on || pll->active_mask)
 			continue;
 
-		DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
+		DRM_DEBUG_KMS("%s enabled but not in use, disabling\n",
+			      pll->info->name);
 
 		pll->info->funcs->disable(dev_priv, pll);
 		pll->on = false;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 24d9aa180e0c..ed46ade0efff 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -121,7 +121,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 	cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state);
 	I915_STATE_WARN(cur_state != state,
 	     "%s assertion failure (expected %s, current %s)\n",
-			pll->name, onoff(state), onoff(cur_state));
+			pll->info->name, onoff(state), onoff(cur_state));
 }
 
 /**
@@ -143,7 +143,7 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
 	mutex_lock(&dev_priv->dpll_lock);
 	WARN_ON(!pll->state.crtc_mask);
 	if (!pll->active_mask) {
-		DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
+		DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name);
 		WARN_ON(pll->on);
 		assert_shared_dpll_disabled(dev_priv, pll);
 
@@ -179,7 +179,7 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
 	pll->active_mask |= crtc_mask;
 
 	DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
-		      pll->name, pll->active_mask, pll->on,
+		      pll->info->name, pll->active_mask, pll->on,
 		      crtc->base.base.id);
 
 	if (old_mask) {
@@ -189,7 +189,7 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
 	}
 	WARN_ON(pll->on);
 
-	DRM_DEBUG_KMS("enabling %s\n", pll->name);
+	DRM_DEBUG_KMS("enabling %s\n", pll->info->name);
 	pll->info->funcs->enable(dev_priv, pll);
 	pll->on = true;
 
@@ -221,7 +221,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
 		goto out;
 
 	DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
-		      pll->name, pll->active_mask, pll->on,
+		      pll->info->name, pll->active_mask, pll->on,
 		      crtc->base.base.id);
 
 	assert_shared_dpll_enabled(dev_priv, pll);
@@ -231,7 +231,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
 	if (pll->active_mask)
 		goto out;
 
-	DRM_DEBUG_KMS("disabling %s\n", pll->name);
+	DRM_DEBUG_KMS("disabling %s\n", pll->info->name);
 	pll->info->funcs->disable(dev_priv, pll);
 	pll->on = false;
 
@@ -263,7 +263,8 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
 			   &shared_dpll[i].hw_state,
 			   sizeof(crtc_state->dpll_hw_state)) == 0) {
 			DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
-				      crtc->base.base.id, crtc->base.name, pll->name,
+				      crtc->base.base.id, crtc->base.name,
+				      pll->info->name,
 				      shared_dpll[i].crtc_mask,
 				      pll->active_mask);
 			return pll;
@@ -275,7 +276,8 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
 		pll = &dev_priv->shared_dplls[i];
 		if (shared_dpll[i].crtc_mask == 0) {
 			DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
-				      crtc->base.base.id, crtc->base.name, pll->name);
+				      crtc->base.base.id, crtc->base.name,
+				      pll->info->name);
 			return pll;
 		}
 	}
@@ -298,7 +300,7 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
 			crtc_state->dpll_hw_state;
 
 	crtc_state->shared_dpll = pll;
-	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
+	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
 			 pipe_name(crtc->pipe));
 
 	shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe;
@@ -429,7 +431,8 @@ ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
 		pll = &dev_priv->shared_dplls[i];
 
 		DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
-			      crtc->base.base.id, crtc->base.name, pll->name);
+			      crtc->base.base.id, crtc->base.name,
+			      pll->info->name);
 	} else {
 		pll = intel_find_shared_dpll(crtc, crtc_state,
 					     DPLL_ID_PCH_PLL_A,
@@ -1824,7 +1827,7 @@ bxt_get_dpll(struct intel_crtc *crtc,
 	pll = intel_get_shared_dpll_by_id(dev_priv, i);
 
 	DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
-		      crtc->base.base.id, crtc->base.name, pll->name);
+		      crtc->base.base.id, crtc->base.name, pll->info->name);
 
 	intel_reference_shared_dpll(pll, crtc_state);
 
@@ -2413,7 +2416,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
 		dev_priv->shared_dplls[i].info = &dpll_info[i];
 
 		dev_priv->shared_dplls[i].id = dpll_info[i].id;
-		dev_priv->shared_dplls[i].name = dpll_info[i].name;
 		dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index f49382207a0a..e5ed3e0269e3 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -209,6 +209,9 @@ struct intel_shared_dpll_funcs {
  * struct dpll_info - display PLL platform specific info
  */
 struct dpll_info {
+	/**
+	 * @name: DPLL name; used for logging
+	 */
 	const char *name;
 	const int id;
 	/**
@@ -240,11 +243,6 @@ struct intel_shared_dpll {
 	 */
 	bool on;
 
-	/**
-	 * @name: DPLL name; used for logging
-	 */
-	const char *name;
-
 	/**
 	 * @id: unique indentifier for this DPLL; should match the index in the
 	 * dev_priv->shared_dplls array
-- 
2.14.3

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[PATCH v2 5/7] drm/i915: use id from intel_shared_dpll.info

[Lucas De Marchi]

Replace all users of pll->id to use pll->info->id. In functions using
this more than once it was preferred to add an id variable to make the
code easier to read.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c   |   2 +-
 drivers/gpu/drm/i915/intel_ddi.c      |   8 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 160 +++++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  10 +--
 4 files changed, 98 insertions(+), 82 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 057fe12124d8..ff90577da450 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3286,7 +3286,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
 
 		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
-			   pll->id);
+			   pll->info->id);
 		seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
 			   pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
 		seq_printf(m, " tracked hardware state:\n");
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8c2d778560f0..90ad621e92bd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -875,7 +875,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 
 static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 {
-	switch (pll->id) {
+	switch (pll->info->id) {
 	case DPLL_ID_WRPLL1:
 		return PORT_CLK_SEL_WRPLL1;
 	case DPLL_ID_WRPLL2:
@@ -889,7 +889,7 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 	case DPLL_ID_LCPLL_2700:
 		return PORT_CLK_SEL_LCPLL_2700;
 	default:
-		MISSING_CASE(pll->id);
+		MISSING_CASE(pll->info->id);
 		return PORT_CLK_SEL_NONE;
 	}
 }
@@ -2131,7 +2131,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
 		val = I915_READ(DPCLKA_CFGCR0);
 		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
 		I915_WRITE(DPCLKA_CFGCR0, val);
 
 		/*
@@ -2148,7 +2148,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 
 		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
 			 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
+		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
 			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
 
 		I915_WRITE(DPLL_CTRL2, val);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index ed46ade0efff..48466b19d1f6 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -291,19 +291,19 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
 {
 	struct intel_shared_dpll_state *shared_dpll;
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-	enum intel_dpll_id i = pll->id;
+	const enum intel_dpll_id id = pll->info->id;
 
 	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
 
-	if (shared_dpll[i].crtc_mask == 0)
-		shared_dpll[i].hw_state =
+	if (shared_dpll[id].crtc_mask == 0)
+		shared_dpll[id].hw_state =
 			crtc_state->dpll_hw_state;
 
 	crtc_state->shared_dpll = pll;
 	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
 			 pipe_name(crtc->pipe));
 
-	shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe;
+	shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
 }
 
 /**
@@ -343,15 +343,16 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 				      struct intel_shared_dpll *pll,
 				      struct intel_dpll_hw_state *hw_state)
 {
+	const enum intel_dpll_id id = pll->info->id;
 	uint32_t val;
 
 	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
 		return false;
 
-	val = I915_READ(PCH_DPLL(pll->id));
+	val = I915_READ(PCH_DPLL(id));
 	hw_state->dpll = val;
-	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
-	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
+	hw_state->fp0 = I915_READ(PCH_FP0(id));
+	hw_state->fp1 = I915_READ(PCH_FP1(id));
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 
@@ -361,8 +362,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
 static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
 				 struct intel_shared_dpll *pll)
 {
-	I915_WRITE(PCH_FP0(pll->id), pll->state.hw_state.fp0);
-	I915_WRITE(PCH_FP1(pll->id), pll->state.hw_state.fp1);
+	const enum intel_dpll_id id = pll->info->id;
+
+	I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0);
+	I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1);
 }
 
 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
@@ -381,13 +384,15 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll)
 {
+	const enum intel_dpll_id id = pll->info->id;
+
 	/* PCH refclock must be enabled first */
 	ibx_assert_pch_refclk_enabled(dev_priv);
 
-	I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
+	I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
 
 	/* Wait for the clocks to stabilize. */
-	POSTING_READ(PCH_DPLL(pll->id));
+	POSTING_READ(PCH_DPLL(id));
 	udelay(150);
 
 	/* The pixel multiplier can only be updated once the
@@ -395,14 +400,15 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
 	 *
 	 * So write it again.
 	 */
-	I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
-	POSTING_READ(PCH_DPLL(pll->id));
+	I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
+	POSTING_READ(PCH_DPLL(id));
 	udelay(200);
 }
 
 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
 				 struct intel_shared_dpll *pll)
 {
+	const enum intel_dpll_id id = pll->info->id;
 	struct drm_device *dev = &dev_priv->drm;
 	struct intel_crtc *crtc;
 
@@ -412,8 +418,8 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
 			assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
 	}
 
-	I915_WRITE(PCH_DPLL(pll->id), 0);
-	POSTING_READ(PCH_DPLL(pll->id));
+	I915_WRITE(PCH_DPLL(id), 0);
+	POSTING_READ(PCH_DPLL(id));
 	udelay(200);
 }
 
@@ -469,8 +475,10 @@ static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll)
 {
-	I915_WRITE(WRPLL_CTL(pll->id), pll->state.hw_state.wrpll);
-	POSTING_READ(WRPLL_CTL(pll->id));
+	const enum intel_dpll_id id = pll->info->id;
+
+	I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);
+	POSTING_READ(WRPLL_CTL(id));
 	udelay(20);
 }
 
@@ -485,11 +493,12 @@ static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
 				  struct intel_shared_dpll *pll)
 {
+	const enum intel_dpll_id id = pll->info->id;
 	uint32_t val;
 
-	val = I915_READ(WRPLL_CTL(pll->id));
-	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
-	POSTING_READ(WRPLL_CTL(pll->id));
+	val = I915_READ(WRPLL_CTL(id));
+	I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
+	POSTING_READ(WRPLL_CTL(id));
 }
 
 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
@@ -506,12 +515,13 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
 				       struct intel_shared_dpll *pll,
 				       struct intel_dpll_hw_state *hw_state)
 {
+	const enum intel_dpll_id id = pll->info->id;
 	uint32_t val;
 
 	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
 		return false;
 
-	val = I915_READ(WRPLL_CTL(pll->id));
+	val = I915_READ(WRPLL_CTL(id));
 	hw_state->wrpll = val;
 
 	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
@@ -917,13 +927,15 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
 				    struct intel_shared_dpll *pll)
 {
+	const enum intel_dpll_id id = pll->info->id;
 	uint32_t val;
 
 	val = I915_READ(DPLL_CTRL1);
 
-	val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) |
-		 DPLL_CTRL1_LINK_RATE_MASK(pll->id));
-	val |= pll->state.hw_state.ctrl1 << (pll->id * 6);
+	val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
+		 DPLL_CTRL1_SSC(id) |
+		 DPLL_CTRL1_LINK_RATE_MASK(id));
+	val |= pll->state.hw_state.ctrl1 << (id * 6);
 
 	I915_WRITE(DPLL_CTRL1, val);
 	POSTING_READ(DPLL_CTRL1);
@@ -933,24 +945,25 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll)
 {
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
+	const enum intel_dpll_id id = pll->info->id;
 
 	skl_ddi_pll_write_ctrl1(dev_priv, pll);
 
-	I915_WRITE(regs[pll->id].cfgcr1, pll->state.hw_state.cfgcr1);
-	I915_WRITE(regs[pll->id].cfgcr2, pll->state.hw_state.cfgcr2);
-	POSTING_READ(regs[pll->id].cfgcr1);
-	POSTING_READ(regs[pll->id].cfgcr2);
+	I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
+	I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
+	POSTING_READ(regs[id].cfgcr1);
+	POSTING_READ(regs[id].cfgcr2);
 
 	/* the enable bit is always bit 31 */
-	I915_WRITE(regs[pll->id].ctl,
-		   I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
+	I915_WRITE(regs[id].ctl,
+		   I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
 
 	if (intel_wait_for_register(dev_priv,
 				    DPLL_STATUS,
-				    DPLL_LOCK(pll->id),
-				    DPLL_LOCK(pll->id),
+				    DPLL_LOCK(id),
+				    DPLL_LOCK(id),
 				    5))
-		DRM_ERROR("DPLL %d not locked\n", pll->id);
+		DRM_ERROR("DPLL %d not locked\n", id);
 }
 
 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
@@ -963,11 +976,12 @@ static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll)
 {
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
+	const enum intel_dpll_id id = pll->info->id;
 
 	/* the enable bit is always bit 31 */
-	I915_WRITE(regs[pll->id].ctl,
-		   I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
-	POSTING_READ(regs[pll->id].ctl);
+	I915_WRITE(regs[id].ctl,
+		   I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);
+	POSTING_READ(regs[id].ctl);
 }
 
 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
@@ -981,6 +995,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 {
 	uint32_t val;
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
+	const enum intel_dpll_id id = pll->info->id;
 	bool ret;
 
 	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
@@ -988,17 +1003,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 
 	ret = false;
 
-	val = I915_READ(regs[pll->id].ctl);
+	val = I915_READ(regs[id].ctl);
 	if (!(val & LCPLL_PLL_ENABLE))
 		goto out;
 
 	val = I915_READ(DPLL_CTRL1);
-	hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
+	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
 
 	/* avoid reading back stale values if HDMI mode is not enabled */
-	if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) {
-		hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
-		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
+	if (val & DPLL_CTRL1_HDMI_MODE(id)) {
+		hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
+		hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
 	}
 	ret = true;
 
@@ -1014,6 +1029,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
 {
 	uint32_t val;
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
+	const enum intel_dpll_id id = pll->info->id;
 	bool ret;
 
 	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
@@ -1022,12 +1038,12 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
 	ret = false;
 
 	/* DPLL0 is always enabled since it drives CDCLK */
-	val = I915_READ(regs[pll->id].ctl);
+	val = I915_READ(regs[id].ctl);
 	if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
 		goto out;
 
 	val = I915_READ(DPLL_CTRL1);
-	hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
+	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
 
 	ret = true;
 
@@ -1427,7 +1443,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll)
 {
 	uint32_t temp;
-	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
+	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
 	enum dpio_phy phy;
 	enum dpio_channel ch;
 
@@ -1546,7 +1562,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
 					struct intel_shared_dpll *pll)
 {
-	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
+	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
 	uint32_t temp;
 
 	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
@@ -1569,7 +1585,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 					struct intel_shared_dpll *pll,
 					struct intel_dpll_hw_state *hw_state)
 {
-	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
+	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
 	uint32_t val;
 	bool ret;
 	enum dpio_phy phy;
@@ -1949,38 +1965,39 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
 static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll)
 {
+	const enum intel_dpll_id id = pll->info->id;
 	uint32_t val;
 
 	/* 1. Enable DPLL power in DPLL_ENABLE. */
-	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	val = I915_READ(CNL_DPLL_ENABLE(id));
 	val |= PLL_POWER_ENABLE;
-	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
+	I915_WRITE(CNL_DPLL_ENABLE(id), val);
 
 	/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
 	if (intel_wait_for_register(dev_priv,
-				    CNL_DPLL_ENABLE(pll->id),
+				    CNL_DPLL_ENABLE(id),
 				    PLL_POWER_STATE,
 				    PLL_POWER_STATE,
 				    5))
-		DRM_ERROR("PLL %d Power not enabled\n", pll->id);
+		DRM_ERROR("PLL %d Power not enabled\n", id);
 
 	/*
 	 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
 	 * select DP mode, and set DP link rate.
 	 */
 	val = pll->state.hw_state.cfgcr0;
-	I915_WRITE(CNL_DPLL_CFGCR0(pll->id), val);
+	I915_WRITE(CNL_DPLL_CFGCR0(id), val);
 
 	/* 4. Reab back to ensure writes completed */
-	POSTING_READ(CNL_DPLL_CFGCR0(pll->id));
+	POSTING_READ(CNL_DPLL_CFGCR0(id));
 
 	/* 3. Configure DPLL_CFGCR0 */
 	/* Avoid touch CFGCR1 if HDMI mode is not enabled */
 	if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
 		val = pll->state.hw_state.cfgcr1;
-		I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
+		I915_WRITE(CNL_DPLL_CFGCR1(id), val);
 		/* 4. Reab back to ensure writes completed */
-		POSTING_READ(CNL_DPLL_CFGCR1(pll->id));
+		POSTING_READ(CNL_DPLL_CFGCR1(id));
 	}
 
 	/*
@@ -1993,17 +2010,17 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 	 */
 
 	/* 6. Enable DPLL in DPLL_ENABLE. */
-	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	val = I915_READ(CNL_DPLL_ENABLE(id));
 	val |= PLL_ENABLE;
-	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
+	I915_WRITE(CNL_DPLL_ENABLE(id), val);
 
 	/* 7. Wait for PLL lock status in DPLL_ENABLE. */
 	if (intel_wait_for_register(dev_priv,
-				    CNL_DPLL_ENABLE(pll->id),
+				    CNL_DPLL_ENABLE(id),
 				    PLL_LOCK,
 				    PLL_LOCK,
 				    5))
-		DRM_ERROR("PLL %d not locked\n", pll->id);
+		DRM_ERROR("PLL %d not locked\n", id);
 
 	/*
 	 * 8. If the frequency will result in a change to the voltage
@@ -2023,6 +2040,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
 				struct intel_shared_dpll *pll)
 {
+	const enum intel_dpll_id id = pll->info->id;
 	uint32_t val;
 
 	/*
@@ -2040,17 +2058,17 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
 	 */
 
 	/* 3. Disable DPLL through DPLL_ENABLE. */
-	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	val = I915_READ(CNL_DPLL_ENABLE(id));
 	val &= ~PLL_ENABLE;
-	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
+	I915_WRITE(CNL_DPLL_ENABLE(id), val);
 
 	/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
 	if (intel_wait_for_register(dev_priv,
-				    CNL_DPLL_ENABLE(pll->id),
+				    CNL_DPLL_ENABLE(id),
 				    PLL_LOCK,
 				    0,
 				    5))
-		DRM_ERROR("PLL %d locked\n", pll->id);
+		DRM_ERROR("PLL %d locked\n", id);
 
 	/*
 	 * 5. If the frequency will result in a change to the voltage
@@ -2062,23 +2080,24 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
 	 */
 
 	/* 6. Disable DPLL power in DPLL_ENABLE. */
-	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	val = I915_READ(CNL_DPLL_ENABLE(id));
 	val &= ~PLL_POWER_ENABLE;
-	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
+	I915_WRITE(CNL_DPLL_ENABLE(id), val);
 
 	/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
 	if (intel_wait_for_register(dev_priv,
-				    CNL_DPLL_ENABLE(pll->id),
+				    CNL_DPLL_ENABLE(id),
 				    PLL_POWER_STATE,
 				    0,
 				    5))
-		DRM_ERROR("PLL %d Power not disabled\n", pll->id);
+		DRM_ERROR("PLL %d Power not disabled\n", id);
 }
 
 static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 				     struct intel_shared_dpll *pll,
 				     struct intel_dpll_hw_state *hw_state)
 {
+	const enum intel_dpll_id id = pll->info->id;
 	uint32_t val;
 	bool ret;
 
@@ -2087,16 +2106,16 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
 
 	ret = false;
 
-	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
+	val = I915_READ(CNL_DPLL_ENABLE(id));
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	val = I915_READ(CNL_DPLL_CFGCR0(pll->id));
+	val = I915_READ(CNL_DPLL_CFGCR0(id));
 	hw_state->cfgcr0 = val;
 
 	/* avoid reading back stale values if HDMI mode is not enabled */
 	if (val & DPLL_CFGCR0_HDMI_MODE) {
-		hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll->id));
+		hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
 	}
 	ret = true;
 
@@ -2415,7 +2434,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
 		WARN_ON(i != dpll_info[i].id);
 		dev_priv->shared_dplls[i].info = &dpll_info[i];
 
-		dev_priv->shared_dplls[i].id = dpll_info[i].id;
 		dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
 	}
 
@@ -2476,7 +2494,7 @@ void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
 	struct intel_shared_dpll_state *shared_dpll_state;
 
 	shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
-	shared_dpll_state[dpll->id].crtc_mask &= ~(1 << crtc->pipe);
+	shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index e5ed3e0269e3..7c95ecce41ee 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -213,6 +213,10 @@ struct dpll_info {
 	 * @name: DPLL name; used for logging
 	 */
 	const char *name;
+	/**
+	 * @id: unique indentifier for this DPLL; should match the index in the
+	 * dev_priv->shared_dplls array
+	 */
 	const int id;
 	/**
 	 * @funcs: platform specific hooks
@@ -243,12 +247,6 @@ struct intel_shared_dpll {
 	 */
 	bool on;
 
-	/**
-	 * @id: unique indentifier for this DPLL; should match the index in the
-	 * dev_priv->shared_dplls array
-	 */
-	enum intel_dpll_id id;
-
 	/**
 	 * @info: platform specific info
 	 */
-- 
2.14.3

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[PATCH v2 6/7] drm/i915: use flags from dpll_info embedded in intel_shared_dpll

[Lucas De Marchi]

Replace all users of pll->flags to use pll->info.flags.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c  |  2 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  2 --
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 18 ++++++++----------
 3 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e55f962a3a0b..485e0489c03c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11649,7 +11649,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
 
 	active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state);
 
-	if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
+	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
 		I915_STATE_WARN(!pll->on && pll->active_mask,
 		     "pll in active use but not on in sw tracking\n");
 		I915_STATE_WARN(pll->on && !pll->active_mask,
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 48466b19d1f6..bda69e1ccd76 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2433,8 +2433,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	for (i = 0; dpll_info[i].id >= 0; i++) {
 		WARN_ON(i != dpll_info[i].id);
 		dev_priv->shared_dplls[i].info = &dpll_info[i];
-
-		dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
 	}
 
 	dev_priv->dpll_mgr = dpll_mgr;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 7c95ecce41ee..e4c01e487be7 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -222,6 +222,14 @@ struct dpll_info {
 	 * @funcs: platform specific hooks
 	 */
 	const struct intel_shared_dpll_funcs *funcs;
+#define INTEL_DPLL_ALWAYS_ON	(1 << 0)
+	/**
+	 * @flags:
+	 *
+	 * INTEL_DPLL_ALWAYS_ON
+	 *     Inform the state checker that the DPLL is kept enabled even if
+	 *     not in use by any CRTC.
+	 */
 	uint32_t flags;
 };
 
@@ -251,16 +259,6 @@ struct intel_shared_dpll {
 	 * @info: platform specific info
 	 */
 	const struct dpll_info *info;
-
-#define INTEL_DPLL_ALWAYS_ON	(1 << 0)
-	/**
-	 * @flags:
-	 *
-	 * INTEL_DPLL_ALWAYS_ON
-	 *     Inform the state checker that the DPLL is kept enabled even if
-	 *     not in use by any CRTC.
-	 */
-	uint32_t flags;
 };
 
 #define SKL_DPLL0 0
-- 
2.14.3

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[PATCH v2 7/7] drm/i915: reorder dpll_info members

[Lucas De Marchi]

Remove 4-bytes hole in this struct an reorder tables accordingly. This
also changes the last element of the tables to be more future-proof.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 48 +++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 13 ++++++----
 2 files changed, 32 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index bda69e1ccd76..d5e114e9660b 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1908,9 +1908,9 @@ struct intel_dpll_mgr {
 };
 
 static const struct dpll_info pch_plls[] = {
-	{ "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 },
-	{ "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 },
-	{ NULL, -1, NULL, 0 },
+	{ "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
+	{ "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
+	{ },
 };
 
 static const struct intel_dpll_mgr pch_pll_mgr = {
@@ -1920,13 +1920,13 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
 };
 
 static const struct dpll_info hsw_plls[] = {
-	{ "WRPLL 1",    DPLL_ID_WRPLL1,     &hsw_ddi_wrpll_funcs, 0 },
-	{ "WRPLL 2",    DPLL_ID_WRPLL2,     &hsw_ddi_wrpll_funcs, 0 },
-	{ "SPLL",       DPLL_ID_SPLL,       &hsw_ddi_spll_funcs,  0 },
-	{ "LCPLL 810",  DPLL_ID_LCPLL_810,  &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
-	{ "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
-	{ "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
-	{ NULL, -1, NULL, },
+	{ "WRPLL 1",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1,     0 },
+	{ "WRPLL 2",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2,     0 },
+	{ "SPLL",       &hsw_ddi_spll_funcs,  DPLL_ID_SPLL,       0 },
+	{ "LCPLL 810",  &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  INTEL_DPLL_ALWAYS_ON },
+	{ "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
+	{ "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
+	{ },
 };
 
 static const struct intel_dpll_mgr hsw_pll_mgr = {
@@ -1936,11 +1936,11 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
 };
 
 static const struct dpll_info skl_plls[] = {
-	{ "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON },
-	{ "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs,   0 },
-	{ "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs,   0 },
-	{ "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs,   0 },
-	{ NULL, -1, NULL, },
+	{ "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
+	{ "DPLL 1", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },
+	{ "DPLL 2", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },
+	{ "DPLL 3", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },
+	{ },
 };
 
 static const struct intel_dpll_mgr skl_pll_mgr = {
@@ -1950,10 +1950,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
 };
 
 static const struct dpll_info bxt_plls[] = {
-	{ "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
-	{ "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
-	{ "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
-	{ NULL, -1, NULL, },
+	{ "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
+	{ "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
+	{ "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
+	{ },
 };
 
 static const struct intel_dpll_mgr bxt_pll_mgr = {
@@ -2387,10 +2387,10 @@ static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
 };
 
 static const struct dpll_info cnl_plls[] = {
-	{ "DPLL 0", DPLL_ID_SKL_DPLL0, &cnl_ddi_pll_funcs, 0 },
-	{ "DPLL 1", DPLL_ID_SKL_DPLL1, &cnl_ddi_pll_funcs, 0 },
-	{ "DPLL 2", DPLL_ID_SKL_DPLL2, &cnl_ddi_pll_funcs, 0 },
-	{ NULL, -1, NULL, },
+	{ "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
+	{ "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
+	{ "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
+	{ },
 };
 
 static const struct intel_dpll_mgr cnl_pll_mgr = {
@@ -2430,7 +2430,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
 
 	dpll_info = dpll_mgr->dpll_info;
 
-	for (i = 0; dpll_info[i].id >= 0; i++) {
+	for (i = 0; dpll_info[i].name; i++) {
 		WARN_ON(i != dpll_info[i].id);
 		dev_priv->shared_dplls[i].info = &dpll_info[i];
 	}
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index e4c01e487be7..4febfaa90bde 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -213,15 +213,18 @@ struct dpll_info {
 	 * @name: DPLL name; used for logging
 	 */
 	const char *name;
-	/**
-	 * @id: unique indentifier for this DPLL; should match the index in the
-	 * dev_priv->shared_dplls array
-	 */
-	const int id;
+
 	/**
 	 * @funcs: platform specific hooks
 	 */
 	const struct intel_shared_dpll_funcs *funcs;
+
+	/**
+	 * @id: unique indentifier for this DPLL; should match the index in the
+	 * dev_priv->shared_dplls array
+	 */
+	enum intel_dpll_id id;
+
 #define INTEL_DPLL_ALWAYS_ON	(1 << 0)
 	/**
 	 * @flags:
-- 
2.14.3

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✗ Fi.CI.CHECKPATCH: warning for drm/i915: move dpll_info inside intel_shared_dpll (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: move dpll_info inside intel_shared_dpll (rev2)
URL   : https://patchwork.freedesktop.org/series/40251/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9ddcc8463efd drm/i915: move dpll_info to header
ccdf20dad80f drm/i915: add dpll_info inside intel_shared_dpll
a1a25f106e34 drm/i915: use funcs from intel_shared_dpll.info
-:23: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#23: FILE: drivers/gpu/drm/i915/intel_display.c:8772:
+		WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
+						&pipe_config->dpll_hw_state));

-:34: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#34: FILE: drivers/gpu/drm/i915/intel_display.c:9249:
+		WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll,
+						&pipe_config->dpll_hw_state));

total: 0 errors, 0 warnings, 2 checks, 105 lines checked
44aef9c720e5 drm/i915: use name from intel_shared_dpll.info
df7663ba80a9 drm/i915: use id from intel_shared_dpll.info
57cd16e26f7e drm/i915: use flags from dpll_info embedded in intel_shared_dpll
4d3d43be797e drm/i915: reorder dpll_info members

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✓ Fi.CI.BAT: success for drm/i915: move dpll_info inside intel_shared_dpll (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: move dpll_info inside intel_shared_dpll (rev2)
URL   : https://patchwork.freedesktop.org/series/40251/
State : success

== Summary ==

Series 40251v2 drm/i915: move dpll_info inside intel_shared_dpll
https://patchwork.freedesktop.org/api/1.0/series/40251/revisions/2/mbox/

---- Possible new issues:

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                incomplete -> PASS       (fi-cfl-s2)

---- Known issues:

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                pass       -> INCOMPLETE (fi-hsw-4770) fdo#104944

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104944 https://bugs.freedesktop.org/show_bug.cgi?id=104944

fi-bdw-5557u     total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  time:435s
fi-bdw-gvtdvm    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:441s
fi-blb-e6850     total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:380s
fi-bsw-n3050     total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  time:545s
fi-bwr-2160      total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 time:300s
fi-bxt-dsi       total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  time:513s
fi-bxt-j4205     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:513s
fi-byt-j1900     total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  time:516s
fi-byt-n2820     total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  time:506s
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:410s
fi-cfl-s2        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:582s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:516s
fi-cnl-drrs      total:285  pass:254  dwarn:3   dfail:0   fail:0   skip:28  time:526s
fi-elk-e7500     total:285  pass:225  dwarn:1   dfail:0   fail:0   skip:59  time:424s
fi-gdg-551       total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 time:318s
fi-glk-1         total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:538s
fi-hsw-4770      total:243  pass:219  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650       total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  time:424s
fi-ivb-3520m     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:473s
fi-ivb-3770      total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  time:431s
fi-kbl-7500u     total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  time:478s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:474s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:514s
fi-pnv-d510      total:285  pass:219  dwarn:1   dfail:0   fail:0   skip:65  time:656s
fi-skl-6260u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:444s
fi-skl-6600u     total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:532s
fi-skl-6700hq    total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:543s
fi-skl-6700k2    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:508s
fi-skl-6770hq    total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:490s
fi-skl-guc       total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:430s
fi-snb-2520m     total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:598s
fi-snb-2600      total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:397s

9d737cebc219c821989021a3115424165ff7b052 drm-tip: 2018y-03m-20d-14h-56m-05s UTC integration manifest
4d3d43be797e drm/i915: reorder dpll_info members
57cd16e26f7e drm/i915: use flags from dpll_info embedded in intel_shared_dpll
df7663ba80a9 drm/i915: use id from intel_shared_dpll.info
44aef9c720e5 drm/i915: use name from intel_shared_dpll.info
a1a25f106e34 drm/i915: use funcs from intel_shared_dpll.info
ccdf20dad80f drm/i915: add dpll_info inside intel_shared_dpll
9ddcc8463efd drm/i915: move dpll_info to header

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8423/issues.html
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✓ Fi.CI.IGT: success for drm/i915: move dpll_info inside intel_shared_dpll (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: move dpll_info inside intel_shared_dpll (rev2)
URL   : https://patchwork.freedesktop.org/series/40251/
State : success

== Summary ==

---- Known issues:

Test kms_flip:
        Subgroup flip-vs-panning-vs-hang:
                pass       -> DMESG-WARN (shard-snb) fdo#103821
Test kms_setmode:
        Subgroup basic:
                pass       -> FAIL       (shard-apl) fdo#99912
Test kms_vblank:
        Subgroup pipe-b-ts-continuation-dpms-suspend:
                incomplete -> PASS       (shard-hsw) fdo#105054

fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#105054 https://bugs.freedesktop.org/show_bug.cgi?id=105054

shard-apl        total:3478 pass:1814 dwarn:1   dfail:0   fail:7   skip:1655 time:13035s
shard-hsw        total:3478 pass:1768 dwarn:1   dfail:0   fail:1   skip:1707 time:11797s
shard-snb        total:3478 pass:1357 dwarn:2   dfail:0   fail:2   skip:2117 time:7223s
Blacklisted hosts:
shard-kbl        total:3478 pass:1938 dwarn:1   dfail:0   fail:10  skip:1529 time:9869s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8423/shards.html
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Re: [PATCH v2 5/7] drm/i915: use id from intel_shared_dpll.info

[Ville Syrjälä]

On Tue, Mar 20, 2018 at 03:06:35PM -0700, Lucas De Marchi wrote:
> Replace all users of pll->id to use pll->info->id. In functions using
> this more than once it was preferred to add an id variable to make the
> code easier to read.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c   |   2 +-
>  drivers/gpu/drm/i915/intel_ddi.c      |   8 +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 160 +++++++++++++++++++---------------
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  10 +--
>  4 files changed, 98 insertions(+), 82 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 057fe12124d8..ff90577da450 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3286,7 +3286,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>  		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
>  
>  		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
> -			   pll->id);
> +			   pll->info->id);
>  		seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
>  			   pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
>  		seq_printf(m, " tracked hardware state:\n");
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 8c2d778560f0..90ad621e92bd 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -875,7 +875,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
>  
>  static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
>  {
> -	switch (pll->id) {
> +	switch (pll->info->id) {
>  	case DPLL_ID_WRPLL1:
>  		return PORT_CLK_SEL_WRPLL1;
>  	case DPLL_ID_WRPLL2:
> @@ -889,7 +889,7 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
>  	case DPLL_ID_LCPLL_2700:
>  		return PORT_CLK_SEL_LCPLL_2700;
>  	default:
> -		MISSING_CASE(pll->id);
> +		MISSING_CASE(pll->info->id);
>  		return PORT_CLK_SEL_NONE;
>  	}
>  }
> @@ -2131,7 +2131,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
>  		val = I915_READ(DPCLKA_CFGCR0);
>  		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> -		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>  		I915_WRITE(DPCLKA_CFGCR0, val);
>  
>  		/*
> @@ -2148,7 +2148,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>  
>  		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
>  			 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
> -		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
> +		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
>  			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
>  
>  		I915_WRITE(DPLL_CTRL2, val);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index ed46ade0efff..48466b19d1f6 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -291,19 +291,19 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
>  {
>  	struct intel_shared_dpll_state *shared_dpll;
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> -	enum intel_dpll_id i = pll->id;
> +	const enum intel_dpll_id id = pll->info->id;

We don't generally make varaibles const. I guess there are a few
exceptions here and there though.

Anyways pathes 1-5 are
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  
>  	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
>  
> -	if (shared_dpll[i].crtc_mask == 0)
> -		shared_dpll[i].hw_state =
> +	if (shared_dpll[id].crtc_mask == 0)
> +		shared_dpll[id].hw_state =
>  			crtc_state->dpll_hw_state;
>  
>  	crtc_state->shared_dpll = pll;
>  	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
>  			 pipe_name(crtc->pipe));
>  
> -	shared_dpll[pll->id].crtc_mask |= 1 << crtc->pipe;
> +	shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
>  }
>  
>  /**
> @@ -343,15 +343,16 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
>  				      struct intel_shared_dpll *pll,
>  				      struct intel_dpll_hw_state *hw_state)
>  {
> +	const enum intel_dpll_id id = pll->info->id;
>  	uint32_t val;
>  
>  	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
>  		return false;
>  
> -	val = I915_READ(PCH_DPLL(pll->id));
> +	val = I915_READ(PCH_DPLL(id));
>  	hw_state->dpll = val;
> -	hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
> -	hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
> +	hw_state->fp0 = I915_READ(PCH_FP0(id));
> +	hw_state->fp1 = I915_READ(PCH_FP1(id));
>  
>  	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
>  
> @@ -361,8 +362,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
>  static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv,
>  				 struct intel_shared_dpll *pll)
>  {
> -	I915_WRITE(PCH_FP0(pll->id), pll->state.hw_state.fp0);
> -	I915_WRITE(PCH_FP1(pll->id), pll->state.hw_state.fp1);
> +	const enum intel_dpll_id id = pll->info->id;
> +
> +	I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0);
> +	I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1);
>  }
>  
>  static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
> @@ -381,13 +384,15 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
>  static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
>  				struct intel_shared_dpll *pll)
>  {
> +	const enum intel_dpll_id id = pll->info->id;
> +
>  	/* PCH refclock must be enabled first */
>  	ibx_assert_pch_refclk_enabled(dev_priv);
>  
> -	I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
> +	I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
>  
>  	/* Wait for the clocks to stabilize. */
> -	POSTING_READ(PCH_DPLL(pll->id));
> +	POSTING_READ(PCH_DPLL(id));
>  	udelay(150);
>  
>  	/* The pixel multiplier can only be updated once the
> @@ -395,14 +400,15 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
>  	 *
>  	 * So write it again.
>  	 */
> -	I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
> -	POSTING_READ(PCH_DPLL(pll->id));
> +	I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll);
> +	POSTING_READ(PCH_DPLL(id));
>  	udelay(200);
>  }
>  
>  static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
>  				 struct intel_shared_dpll *pll)
>  {
> +	const enum intel_dpll_id id = pll->info->id;
>  	struct drm_device *dev = &dev_priv->drm;
>  	struct intel_crtc *crtc;
>  
> @@ -412,8 +418,8 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
>  			assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
>  	}
>  
> -	I915_WRITE(PCH_DPLL(pll->id), 0);
> -	POSTING_READ(PCH_DPLL(pll->id));
> +	I915_WRITE(PCH_DPLL(id), 0);
> +	POSTING_READ(PCH_DPLL(id));
>  	udelay(200);
>  }
>  
> @@ -469,8 +475,10 @@ static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
>  static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
>  			       struct intel_shared_dpll *pll)
>  {
> -	I915_WRITE(WRPLL_CTL(pll->id), pll->state.hw_state.wrpll);
> -	POSTING_READ(WRPLL_CTL(pll->id));
> +	const enum intel_dpll_id id = pll->info->id;
> +
> +	I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll);
> +	POSTING_READ(WRPLL_CTL(id));
>  	udelay(20);
>  }
>  
> @@ -485,11 +493,12 @@ static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
>  static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
>  				  struct intel_shared_dpll *pll)
>  {
> +	const enum intel_dpll_id id = pll->info->id;
>  	uint32_t val;
>  
> -	val = I915_READ(WRPLL_CTL(pll->id));
> -	I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
> -	POSTING_READ(WRPLL_CTL(pll->id));
> +	val = I915_READ(WRPLL_CTL(id));
> +	I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE);
> +	POSTING_READ(WRPLL_CTL(id));
>  }
>  
>  static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
> @@ -506,12 +515,13 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
>  				       struct intel_shared_dpll *pll,
>  				       struct intel_dpll_hw_state *hw_state)
>  {
> +	const enum intel_dpll_id id = pll->info->id;
>  	uint32_t val;
>  
>  	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
>  		return false;
>  
> -	val = I915_READ(WRPLL_CTL(pll->id));
> +	val = I915_READ(WRPLL_CTL(id));
>  	hw_state->wrpll = val;
>  
>  	intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
> @@ -917,13 +927,15 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
>  static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
>  				    struct intel_shared_dpll *pll)
>  {
> +	const enum intel_dpll_id id = pll->info->id;
>  	uint32_t val;
>  
>  	val = I915_READ(DPLL_CTRL1);
>  
> -	val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) |
> -		 DPLL_CTRL1_LINK_RATE_MASK(pll->id));
> -	val |= pll->state.hw_state.ctrl1 << (pll->id * 6);
> +	val &= ~(DPLL_CTRL1_HDMI_MODE(id) |
> +		 DPLL_CTRL1_SSC(id) |
> +		 DPLL_CTRL1_LINK_RATE_MASK(id));
> +	val |= pll->state.hw_state.ctrl1 << (id * 6);
>  
>  	I915_WRITE(DPLL_CTRL1, val);
>  	POSTING_READ(DPLL_CTRL1);
> @@ -933,24 +945,25 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  			       struct intel_shared_dpll *pll)
>  {
>  	const struct skl_dpll_regs *regs = skl_dpll_regs;
> +	const enum intel_dpll_id id = pll->info->id;
>  
>  	skl_ddi_pll_write_ctrl1(dev_priv, pll);
>  
> -	I915_WRITE(regs[pll->id].cfgcr1, pll->state.hw_state.cfgcr1);
> -	I915_WRITE(regs[pll->id].cfgcr2, pll->state.hw_state.cfgcr2);
> -	POSTING_READ(regs[pll->id].cfgcr1);
> -	POSTING_READ(regs[pll->id].cfgcr2);
> +	I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
> +	I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
> +	POSTING_READ(regs[id].cfgcr1);
> +	POSTING_READ(regs[id].cfgcr2);
>  
>  	/* the enable bit is always bit 31 */
> -	I915_WRITE(regs[pll->id].ctl,
> -		   I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
> +	I915_WRITE(regs[id].ctl,
> +		   I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
>  
>  	if (intel_wait_for_register(dev_priv,
>  				    DPLL_STATUS,
> -				    DPLL_LOCK(pll->id),
> -				    DPLL_LOCK(pll->id),
> +				    DPLL_LOCK(id),
> +				    DPLL_LOCK(id),
>  				    5))
> -		DRM_ERROR("DPLL %d not locked\n", pll->id);
> +		DRM_ERROR("DPLL %d not locked\n", id);
>  }
>  
>  static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
> @@ -963,11 +976,12 @@ static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  				struct intel_shared_dpll *pll)
>  {
>  	const struct skl_dpll_regs *regs = skl_dpll_regs;
> +	const enum intel_dpll_id id = pll->info->id;
>  
>  	/* the enable bit is always bit 31 */
> -	I915_WRITE(regs[pll->id].ctl,
> -		   I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
> -	POSTING_READ(regs[pll->id].ctl);
> +	I915_WRITE(regs[id].ctl,
> +		   I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE);
> +	POSTING_READ(regs[id].ctl);
>  }
>  
>  static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
> @@ -981,6 +995,7 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  {
>  	uint32_t val;
>  	const struct skl_dpll_regs *regs = skl_dpll_regs;
> +	const enum intel_dpll_id id = pll->info->id;
>  	bool ret;
>  
>  	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
> @@ -988,17 +1003,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  
>  	ret = false;
>  
> -	val = I915_READ(regs[pll->id].ctl);
> +	val = I915_READ(regs[id].ctl);
>  	if (!(val & LCPLL_PLL_ENABLE))
>  		goto out;
>  
>  	val = I915_READ(DPLL_CTRL1);
> -	hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
> +	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
>  
>  	/* avoid reading back stale values if HDMI mode is not enabled */
> -	if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) {
> -		hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
> -		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
> +	if (val & DPLL_CTRL1_HDMI_MODE(id)) {
> +		hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1);
> +		hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2);
>  	}
>  	ret = true;
>  
> @@ -1014,6 +1029,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
>  {
>  	uint32_t val;
>  	const struct skl_dpll_regs *regs = skl_dpll_regs;
> +	const enum intel_dpll_id id = pll->info->id;
>  	bool ret;
>  
>  	if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
> @@ -1022,12 +1038,12 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
>  	ret = false;
>  
>  	/* DPLL0 is always enabled since it drives CDCLK */
> -	val = I915_READ(regs[pll->id].ctl);
> +	val = I915_READ(regs[id].ctl);
>  	if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
>  		goto out;
>  
>  	val = I915_READ(DPLL_CTRL1);
> -	hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
> +	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
>  
>  	ret = true;
>  
> @@ -1427,7 +1443,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  				struct intel_shared_dpll *pll)
>  {
>  	uint32_t temp;
> -	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
> +	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
>  	enum dpio_phy phy;
>  	enum dpio_channel ch;
>  
> @@ -1546,7 +1562,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  					struct intel_shared_dpll *pll)
>  {
> -	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
> +	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
>  	uint32_t temp;
>  
>  	temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> @@ -1569,7 +1585,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  					struct intel_shared_dpll *pll,
>  					struct intel_dpll_hw_state *hw_state)
>  {
> -	enum port port = (enum port)pll->id;	/* 1:1 port->PLL mapping */
> +	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
>  	uint32_t val;
>  	bool ret;
>  	enum dpio_phy phy;
> @@ -1949,38 +1965,39 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
>  static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  			       struct intel_shared_dpll *pll)
>  {
> +	const enum intel_dpll_id id = pll->info->id;
>  	uint32_t val;
>  
>  	/* 1. Enable DPLL power in DPLL_ENABLE. */
> -	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
> +	val = I915_READ(CNL_DPLL_ENABLE(id));
>  	val |= PLL_POWER_ENABLE;
> -	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
> +	I915_WRITE(CNL_DPLL_ENABLE(id), val);
>  
>  	/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
>  	if (intel_wait_for_register(dev_priv,
> -				    CNL_DPLL_ENABLE(pll->id),
> +				    CNL_DPLL_ENABLE(id),
>  				    PLL_POWER_STATE,
>  				    PLL_POWER_STATE,
>  				    5))
> -		DRM_ERROR("PLL %d Power not enabled\n", pll->id);
> +		DRM_ERROR("PLL %d Power not enabled\n", id);
>  
>  	/*
>  	 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,
>  	 * select DP mode, and set DP link rate.
>  	 */
>  	val = pll->state.hw_state.cfgcr0;
> -	I915_WRITE(CNL_DPLL_CFGCR0(pll->id), val);
> +	I915_WRITE(CNL_DPLL_CFGCR0(id), val);
>  
>  	/* 4. Reab back to ensure writes completed */
> -	POSTING_READ(CNL_DPLL_CFGCR0(pll->id));
> +	POSTING_READ(CNL_DPLL_CFGCR0(id));
>  
>  	/* 3. Configure DPLL_CFGCR0 */
>  	/* Avoid touch CFGCR1 if HDMI mode is not enabled */
>  	if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
>  		val = pll->state.hw_state.cfgcr1;
> -		I915_WRITE(CNL_DPLL_CFGCR1(pll->id), val);
> +		I915_WRITE(CNL_DPLL_CFGCR1(id), val);
>  		/* 4. Reab back to ensure writes completed */
> -		POSTING_READ(CNL_DPLL_CFGCR1(pll->id));
> +		POSTING_READ(CNL_DPLL_CFGCR1(id));
>  	}
>  
>  	/*
> @@ -1993,17 +2010,17 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  	 */
>  
>  	/* 6. Enable DPLL in DPLL_ENABLE. */
> -	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
> +	val = I915_READ(CNL_DPLL_ENABLE(id));
>  	val |= PLL_ENABLE;
> -	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
> +	I915_WRITE(CNL_DPLL_ENABLE(id), val);
>  
>  	/* 7. Wait for PLL lock status in DPLL_ENABLE. */
>  	if (intel_wait_for_register(dev_priv,
> -				    CNL_DPLL_ENABLE(pll->id),
> +				    CNL_DPLL_ENABLE(id),
>  				    PLL_LOCK,
>  				    PLL_LOCK,
>  				    5))
> -		DRM_ERROR("PLL %d not locked\n", pll->id);
> +		DRM_ERROR("PLL %d not locked\n", id);
>  
>  	/*
>  	 * 8. If the frequency will result in a change to the voltage
> @@ -2023,6 +2040,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  				struct intel_shared_dpll *pll)
>  {
> +	const enum intel_dpll_id id = pll->info->id;
>  	uint32_t val;
>  
>  	/*
> @@ -2040,17 +2058,17 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  	 */
>  
>  	/* 3. Disable DPLL through DPLL_ENABLE. */
> -	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
> +	val = I915_READ(CNL_DPLL_ENABLE(id));
>  	val &= ~PLL_ENABLE;
> -	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
> +	I915_WRITE(CNL_DPLL_ENABLE(id), val);
>  
>  	/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
>  	if (intel_wait_for_register(dev_priv,
> -				    CNL_DPLL_ENABLE(pll->id),
> +				    CNL_DPLL_ENABLE(id),
>  				    PLL_LOCK,
>  				    0,
>  				    5))
> -		DRM_ERROR("PLL %d locked\n", pll->id);
> +		DRM_ERROR("PLL %d locked\n", id);
>  
>  	/*
>  	 * 5. If the frequency will result in a change to the voltage
> @@ -2062,23 +2080,24 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  	 */
>  
>  	/* 6. Disable DPLL power in DPLL_ENABLE. */
> -	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
> +	val = I915_READ(CNL_DPLL_ENABLE(id));
>  	val &= ~PLL_POWER_ENABLE;
> -	I915_WRITE(CNL_DPLL_ENABLE(pll->id), val);
> +	I915_WRITE(CNL_DPLL_ENABLE(id), val);
>  
>  	/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
>  	if (intel_wait_for_register(dev_priv,
> -				    CNL_DPLL_ENABLE(pll->id),
> +				    CNL_DPLL_ENABLE(id),
>  				    PLL_POWER_STATE,
>  				    0,
>  				    5))
> -		DRM_ERROR("PLL %d Power not disabled\n", pll->id);
> +		DRM_ERROR("PLL %d Power not disabled\n", id);
>  }
>  
>  static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  				     struct intel_shared_dpll *pll,
>  				     struct intel_dpll_hw_state *hw_state)
>  {
> +	const enum intel_dpll_id id = pll->info->id;
>  	uint32_t val;
>  	bool ret;
>  
> @@ -2087,16 +2106,16 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  
>  	ret = false;
>  
> -	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
> +	val = I915_READ(CNL_DPLL_ENABLE(id));
>  	if (!(val & PLL_ENABLE))
>  		goto out;
>  
> -	val = I915_READ(CNL_DPLL_CFGCR0(pll->id));
> +	val = I915_READ(CNL_DPLL_CFGCR0(id));
>  	hw_state->cfgcr0 = val;
>  
>  	/* avoid reading back stale values if HDMI mode is not enabled */
>  	if (val & DPLL_CFGCR0_HDMI_MODE) {
> -		hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll->id));
> +		hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id));
>  	}
>  	ret = true;
>  
> @@ -2415,7 +2434,6 @@ void intel_shared_dpll_init(struct drm_device *dev)
>  		WARN_ON(i != dpll_info[i].id);
>  		dev_priv->shared_dplls[i].info = &dpll_info[i];
>  
> -		dev_priv->shared_dplls[i].id = dpll_info[i].id;
>  		dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
>  	}
>  
> @@ -2476,7 +2494,7 @@ void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
>  	struct intel_shared_dpll_state *shared_dpll_state;
>  
>  	shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
> -	shared_dpll_state[dpll->id].crtc_mask &= ~(1 << crtc->pipe);
> +	shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index e5ed3e0269e3..7c95ecce41ee 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -213,6 +213,10 @@ struct dpll_info {
>  	 * @name: DPLL name; used for logging
>  	 */
>  	const char *name;
> +	/**
> +	 * @id: unique indentifier for this DPLL; should match the index in the
> +	 * dev_priv->shared_dplls array
> +	 */
>  	const int id;
>  	/**
>  	 * @funcs: platform specific hooks
> @@ -243,12 +247,6 @@ struct intel_shared_dpll {
>  	 */
>  	bool on;
>  
> -	/**
> -	 * @id: unique indentifier for this DPLL; should match the index in the
> -	 * dev_priv->shared_dplls array
> -	 */
> -	enum intel_dpll_id id;
> -
>  	/**
>  	 * @info: platform specific info
>  	 */
> -- 
> 2.14.3

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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Re: [PATCH v2 7/7] drm/i915: reorder dpll_info members

[Ville Syrjälä]

On Tue, Mar 20, 2018 at 03:06:37PM -0700, Lucas De Marchi wrote:
> Remove 4-bytes hole in this struct an reorder tables accordingly. This
> also changes the last element of the tables to be more future-proof.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 48 +++++++++++++++++------------------
>  drivers/gpu/drm/i915/intel_dpll_mgr.h | 13 ++++++----
>  2 files changed, 32 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index bda69e1ccd76..d5e114e9660b 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1908,9 +1908,9 @@ struct intel_dpll_mgr {
>  };
>  
>  static const struct dpll_info pch_plls[] = {
> -	{ "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 },
> -	{ "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 },
> -	{ NULL, -1, NULL, 0 },
> +	{ "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
> +	{ "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },

I usually prefer named initializer to be used pretty much everywhere.

Patches 6-7 are
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
regardless.

> +	{ },
>  };
>  
>  static const struct intel_dpll_mgr pch_pll_mgr = {
> @@ -1920,13 +1920,13 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
>  };
>  
>  static const struct dpll_info hsw_plls[] = {
> -	{ "WRPLL 1",    DPLL_ID_WRPLL1,     &hsw_ddi_wrpll_funcs, 0 },
> -	{ "WRPLL 2",    DPLL_ID_WRPLL2,     &hsw_ddi_wrpll_funcs, 0 },
> -	{ "SPLL",       DPLL_ID_SPLL,       &hsw_ddi_spll_funcs,  0 },
> -	{ "LCPLL 810",  DPLL_ID_LCPLL_810,  &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
> -	{ "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
> -	{ "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
> -	{ NULL, -1, NULL, },
> +	{ "WRPLL 1",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1,     0 },
> +	{ "WRPLL 2",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2,     0 },
> +	{ "SPLL",       &hsw_ddi_spll_funcs,  DPLL_ID_SPLL,       0 },
> +	{ "LCPLL 810",  &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  INTEL_DPLL_ALWAYS_ON },
> +	{ "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
> +	{ "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
> +	{ },
>  };
>  
>  static const struct intel_dpll_mgr hsw_pll_mgr = {
> @@ -1936,11 +1936,11 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
>  };
>  
>  static const struct dpll_info skl_plls[] = {
> -	{ "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON },
> -	{ "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs,   0 },
> -	{ "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs,   0 },
> -	{ "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs,   0 },
> -	{ NULL, -1, NULL, },
> +	{ "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
> +	{ "DPLL 1", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },
> +	{ "DPLL 2", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },
> +	{ "DPLL 3", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },
> +	{ },
>  };
>  
>  static const struct intel_dpll_mgr skl_pll_mgr = {
> @@ -1950,10 +1950,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
>  };
>  
>  static const struct dpll_info bxt_plls[] = {
> -	{ "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
> -	{ "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
> -	{ "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
> -	{ NULL, -1, NULL, },
> +	{ "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> +	{ "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> +	{ "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> +	{ },
>  };
>  
>  static const struct intel_dpll_mgr bxt_pll_mgr = {
> @@ -2387,10 +2387,10 @@ static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
>  };
>  
>  static const struct dpll_info cnl_plls[] = {
> -	{ "DPLL 0", DPLL_ID_SKL_DPLL0, &cnl_ddi_pll_funcs, 0 },
> -	{ "DPLL 1", DPLL_ID_SKL_DPLL1, &cnl_ddi_pll_funcs, 0 },
> -	{ "DPLL 2", DPLL_ID_SKL_DPLL2, &cnl_ddi_pll_funcs, 0 },
> -	{ NULL, -1, NULL, },
> +	{ "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> +	{ "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> +	{ "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> +	{ },
>  };
>  
>  static const struct intel_dpll_mgr cnl_pll_mgr = {
> @@ -2430,7 +2430,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>  
>  	dpll_info = dpll_mgr->dpll_info;
>  
> -	for (i = 0; dpll_info[i].id >= 0; i++) {
> +	for (i = 0; dpll_info[i].name; i++) {
>  		WARN_ON(i != dpll_info[i].id);
>  		dev_priv->shared_dplls[i].info = &dpll_info[i];
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index e4c01e487be7..4febfaa90bde 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -213,15 +213,18 @@ struct dpll_info {
>  	 * @name: DPLL name; used for logging
>  	 */
>  	const char *name;
> -	/**
> -	 * @id: unique indentifier for this DPLL; should match the index in the
> -	 * dev_priv->shared_dplls array
> -	 */
> -	const int id;
> +
>  	/**
>  	 * @funcs: platform specific hooks
>  	 */
>  	const struct intel_shared_dpll_funcs *funcs;
> +
> +	/**
> +	 * @id: unique indentifier for this DPLL; should match the index in the
> +	 * dev_priv->shared_dplls array
> +	 */
> +	enum intel_dpll_id id;
> +
>  #define INTEL_DPLL_ALWAYS_ON	(1 << 0)
>  	/**
>  	 * @flags:
> -- 
> 2.14.3

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2 7/7] drm/i915: reorder dpll_info members

[Rodrigo Vivi]

On Fri, Mar 23, 2018 at 06:25:52PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 20, 2018 at 03:06:37PM -0700, Lucas De Marchi wrote:
> > Remove 4-bytes hole in this struct an reorder tables accordingly. This
> > also changes the last element of the tables to be more future-proof.
> > 
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dpll_mgr.c | 48 +++++++++++++++++------------------
> >  drivers/gpu/drm/i915/intel_dpll_mgr.h | 13 ++++++----
> >  2 files changed, 32 insertions(+), 29 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index bda69e1ccd76..d5e114e9660b 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -1908,9 +1908,9 @@ struct intel_dpll_mgr {
> >  };
> >  
> >  static const struct dpll_info pch_plls[] = {
> > -	{ "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 },
> > -	{ "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 },
> > -	{ NULL, -1, NULL, 0 },
> > +	{ "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
> > +	{ "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
> 
> I usually prefer named initializer to be used pretty much everywhere.
> 
> Patches 6-7 are
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> regardless.

pushed to dinq. Thanks for patches and reviews.

> 
> > +	{ },
> >  };
> >  
> >  static const struct intel_dpll_mgr pch_pll_mgr = {
> > @@ -1920,13 +1920,13 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
> >  };
> >  
> >  static const struct dpll_info hsw_plls[] = {
> > -	{ "WRPLL 1",    DPLL_ID_WRPLL1,     &hsw_ddi_wrpll_funcs, 0 },
> > -	{ "WRPLL 2",    DPLL_ID_WRPLL2,     &hsw_ddi_wrpll_funcs, 0 },
> > -	{ "SPLL",       DPLL_ID_SPLL,       &hsw_ddi_spll_funcs,  0 },
> > -	{ "LCPLL 810",  DPLL_ID_LCPLL_810,  &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
> > -	{ "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
> > -	{ "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
> > -	{ NULL, -1, NULL, },
> > +	{ "WRPLL 1",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1,     0 },
> > +	{ "WRPLL 2",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2,     0 },
> > +	{ "SPLL",       &hsw_ddi_spll_funcs,  DPLL_ID_SPLL,       0 },
> > +	{ "LCPLL 810",  &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  INTEL_DPLL_ALWAYS_ON },
> > +	{ "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
> > +	{ "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
> > +	{ },
> >  };
> >  
> >  static const struct intel_dpll_mgr hsw_pll_mgr = {
> > @@ -1936,11 +1936,11 @@ static const struct intel_dpll_mgr hsw_pll_mgr = {
> >  };
> >  
> >  static const struct dpll_info skl_plls[] = {
> > -	{ "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON },
> > -	{ "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs,   0 },
> > -	{ "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs,   0 },
> > -	{ "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs,   0 },
> > -	{ NULL, -1, NULL, },
> > +	{ "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
> > +	{ "DPLL 1", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },
> > +	{ "DPLL 2", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },
> > +	{ "DPLL 3", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },
> > +	{ },
> >  };
> >  
> >  static const struct intel_dpll_mgr skl_pll_mgr = {
> > @@ -1950,10 +1950,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
> >  };
> >  
> >  static const struct dpll_info bxt_plls[] = {
> > -	{ "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
> > -	{ "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
> > -	{ "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
> > -	{ NULL, -1, NULL, },
> > +	{ "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> > +	{ "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> > +	{ "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> > +	{ },
> >  };
> >  
> >  static const struct intel_dpll_mgr bxt_pll_mgr = {
> > @@ -2387,10 +2387,10 @@ static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
> >  };
> >  
> >  static const struct dpll_info cnl_plls[] = {
> > -	{ "DPLL 0", DPLL_ID_SKL_DPLL0, &cnl_ddi_pll_funcs, 0 },
> > -	{ "DPLL 1", DPLL_ID_SKL_DPLL1, &cnl_ddi_pll_funcs, 0 },
> > -	{ "DPLL 2", DPLL_ID_SKL_DPLL2, &cnl_ddi_pll_funcs, 0 },
> > -	{ NULL, -1, NULL, },
> > +	{ "DPLL 0", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
> > +	{ "DPLL 1", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
> > +	{ "DPLL 2", &cnl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
> > +	{ },
> >  };
> >  
> >  static const struct intel_dpll_mgr cnl_pll_mgr = {
> > @@ -2430,7 +2430,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> >  
> >  	dpll_info = dpll_mgr->dpll_info;
> >  
> > -	for (i = 0; dpll_info[i].id >= 0; i++) {
> > +	for (i = 0; dpll_info[i].name; i++) {
> >  		WARN_ON(i != dpll_info[i].id);
> >  		dev_priv->shared_dplls[i].info = &dpll_info[i];
> >  	}
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > index e4c01e487be7..4febfaa90bde 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > @@ -213,15 +213,18 @@ struct dpll_info {
> >  	 * @name: DPLL name; used for logging
> >  	 */
> >  	const char *name;
> > -	/**
> > -	 * @id: unique indentifier for this DPLL; should match the index in the
> > -	 * dev_priv->shared_dplls array
> > -	 */
> > -	const int id;
> > +
> >  	/**
> >  	 * @funcs: platform specific hooks
> >  	 */
> >  	const struct intel_shared_dpll_funcs *funcs;
> > +
> > +	/**
> > +	 * @id: unique indentifier for this DPLL; should match the index in the
> > +	 * dev_priv->shared_dplls array
> > +	 */
> > +	enum intel_dpll_id id;
> > +
> >  #define INTEL_DPLL_ALWAYS_ON	(1 << 0)
> >  	/**
> >  	 * @flags:
> > -- 
> > 2.14.3
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
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