* [PATCH] drm/i915: Actually flush interrupts on reset not just wedging
@ 2018-03-23 9:08 Chris Wilson
2018-03-23 9:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: Chris Wilson @ 2018-03-23 9:08 UTC (permalink / raw)
To: intel-gfx
Commit 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU
reset") got confused and only applied the flush to the set-wedge path
(which itself is proving troublesome), but we also need the
serialisation on the regular reset path. Oops.
Move the interrupt into reset_irq() and make it common to the reset and
final set-wedge.
References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 105 ++++++++++++++++++++-------------------
1 file changed, 53 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ce09c5ad334f..2e53882b826b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -740,6 +740,57 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
}
}
+static void clear_gtiir(struct intel_engine_cs *engine)
+{
+ static const u8 gtiir[] = {
+ [RCS] = 0,
+ [BCS] = 0,
+ [VCS] = 1,
+ [VCS2] = 1,
+ [VECS] = 3,
+ };
+ struct drm_i915_private *dev_priv = engine->i915;
+ int i;
+
+ /* TODO: correctly reset irqs for gen11 */
+ if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
+ return;
+
+ GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
+
+ /*
+ * Clear any pending interrupt state.
+ *
+ * We do it twice out of paranoia that some of the IIR are
+ * double buffered, and so if we only reset it once there may
+ * still be an interrupt pending.
+ */
+ for (i = 0; i < 2; i++) {
+ I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
+ engine->irq_keep_mask);
+ POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
+ }
+ GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
+ engine->irq_keep_mask);
+}
+
+static void reset_irq(struct intel_engine_cs *engine)
+{
+ /* Mark all CS interrupts as complete */
+ smp_store_mb(engine->execlists.active, 0);
+ synchronize_hardirq(engine->i915->drm.irq);
+
+ clear_gtiir(engine);
+
+ /*
+ * The port is checked prior to scheduling a tasklet, but
+ * just in case we have suspended the tasklet to do the
+ * wedging make sure that when it wakes, it decides there
+ * is no work to do by clearing the irq_posted bit.
+ */
+ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+}
+
static void execlists_cancel_requests(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -765,6 +816,8 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
*/
local_irq_save(flags);
+ reset_irq(engine);
+
/* Cancel the requests on the HW and clear the ELSP tracker. */
execlists_cancel_port_requests(execlists);
@@ -805,18 +858,6 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
spin_unlock(&engine->timeline->lock);
- /* Mark all CS interrupts as complete */
- smp_store_mb(execlists->active, 0);
- synchronize_hardirq(engine->i915->drm.irq);
-
- /*
- * The port is checked prior to scheduling a tasklet, but
- * just in case we have suspended the tasklet to do the
- * wedging make sure that when it wakes, it decides there
- * is no work to do by clearing the irq_posted bit.
- */
- clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
-
local_irq_restore(flags);
}
@@ -1566,14 +1607,6 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return ret;
}
-static u8 gtiir[] = {
- [RCS] = 0,
- [BCS] = 0,
- [VCS] = 1,
- [VCS2] = 1,
- [VECS] = 3,
-};
-
static void enable_execlists(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -1657,35 +1690,6 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
return init_workarounds_ring(engine);
}
-static void reset_irq(struct intel_engine_cs *engine)
-{
- struct drm_i915_private *dev_priv = engine->i915;
- int i;
-
- /* TODO: correctly reset irqs for gen11 */
- if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
- return;
-
- GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
-
- /*
- * Clear any pending interrupt state.
- *
- * We do it twice out of paranoia that some of the IIR are double
- * buffered, and if we only reset it once there may still be
- * an interrupt pending.
- */
- for (i = 0; i < 2; i++) {
- I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
- engine->irq_keep_mask);
- POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
- }
- GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
- engine->irq_keep_mask);
-
- clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
-}
-
static void reset_common_ring(struct intel_engine_cs *engine,
struct i915_request *request)
{
@@ -1717,9 +1721,6 @@ static void reset_common_ring(struct intel_engine_cs *engine,
__unwind_incomplete_requests(engine);
spin_unlock(&engine->timeline->lock);
- /* Mark all CS interrupts as complete */
- execlists->active = 0;
-
local_irq_restore(flags);
/*
--
2.16.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Actually flush interrupts on reset not just wedging
2018-03-23 9:08 [PATCH] drm/i915: Actually flush interrupts on reset not just wedging Chris Wilson
@ 2018-03-23 9:55 ` Patchwork
2018-03-23 10:10 ` ✗ Fi.CI.BAT: failure " Patchwork
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-03-23 9:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Actually flush interrupts on reset not just wedging
URL : https://patchwork.freedesktop.org/series/40550/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cac6dd787287 drm/i915: Actually flush interrupts on reset not just wedging
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#17:
References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
-:17: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")'
#17:
References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
total: 1 errors, 1 warnings, 0 checks, 141 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Actually flush interrupts on reset not just wedging
2018-03-23 9:08 [PATCH] drm/i915: Actually flush interrupts on reset not just wedging Chris Wilson
2018-03-23 9:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2018-03-23 10:10 ` Patchwork
2018-03-23 10:18 ` [PATCH v2] " Chris Wilson
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-03-23 10:10 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Actually flush interrupts on reset not just wedging
URL : https://patchwork.freedesktop.org/series/40550/
State : failure
== Summary ==
Series 40550v1 drm/i915: Actually flush interrupts on reset not just wedging
https://patchwork.freedesktop.org/api/1.0/series/40550/revisions/1/mbox/
---- Possible new issues:
Test gem_busy:
Subgroup basic-hang-default:
pass -> INCOMPLETE (fi-bdw-5557u)
pass -> INCOMPLETE (fi-bdw-gvtdvm)
pass -> INCOMPLETE (fi-bsw-n3050)
pass -> INCOMPLETE (fi-bxt-j4205)
pass -> INCOMPLETE (fi-cfl-8700k)
pass -> INCOMPLETE (fi-cfl-u)
pass -> INCOMPLETE (fi-cnl-y3)
pass -> INCOMPLETE (fi-glk-1)
pass -> INCOMPLETE (fi-kbl-7500u)
pass -> INCOMPLETE (fi-kbl-7567u)
pass -> INCOMPLETE (fi-kbl-r)
---- Known issues:
Test gem_busy:
Subgroup basic-hang-default:
pass -> INCOMPLETE (fi-skl-6260u) fdo#104108 +5
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-bdw-gvtdvm total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:384s
fi-bsw-n3050 total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:302s
fi-bxt-j4205 total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:518s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:507s
fi-cfl-8700k total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-cfl-u total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-cnl-y3 total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:426s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:314s
fi-glk-1 total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:405s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:420s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:461s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:428s
fi-kbl-7500u total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-kbl-7567u total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-kbl-r total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:648s
fi-skl-6260u total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-skl-6600u total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-skl-6700k2 total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-skl-6770hq total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-skl-guc total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-skl-gvtdvm total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:576s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:401s
Blacklisted hosts:
fi-cfl-s3 total:11 pass:10 dwarn:0 dfail:0 fail:0 skip:0
4db112a713cbe4fa2e65a2f1c5c21bf1076aae49 drm-tip: 2018y-03m-23d-09h-23m-53s UTC integration manifest
cac6dd787287 drm/i915: Actually flush interrupts on reset not just wedging
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8467/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2] drm/i915: Actually flush interrupts on reset not just wedging
2018-03-23 9:08 [PATCH] drm/i915: Actually flush interrupts on reset not just wedging Chris Wilson
2018-03-23 9:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-03-23 10:10 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-03-23 10:18 ` Chris Wilson
2018-03-23 10:53 ` Mika Kuoppala
2018-03-23 12:37 ` Mika Kuoppala
2018-03-23 11:41 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Actually flush interrupts on reset not just wedging (rev2) Patchwork
` (4 subsequent siblings)
7 siblings, 2 replies; 13+ messages in thread
From: Chris Wilson @ 2018-03-23 10:18 UTC (permalink / raw)
To: intel-gfx
Commit 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU
reset") got confused and only applied the flush to the set-wedge path
(which itself is proving troublesome), but we also need the
serialisation on the regular reset path. Oops.
Move the interrupt into reset_irq() and make it common to the reset and
final set-wedge.
v2: reset_irq() after port cancellation, as we assert that
execlists->active is sane for cancellation (and is being reset by
reset_irq).
References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 107 +++++++++++++++++++--------------------
1 file changed, 53 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ce09c5ad334f..b4ab06b05e58 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -740,6 +740,57 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
}
}
+static void clear_gtiir(struct intel_engine_cs *engine)
+{
+ static const u8 gtiir[] = {
+ [RCS] = 0,
+ [BCS] = 0,
+ [VCS] = 1,
+ [VCS2] = 1,
+ [VECS] = 3,
+ };
+ struct drm_i915_private *dev_priv = engine->i915;
+ int i;
+
+ /* TODO: correctly reset irqs for gen11 */
+ if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
+ return;
+
+ GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
+
+ /*
+ * Clear any pending interrupt state.
+ *
+ * We do it twice out of paranoia that some of the IIR are
+ * double buffered, and so if we only reset it once there may
+ * still be an interrupt pending.
+ */
+ for (i = 0; i < 2; i++) {
+ I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
+ engine->irq_keep_mask);
+ POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
+ }
+ GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
+ engine->irq_keep_mask);
+}
+
+static void reset_irq(struct intel_engine_cs *engine)
+{
+ /* Mark all CS interrupts as complete */
+ smp_store_mb(engine->execlists.active, 0);
+ synchronize_hardirq(engine->i915->drm.irq);
+
+ clear_gtiir(engine);
+
+ /*
+ * The port is checked prior to scheduling a tasklet, but
+ * just in case we have suspended the tasklet to do the
+ * wedging make sure that when it wakes, it decides there
+ * is no work to do by clearing the irq_posted bit.
+ */
+ clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+}
+
static void execlists_cancel_requests(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -767,6 +818,7 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
/* Cancel the requests on the HW and clear the ELSP tracker. */
execlists_cancel_port_requests(execlists);
+ reset_irq(engine);
spin_lock(&engine->timeline->lock);
@@ -805,18 +857,6 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
spin_unlock(&engine->timeline->lock);
- /* Mark all CS interrupts as complete */
- smp_store_mb(execlists->active, 0);
- synchronize_hardirq(engine->i915->drm.irq);
-
- /*
- * The port is checked prior to scheduling a tasklet, but
- * just in case we have suspended the tasklet to do the
- * wedging make sure that when it wakes, it decides there
- * is no work to do by clearing the irq_posted bit.
- */
- clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
-
local_irq_restore(flags);
}
@@ -1566,14 +1606,6 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
return ret;
}
-static u8 gtiir[] = {
- [RCS] = 0,
- [BCS] = 0,
- [VCS] = 1,
- [VCS2] = 1,
- [VECS] = 3,
-};
-
static void enable_execlists(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
@@ -1657,35 +1689,6 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
return init_workarounds_ring(engine);
}
-static void reset_irq(struct intel_engine_cs *engine)
-{
- struct drm_i915_private *dev_priv = engine->i915;
- int i;
-
- /* TODO: correctly reset irqs for gen11 */
- if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
- return;
-
- GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
-
- /*
- * Clear any pending interrupt state.
- *
- * We do it twice out of paranoia that some of the IIR are double
- * buffered, and if we only reset it once there may still be
- * an interrupt pending.
- */
- for (i = 0; i < 2; i++) {
- I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
- engine->irq_keep_mask);
- POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
- }
- GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
- engine->irq_keep_mask);
-
- clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
-}
-
static void reset_common_ring(struct intel_engine_cs *engine,
struct i915_request *request)
{
@@ -1699,8 +1702,6 @@ static void reset_common_ring(struct intel_engine_cs *engine,
/* See execlists_cancel_requests() for the irq/spinlock split. */
local_irq_save(flags);
- reset_irq(engine);
-
/*
* Catch up with any missed context-switch interrupts.
*
@@ -1711,15 +1712,13 @@ static void reset_common_ring(struct intel_engine_cs *engine,
* requests were completed.
*/
execlists_cancel_port_requests(execlists);
+ reset_irq(engine);
/* Push back any incomplete requests for replay after the reset. */
spin_lock(&engine->timeline->lock);
__unwind_incomplete_requests(engine);
spin_unlock(&engine->timeline->lock);
- /* Mark all CS interrupts as complete */
- execlists->active = 0;
-
local_irq_restore(flags);
/*
--
2.16.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2] drm/i915: Actually flush interrupts on reset not just wedging
2018-03-23 10:18 ` [PATCH v2] " Chris Wilson
@ 2018-03-23 10:53 ` Mika Kuoppala
2018-03-23 11:01 ` Chris Wilson
2018-03-23 12:37 ` Mika Kuoppala
1 sibling, 1 reply; 13+ messages in thread
From: Mika Kuoppala @ 2018-03-23 10:53 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Commit 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU
> reset") got confused and only applied the flush to the set-wedge path
> (which itself is proving troublesome), but we also need the
> serialisation on the regular reset path. Oops.
>
> Move the interrupt into reset_irq() and make it common to the reset and
> final set-wedge.
>
> v2: reset_irq() after port cancellation, as we assert that
> execlists->active is sane for cancellation (and is being reset by
> reset_irq).
>
> References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 107 +++++++++++++++++++--------------------
> 1 file changed, 53 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ce09c5ad334f..b4ab06b05e58 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -740,6 +740,57 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
> }
> }
>
> +static void clear_gtiir(struct intel_engine_cs *engine)
> +{
> + static const u8 gtiir[] = {
> + [RCS] = 0,
> + [BCS] = 0,
> + [VCS] = 1,
> + [VCS2] = 1,
> + [VECS] = 3,
> + };
> + struct drm_i915_private *dev_priv = engine->i915;
> + int i;
> +
> + /* TODO: correctly reset irqs for gen11 */
> + if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
> + return;
> +
> + GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
> +
> + /*
> + * Clear any pending interrupt state.
> + *
> + * We do it twice out of paranoia that some of the IIR are
> + * double buffered, and so if we only reset it once there may
> + * still be an interrupt pending.
> + */
> + for (i = 0; i < 2; i++) {
> + I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
> + engine->irq_keep_mask);
> + POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
> + }
> + GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
> + engine->irq_keep_mask);
> +}
> +
> +static void reset_irq(struct intel_engine_cs *engine)
> +{
> + /* Mark all CS interrupts as complete */
> + smp_store_mb(engine->execlists.active, 0);
> + synchronize_hardirq(engine->i915->drm.irq);
> +
> + clear_gtiir(engine);
Should clearing the iir be before we synchronize?
Our master irq is off, so no bit can light up,
clear iir, prevent tasklet with active and synchronize.
For documentation it would be nice that we have
assert that the tasklet is indeed disabled.
-Mika
> +
> + /*
> + * The port is checked prior to scheduling a tasklet, but
> + * just in case we have suspended the tasklet to do the
> + * wedging make sure that when it wakes, it decides there
> + * is no work to do by clearing the irq_posted bit.
> + */
> + clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
> +}
> +
> static void execlists_cancel_requests(struct intel_engine_cs *engine)
> {
> struct intel_engine_execlists * const execlists = &engine->execlists;
> @@ -767,6 +818,7 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
>
> /* Cancel the requests on the HW and clear the ELSP tracker. */
> execlists_cancel_port_requests(execlists);
> + reset_irq(engine);
>
> spin_lock(&engine->timeline->lock);
>
> @@ -805,18 +857,6 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
>
> spin_unlock(&engine->timeline->lock);
>
> - /* Mark all CS interrupts as complete */
> - smp_store_mb(execlists->active, 0);
> - synchronize_hardirq(engine->i915->drm.irq);
> -
> - /*
> - * The port is checked prior to scheduling a tasklet, but
> - * just in case we have suspended the tasklet to do the
> - * wedging make sure that when it wakes, it decides there
> - * is no work to do by clearing the irq_posted bit.
> - */
> - clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
> -
> local_irq_restore(flags);
> }
>
> @@ -1566,14 +1606,6 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> return ret;
> }
>
> -static u8 gtiir[] = {
> - [RCS] = 0,
> - [BCS] = 0,
> - [VCS] = 1,
> - [VCS2] = 1,
> - [VECS] = 3,
> -};
> -
> static void enable_execlists(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *dev_priv = engine->i915;
> @@ -1657,35 +1689,6 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
> return init_workarounds_ring(engine);
> }
>
> -static void reset_irq(struct intel_engine_cs *engine)
> -{
> - struct drm_i915_private *dev_priv = engine->i915;
> - int i;
> -
> - /* TODO: correctly reset irqs for gen11 */
> - if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
> - return;
> -
> - GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
> -
> - /*
> - * Clear any pending interrupt state.
> - *
> - * We do it twice out of paranoia that some of the IIR are double
> - * buffered, and if we only reset it once there may still be
> - * an interrupt pending.
> - */
> - for (i = 0; i < 2; i++) {
> - I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
> - engine->irq_keep_mask);
> - POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
> - }
> - GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
> - engine->irq_keep_mask);
> -
> - clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
> -}
> -
> static void reset_common_ring(struct intel_engine_cs *engine,
> struct i915_request *request)
> {
> @@ -1699,8 +1702,6 @@ static void reset_common_ring(struct intel_engine_cs *engine,
> /* See execlists_cancel_requests() for the irq/spinlock split. */
> local_irq_save(flags);
>
> - reset_irq(engine);
> -
> /*
> * Catch up with any missed context-switch interrupts.
> *
> @@ -1711,15 +1712,13 @@ static void reset_common_ring(struct intel_engine_cs *engine,
> * requests were completed.
> */
> execlists_cancel_port_requests(execlists);
> + reset_irq(engine);
>
> /* Push back any incomplete requests for replay after the reset. */
> spin_lock(&engine->timeline->lock);
> __unwind_incomplete_requests(engine);
> spin_unlock(&engine->timeline->lock);
>
> - /* Mark all CS interrupts as complete */
> - execlists->active = 0;
> -
> local_irq_restore(flags);
>
> /*
> --
> 2.16.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2] drm/i915: Actually flush interrupts on reset not just wedging
2018-03-23 10:53 ` Mika Kuoppala
@ 2018-03-23 11:01 ` Chris Wilson
0 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2018-03-23 11:01 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: Michel
Quoting Mika Kuoppala (2018-03-23 10:53:00)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Commit 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU
> > reset") got confused and only applied the flush to the set-wedge path
> > (which itself is proving troublesome), but we also need the
> > serialisation on the regular reset path. Oops.
> >
> > Move the interrupt into reset_irq() and make it common to the reset and
> > final set-wedge.
> >
> > v2: reset_irq() after port cancellation, as we assert that
> > execlists->active is sane for cancellation (and is being reset by
> > reset_irq).
> >
> > References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Michel Thierry <michel.thierry@intel.com>
> > Cc: Michał Winiarski <michal.winiarski@intel.com>
> > Cc: Jeff McGee <jeff.mcgee@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_lrc.c | 107 +++++++++++++++++++--------------------
> > 1 file changed, 53 insertions(+), 54 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index ce09c5ad334f..b4ab06b05e58 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -740,6 +740,57 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
> > }
> > }
> >
> > +static void clear_gtiir(struct intel_engine_cs *engine)
> > +{
> > + static const u8 gtiir[] = {
> > + [RCS] = 0,
> > + [BCS] = 0,
> > + [VCS] = 1,
> > + [VCS2] = 1,
> > + [VECS] = 3,
> > + };
> > + struct drm_i915_private *dev_priv = engine->i915;
> > + int i;
> > +
> > + /* TODO: correctly reset irqs for gen11 */
> > + if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
> > + return;
> > +
> > + GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
> > +
> > + /*
> > + * Clear any pending interrupt state.
> > + *
> > + * We do it twice out of paranoia that some of the IIR are
> > + * double buffered, and so if we only reset it once there may
> > + * still be an interrupt pending.
> > + */
> > + for (i = 0; i < 2; i++) {
> > + I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
> > + engine->irq_keep_mask);
> > + POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
> > + }
> > + GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
> > + engine->irq_keep_mask);
> > +}
> > +
> > +static void reset_irq(struct intel_engine_cs *engine)
> > +{
> > + /* Mark all CS interrupts as complete */
> > + smp_store_mb(engine->execlists.active, 0);
> > + synchronize_hardirq(engine->i915->drm.irq);
> > +
> > + clear_gtiir(engine);
>
> Should clearing the iir be before we synchronize?
> Our master irq is off, so no bit can light up,
> clear iir, prevent tasklet with active and synchronize.
After I think. Before we risk running at the same time as an interrupt
handler on another thread. Hence the mb on disabling the execlists
(corresponding with the READ_ONE(active) in gen8_cs_irq_handler).
Not that is makes much difference (since we don't trust the consistentcy
of IIR inside the irq handler, because we do randomly reset it), but I
think it makes sense; clear off the interrupt handler, cancel IIR, let
the system resume processing interrupts.
> For documentation it would be nice that we have
> assert that the tasklet is indeed disabled.
Not without poking inside tasklet :) In a couple of patches time I plan
to have tasklet_disable/tasklet_enable from inside intel_lrc. I'll
shovel something in then.
-Chris
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Actually flush interrupts on reset not just wedging (rev2)
2018-03-23 9:08 [PATCH] drm/i915: Actually flush interrupts on reset not just wedging Chris Wilson
` (2 preceding siblings ...)
2018-03-23 10:18 ` [PATCH v2] " Chris Wilson
@ 2018-03-23 11:41 ` Patchwork
2018-03-23 11:56 ` ✗ Fi.CI.BAT: failure " Patchwork
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-03-23 11:41 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Actually flush interrupts on reset not just wedging (rev2)
URL : https://patchwork.freedesktop.org/series/40550/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a91768efb72a drm/i915: Actually flush interrupts on reset not just wedging
-:21: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#21:
References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
-:21: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")'
#21:
References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
total: 1 errors, 1 warnings, 0 checks, 155 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Actually flush interrupts on reset not just wedging (rev2)
2018-03-23 9:08 [PATCH] drm/i915: Actually flush interrupts on reset not just wedging Chris Wilson
` (3 preceding siblings ...)
2018-03-23 11:41 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Actually flush interrupts on reset not just wedging (rev2) Patchwork
@ 2018-03-23 11:56 ` Patchwork
2018-03-23 12:06 ` Chris Wilson
2018-03-23 14:59 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
` (2 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Patchwork @ 2018-03-23 11:56 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Actually flush interrupts on reset not just wedging (rev2)
URL : https://patchwork.freedesktop.org/series/40550/
State : failure
== Summary ==
Series 40550v2 drm/i915: Actually flush interrupts on reset not just wedging
https://patchwork.freedesktop.org/api/1.0/series/40550/revisions/2/mbox/
---- Possible new issues:
Test kms_pipe_crc_basic:
Subgroup nonblocking-crc-pipe-a:
pass -> INCOMPLETE (fi-elk-e7500)
---- Known issues:
Test prime_vgem:
Subgroup basic-fence-flip:
pass -> FAIL (fi-ilk-650) fdo#104008
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:433s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:444s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:380s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:539s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:298s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:516s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:512s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:519s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:505s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:411s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:510s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:583s
fi-elk-e7500 total:229 pass:180 dwarn:1 dfail:0 fail:0 skip:47
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:318s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:534s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:404s
fi-ilk-650 total:285 pass:224 dwarn:0 dfail:0 fail:1 skip:60 time:418s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:471s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:427s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:477s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:473s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:512s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:653s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:441s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:533s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:502s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:503s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:435s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:446s
fi-snb-2520m total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:587s
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:401s
Blacklisted hosts:
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:568s
fi-cnl-psr total:224 pass:198 dwarn:0 dfail:0 fail:1 skip:24
fi-glk-j4005 failed to collect. IGT log at Patchwork_8469/fi-glk-j4005/run0.log
cd07c5746555228b6e288618b40f35c8cc5e1270 drm-tip: 2018y-03m-23d-10h-46m-36s UTC integration manifest
a91768efb72a drm/i915: Actually flush interrupts on reset not just wedging
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8469/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: Actually flush interrupts on reset not just wedging (rev2)
2018-03-23 11:56 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-03-23 12:06 ` Chris Wilson
0 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2018-03-23 12:06 UTC (permalink / raw)
To: Patchwork; +Cc: intel-gfx
Quoting Patchwork (2018-03-23 11:56:41)
> == Series Details ==
>
> Series: drm/i915: Actually flush interrupts on reset not just wedging (rev2)
> URL : https://patchwork.freedesktop.org/series/40550/
> State : failure
>
> == Summary ==
>
> Series 40550v2 drm/i915: Actually flush interrupts on reset not just wedging
> https://patchwork.freedesktop.org/api/1.0/series/40550/revisions/2/mbox/
>
> ---- Possible new issues:
>
> Test kms_pipe_crc_basic:
> Subgroup nonblocking-crc-pipe-a:
> pass -> INCOMPLETE (fi-elk-e7500)
You call that a failure! I call that an outright success after last
time!
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2] drm/i915: Actually flush interrupts on reset not just wedging
2018-03-23 10:18 ` [PATCH v2] " Chris Wilson
2018-03-23 10:53 ` Mika Kuoppala
@ 2018-03-23 12:37 ` Mika Kuoppala
1 sibling, 0 replies; 13+ messages in thread
From: Mika Kuoppala @ 2018-03-23 12:37 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Commit 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU
> reset") got confused and only applied the flush to the set-wedge path
> (which itself is proving troublesome), but we also need the
> serialisation on the regular reset path. Oops.
>
> Move the interrupt into reset_irq() and make it common to the reset and
> final set-wedge.
>
> v2: reset_irq() after port cancellation, as we assert that
> execlists->active is sane for cancellation (and is being reset by
> reset_irq).
>
> References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Jeff McGee <jeff.mcgee@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 107 +++++++++++++++++++--------------------
> 1 file changed, 53 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ce09c5ad334f..b4ab06b05e58 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -740,6 +740,57 @@ execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
> }
> }
>
> +static void clear_gtiir(struct intel_engine_cs *engine)
> +{
> + static const u8 gtiir[] = {
> + [RCS] = 0,
> + [BCS] = 0,
> + [VCS] = 1,
> + [VCS2] = 1,
> + [VECS] = 3,
> + };
> + struct drm_i915_private *dev_priv = engine->i915;
> + int i;
> +
> + /* TODO: correctly reset irqs for gen11 */
> + if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
> + return;
> +
> + GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
> +
> + /*
> + * Clear any pending interrupt state.
> + *
> + * We do it twice out of paranoia that some of the IIR are
> + * double buffered, and so if we only reset it once there may
> + * still be an interrupt pending.
> + */
> + for (i = 0; i < 2; i++) {
> + I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
> + engine->irq_keep_mask);
> + POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
> + }
> + GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
> + engine->irq_keep_mask);
> +}
> +
> +static void reset_irq(struct intel_engine_cs *engine)
> +{
> + /* Mark all CS interrupts as complete */
> + smp_store_mb(engine->execlists.active, 0);
> + synchronize_hardirq(engine->i915->drm.irq);
> +
> + clear_gtiir(engine);
> +
> + /*
> + * The port is checked prior to scheduling a tasklet, but
> + * just in case we have suspended the tasklet to do the
> + * wedging make sure that when it wakes, it decides there
> + * is no work to do by clearing the irq_posted bit.
> + */
> + clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
> +}
> +
> static void execlists_cancel_requests(struct intel_engine_cs *engine)
> {
> struct intel_engine_execlists * const execlists = &engine->execlists;
> @@ -767,6 +818,7 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
>
> /* Cancel the requests on the HW and clear the ELSP tracker. */
> execlists_cancel_port_requests(execlists);
> + reset_irq(engine);
>
> spin_lock(&engine->timeline->lock);
>
> @@ -805,18 +857,6 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine)
>
> spin_unlock(&engine->timeline->lock);
>
> - /* Mark all CS interrupts as complete */
> - smp_store_mb(execlists->active, 0);
> - synchronize_hardirq(engine->i915->drm.irq);
> -
> - /*
> - * The port is checked prior to scheduling a tasklet, but
> - * just in case we have suspended the tasklet to do the
> - * wedging make sure that when it wakes, it decides there
> - * is no work to do by clearing the irq_posted bit.
> - */
> - clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
> -
> local_irq_restore(flags);
> }
>
> @@ -1566,14 +1606,6 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> return ret;
> }
>
> -static u8 gtiir[] = {
> - [RCS] = 0,
> - [BCS] = 0,
> - [VCS] = 1,
> - [VCS2] = 1,
> - [VECS] = 3,
> -};
> -
> static void enable_execlists(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *dev_priv = engine->i915;
> @@ -1657,35 +1689,6 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine)
> return init_workarounds_ring(engine);
> }
>
> -static void reset_irq(struct intel_engine_cs *engine)
> -{
> - struct drm_i915_private *dev_priv = engine->i915;
> - int i;
> -
> - /* TODO: correctly reset irqs for gen11 */
> - if (WARN_ON_ONCE(INTEL_GEN(engine->i915) >= 11))
> - return;
> -
> - GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir));
> -
> - /*
> - * Clear any pending interrupt state.
> - *
> - * We do it twice out of paranoia that some of the IIR are double
> - * buffered, and if we only reset it once there may still be
> - * an interrupt pending.
> - */
> - for (i = 0; i < 2; i++) {
> - I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]),
> - engine->irq_keep_mask);
> - POSTING_READ(GEN8_GT_IIR(gtiir[engine->id]));
> - }
> - GEM_BUG_ON(I915_READ(GEN8_GT_IIR(gtiir[engine->id])) &
> - engine->irq_keep_mask);
> -
> - clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
> -}
> -
> static void reset_common_ring(struct intel_engine_cs *engine,
> struct i915_request *request)
> {
> @@ -1699,8 +1702,6 @@ static void reset_common_ring(struct intel_engine_cs *engine,
> /* See execlists_cancel_requests() for the irq/spinlock split. */
> local_irq_save(flags);
>
> - reset_irq(engine);
> -
> /*
> * Catch up with any missed context-switch interrupts.
> *
> @@ -1711,15 +1712,13 @@ static void reset_common_ring(struct intel_engine_cs *engine,
> * requests were completed.
> */
> execlists_cancel_port_requests(execlists);
> + reset_irq(engine);
>
> /* Push back any incomplete requests for replay after the reset. */
> spin_lock(&engine->timeline->lock);
> __unwind_incomplete_requests(engine);
> spin_unlock(&engine->timeline->lock);
>
> - /* Mark all CS interrupts as complete */
> - execlists->active = 0;
> -
> local_irq_restore(flags);
>
> /*
> --
> 2.16.2
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^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Actually flush interrupts on reset not just wedging (rev2)
2018-03-23 9:08 [PATCH] drm/i915: Actually flush interrupts on reset not just wedging Chris Wilson
` (4 preceding siblings ...)
2018-03-23 11:56 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-03-23 14:59 ` Patchwork
2018-03-23 15:14 ` ✓ Fi.CI.BAT: success " Patchwork
2018-03-23 16:59 ` ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-03-23 14:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Actually flush interrupts on reset not just wedging (rev2)
URL : https://patchwork.freedesktop.org/series/40550/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b3648d43615e drm/i915: Actually flush interrupts on reset not just wedging
-:21: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#21:
References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
-:21: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")'
#21:
References: 0f36a85c3bd5 ("drm/i915: Flush pending interrupt following a GPU reset")
total: 1 errors, 1 warnings, 0 checks, 155 lines checked
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^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Actually flush interrupts on reset not just wedging (rev2)
2018-03-23 9:08 [PATCH] drm/i915: Actually flush interrupts on reset not just wedging Chris Wilson
` (5 preceding siblings ...)
2018-03-23 14:59 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
@ 2018-03-23 15:14 ` Patchwork
2018-03-23 16:59 ` ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-03-23 15:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Actually flush interrupts on reset not just wedging (rev2)
URL : https://patchwork.freedesktop.org/series/40550/
State : success
== Summary ==
Series 40550v2 drm/i915: Actually flush interrupts on reset not just wedging
https://patchwork.freedesktop.org/api/1.0/series/40550/revisions/2/mbox/
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fi-bdw-5557u total:285 pass:264 dwarn:0 dfail:0 fail:0 skip:21 time:436s
fi-bdw-gvtdvm total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:441s
fi-blb-e6850 total:285 pass:220 dwarn:1 dfail:0 fail:0 skip:64 time:381s
fi-bsw-n3050 total:285 pass:239 dwarn:0 dfail:0 fail:0 skip:46 time:536s
fi-bwr-2160 total:285 pass:180 dwarn:0 dfail:0 fail:0 skip:105 time:299s
fi-bxt-dsi total:285 pass:255 dwarn:0 dfail:0 fail:0 skip:30 time:520s
fi-bxt-j4205 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:513s
fi-byt-j1900 total:285 pass:250 dwarn:0 dfail:0 fail:0 skip:35 time:523s
fi-byt-n2820 total:285 pass:246 dwarn:0 dfail:0 fail:0 skip:39 time:516s
fi-cfl-8700k total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:414s
fi-cfl-u total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:514s
fi-cnl-y3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:585s
fi-elk-e7500 total:285 pass:225 dwarn:1 dfail:0 fail:0 skip:59 time:429s
fi-gdg-551 total:285 pass:176 dwarn:0 dfail:0 fail:1 skip:108 time:316s
fi-glk-1 total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:540s
fi-hsw-4770 total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:403s
fi-ilk-650 total:285 pass:225 dwarn:0 dfail:0 fail:0 skip:60 time:423s
fi-ivb-3520m total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:476s
fi-ivb-3770 total:285 pass:252 dwarn:0 dfail:0 fail:0 skip:33 time:430s
fi-kbl-7500u total:285 pass:260 dwarn:1 dfail:0 fail:0 skip:24 time:476s
fi-kbl-7567u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:470s
fi-kbl-r total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:515s
fi-pnv-d510 total:285 pass:219 dwarn:1 dfail:0 fail:0 skip:65 time:653s
fi-skl-6260u total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:443s
fi-skl-6600u total:285 pass:258 dwarn:0 dfail:0 fail:0 skip:27 time:552s
fi-skl-6700k2 total:285 pass:261 dwarn:0 dfail:0 fail:0 skip:24 time:500s
fi-skl-6770hq total:285 pass:265 dwarn:0 dfail:0 fail:0 skip:20 time:501s
fi-skl-guc total:285 pass:257 dwarn:0 dfail:0 fail:0 skip:28 time:430s
fi-skl-gvtdvm total:285 pass:262 dwarn:0 dfail:0 fail:0 skip:23 time:449s
fi-snb-2520m total:3 pass:2 dwarn:0 dfail:0 fail:0 skip:0
fi-snb-2600 total:285 pass:245 dwarn:0 dfail:0 fail:0 skip:40 time:406s
Blacklisted hosts:
fi-cfl-s3 total:285 pass:259 dwarn:0 dfail:0 fail:0 skip:26 time:568s
fi-cnl-psr total:224 pass:198 dwarn:0 dfail:0 fail:1 skip:24
fi-glk-j4005 total:285 pass:256 dwarn:0 dfail:0 fail:0 skip:29 time:489s
4ff2198305421dab54e106502c38de82813eb461 drm-tip: 2018y-03m-23d-11h-56m-39s UTC integration manifest
b3648d43615e drm/i915: Actually flush interrupts on reset not just wedging
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8472/issues.html
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: Actually flush interrupts on reset not just wedging (rev2)
2018-03-23 9:08 [PATCH] drm/i915: Actually flush interrupts on reset not just wedging Chris Wilson
` (6 preceding siblings ...)
2018-03-23 15:14 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-03-23 16:59 ` Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-03-23 16:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Actually flush interrupts on reset not just wedging (rev2)
URL : https://patchwork.freedesktop.org/series/40550/
State : success
== Summary ==
---- Known issues:
Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-atomic:
fail -> PASS (shard-hsw) fdo#104873
Test kms_flip:
Subgroup 2x-flip-vs-expired-vblank:
fail -> PASS (shard-hsw) fdo#102887
Subgroup 2x-plain-flip-ts-check:
pass -> FAIL (shard-hsw) fdo#100368 +1
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-apl) fdo#99912
Test kms_sysfs_edid_timing:
pass -> WARN (shard-apl) fdo#100047
fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
shard-apl total:3484 pass:1821 dwarn:1 dfail:0 fail:6 skip:1655 time:13026s
shard-hsw total:3484 pass:1772 dwarn:1 dfail:0 fail:3 skip:1707 time:11640s
shard-snb total:3484 pass:1363 dwarn:1 dfail:0 fail:3 skip:2117 time:7042s
Blacklisted hosts:
shard-kbl total:3484 pass:1941 dwarn:4 dfail:1 fail:9 skip:1529 time:9892s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8472/shards.html
_______________________________________________
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2018-03-23 16:59 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-23 9:08 [PATCH] drm/i915: Actually flush interrupts on reset not just wedging Chris Wilson
2018-03-23 9:55 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-03-23 10:10 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-03-23 10:18 ` [PATCH v2] " Chris Wilson
2018-03-23 10:53 ` Mika Kuoppala
2018-03-23 11:01 ` Chris Wilson
2018-03-23 12:37 ` Mika Kuoppala
2018-03-23 11:41 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Actually flush interrupts on reset not just wedging (rev2) Patchwork
2018-03-23 11:56 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-03-23 12:06 ` Chris Wilson
2018-03-23 14:59 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2018-03-23 15:14 ` ✓ Fi.CI.BAT: success " Patchwork
2018-03-23 16:59 ` ✓ Fi.CI.IGT: " Patchwork
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