* [Qemu-devel] [PATCH for-2.12] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops
@ 2018-03-27 3:47 Richard Henderson
2018-03-27 5:45 ` Emilio G. Cota
2018-03-27 14:39 ` Philippe Mathieu-Daudé
0 siblings, 2 replies; 3+ messages in thread
From: Richard Henderson @ 2018-03-27 3:47 UTC (permalink / raw)
To: qemu-devel; +Cc: mjc, patches
Failure to do so results in the tcg optimizer sign-extending
any constant fold from 32-bits. This turns out to be visible
in the RISC-V testsuite using a host that emits these opcodes
(e.g. any non-x86_64).
Reported-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-opc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index d81a6c4535..e3a43aabb6 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -182,8 +182,8 @@ DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
-DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
-DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
+DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
+DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
--
2.14.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH for-2.12] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops
2018-03-27 3:47 [Qemu-devel] [PATCH for-2.12] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops Richard Henderson
@ 2018-03-27 5:45 ` Emilio G. Cota
2018-03-27 14:39 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 3+ messages in thread
From: Emilio G. Cota @ 2018-03-27 5:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, patches, mjc
On Tue, Mar 27, 2018 at 11:47:57 +0800, Richard Henderson wrote:
> Failure to do so results in the tcg optimizer sign-extending
> any constant fold from 32-bits. This turns out to be visible
> in the RISC-V testsuite using a host that emits these opcodes
> (e.g. any non-x86_64).
>
> Reported-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
E.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH for-2.12] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops
2018-03-27 3:47 [Qemu-devel] [PATCH for-2.12] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops Richard Henderson
2018-03-27 5:45 ` Emilio G. Cota
@ 2018-03-27 14:39 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 3+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-27 14:39 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: patches, mjc
On 03/27/2018 12:47 AM, Richard Henderson wrote:
> Failure to do so results in the tcg optimizer sign-extending
> any constant fold from 32-bits. This turns out to be visible
> in the RISC-V testsuite using a host that emits these opcodes
> (e.g. any non-x86_64).
>
> Reported-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> tcg/tcg-opc.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index d81a6c4535..e3a43aabb6 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -182,8 +182,8 @@ DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
> DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
> DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
> DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
> -DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
> -DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
> +DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
> +DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
>
> #define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
> #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-03-27 3:47 [Qemu-devel] [PATCH for-2.12] tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops Richard Henderson
2018-03-27 5:45 ` Emilio G. Cota
2018-03-27 14:39 ` Philippe Mathieu-Daudé
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