[PATCH] drm/amd/powerplay: Enable ACG SS feature

[PATCH] drm/amd/powerplay: Enable ACG SS feature

[Kenneth Feng]

port the new atomfirmware.h change in order to
support ACG SS feature and populate the ACG SS
parameters into SMU

Change-Id: I3297b93b166abc6e430d14ccdd362e353771ea36
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
---
 drivers/gpu/drm/amd/include/atomfirmware.h         | 12 ++++++++----
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 10 +++++++---
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 22 +++++++++++++---------
 .../amd/powerplay/hwmgr/vega12_processpptables.c   | 11 ++++++++---
 .../drm/amd/powerplay/inc/vega12/smu9_driver_if.h  | 14 +++++++++-----
 5 files changed, 45 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 3ae3da4..0f5ad54 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1264,9 +1264,9 @@ struct atom_smc_dpm_info_v4_1
   uint8_t  ledpin2;
   uint8_t  padding8_4;
 
-  uint8_t  gfxclkspreadenabled;
-  uint8_t  gfxclkspreadpercent;
-  uint16_t gfxclkspreadfreq;
+	uint8_t  pllgfxclkspreadenabled;
+	uint8_t  pllgfxclkspreadpercent;
+	uint16_t pllgfxclkspreadfreq;
 
   uint8_t uclkspreadenabled;
   uint8_t uclkspreadpercent;
@@ -1276,7 +1276,11 @@ struct atom_smc_dpm_info_v4_1
   uint8_t socclkspreadpercent;
   uint16_t socclkspreadfreq;
 
-  uint32_t boardreserved[3];
+	uint8_t  acggfxclkspreadenabled;
+	uint8_t  acggfxclkspreadpercent;
+	uint16_t acggfxclkspreadfreq;
+
+	uint32_t boardreserved[10];
 };
 
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
index 55f9b30..ad42caa 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
@@ -616,9 +616,9 @@ int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
 	param->ledpin1 = info->ledpin1;
 	param->ledpin2 = info->ledpin2;
 
-	param->gfxclkspreadenabled = info->gfxclkspreadenabled;
-	param->gfxclkspreadpercent = info->gfxclkspreadpercent;
-	param->gfxclkspreadfreq = info->gfxclkspreadfreq;
+	param->pllgfxclkspreadenabled = info->pllgfxclkspreadenabled;
+	param->pllgfxclkspreadpercent = info->pllgfxclkspreadpercent;
+	param->pllgfxclkspreadfreq = info->pllgfxclkspreadfreq;
 
 	param->uclkspreadenabled = info->uclkspreadenabled;
 	param->uclkspreadpercent = info->uclkspreadpercent;
@@ -628,5 +628,9 @@ int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
 	param->socclkspreadpercent = info->socclkspreadpercent;
 	param->socclkspreadfreq = info->socclkspreadfreq;
 
+	param->acggfxclkspreadenabled = info->acggfxclkspreadenabled;
+	param->acggfxclkspreadpercent = info->acggfxclkspreadpercent;
+	param->acggfxclkspreadfreq = info->acggfxclkspreadfreq;
+
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
index a957d8f..5b39c48 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
@@ -192,17 +192,21 @@ struct pp_atomfwctrl_smc_dpm_parameters
   uint8_t  ledpin1;
   uint8_t  ledpin2;
 
-  uint8_t  gfxclkspreadenabled;
-  uint8_t  gfxclkspreadpercent;
-  uint16_t gfxclkspreadfreq;
+	uint8_t  pllgfxclkspreadenabled;
+	uint8_t  pllgfxclkspreadpercent;
+	uint16_t pllgfxclkspreadfreq;
 
-  uint8_t  uclkspreadenabled;
-  uint8_t  uclkspreadpercent;
-  uint16_t uclkspreadfreq;
+	uint8_t  uclkspreadenabled;
+	uint8_t  uclkspreadpercent;
+	uint16_t uclkspreadfreq;
 
-  uint8_t socclkspreadenabled;
-  uint8_t socclkspreadpercent;
-  uint16_t socclkspreadfreq;
+	uint8_t socclkspreadenabled;
+	uint8_t socclkspreadpercent;
+	uint16_t socclkspreadfreq;
+
+	uint8_t  acggfxclkspreadenabled;
+	uint8_t  acggfxclkspreadpercent;
+	uint16_t acggfxclkspreadfreq;
 };
 
 int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
index e7d7949..b34113f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
@@ -208,9 +208,9 @@ static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable
 	ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1;
 	ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2;
 
-	ppsmc_pptable->GfxclkSpreadEnabled = smc_dpm_table.gfxclkspreadenabled;
-	ppsmc_pptable->GfxclkSpreadPercent = smc_dpm_table.gfxclkspreadpercent;
-	ppsmc_pptable->GfxclkSpreadFreq = smc_dpm_table.gfxclkspreadfreq;
+	ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table.pllgfxclkspreadenabled;
+	ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table.pllgfxclkspreadpercent;
+	ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table.pllgfxclkspreadfreq;
 
 	ppsmc_pptable->UclkSpreadEnabled = 0;
 	ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent;
@@ -220,6 +220,11 @@ static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable
 	ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent;
 	ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq;
 
+	ppsmc_pptable->AcgGfxclkSpreadEnabled = smc_dpm_table.acggfxclkspreadenabled;
+	ppsmc_pptable->AcgGfxclkSpreadPercent = smc_dpm_table.acggfxclkspreadpercent;
+	ppsmc_pptable->AcgGfxclkSpreadFreq = smc_dpm_table.acggfxclkspreadfreq;
+
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
index cd2e503..fb696e3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
@@ -127,7 +127,7 @@
 #define FEATURE_GFX_EDC_MASK            (1 << FEATURE_GFX_EDC_BIT            )
 #define FEATURE_GFXOFF_MASK             (1 << FEATURE_GFXOFF_BIT             )
 #define FEATURE_CG_MASK                 (1 << FEATURE_CG_BIT                 )
-#define FEATURE_ACG_MASK                (1 << FEATURE_ACG_BIT                )
+#define FEATURE_ACG_MASK          (1 << FEATURE_ACG_BIT)
 #define FEATURE_SPARE_29_MASK           (1 << FEATURE_SPARE_29_BIT           )
 #define FEATURE_SPARE_30_MASK           (1 << FEATURE_SPARE_30_BIT           )
 #define FEATURE_SPARE_31_MASK           (1 << FEATURE_SPARE_31_BIT           )
@@ -481,9 +481,9 @@ typedef struct {
   uint8_t      padding8_4;
 
 
-  uint8_t      GfxclkSpreadEnabled;
-  uint8_t      GfxclkSpreadPercent;
-  uint16_t     GfxclkSpreadFreq;
+	uint8_t      PllGfxclkSpreadEnabled;
+	uint8_t      PllGfxclkSpreadPercent;
+	uint16_t     PllGfxclkSpreadFreq;
 
   uint8_t      UclkSpreadEnabled;
   uint8_t      UclkSpreadPercent;
@@ -493,7 +493,11 @@ typedef struct {
   uint8_t      SocclkSpreadPercent;
   uint16_t     SocclkSpreadFreq;
 
-  uint32_t     BoardReserved[3];
+	uint8_t      AcgGfxclkSpreadEnabled;
+	uint8_t      AcgGfxclkSpreadPercent;
+	uint16_t     AcgGfxclkSpreadFreq;
+
+	uint32_t     BoardReserved[10];
 
 
   uint32_t     MmHubPadding[7];
-- 
2.7.4

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RE: [PATCH] drm/amd/powerplay: Enable ACG SS feature

[Quan, Evan]

Hi Kenneth,

There are several places which fix old coding style(comment inline). Please drop them since this is not a patch to fix coding style.
Other than that, the patch is reviewed-by: Evan Quan <evan.quan@amd.com>

Regards,
Evan
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Kenneth Feng
> Sent: Wednesday, March 28, 2018 3:51 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth <Kenneth.Feng@amd.com>
> Subject: [PATCH] drm/amd/powerplay: Enable ACG SS feature
> 
> port the new atomfirmware.h change in order to support ACG SS feature and
> populate the ACG SS parameters into SMU
> 
> Change-Id: I3297b93b166abc6e430d14ccdd362e353771ea36
> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
> ---
>  drivers/gpu/drm/amd/include/atomfirmware.h         | 12 ++++++++----
>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 10 +++++++---
> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 22
> +++++++++++++---------
>  .../amd/powerplay/hwmgr/vega12_processpptables.c   | 11 ++++++++---
>  .../drm/amd/powerplay/inc/vega12/smu9_driver_if.h  | 14 +++++++++-----
>  5 files changed, 45 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
> b/drivers/gpu/drm/amd/include/atomfirmware.h
> index 3ae3da4..0f5ad54 100644
> --- a/drivers/gpu/drm/amd/include/atomfirmware.h
> +++ b/drivers/gpu/drm/amd/include/atomfirmware.h
> @@ -1264,9 +1264,9 @@ struct atom_smc_dpm_info_v4_1
>    uint8_t  ledpin2;
>    uint8_t  padding8_4;
> 
> -  uint8_t  gfxclkspreadenabled;
> -  uint8_t  gfxclkspreadpercent;
> -  uint16_t gfxclkspreadfreq;
> +	uint8_t  pllgfxclkspreadenabled;
> +	uint8_t  pllgfxclkspreadpercent;
> +	uint16_t pllgfxclkspreadfreq;
> 
>    uint8_t uclkspreadenabled;
>    uint8_t uclkspreadpercent;
> @@ -1276,7 +1276,11 @@ struct atom_smc_dpm_info_v4_1
>    uint8_t socclkspreadpercent;
>    uint16_t socclkspreadfreq;
> 
> -  uint32_t boardreserved[3];
> +	uint8_t  acggfxclkspreadenabled;
> +	uint8_t  acggfxclkspreadpercent;
> +	uint16_t acggfxclkspreadfreq;
> +
> +	uint32_t boardreserved[10];
>  };
> 
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> index 55f9b30..ad42caa 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> @@ -616,9 +616,9 @@ int pp_atomfwctrl_get_smc_dpm_information(struct
> pp_hwmgr *hwmgr,
>  	param->ledpin1 = info->ledpin1;
>  	param->ledpin2 = info->ledpin2;
> 
> -	param->gfxclkspreadenabled = info->gfxclkspreadenabled;
> -	param->gfxclkspreadpercent = info->gfxclkspreadpercent;
> -	param->gfxclkspreadfreq = info->gfxclkspreadfreq;
> +	param->pllgfxclkspreadenabled = info->pllgfxclkspreadenabled;
> +	param->pllgfxclkspreadpercent = info->pllgfxclkspreadpercent;
> +	param->pllgfxclkspreadfreq = info->pllgfxclkspreadfreq;
> 
>  	param->uclkspreadenabled = info->uclkspreadenabled;
>  	param->uclkspreadpercent = info->uclkspreadpercent; @@ -628,5
> +628,9 @@ int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr
> *hwmgr,
>  	param->socclkspreadpercent = info->socclkspreadpercent;
>  	param->socclkspreadfreq = info->socclkspreadfreq;
> 
> +	param->acggfxclkspreadenabled = info->acggfxclkspreadenabled;
> +	param->acggfxclkspreadpercent = info->acggfxclkspreadpercent;
> +	param->acggfxclkspreadfreq = info->acggfxclkspreadfreq;
> +
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> index a957d8f..5b39c48 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> @@ -192,17 +192,21 @@ struct pp_atomfwctrl_smc_dpm_parameters
>    uint8_t  ledpin1;
>    uint8_t  ledpin2;
> 
> -  uint8_t  gfxclkspreadenabled;
> -  uint8_t  gfxclkspreadpercent;
> -  uint16_t gfxclkspreadfreq;
> +	uint8_t  pllgfxclkspreadenabled;
> +	uint8_t  pllgfxclkspreadpercent;
> +	uint16_t pllgfxclkspreadfreq;
> 
> -  uint8_t  uclkspreadenabled;
> -  uint8_t  uclkspreadpercent;
> -  uint16_t uclkspreadfreq;
> +	uint8_t  uclkspreadenabled;
> +	uint8_t  uclkspreadpercent;
> +	uint16_t uclkspreadfreq;
>
[Evan] Not to fix old coding style
> -  uint8_t socclkspreadenabled;
> -  uint8_t socclkspreadpercent;
> -  uint16_t socclkspreadfreq;
> +	uint8_t socclkspreadenabled;
> +	uint8_t socclkspreadpercent;
> +	uint16_t socclkspreadfreq;
> +
[Evan] Not to fix coding style
> +	uint8_t  acggfxclkspreadenabled;
> +	uint8_t  acggfxclkspreadpercent;
> +	uint16_t acggfxclkspreadfreq;
>  };
> 
>  int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
> diff --git
> a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
> index e7d7949..b34113f 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c
> @@ -208,9 +208,9 @@ static int append_vbios_pptable(struct pp_hwmgr
> *hwmgr, PPTable_t *ppsmc_pptable
>  	ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1;
>  	ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2;
> 
> -	ppsmc_pptable->GfxclkSpreadEnabled =
> smc_dpm_table.gfxclkspreadenabled;
> -	ppsmc_pptable->GfxclkSpreadPercent =
> smc_dpm_table.gfxclkspreadpercent;
> -	ppsmc_pptable->GfxclkSpreadFreq =
> smc_dpm_table.gfxclkspreadfreq;
> +	ppsmc_pptable->PllGfxclkSpreadEnabled =
> smc_dpm_table.pllgfxclkspreadenabled;
> +	ppsmc_pptable->PllGfxclkSpreadPercent =
> smc_dpm_table.pllgfxclkspreadpercent;
> +	ppsmc_pptable->PllGfxclkSpreadFreq =
> +smc_dpm_table.pllgfxclkspreadfreq;
> 
>  	ppsmc_pptable->UclkSpreadEnabled = 0;
>  	ppsmc_pptable->UclkSpreadPercent =
> smc_dpm_table.uclkspreadpercent; @@ -220,6 +220,11 @@ static int
> append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t
> *ppsmc_pptable
>  	ppsmc_pptable->SocclkSpreadPercent =
> smc_dpm_table.socclkspreadpercent;
>  	ppsmc_pptable->SocclkSpreadFreq =
> smc_dpm_table.socclkspreadfreq;
> 
> +	ppsmc_pptable->AcgGfxclkSpreadEnabled =
> smc_dpm_table.acggfxclkspreadenabled;
> +	ppsmc_pptable->AcgGfxclkSpreadPercent =
> smc_dpm_table.acggfxclkspreadpercent;
> +	ppsmc_pptable->AcgGfxclkSpreadFreq =
> +smc_dpm_table.acggfxclkspreadfreq;
> +
> +
>  	return 0;
>  }
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
> b/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
> index cd2e503..fb696e3 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/vega12/smu9_driver_if.h
> @@ -127,7 +127,7 @@
>  #define FEATURE_GFX_EDC_MASK            (1 <<
> FEATURE_GFX_EDC_BIT            )
>  #define FEATURE_GFXOFF_MASK             (1 << FEATURE_GFXOFF_BIT             )
>  #define FEATURE_CG_MASK                 (1 << FEATURE_CG_BIT                 )
> -#define FEATURE_ACG_MASK                (1 << FEATURE_ACG_BIT                )
> +#define FEATURE_ACG_MASK          (1 << FEATURE_ACG_BIT)
[Evan] Not to fix coding style
>  #define FEATURE_SPARE_29_MASK           (1 <<
> FEATURE_SPARE_29_BIT           )
>  #define FEATURE_SPARE_30_MASK           (1 <<
> FEATURE_SPARE_30_BIT           )
>  #define FEATURE_SPARE_31_MASK           (1 <<
> FEATURE_SPARE_31_BIT           )
> @@ -481,9 +481,9 @@ typedef struct {
>    uint8_t      padding8_4;
> 
> 
> -  uint8_t      GfxclkSpreadEnabled;
> -  uint8_t      GfxclkSpreadPercent;
> -  uint16_t     GfxclkSpreadFreq;
> +	uint8_t      PllGfxclkSpreadEnabled;
> +	uint8_t      PllGfxclkSpreadPercent;
> +	uint16_t     PllGfxclkSpreadFreq;
> 
>    uint8_t      UclkSpreadEnabled;
>    uint8_t      UclkSpreadPercent;
> @@ -493,7 +493,11 @@ typedef struct {
>    uint8_t      SocclkSpreadPercent;
>    uint16_t     SocclkSpreadFreq;
> 
> -  uint32_t     BoardReserved[3];
> +	uint8_t      AcgGfxclkSpreadEnabled;
> +	uint8_t      AcgGfxclkSpreadPercent;
> +	uint16_t     AcgGfxclkSpreadFreq;
> +
> +	uint32_t     BoardReserved[10];
> 
> 
>    uint32_t     MmHubPadding[7];
> --
> 2.7.4
> 
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Re: [PATCH] drm/amd/powerplay: Enable ACG SS feature

[Huang Rui]

On Wed, Mar 28, 2018 at 03:51:16PM +0800, Kenneth Feng wrote:
> port the new atomfirmware.h change in order to
> support ACG SS feature and populate the ACG SS
> parameters into SMU
> 

We would better to say "update atomfirmware header". Because the guys who
are in community not from AMD will not know where you port it.

> Change-Id: I3297b93b166abc6e430d14ccdd362e353771ea36
> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
> ---
>  drivers/gpu/drm/amd/include/atomfirmware.h         | 12 ++++++++----
>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 10 +++++++---
>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 22 +++++++++++++---------
>  .../amd/powerplay/hwmgr/vega12_processpptables.c   | 11 ++++++++---
>  .../drm/amd/powerplay/inc/vega12/smu9_driver_if.h  | 14 +++++++++-----
>  5 files changed, 45 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
> index 3ae3da4..0f5ad54 100644
> --- a/drivers/gpu/drm/amd/include/atomfirmware.h
> +++ b/drivers/gpu/drm/amd/include/atomfirmware.h
> @@ -1264,9 +1264,9 @@ struct atom_smc_dpm_info_v4_1
>    uint8_t  ledpin2;
>    uint8_t  padding8_4;
>  
> -  uint8_t  gfxclkspreadenabled;
> -  uint8_t  gfxclkspreadpercent;
> -  uint16_t gfxclkspreadfreq;
> +	uint8_t  pllgfxclkspreadenabled;
> +	uint8_t  pllgfxclkspreadpercent;
> +	uint16_t pllgfxclkspreadfreq;
>  

<snip>

> -	param->gfxclkspreadenabled = info->gfxclkspreadenabled;
> -	param->gfxclkspreadpercent = info->gfxclkspreadpercent;
> -	param->gfxclkspreadfreq = info->gfxclkspreadfreq;
> +	param->pllgfxclkspreadenabled = info->pllgfxclkspreadenabled;
> +	param->pllgfxclkspreadpercent = info->pllgfxclkspreadpercent;
> +	param->pllgfxclkspreadfreq = info->pllgfxclkspreadfreq;
>  

<snip>

> -  uint8_t  gfxclkspreadenabled;
> -  uint8_t  gfxclkspreadpercent;
> -  uint16_t gfxclkspreadfreq;
> +	uint8_t  pllgfxclkspreadenabled;
> +	uint8_t  pllgfxclkspreadpercent;
> +	uint16_t pllgfxclkspreadfreq;

<snip>

> -	ppsmc_pptable->GfxclkSpreadEnabled = smc_dpm_table.gfxclkspreadenabled;
> -	ppsmc_pptable->GfxclkSpreadPercent = smc_dpm_table.gfxclkspreadpercent;
> -	ppsmc_pptable->GfxclkSpreadFreq = smc_dpm_table.gfxclkspreadfreq;
> +	ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table.pllgfxclkspreadenabled;
> +	ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table.pllgfxclkspreadpercent;
> +	ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table.pllgfxclkspreadfreq;

<snip>

>  
> -  uint8_t      GfxclkSpreadEnabled;
> -  uint8_t      GfxclkSpreadPercent;
> -  uint16_t     GfxclkSpreadFreq;
> +	uint8_t      PllGfxclkSpreadEnabled;
> +	uint8_t      PllGfxclkSpreadPercent;
> +	uint16_t     PllGfxclkSpreadFreq;
>  

Above changes that in this patch actually just rename "gfxclkspread*" to
"pplgfxclkstread*", and not related directly with ACG. So I suggested that
you can make another patch as "drm/amd/powerplay: rename gfxclk to
pplgfxclk to align atom firmware interfaces". 

With that fixed, patches are
Reviewed-by: Huang Rui <ray.huang@amd.com>

Thanks,
Ray
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