[PATCH 0/2] MCA support on Centaur CPU

[PATCH 0/2] MCA support on Centaur CPU

[David Wang]

This patch set is to provide MCA support on new Centaur CPU. 

The first patch is used to tell the kernel that newer Centaur CPU support 
MCE broadcasting.

The second patch is used to tell the kernel that newer Centaur CPU support 
CMCI. 

David Wang (2):
  x86/mce: new centaur CPUs support MCE broadcasting
  x86/mce: add CMCI support for centaur CPUs

 arch/x86/kernel/cpu/mcheck/mce.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

-- 
1.9.1

[PATCH 1/2] x86/mce: new centaur CPUs support MCE broadcasting

[David Wang]

This patch is used to tell the kernel that newer Centaur CPU support MCE
broadcasting.

Signed-off-by: David Wang <davidwang@zhaoxin.com>
---
 arch/x86/kernel/cpu/mcheck/mce.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 7065846..82b25e1 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1688,6 +1688,17 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
 		if (c->x86 == 6 && c->x86_model == 45)
 			quirk_no_way_out = quirk_sandybridge_ifu;
 	}
+
+	if (c->x86_vendor == X86_VENDOR_CENTAUR) {
+		/*
+		 * All newer centaur CPUs support MCE broadcasting. Enable
+		 * synchronization with a one second timeout.
+		 */
+		if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0xf && c->x86_mask >=0xe)) &&
+			cfg->monarch_timeout < 0)
+			cfg->monarch_timeout = USEC_PER_SEC;
+	}
+
 	if (cfg->monarch_timeout < 0)
 		cfg->monarch_timeout = 0;
 	if (cfg->bootlog != 0)
-- 
1.9.1

[1/2] x86/mce: new centaur CPUs support MCE broadcasting

[davidwang]

This patch is used to tell the kernel that newer Centaur CPU support MCE
broadcasting.

Signed-off-by: David Wang <davidwang@zhaoxin.com>
---
 arch/x86/kernel/cpu/mcheck/mce.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 7065846..82b25e1 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1688,6 +1688,17 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
 		if (c->x86 == 6 && c->x86_model == 45)
 			quirk_no_way_out = quirk_sandybridge_ifu;
 	}
+
+	if (c->x86_vendor == X86_VENDOR_CENTAUR) {
+		/*
+		 * All newer centaur CPUs support MCE broadcasting. Enable
+		 * synchronization with a one second timeout.
+		 */
+		if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0xf && c->x86_mask >=0xe)) &&
+			cfg->monarch_timeout < 0)
+			cfg->monarch_timeout = USEC_PER_SEC;
+	}
+
 	if (cfg->monarch_timeout < 0)
 		cfg->monarch_timeout = 0;
 	if (cfg->bootlog != 0)

[PATCH 2/2] x86/mce: add CMCI support for centaur CPUs

[David Wang]

This patch is used to tell the kernel that centaur CPUs support CMCI
mechanism which is compatible with INTEL CMCI.

Signed-off-by: David Wang <davidwang@zhaoxin.com>
---
 arch/x86/kernel/cpu/mcheck/mce.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 82b25e1..62aa85c 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1751,6 +1751,7 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
 {
 	switch (c->x86_vendor) {
 	case X86_VENDOR_INTEL:
+	case X86_VENDOR_CENTAUR:
 		mce_intel_feature_init(c);
 		mce_adjust_timer = cmci_intel_adjust_timer;
 		break;
-- 
1.9.1

[2/2] x86/mce: add CMCI support for centaur CPUs

[davidwang]

This patch is used to tell the kernel that centaur CPUs support CMCI
mechanism which is compatible with INTEL CMCI.

Signed-off-by: David Wang <davidwang@zhaoxin.com>
---
 arch/x86/kernel/cpu/mcheck/mce.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 82b25e1..62aa85c 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1751,6 +1751,7 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
 {
 	switch (c->x86_vendor) {
 	case X86_VENDOR_INTEL:
+	case X86_VENDOR_CENTAUR:
 		mce_intel_feature_init(c);
 		mce_adjust_timer = cmci_intel_adjust_timer;
 		break;

Re: [PATCH 1/2] x86/mce: new centaur CPUs support MCE broadcasting

[Borislav Petkov]

On Fri, Mar 30, 2018 at 05:53:41PM +0800, David Wang wrote:
> This patch is used to tell the kernel that newer Centaur CPU support MCE
> broadcasting.
> 
> Signed-off-by: David Wang <davidwang@zhaoxin.com>
> ---
>  arch/x86/kernel/cpu/mcheck/mce.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
> index 7065846..82b25e1 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce.c
> @@ -1688,6 +1688,17 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
>  		if (c->x86 == 6 && c->x86_model == 45)
>  			quirk_no_way_out = quirk_sandybridge_ifu;
>  	}
> +
> +	if (c->x86_vendor == X86_VENDOR_CENTAUR) {
> +		/*
> +		 * All newer centaur CPUs support MCE broadcasting. Enable
> +		 * synchronization with a one second timeout.
> +		 */
> +		if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0xf && c->x86_mask >=0xe)) &&

Are some specs or manuals available somewhere on the web for those?

Thx.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

[1/2] x86/mce: new centaur CPUs support MCE broadcasting

[Borislav Petkov]

On Fri, Mar 30, 2018 at 05:53:41PM +0800, David Wang wrote:
> This patch is used to tell the kernel that newer Centaur CPU support MCE
> broadcasting.
> 
> Signed-off-by: David Wang <davidwang@zhaoxin.com>
> ---
>  arch/x86/kernel/cpu/mcheck/mce.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
> index 7065846..82b25e1 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce.c
> @@ -1688,6 +1688,17 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
>  		if (c->x86 == 6 && c->x86_model == 45)
>  			quirk_no_way_out = quirk_sandybridge_ifu;
>  	}
> +
> +	if (c->x86_vendor == X86_VENDOR_CENTAUR) {
> +		/*
> +		 * All newer centaur CPUs support MCE broadcasting. Enable
> +		 * synchronization with a one second timeout.
> +		 */
> +		if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0xf && c->x86_mask >=0xe)) &&

Are some specs or manuals available somewhere on the web for those?

Thx.

Re: [PATCH 0/2] MCA support on Centaur CPU

[Ingo Molnar]

* David Wang <davidwang@zhaoxin.com> wrote:

> This patch set is to provide MCA support on new Centaur CPU. 
> 
> The first patch is used to tell the kernel that newer Centaur CPU support 
> MCE broadcasting.
> 
> The second patch is used to tell the kernel that newer Centaur CPU support 
> CMCI. 
> 
> David Wang (2):
>   x86/mce: new centaur CPUs support MCE broadcasting
>   x86/mce: add CMCI support for centaur CPUs
> 
>  arch/x86/kernel/cpu/mcheck/mce.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Please capitalize 'Centaur' properly in the changelogs and in comments.

Thanks,

	Ingo

Re: 答复: [PATCH 1/2] x86/mce: new centaur CPUs support MCE broadcasting

[Borislav Petkov]

On Wed, Apr 04, 2018 at 02:34:52AM +0000, David Wang wrote:
> Those are new processors and main usage of CentaurHauls CPUs in recent
> years is for limited and/or embedded instead of distribution markets.
> So there is no plan or resource to create such document for public
> access. Is public spec mandatory for code check-in? We can provide
> platforms for verification instead.

Nah, not needed. As long as the code paths don't break anything else and
as long as we can CC you to fix bugs people report, we're good. :-)

Btw, please do not top-post on a public ML.

Thx.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

[1/2] x86/mce: new centaur CPUs support MCE broadcasting

[Borislav Petkov]

On Wed, Apr 04, 2018 at 02:34:52AM +0000, David Wang wrote:
> Those are new processors and main usage of CentaurHauls CPUs in recent
> years is for limited and/or embedded instead of distribution markets.
> So there is no plan or resource to create such document for public
> access. Is public spec mandatory for code check-in? We can provide
> platforms for verification instead.

Nah, not needed. As long as the code paths don't break anything else and
as long as we can CC you to fix bugs people report, we're good. :-)

Btw, please do not top-post on a public ML.

Thx.

答复: 答复: [PATCH 1/2] x86/mce: new centaur CPUs support MCE broadcasting

[David Wang]

> -----邮件原件-----
> 发件人: Borislav Petkov [mailto:bp@alien8.de]
> 发送时间: 2018年4月4日 19:18
> 收件人: David Wang <DavidWang@zhaoxin.com>
> 抄送: tony.luck@intel.com; tglx@linutronix.de; mingo@redhat.com;
> hpa@zytor.com; x86@kernel.org; linux-edac@vger.kernel.org;
> linux-kernel@vger.kernel.org; Bruce Chang (VAS)
> <BruceChang@via-alliance.com>; Cooper Yan(BJ-RD)
> <CooperYan@zhaoxin.com>; Qiyuan Wang(BJ-RD)
> <QiyuanWang@zhaoxin.com>; Benjamin Pan <BenjaminPan@viatech.com>;
> Luke Lin <LukeLin@viacpu.com>; Tim Guo(BJ-RD) <TimGuo@zhaoxin.com>
> 主题: Re: 答复: [PATCH 1/2] x86/mce: new centaur CPUs support MCE
> broadcasting
> 
> On Wed, Apr 04, 2018 at 02:34:52AM +0000, David Wang wrote:
> > Those are new processors and main usage of CentaurHauls CPUs in recent
> > years is for limited and/or embedded instead of distribution markets.
> > So there is no plan or resource to create such document for public
> > access. Is public spec mandatory for code check-in? We can provide
> > platforms for verification instead.
> 
> Nah, not needed. As long as the code paths don't break anything else and as
> long as we can CC you to fix bugs people report, we're good. :-)
> 
> Btw, please do not top-post on a public ML.

I got it.
Thanks.

---
David

> 
> Thx.
> 
> --
> Regards/Gruss,
>     Boris.
> 
> Good mailing practices for 400: avoid top-posting and trim the reply.

[1/2] x86/mce: new centaur CPUs support MCE broadcasting

[davidwang]

> -----邮件原件-----
> 发件人: Borislav Petkov [mailto:bp@alien8.de]
> 发送时间: 2018年4月4日 19:18
> 收件人: David Wang <DavidWang@zhaoxin.com>
> 抄送: tony.luck@intel.com; tglx@linutronix.de; mingo@redhat.com;
> hpa@zytor.com; x86@kernel.org; linux-edac@vger.kernel.org;
> linux-kernel@vger.kernel.org; Bruce Chang (VAS)
> <BruceChang@via-alliance.com>; Cooper Yan(BJ-RD)
> <CooperYan@zhaoxin.com>; Qiyuan Wang(BJ-RD)
> <QiyuanWang@zhaoxin.com>; Benjamin Pan <BenjaminPan@viatech.com>;
> Luke Lin <LukeLin@viacpu.com>; Tim Guo(BJ-RD) <TimGuo@zhaoxin.com>
> 主题: Re: 答复: [PATCH 1/2] x86/mce: new centaur CPUs support MCE
> broadcasting
> 
> On Wed, Apr 04, 2018 at 02:34:52AM +0000, David Wang wrote:
> > Those are new processors and main usage of CentaurHauls CPUs in recent
> > years is for limited and/or embedded instead of distribution markets.
> > So there is no plan or resource to create such document for public
> > access. Is public spec mandatory for code check-in? We can provide
> > platforms for verification instead.
> 
> Nah, not needed. As long as the code paths don't break anything else and as
> long as we can CC you to fix bugs people report, we're good. :-)
> 
> Btw, please do not top-post on a public ML.

I got it.
Thanks.
---
David

> 
> Thx.
> 
> --
> Regards/Gruss,
>     Boris.
> 
> Good mailing practices for 400: avoid top-posting and trim the reply.

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