From: Maxime Ripard <maxime.ripard@bootlin.com> To: Sergey Suloev <ssuloev@orpaltech.com> Cc: Chen-Yu Tsai <wens@csie.org>, Mark Brown <broonie@kernel.org>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org Subject: Re: [PATCH v3 3/6] spi: sun6i: restrict transfer length in PIO-mode Date: Tue, 10 Apr 2018 16:05:04 +0200 [thread overview] Message-ID: <20180410140504.i7kszskwxuoygt5s@flea> (raw) In-Reply-To: <0e2fefa5-b6e7-5e42-cf6e-8fc921f972dd@orpaltech.com> [-- Attachment #1: Type: text/plain, Size: 1208 bytes --] On Mon, Apr 09, 2018 at 02:59:57PM +0300, Sergey Suloev wrote: > > > But as soon as sun4i SPI driver is correctly declaring > > > max_transfer_size then "smart" clients will work well by limiting a > > > single transfer size to FIFO depth. I tested it with real hardware, > > > again. > > This is really not my point. What would prevent you from doing > > multiple transfers in that case, and filling the FIFO entirely, > > waiting for it to be done, then resuming until you have sent the right > > number of bytes? > > Because it makes no sense IMHO. I can't see any single point in allowing > long PIO transfers. Can you find at least one ? I'm probably going to state the obvious here, but to allow long transfers? > I think we should reuse as much SPI core code as possible. The SPI > core can handle an SPI message with multiple transfers, all we need > is to have max_transfer_size = FIFO depth and restrict it in > transfer_one(). There's not a single call to the max_transfer_size hook in the SPI core in 4.16, so that seems a bit too optimistic. Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --]
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From: maxime.ripard@bootlin.com (Maxime Ripard) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/6] spi: sun6i: restrict transfer length in PIO-mode Date: Tue, 10 Apr 2018 16:05:04 +0200 [thread overview] Message-ID: <20180410140504.i7kszskwxuoygt5s@flea> (raw) In-Reply-To: <0e2fefa5-b6e7-5e42-cf6e-8fc921f972dd@orpaltech.com> On Mon, Apr 09, 2018 at 02:59:57PM +0300, Sergey Suloev wrote: > > > But as soon as sun4i SPI driver? is correctly declaring > > > max_transfer_size then "smart" clients will work well by limiting a > > > single transfer size to FIFO depth. I tested it with real hardware, > > > again. > > This is really not my point. What would prevent you from doing > > multiple transfers in that case, and filling the FIFO entirely, > > waiting for it to be done, then resuming until you have sent the right > > number of bytes? > > Because it makes no sense IMHO. I can't see any single point in allowing > long PIO transfers. Can you find at least one ? I'm probably going to state the obvious here, but to allow long transfers? > I think we should reuse as much SPI core code as possible. The SPI > core can handle an SPI message with multiple transfers, all we need > is to have max_transfer_size = FIFO depth and restrict it in > transfer_one(). There's not a single call to the max_transfer_size hook in the SPI core in 4.16, so that seems a bit too optimistic. Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 833 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20180410/ab69b7d9/attachment-0001.sig>
next prev parent reply other threads:[~2018-04-10 14:05 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-04-03 15:44 [PATCH v3 0/6] spi: Add support for DMA transfers in sun6i SPI driver Sergey Suloev 2018-04-03 15:44 ` Sergey Suloev 2018-04-03 15:44 ` [PATCH v3 1/6] spi: sun6i: coding style/readability improvements Sergey Suloev 2018-04-03 15:44 ` Sergey Suloev 2018-04-03 15:44 ` Sergey Suloev 2018-04-04 6:45 ` Maxime Ripard 2018-04-04 6:45 ` Maxime Ripard 2018-04-03 15:44 ` [PATCH v3 2/6] spi: sun6i: handle chip select polarity flag Sergey Suloev 2018-04-03 15:44 ` Sergey Suloev 2018-04-03 15:44 ` [PATCH v3 3/6] spi: sun6i: restrict transfer length in PIO-mode Sergey Suloev 2018-04-03 15:44 ` Sergey Suloev 2018-04-04 6:50 ` Maxime Ripard 2018-04-04 6:50 ` Maxime Ripard 2018-04-04 11:35 ` Sergey Suloev 2018-04-04 11:35 ` Sergey Suloev 2018-04-05 9:19 ` Maxime Ripard 2018-04-05 9:19 ` Maxime Ripard 2018-04-05 9:59 ` Sergey Suloev 2018-04-05 9:59 ` Sergey Suloev 2018-04-05 13:17 ` Mark Brown 2018-04-05 13:17 ` Mark Brown 2018-04-05 13:44 ` Sergey Suloev 2018-04-05 13:44 ` Sergey Suloev 2018-04-06 7:34 ` Maxime Ripard 2018-04-06 7:34 ` Maxime Ripard 2018-04-06 15:48 ` Sergey Suloev 2018-04-06 15:48 ` Sergey Suloev 2018-04-09 9:27 ` Maxime Ripard 2018-04-09 9:27 ` Maxime Ripard 2018-04-09 10:26 ` Sergey Suloev 2018-04-09 10:26 ` Sergey Suloev 2018-04-09 10:50 ` Mark Brown 2018-04-09 10:50 ` Mark Brown 2018-04-09 11:10 ` Sergey Suloev 2018-04-09 11:10 ` Sergey Suloev 2018-04-09 11:27 ` Mark Brown 2018-04-09 11:27 ` Mark Brown 2018-04-09 11:36 ` Maxime Ripard 2018-04-09 11:36 ` Maxime Ripard 2018-04-09 11:59 ` Sergey Suloev 2018-04-09 11:59 ` Sergey Suloev 2018-04-10 14:05 ` Maxime Ripard [this message] 2018-04-10 14:05 ` Maxime Ripard 2018-04-06 15:54 ` Sergey Suloev 2018-04-06 15:54 ` Sergey Suloev 2018-04-05 10:07 ` Mark Brown 2018-04-05 10:07 ` Mark Brown 2018-04-03 15:44 ` [PATCH v3 4/6] spi: sun6i: use completion provided by SPI core Sergey Suloev 2018-04-03 15:44 ` Sergey Suloev 2018-04-03 15:44 ` Sergey Suloev 2018-04-04 6:53 ` Maxime Ripard 2018-04-04 6:53 ` Maxime Ripard 2018-04-03 15:44 ` [PATCH v3 5/6] spi: sun6i: introduce register set/unset helpers Sergey Suloev 2018-04-03 15:44 ` Sergey Suloev 2018-04-04 1:32 ` kbuild test robot 2018-04-04 1:32 ` kbuild test robot 2018-04-04 7:02 ` Maxime Ripard 2018-04-04 7:02 ` Maxime Ripard 2018-04-03 15:44 ` [PATCH v3 6/6] spi: sun6i: add DMA transfers support Sergey Suloev 2018-04-03 15:44 ` Sergey Suloev 2018-04-04 7:00 ` Maxime Ripard 2018-04-04 7:00 ` Maxime Ripard
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