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From: Vinod Koul <vinod.koul@intel.com>
To: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Cc: dan.j.williams@intel.com, michal.simek@xilinx.com,
	appana.durga.rao@xilinx.com, radheys@xilinx.com, lars@metafoo.de,
	dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: [RFC,2/6] dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev dma client
Date: Wed, 11 Apr 2018 14:38:55 +0530	[thread overview]
Message-ID: <20180411090854.GY6014@localhost> (raw)

On Mon, Apr 02, 2018 at 04:09:02PM +0530, Radhey Shyam Pandey wrote:

> +
> +		if (chan->xdev->has_axieth_connected) {
> +			seg = list_first_entry(&desc->segments,
> +					struct xilinx_axidma_tx_segment, node);
> +			if (cb.callback_param) {
> +				app_w = (u32 *) cb.callback_param;

why are you interpreting callback_param? This is plainly wrong.
we do not know what is the interpretation of callback_param and it is
internal to submitter.

What exactly is the problem you are trying to solve?

> +				hw = &seg->hw;
> +				*app_w = hw->status & XILINX_DMA_MAX_TRANS_LEN;
> +				memcpy(app_w, hw->app, sizeof(u32) *
> +					XILINX_DMA_NUM_APP_WORDS);
> +			}

WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vinod.koul@intel.com>
To: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Cc: dan.j.williams@intel.com, michal.simek@xilinx.com,
	appana.durga.rao@xilinx.com, radheys@xilinx.com, lars@metafoo.de,
	dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [RFC 2/6] dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev dma client
Date: Wed, 11 Apr 2018 14:38:55 +0530	[thread overview]
Message-ID: <20180411090854.GY6014@localhost> (raw)
In-Reply-To: <1522665546-10035-3-git-send-email-radheys@xilinx.com>

On Mon, Apr 02, 2018 at 04:09:02PM +0530, Radhey Shyam Pandey wrote:

> +
> +		if (chan->xdev->has_axieth_connected) {
> +			seg = list_first_entry(&desc->segments,
> +					struct xilinx_axidma_tx_segment, node);
> +			if (cb.callback_param) {
> +				app_w = (u32 *) cb.callback_param;

why are you interpreting callback_param? This is plainly wrong.
we do not know what is the interpretation of callback_param and it is
internal to submitter.

What exactly is the problem you are trying to solve?

> +				hw = &seg->hw;
> +				*app_w = hw->status & XILINX_DMA_MAX_TRANS_LEN;
> +				memcpy(app_w, hw->app, sizeof(u32) *
> +					XILINX_DMA_NUM_APP_WORDS);
> +			}

-- 
~Vinod

WARNING: multiple messages have this Message-ID (diff)
From: vinod.koul@intel.com (Vinod Koul)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC 2/6] dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev dma client
Date: Wed, 11 Apr 2018 14:38:55 +0530	[thread overview]
Message-ID: <20180411090854.GY6014@localhost> (raw)
In-Reply-To: <1522665546-10035-3-git-send-email-radheys@xilinx.com>

On Mon, Apr 02, 2018 at 04:09:02PM +0530, Radhey Shyam Pandey wrote:

> +
> +		if (chan->xdev->has_axieth_connected) {
> +			seg = list_first_entry(&desc->segments,
> +					struct xilinx_axidma_tx_segment, node);
> +			if (cb.callback_param) {
> +				app_w = (u32 *) cb.callback_param;

why are you interpreting callback_param? This is plainly wrong.
we do not know what is the interpretation of callback_param and it is
internal to submitter.

What exactly is the problem you are trying to solve?

> +				hw = &seg->hw;
> +				*app_w = hw->status & XILINX_DMA_MAX_TRANS_LEN;
> +				memcpy(app_w, hw->app, sizeof(u32) *
> +					XILINX_DMA_NUM_APP_WORDS);
> +			}

-- 
~Vinod

             reply	other threads:[~2018-04-11  9:08 UTC|newest]

Thread overview: 128+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-11  9:08 Vinod Koul [this message]
2018-04-11  9:08 ` [RFC 2/6] dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev dma client Vinod Koul
2018-04-11  9:08 ` Vinod Koul
  -- strict thread matches above, loose matches on Subject: below --
2018-07-31  4:29 [RFC] dmaengine: Add metadat_ops for dma_async_tx_descriptor Vinod Koul
2018-07-31  4:29 ` Vinod
2018-07-31  4:29 ` Vinod
2018-07-30  9:46 Peter Ujfalusi
2018-07-30  9:46 ` Peter Ujfalusi
2018-07-30  9:46 ` Peter Ujfalusi
2018-07-24 11:14 Vinod Koul
2018-07-24 11:14 ` Vinod
2018-07-24 11:14 ` Vinod
2018-07-20 13:42 Peter Ujfalusi
2018-07-20 13:42 ` Peter Ujfalusi
2018-07-20 13:42 ` Peter Ujfalusi
2018-07-19  9:22 Vinod Koul
2018-07-19  9:22 ` Vinod
2018-07-19  9:22 ` Vinod
2018-07-18 10:06 Peter Ujfalusi
2018-07-18 10:06 ` Peter Ujfalusi
2018-07-18 10:06 ` Peter Ujfalusi
2018-07-10  5:52 Vinod Koul
2018-07-10  5:52 ` Vinod
2018-07-10  5:52 ` Vinod
2018-07-02  6:59 Radhey Shyam Pandey
2018-07-02  6:59 ` Radhey Shyam Pandey
2018-07-02  6:59 ` Radhey Shyam Pandey
2018-06-01 10:24 Peter Ujfalusi
2018-06-01 10:24 ` Peter Ujfalusi
2018-06-01 10:24 ` Peter Ujfalusi
2018-06-01 10:17 [RFC,2/6] dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev dma client Peter Ujfalusi
2018-06-01 10:17 ` [RFC 2/6] " Peter Ujfalusi
2018-06-01 10:17 ` Peter Ujfalusi
2018-05-30 17:29 [RFC,2/6] " Radhey Shyam Pandey
2018-05-30 17:29 ` [RFC 2/6] " Radhey Shyam Pandey
2018-05-30 17:29 ` Radhey Shyam Pandey
2018-05-29 15:04 [RFC,2/6] " Peter Ujfalusi
2018-05-29 15:04 ` [RFC 2/6] " Peter Ujfalusi
2018-05-29 15:04 ` Peter Ujfalusi
2018-05-17  6:39 [RFC,2/6] " Radhey Shyam Pandey
2018-05-17  6:39 ` [RFC 2/6] " Radhey Shyam Pandey
2018-05-17  6:39 ` Radhey Shyam Pandey
2018-04-24  9:50 [RFC,2/6] " Peter Ujfalusi
2018-04-24  9:50 ` [RFC 2/6] " Peter Ujfalusi
2018-04-24  9:50 ` Peter Ujfalusi
2018-04-24  3:55 [RFC,2/6] " Vinod Koul
2018-04-24  3:55 ` [RFC 2/6] " Vinod Koul
2018-04-24  3:55 ` Vinod Koul
2018-04-23  5:23 [RFC,4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Vinod Koul
2018-04-23  5:23 ` [RFC 4/6] " Vinod Koul
2018-04-23  5:23 ` Vinod Koul
2018-04-19 11:40 [RFC,2/6] dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev dma client Peter Ujfalusi
2018-04-19 11:40 ` [RFC 2/6] " Peter Ujfalusi
2018-04-19 11:40 ` Peter Ujfalusi
2018-04-18 13:06 [RFC,2/6] " Lars-Peter Clausen
2018-04-18 13:06 ` [RFC 2/6] " Lars-Peter Clausen
2018-04-18 13:06 ` Lars-Peter Clausen
2018-04-18  7:03 [RFC,2/6] " Peter Ujfalusi
2018-04-18  7:03 ` [RFC 2/6] " Peter Ujfalusi
2018-04-18  7:03 ` Peter Ujfalusi
2018-04-18  6:39 [RFC,2/6] " Peter Ujfalusi
2018-04-18  6:39 ` [RFC 2/6] " Peter Ujfalusi
2018-04-18  6:39 ` Peter Ujfalusi
2018-04-18  6:31 [RFC,2/6] " Peter Ujfalusi
2018-04-18  6:31 ` [RFC 2/6] " Peter Ujfalusi
2018-04-18  6:31 ` Peter Ujfalusi
2018-04-17 15:54 [RFC,2/6] " Lars-Peter Clausen
2018-04-17 15:54 ` [RFC 2/6] " Lars-Peter Clausen
2018-04-17 15:54 ` Lars-Peter Clausen
2018-04-17 15:44 [RFC,2/6] " Lars-Peter Clausen
2018-04-17 15:44 ` [RFC 2/6] " Lars-Peter Clausen
2018-04-17 15:44 ` Lars-Peter Clausen
2018-04-17 15:42 [RFC,2/6] " Vinod Koul
2018-04-17 15:42 ` [RFC 2/6] " Vinod Koul
2018-04-17 15:42 ` Vinod Koul
2018-04-17 14:53 [RFC,2/6] " Peter Ujfalusi
2018-04-17 14:53 ` [RFC 2/6] " Peter Ujfalusi
2018-04-17 14:53 ` Peter Ujfalusi
2018-04-17 13:58 [RFC,2/6] " Lars-Peter Clausen
2018-04-17 13:58 ` [RFC 2/6] " Lars-Peter Clausen
2018-04-17 13:58 ` Lars-Peter Clausen
2018-04-17 13:46 [RFC,2/6] " Peter Ujfalusi
2018-04-17 13:46 ` [RFC 2/6] " Peter Ujfalusi
2018-04-17 13:46 ` Peter Ujfalusi
2018-04-17 12:54 [RFC,2/6] " Lars-Peter Clausen
2018-04-17 12:54 ` [RFC 2/6] " Lars-Peter Clausen
2018-04-17 12:54 ` Lars-Peter Clausen
2018-04-17 12:48 [RFC,5/6] dmaengine: xilinx_dma: Program interrupt delay timeout Radhey Shyam Pandey
2018-04-17 12:48 ` [RFC 5/6] " Radhey Shyam Pandey
2018-04-17 12:48 ` Radhey Shyam Pandey
2018-04-17 12:28 [RFC,4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Radhey Shyam Pandey
2018-04-17 12:28 ` [RFC 4/6] " Radhey Shyam Pandey
2018-04-17 12:28 ` Radhey Shyam Pandey
2018-04-17 11:43 [RFC,2/6] dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev dma client Radhey Shyam Pandey
2018-04-17 11:43 ` [RFC 2/6] " Radhey Shyam Pandey
2018-04-17 11:43 ` Radhey Shyam Pandey
2018-04-17 10:54 [RFC,1/6] dt-bindings: dma: xilinx_dma: Add optional property has_axieth_connected Radhey Shyam Pandey
2018-04-17 10:54 ` [RFC 1/6] " Radhey Shyam Pandey
2018-04-17 10:54 ` Radhey Shyam Pandey
2018-04-11  9:11 [RFC,5/6] dmaengine: xilinx_dma: Program interrupt delay timeout Vinod Koul
2018-04-11  9:11 ` [RFC 5/6] " Vinod Koul
2018-04-11  9:11 ` Vinod Koul
2018-04-11  9:11 [RFC,4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Vinod Koul
2018-04-11  9:11 ` [RFC 4/6] " Vinod Koul
2018-04-11  9:11 ` Vinod Koul
2018-04-11  9:05 [RFC,1/6] dt-bindings: dma: xilinx_dma: Add optional property has_axieth_connected Vinod Koul
2018-04-11  9:05 ` [RFC 1/6] " Vinod Koul
2018-04-11  9:05 ` Vinod Koul
2018-04-02 10:39 [RFC,6/6] dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase Radhey Shyam Pandey
2018-04-02 10:39 ` [RFC 6/6] " Radhey Shyam Pandey
2018-04-02 10:39 ` Radhey Shyam Pandey
2018-04-02 10:39 [RFC,5/6] dmaengine: xilinx_dma: Program interrupt delay timeout Radhey Shyam Pandey
2018-04-02 10:39 ` [RFC 5/6] " Radhey Shyam Pandey
2018-04-02 10:39 ` Radhey Shyam Pandey
2018-04-02 10:39 [RFC,4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Radhey Shyam Pandey
2018-04-02 10:39 ` [RFC 4/6] " Radhey Shyam Pandey
2018-04-02 10:39 ` Radhey Shyam Pandey
2018-04-02 10:39 [RFC,3/6] dmaengine: xilinx_dma: Increase AXI DMA transaction segment count Radhey Shyam Pandey
2018-04-02 10:39 ` [RFC 3/6] " Radhey Shyam Pandey
2018-04-02 10:39 ` Radhey Shyam Pandey
2018-04-02 10:39 [RFC,2/6] dmaengine: xilinx_dma: Pass AXI4-Stream control words to netdev dma client Radhey Shyam Pandey
2018-04-02 10:39 ` [RFC 2/6] " Radhey Shyam Pandey
2018-04-02 10:39 ` Radhey Shyam Pandey
2018-04-02 10:39 [RFC,1/6] dt-bindings: dma: xilinx_dma: Add optional property has_axieth_connected Radhey Shyam Pandey
2018-04-02 10:39 ` [RFC 1/6] " Radhey Shyam Pandey
2018-04-02 10:39 ` Radhey Shyam Pandey
2018-04-02 10:39 [RFC 0/6] Xilinx DMA enhancements and optimization Radhey Shyam Pandey
2018-04-02 10:39 ` Radhey Shyam Pandey

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