* [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support
@ 2017-11-30 1:24 Andre Przywara
2017-11-30 1:24 ` [U-Boot] [RFC PATCH 01/13] serial: s5p: rework Samsung UART driver to get rid of uart.h Andre Przywara
` (13 more replies)
0 siblings, 14 replies; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:24 UTC (permalink / raw)
To: u-boot
Hi,
this is a first draft of the things Amit and I have been working on in
the last months. It introduces support for an SoC called "Nexell S5P6818".
This is an Octa-core ARMv8 SoC with Cortex-A53 cores, which apparently is
closely related to (older) Samsung SoCs. Many peripherals are compatible
to Samsung IP (UART, MMC, Ethernet, timers, ...), but some core peripherals
like the clocks and the pin controller seem to be completely different.
We used the NanoPi M3 board [1] for testing, which uses this SoC along with
the usual suspects of on-board components and connectors.
This port is done completely from scratch, by just looking at the manual.
This allows a much cleaner and modern U-Boot support than the BSP code.
The ARM Generic Timer (aka. arch timer) does not seem to work on this SoC.
Ideally there would be some (hidden?) register enabling the right clock
source, though we haven't found one (yet). But as also other code for this
SoC out there on the net does not seem to be able to use the arch timer,
I am not too hopeful here. While this does not impose a real problem to
U-Boot (patch 3/13 takes care of that), it is a showstopper for mainline
arm64 Linux, which heavily relies on the arch timer (since it's a mandatory
part of the ARMv8 architecture). There is only a very small chance that the
arch timer ever becomes optional in the mainline arm64 kernel. However our
arm(32) kernel ports works quite nicely so far, also a (hacked) arm64 kernel
boots to the prompt. We will submit Linux patches at a later time.
We would be grateful to get some comments on the patches.
The first five patches adapt existing code to simplify support for this
SoC. The following six patches then successively enable and add SoC support,
culmulating in the addition of a nanopi_m3_defconfig file in patch 11/13.
The SoC support code is actually architecture agnostic, though up until
the last patch it generates an AArch64 binary. To overcome the problems
with the arch timer mentioned above, the final patch switches the port
over to AArch32, which can more naturally launch arm kernels.
This code so far does not include an SPL, instead it relies on some vendor
provided code to initialise the DRAM and load U-Boot proper. The original
BSP code provided a binary blob for that (called "secondboot"), although
there is some GPLed version of that available on github([2]).
We can load a 32-bit U-Boot with both the vendor blob and Rafaello's GPL
version, the 64-bit version is only usable with the GPL code.
Instruction on how to create a bootable SD card are contained in the
arch/arm/mach-nexell/README file.
We would be very grateful to get some first feedback on those patches
and the approach in general taken here.
Cheers,
Andre.
[1] http://nanopi.io/nanopi-m3.html
[2] https://github.com/rafaello7/bl1-nanopi-m3
Amit Singh Tomar (4):
reset: add driver for generic reset controllers
mmc: add MMC (glue) driver for Nexell SoCs
arm: nexell: add ARM64 MMU regions
arm: nexell: add timer support
Andre Przywara (9):
serial: s5p: rework Samsung UART driver to get rid of uart.h
serial: S5P/Samsung: refactor and Kconfig-ize UART selection
arm: move SYS_ARCH_TIMER to KConfig
arm: add basic framework for Nexell S5P6818 support
arm: nexell: embed NSIH header
arm: nexell: add UART support
arm: nexell: add preliminary S5P6818 SoC device tree
arm: add NanoPi M3 board support
arm: nexell: switch to 32-bit
arch/arm/Kconfig | 29 +++++
arch/arm/Makefile | 1 +
arch/arm/cpu/armv8/Makefile | 2 +-
arch/arm/dts/s5p6818-nanopi-m3.dts | 30 +++++
arch/arm/dts/s5p6818.dtsi | 196 ++++++++++++++++++++++++++++++
arch/arm/dts/s5pc1xx-goni.dts | 2 +-
arch/arm/dts/s5pc1xx-smdkc100.dts | 2 +-
arch/arm/include/asm/arch-nexell/boot0.h | 35 ++++++
arch/arm/include/asm/arch-nexell/clk.h | 15 +++
arch/arm/include/asm/arch-nexell/pwm.h | 62 ++++++++++
arch/arm/mach-exynos/include/mach/uart.h | 44 -------
arch/arm/mach-imx/mx7ulp/Kconfig | 1 +
arch/arm/mach-nexell/Kconfig | 9 ++
arch/arm/mach-nexell/Makefile | 10 ++
arch/arm/mach-nexell/README | 49 ++++++++
arch/arm/mach-nexell/board.c | 128 +++++++++++++++++++
arch/arm/mach-nexell/mmu-arm64.c | 39 ++++++
arch/arm/mach-s5pc1xx/Kconfig | 2 +
arch/arm/mach-s5pc1xx/include/mach/uart.h | 44 -------
configs/nanopi_m3_defconfig | 12 ++
drivers/mmc/Kconfig | 8 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/nexell_dw_mmc.c | 159 ++++++++++++++++++++++++
drivers/reset/Kconfig | 6 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-generic.c | 111 +++++++++++++++++
drivers/serial/Kconfig | 6 +
drivers/serial/Makefile | 2 +-
drivers/serial/serial_s5p.c | 45 ++++++-
include/configs/mx7ulp_evk.h | 1 -
include/configs/s5p6818.h | 35 ++++++
include/configs/ti_armv7_keystone2.h | 1 -
scripts/config_whitelist.txt | 1 -
33 files changed, 989 insertions(+), 100 deletions(-)
create mode 100644 arch/arm/dts/s5p6818-nanopi-m3.dts
create mode 100644 arch/arm/dts/s5p6818.dtsi
create mode 100644 arch/arm/include/asm/arch-nexell/boot0.h
create mode 100644 arch/arm/include/asm/arch-nexell/clk.h
create mode 100644 arch/arm/include/asm/arch-nexell/pwm.h
delete mode 100644 arch/arm/mach-exynos/include/mach/uart.h
create mode 100644 arch/arm/mach-nexell/Kconfig
create mode 100644 arch/arm/mach-nexell/Makefile
create mode 100644 arch/arm/mach-nexell/README
create mode 100644 arch/arm/mach-nexell/board.c
create mode 100644 arch/arm/mach-nexell/mmu-arm64.c
delete mode 100644 arch/arm/mach-s5pc1xx/include/mach/uart.h
create mode 100644 configs/nanopi_m3_defconfig
create mode 100644 drivers/mmc/nexell_dw_mmc.c
create mode 100644 drivers/reset/reset-generic.c
create mode 100644 include/configs/s5p6818.h
--
2.14.1
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 01/13] serial: s5p: rework Samsung UART driver to get rid of uart.h
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
@ 2017-11-30 1:24 ` Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 02/13] serial: S5P/Samsung: refactor and Kconfig-ize UART selection Andre Przywara
` (12 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:24 UTC (permalink / raw)
To: u-boot
At the moment the serial_s5p driver takes care of both Exynos UARTs
as well as those from older Samsung SoCs (s3c/s5p series).
Looking more closely the only difference between those two groups is
how the fractional baud rate is programmed: via a "divslot" (s3c) or as
a proper fractional value (Exynos).
Instead of intricately expressing this via a special header file (which
is otherwise identical), let's use the blessings of DT to tackle this:
The S5P series of SoCs use their own compatible string, in line with
what the official DTs from the Linux kernel do. We then switch between
divslot and fractional value based on the compatible string used.
This allows us to get rid of the uart.h header files and make the
driver more flexible.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/dts/s5pc1xx-goni.dts | 2 +-
arch/arm/dts/s5pc1xx-smdkc100.dts | 2 +-
arch/arm/mach-exynos/include/mach/uart.h | 44 ------------------------------
arch/arm/mach-s5pc1xx/include/mach/uart.h | 44 ------------------------------
drivers/serial/serial_s5p.c | 45 +++++++++++++++++++++++++++----
5 files changed, 42 insertions(+), 95 deletions(-)
delete mode 100644 arch/arm/mach-exynos/include/mach/uart.h
delete mode 100644 arch/arm/mach-s5pc1xx/include/mach/uart.h
diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts
index 182325a091..964c7a6b67 100644
--- a/arch/arm/dts/s5pc1xx-goni.dts
+++ b/arch/arm/dts/s5pc1xx-goni.dts
@@ -28,7 +28,7 @@
};
serial at e2900800 {
- compatible = "samsung,exynos4210-uart";
+ compatible = "samsung,s5pv210-uart";
reg = <0xe2900800 0x400>;
id = <2>;
};
diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts b/arch/arm/dts/s5pc1xx-smdkc100.dts
index 95f15ed48d..9f813eadbc 100644
--- a/arch/arm/dts/s5pc1xx-smdkc100.dts
+++ b/arch/arm/dts/s5pc1xx-smdkc100.dts
@@ -27,7 +27,7 @@
};
serial at ec000000 {
- compatible = "samsung,exynos4210-uart";
+ compatible = "samsung,s5pv210-uart";
reg = <0xec000000 0x100>;
interrupts = <0 51 0>;
id = <0>;
diff --git a/arch/arm/mach-exynos/include/mach/uart.h b/arch/arm/mach-exynos/include/mach/uart.h
deleted file mode 100644
index 33d6ba3b64..0000000000
--- a/arch/arm/mach-exynos/include/mach/uart.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_UART_H_
-#define __ASM_ARCH_UART_H_
-
-#ifndef __ASSEMBLY__
-/* baudrate rest value */
-union br_rest {
- unsigned short slot; /* udivslot */
- unsigned char value; /* ufracval */
-};
-
-struct s5p_uart {
- unsigned int ulcon;
- unsigned int ucon;
- unsigned int ufcon;
- unsigned int umcon;
- unsigned int utrstat;
- unsigned int uerstat;
- unsigned int ufstat;
- unsigned int umstat;
- unsigned char utxh;
- unsigned char res1[3];
- unsigned char urxh;
- unsigned char res2[3];
- unsigned int ubrdiv;
- union br_rest rest;
- unsigned char res3[0xffd0];
-};
-
-static inline int s5p_uart_divslot(void)
-{
- return 0;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/mach-s5pc1xx/include/mach/uart.h b/arch/arm/mach-s5pc1xx/include/mach/uart.h
deleted file mode 100644
index 26db098842..0000000000
--- a/arch/arm/mach-s5pc1xx/include/mach/uart.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_UART_H_
-#define __ASM_ARCH_UART_H_
-
-#ifndef __ASSEMBLY__
-/* baudrate rest value */
-union br_rest {
- unsigned short slot; /* udivslot */
- unsigned char value; /* ufracval */
-};
-
-struct s5p_uart {
- unsigned int ulcon;
- unsigned int ucon;
- unsigned int ufcon;
- unsigned int umcon;
- unsigned int utrstat;
- unsigned int uerstat;
- unsigned int ufstat;
- unsigned int umstat;
- unsigned char utxh;
- unsigned char res1[3];
- unsigned char urxh;
- unsigned char res2[3];
- unsigned int ubrdiv;
- union br_rest rest;
- unsigned char res3[0x3d0];
-};
-
-static inline int s5p_uart_divslot(void)
-{
- return 1;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index a2f692bf05..8f46cd149e 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -15,12 +15,34 @@
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
-#include <asm/arch/uart.h>
#include <serial.h>
#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
+/* baudrate rest value */
+union br_rest {
+ unsigned short slot; /* udivslot */
+ unsigned char value; /* ufracval */
+};
+
+struct s5p_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned int ubrdiv;
+ union br_rest rest;
+};
+
#define RX_FIFO_COUNT_SHIFT 0
#define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT)
#define RX_FIFO_FULL (1 << 8)
@@ -28,10 +50,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT)
#define TX_FIFO_FULL (1 << 24)
+#define UART_HAS_DIVSLOT 1
+
/* Information about a serial port */
struct s5p_serial_platdata {
struct s5p_uart *reg; /* address of registers in physical memory */
u8 port_id; /* uart port number */
+ bool has_divslot;
};
/*
@@ -72,7 +97,7 @@ static void __maybe_unused s5p_serial_init(struct s5p_uart *uart)
}
static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk,
- int baudrate)
+ int baudrate, bool has_divslot)
{
u32 val;
@@ -80,7 +105,7 @@ static void __maybe_unused s5p_serial_baud(struct s5p_uart *uart, uint uclk,
writel(val / 16 - 1, &uart->ubrdiv);
- if (s5p_uart_divslot())
+ if (has_divslot)
writew(udivslot[val % 16], &uart->rest.slot);
else
writeb(val % 16, &uart->rest.value);
@@ -105,7 +130,7 @@ int s5p_serial_setbrg(struct udevice *dev, int baudrate)
uclk = get_uart_clk(plat->port_id);
#endif
- s5p_serial_baud(uart, uclk, baudrate);
+ s5p_serial_baud(uart, uclk, baudrate, plat->has_divslot);
return 0;
}
@@ -180,6 +205,7 @@ static int s5p_serial_pending(struct udevice *dev, bool input)
static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
{
struct s5p_serial_platdata *plat = dev->platdata;
+ unsigned long driver_data;
fdt_addr_t addr;
addr = devfdt_get_addr(dev);
@@ -189,6 +215,10 @@ static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
plat->reg = (struct s5p_uart *)addr;
plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"id", dev->seq);
+
+ driver_data = dev_get_driver_data(dev);
+ plat->has_divslot = driver_data & UART_HAS_DIVSLOT;
+
return 0;
}
@@ -200,7 +230,12 @@ static const struct dm_serial_ops s5p_serial_ops = {
};
static const struct udevice_id s5p_serial_ids[] = {
- { .compatible = "samsung,exynos4210-uart" },
+ { .compatible = "samsung,s3c2412-uart", .data = UART_HAS_DIVSLOT },
+ { .compatible = "samsung,s3c2440-uart", .data = UART_HAS_DIVSLOT },
+ { .compatible = "samsung,s3c6400-uart", .data = UART_HAS_DIVSLOT },
+ { .compatible = "samsung,s5pv210-uart", .data = UART_HAS_DIVSLOT },
+ { .compatible = "samsung,exynos4210-uart", .data = 0 },
+ { .compatible = "samsung,exynos5433-uart", .data = 0 },
{ }
};
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 02/13] serial: S5P/Samsung: refactor and Kconfig-ize UART selection
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
2017-11-30 1:24 ` [U-Boot] [RFC PATCH 01/13] serial: s5p: rework Samsung UART driver to get rid of uart.h Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig Andre Przywara
` (11 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
Currently the UART used by some Samsung SoCs is selected by the
generic CONFIG_S5P define. This makes it hard to re-use that UART
without pulling in the whole of the S5P code. Also the Exynos SoCs
use this driver, which is in fact a generic Samsung UART driver.
So create a new Kconfig symbol CONFIG_SAMSUNG_UART to reflect this and
change the existing boards to use this symbol.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/Kconfig | 1 +
arch/arm/mach-s5pc1xx/Kconfig | 2 ++
drivers/serial/Kconfig | 6 ++++++
drivers/serial/Makefile | 2 +-
4 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e50ba930a1..88c8417120 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -557,6 +557,7 @@ config ARCH_EXYNOS
select DM_I2C
select DM_SPI_FLASH
select DM_SERIAL
+ select SAMSUNG_UART
select DM_SPI
select DM_GPIO
select DM_KEYBOARD
diff --git a/arch/arm/mach-s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig
index 04acdaad79..ab6628736c 100644
--- a/arch/arm/mach-s5pc1xx/Kconfig
+++ b/arch/arm/mach-s5pc1xx/Kconfig
@@ -7,10 +7,12 @@ choice
config TARGET_S5P_GONI
bool "S5P Goni board"
select OF_CONTROL
+ select SAMSUNG_UART
config TARGET_SMDKC100
bool "Support smdkc100 board"
select OF_CONTROL
+ select SAMSUNG_UART
endchoice
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 122b8e786a..a35100e7e7 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -428,6 +428,12 @@ config PIC32_SERIAL
help
Support for the UART found on Microchip PIC32 SoC's.
+config SAMSUNG_UART
+ bool "Samsung S5P/Nexell UART support"
+ help
+ Support for the UART found on various Samsung SoCs, for instance
+ in the Exynos series or the S5P chips.
+
config SYS_NS16550
bool "NS16550 UART or compatible"
help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 7adcee3e10..d7f6e6598f 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
obj-$(CONFIG_SYS_NS16550) += ns16550.o
-obj-$(CONFIG_S5P) += serial_s5p.o
+obj-$(CONFIG_SAMSUNG_UART) += serial_s5p.o
obj-$(CONFIG_MXC_UART) += serial_mxc.o
obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
2017-11-30 1:24 ` [U-Boot] [RFC PATCH 01/13] serial: s5p: rework Samsung UART driver to get rid of uart.h Andre Przywara
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 02/13] serial: S5P/Samsung: refactor and Kconfig-ize UART selection Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:30 ` Simon Glass
` (2 more replies)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 04/13] reset: add driver for generic reset controllers Andre Przywara
` (10 subsequent siblings)
13 siblings, 3 replies; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch
timer) in U-Boot.
At the moment it is mandatory for ARMv8 and used by two ARMv7 boards.
Add a proper Kconfig symbol to express this dependency properly,
allowing certain board configuration to later disable arch timer in case
there are any problems with it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/Kconfig | 11 +++++++++++
arch/arm/cpu/armv8/Makefile | 2 +-
arch/arm/mach-imx/mx7ulp/Kconfig | 1 +
include/configs/mx7ulp_evk.h | 1 -
include/configs/ti_armv7_keystone2.h | 1 -
scripts/config_whitelist.txt | 1 -
6 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 88c8417120..cfde0758ef 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -209,6 +209,16 @@ config SYS_CACHELINE_SIZE
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
+config SYS_ARCH_TIMER
+ bool "ARM Generic Timer support"
+ depends on CPU_V7 || ARM64
+ default y if ARM64
+ help
+ The ARM Generic Timer (aka arch-timer) provides an architected
+ interface to a timer source on an SoC.
+ It is mandantory for ARMv8 implementation and widely available
+ on ARMv7 systems.
+
config ARM_SMCCC
bool "Support for ARM SMC Calling Convention (SMCCC)"
depends on CPU_V7 || ARM64
@@ -586,6 +596,7 @@ config ARCH_KEYSTONE
select SUPPORT_SPL
select SYS_THUMB_BUILD
select CMD_POWEROFF
+ select SYS_ARCH_TIMER
imply CMD_MTDPARTS
imply FIT
imply CMD_SAVES
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 1249547436..d18b38eb9e 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -9,7 +9,7 @@ extra-y := start.o
obj-y += cpu.o
ifndef CONFIG_$(SPL_TPL_)TIMER
-obj-y += generic_timer.o
+obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
endif
obj-y += cache_v8.o
obj-y += exceptions.o
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 1bdc85a9a0..d4b0299dbd 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -9,6 +9,7 @@ choice
config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
+ select SYS_ARCH_TIMER
endchoice
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 6ab8db36a8..3d08ba233c 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -47,7 +47,6 @@
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
-#define CONFIG_SYS_ARCH_TIMER
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
#define CONFIG_INITRD_TAG
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 562bb65636..dca6cf004c 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -17,7 +17,6 @@
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_ARCH_TIMER
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x0c000000
#endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 4ce87484c3..b222ae1172 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2285,7 +2285,6 @@ CONFIG_SYS_APP1_BASE
CONFIG_SYS_APP1_SIZE
CONFIG_SYS_APP2_BASE
CONFIG_SYS_APP2_SIZE
-CONFIG_SYS_ARCH_TIMER
CONFIG_SYS_ARM_CACHE_WRITETHROUGH
CONFIG_SYS_AT91_CPU_NAME
CONFIG_SYS_AT91_MAIN_CLOCK
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 04/13] reset: add driver for generic reset controllers
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (2 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 05/13] mmc: add MMC (glue) driver for Nexell SoCs Andre Przywara
` (9 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
From: Amit Singh Tomar <amittomer25@gmail.com>
The simplest and most generic form of a reset controller just exposes
multiple MMIO registers, where each bit toggles a separate reset line.
Add a generic driver to describe this kind of reset controller.
This is used on the Nexell S5P6818, for instance, but also by other
SoCs.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
[Andre: make more generic, let it cover multiple registers, slight rework]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/reset/Kconfig | 6 +++
drivers/reset/Makefile | 1 +
drivers/reset/reset-generic.c | 111 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 118 insertions(+)
create mode 100644 drivers/reset/reset-generic.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index ce46e2752c..3032b0064c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -12,6 +12,12 @@ config DM_RESET
although driving such reset isgnals using GPIOs may be more
appropriate in this case.
+config GENERIC_RESET
+ bool "Generic Reset controller driver"
+ depends on DM_RESET
+ help
+ Support Generic reset controller.
+
config SANDBOX_RESET
bool "Enable the sandbox reset test driver"
depends on DM_MAILBOX && SANDBOX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 252cefeed5..81680837ef 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
+obj-$(CONFIG_GENERIC_RESET) += reset-generic.o
diff --git a/drivers/reset/reset-generic.c b/drivers/reset/reset-generic.c
new file mode 100644
index 0000000000..0a7740202d
--- /dev/null
+++ b/drivers/reset/reset-generic.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2017 Amit Singh Tomar <amittomer25@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset-uclass.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct generic_reset_priv {
+ void __iomem *membase;
+ int max_reset;
+};
+
+#define BITS_PER_BYTE 8
+static int generic_reset_toggle(struct reset_ctl *rst, bool assert)
+{
+ struct generic_reset_priv *priv = dev_get_priv(rst->dev);
+ int reg_width = sizeof(u32);
+ int bank, offset;
+ u32 reg;
+
+ if (rst->id >= priv->max_reset)
+ return -EINVAL;
+
+ bank = rst->id / (reg_width * BITS_PER_BYTE);
+ offset = rst->id % (reg_width * BITS_PER_BYTE);
+
+ reg = readl(priv->membase + (bank * reg_width));
+ if (assert)
+ writel(reg & ~BIT(offset), priv->membase + (bank * reg_width));
+ else
+ writel(reg | BIT(offset), priv->membase + (bank * reg_width));
+
+ return 0;
+}
+
+static int generic_reset_assert(struct reset_ctl *rst)
+{
+ return generic_reset_toggle(rst, true);
+}
+
+static int generic_reset_deassert(struct reset_ctl *rst)
+{
+ return generic_reset_toggle(rst, false);
+}
+
+static int generic_reset_free(struct reset_ctl *rst)
+{
+ return 0;
+}
+
+static int generic_reset_request(struct reset_ctl *rst)
+{
+ struct generic_reset_priv *priv = dev_get_priv(rst->dev);
+
+ if (rst->id >= priv->max_reset)
+ return -EINVAL;
+
+ return generic_reset_assert(rst);
+}
+
+struct reset_ops generic_reset_reset_ops = {
+ .free = generic_reset_free,
+ .request = generic_reset_request,
+ .rst_assert = generic_reset_assert,
+ .rst_deassert = generic_reset_deassert,
+};
+
+static const struct udevice_id generic_reset_ids[] = {
+ { .compatible = "generic-reset" },
+ { .compatible = "nexell,s5p6818-reset" },
+ { }
+};
+
+static int generic_reset_probe(struct udevice *dev)
+{
+ struct generic_reset_priv *priv = dev_get_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->max_reset = dev_read_u32_default(dev, "num-resets", -1);
+ if (priv->max_reset == -1)
+ priv->max_reset = size * BITS_PER_BYTE;
+
+ priv->membase = devm_ioremap(dev, addr, size);
+ if (!priv->membase)
+ return -EFAULT;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(generic_reset) = {
+ .name = "generic_reset",
+ .id = UCLASS_RESET,
+ .of_match = generic_reset_ids,
+ .ops = &generic_reset_reset_ops,
+ .probe = generic_reset_probe,
+ .priv_auto_alloc_size = sizeof(struct generic_reset_priv),
+};
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 05/13] mmc: add MMC (glue) driver for Nexell SoCs
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (3 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 04/13] reset: add driver for generic reset controllers Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 06/13] arm: add basic framework for Nexell S5P6818 support Andre Przywara
` (8 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
From: Amit Singh Tomar <amittomer25@gmail.com>
The Nexell SoCs contain multiple MMC devices, which can be driven by
U-Boot's DesignWare MMC driver, if supported by the required glue driver
file.
Provide that file along with the Makefile/Kconfig changes.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/mmc/Kconfig | 8 +++
drivers/mmc/Makefile | 1 +
drivers/mmc/nexell_dw_mmc.c | 159 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 168 insertions(+)
create mode 100644 drivers/mmc/nexell_dw_mmc.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 62ce0af7d3..243878aa65 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -91,6 +91,14 @@ config MMC_DW_K3
Synopsys DesignWare Memory Card Interface driver. Select this option
for platforms based on Hisilicon K3 SoC's.
+config MMC_DW_NEXELL
+ bool "NEXELL SD/MMC controller support"
+ depends on ARCH_NEXELL && DM_MMC && OF_CONTROL
+ depends on MMC_DW
+ help
+ This enables support for the Nexell SD/MMM controller, which is
+ based on Designware IP.
+
config MMC_DW_ROCKCHIP
bool "Rockchip SD/MMC controller support"
depends on DM_MMC && OF_CONTROL
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index d505f37f01..0fb6eb7803 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o
obj-$(CONFIG_MMC_DW) += dw_mmc.o
obj-$(CONFIG_MMC_DW_EXYNOS) += exynos_dw_mmc.o
obj-$(CONFIG_MMC_DW_K3) += hi6220_dw_mmc.o
+obj-$(CONFIG_MMC_DW_NEXELL) += nexell_dw_mmc.o
obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c
new file mode 100644
index 0000000000..e96395cdaf
--- /dev/null
+++ b/drivers/mmc/nexell_dw_mmc.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2017 Amit Singh Tomar <amittomer25@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <dwmmc.h>
+#include <errno.h>
+#include <mapmem.h>
+#include <linux/err.h>
+#include <reset.h>
+#include <asm/arch/clk.h>
+
+#define SDMMCCLKENB 0xC00C5000
+#define SDMMCCLKGEN0L 0xC00C5004
+#define PLL_SEL_MASK GENMASK(4, 2)
+#define CLK_DIV_MASK GENMASK(12, 5)
+#define PLLSEL_SHIFT 0x2
+#define PLL0_SEL 0
+#define PLL1_SEL 1
+#define PLL2_SEL 2
+#define SDMMC_CLK_ENB 0xc /* Magic bit to enable/generate SDMMC clock */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct nexell_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct nexell_dwmmc_priv {
+ struct clk clk;
+ struct dwmci_host host;
+ struct reset_ctl reset_ctl;
+ int fifo_depth;
+ bool fifo_mode;
+};
+
+/* Should this be done from CCF ? */
+static void nexell_dwmci_clksel(struct dwmci_host *host)
+{
+ u32 val;
+
+ /* Enable SDMMC clock */
+ val = readl(SDMMCCLKENB);
+ val |= SDMMC_CLK_ENB;
+ writel(val, SDMMCCLKENB);
+
+ /* Select PLL1 as clock source */
+ val = readl(SDMMCCLKGEN0L);
+ val = val & ~(PLL_SEL_MASK);
+ val |= (PLL1_SEL << PLLSEL_SHIFT) & PLL_SEL_MASK;
+ writel(val, SDMMCCLKGEN0L);
+}
+
+static int nexell_dwmmc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct nexell_dwmmc_priv *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ int fifo_depth, ret;
+
+ ret = reset_get_by_name(dev, "mmc", &priv->reset_ctl);
+ if (ret) {
+ printf("reset_get_by_name(rst) failed: %d", ret);
+ return ret;
+ }
+
+ fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "fifo-depth", 0);
+ if (fifo_depth < 0) {
+ printf("DWMMC: Can't get FIFO depth\n");
+ return -EINVAL;
+ }
+
+ host->name = dev->name;
+ host->ioaddr = (void *)devfdt_get_addr(dev);
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "bus-width", 4);
+
+ ret = reset_assert(&priv->reset_ctl);
+ if (ret)
+ return ret;
+
+ host->clksel = nexell_dwmci_clksel;
+
+ ret = reset_deassert(&priv->reset_ctl);
+ if (ret)
+ return ret;
+
+ host->dev_index = 0;
+ host->bus_hz = get_mmc_clk(host->dev_index);
+ host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) |
+ TX_WMARK(fifo_depth / 2);
+ host->priv = priv;
+
+ return 0;
+}
+
+static int nexell_dwmmc_probe(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+ struct nexell_mmc_plat *plat = dev_get_platdata(dev);
+#endif
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct nexell_dwmmc_priv *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+
+#ifdef CONFIG_BLK
+ dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
+ host->mmc = &plat->mmc;
+#else
+ int ret;
+
+ ret = add_dwmci(host, host->bus_hz, 400000);
+ if (ret)
+ return ret;
+#endif
+
+ host->mmc->priv = &priv->host;
+ upriv->mmc = host->mmc;
+ host->mmc->dev = dev;
+
+ return 0;
+}
+
+static int nexell_dwmmc_bind(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+ struct nexell_mmc_plat *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+ if (ret)
+ return ret;
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id nexell_dwmmc_ids[] = {
+ { .compatible = "nexell,s5p6818-dw-mshc" },
+ { }
+};
+
+U_BOOT_DRIVER(nexell_dwmmc_drv) = {
+ .name = "nexell_s5p6818_dw_mshc",
+ .id = UCLASS_MMC,
+ .of_match = nexell_dwmmc_ids,
+ .ops = &dm_dwmci_ops,
+ .ofdata_to_platdata = nexell_dwmmc_ofdata_to_platdata,
+ .bind = nexell_dwmmc_bind,
+ .probe = nexell_dwmmc_probe,
+ .priv_auto_alloc_size = sizeof(struct nexell_dwmmc_priv),
+ .platdata_auto_alloc_size = sizeof(struct nexell_mmc_plat),
+};
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 06/13] arm: add basic framework for Nexell S5P6818 support
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (4 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 05/13] mmc: add MMC (glue) driver for Nexell SoCs Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 07/13] arm: nexell: embed NSIH header Andre Przywara
` (7 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
The Nexell S5P6818 is a typical SoC with ARM Cortex-A53 cores.
It has many peripherals derived from Samsung SoCs (MMC, serial, I2C,
Ethernet, ...).
Add the required files to introduce this new SoC (family?) to U-Boot.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/Kconfig | 6 ++++++
arch/arm/Makefile | 1 +
arch/arm/mach-nexell/Kconfig | 9 +++++++++
arch/arm/mach-nexell/Makefile | 7 +++++++
arch/arm/mach-nexell/board.c | 41 +++++++++++++++++++++++++++++++++++++++++
include/configs/s5p6818.h | 33 +++++++++++++++++++++++++++++++++
6 files changed, 97 insertions(+)
create mode 100644 arch/arm/mach-nexell/Kconfig
create mode 100644 arch/arm/mach-nexell/Makefile
create mode 100644 arch/arm/mach-nexell/board.c
create mode 100644 include/configs/s5p6818.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cfde0758ef..c11e3f1f85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -652,6 +652,10 @@ config ARCH_MX5
select CPU_V7
select BOARD_EARLY_INIT_F
+config ARCH_NEXELL
+ bool "Nexell S5P support"
+ select ARM64
+
config ARCH_QEMU
bool "QEMU Virtual Platform"
select CPU_V7
@@ -1197,6 +1201,8 @@ source "arch/arm/mach-imx/mx6/Kconfig"
source "arch/arm/mach-imx/mx5/Kconfig"
+source "arch/arm/mach-nexell/Kconfig"
+
source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0e0ae77822..d71d50a1f4 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -61,6 +61,7 @@ machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MVEBU) += mvebu
+machine-$(CONFIG_ARCH_NEXELL) += nexell
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
diff --git a/arch/arm/mach-nexell/Kconfig b/arch/arm/mach-nexell/Kconfig
new file mode 100644
index 0000000000..71aa5e641d
--- /dev/null
+++ b/arch/arm/mach-nexell/Kconfig
@@ -0,0 +1,9 @@
+if ARCH_NEXELL
+
+config SYS_SOC
+ default "nexell"
+
+config SYS_CONFIG_NAME
+ default "s5p6818"
+
+endif
diff --git a/arch/arm/mach-nexell/Makefile b/arch/arm/mach-nexell/Makefile
new file mode 100644
index 0000000000..bf103480bb
--- /dev/null
+++ b/arch/arm/mach-nexell/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Andre Przywara <andre.przywara@arm.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/arch/arm/mach-nexell/board.c b/arch/arm/mach-nexell/board.c
new file mode 100644
index 0000000000..f0d258b71c
--- /dev/null
+++ b/arch/arm/mach-nexell/board.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2017 Andre Przywara <andre.przywara@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* TODO: dummy implementation for now, add proper reset code */
+void reset_cpu(ulong addr)
+{
+}
+
+/* TODO: enhance when multiple SoCs are supported (S5P4418) */
+int print_cpuinfo(void)
+{
+ puts("CPU: Nexell S5P6818\n");
+
+ return 0;
+}
+
+/* TODO: dummy for now, either implement DRAM init or rely on vendor code */
+int dram_init(void)
+{
+ /* TODO: hard coded for now, read from DT? */
+ gd->ram_size = 0x40000000;
+
+ return 0;
+}
+
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
+
+int board_init(void)
+{
+ return 0;
+}
diff --git a/include/configs/s5p6818.h b/include/configs/s5p6818.h
new file mode 100644
index 0000000000..4d394dbec9
--- /dev/null
+++ b/include/configs/s5p6818.h
@@ -0,0 +1,33 @@
+#ifndef __CONFIG_S5P6818_H
+#define __CONFIG_S5P6818_H
+
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_MAX_FLASH_BANKS 0
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS "fdt_high=0xffffffffffffffff"
+
+/* using SRAM for SPL init here */
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffff0000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* 64 KiB */
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
+
+#define CONFIG_SYS_TEXT_BASE 0x42c00000
+#define CONFIG_SYS_LOAD_ADDR 0x41000000
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20))
+
+#define CONFIG_SYS_TIMER_COUNTER 0xc0017040 /* TCNTO4 */
+
+#endif /* __CONFIG_H */
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 07/13] arm: nexell: embed NSIH header
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (5 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 06/13] arm: add basic framework for Nexell S5P6818 support Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 08/13] arm: nexell: add ARM64 MMU regions Andre Przywara
` (6 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
The primary boot loaders provided by the SoC vendor or derived from that
use an image format called "NSIH" to learn the load address and size of
the boot payload. This header occupies 512 bytes, but contains only a
few essential words of information.
Use the boot0 feature to prepend this header before the actual U-Boot
proper. We automatically fill it with the required information, also
add a branch instruction to be able to enter at the beginning of the
header.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arch-nexell/boot0.h | 35 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
create mode 100644 arch/arm/include/asm/arch-nexell/boot0.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c11e3f1f85..b0f3ee7289 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -655,6 +655,7 @@ config ARCH_MX5
config ARCH_NEXELL
bool "Nexell S5P support"
select ARM64
+ select ENABLE_ARM_SOC_BOOT0_HOOK
config ARCH_QEMU
bool "QEMU Virtual Platform"
diff --git a/arch/arm/include/asm/arch-nexell/boot0.h b/arch/arm/include/asm/arch-nexell/boot0.h
new file mode 100644
index 0000000000..b2adb06b4c
--- /dev/null
+++ b/arch/arm/include/asm/arch-nexell/boot0.h
@@ -0,0 +1,35 @@
+/*
+ * Nexell NSIH header, to allow loading U-Boot from secondboot.
+ *
+ * Both the proprietary and the GPL version of the first stage boot loader
+ * look for this magic header to determine the size and load address of
+ * the payload (similar to the information in an U-Boot image header).
+ * Make them happy by providing the essential bits:
+ * @0x040: device address: 0 for SDMMC
+ * @0x044: load size
+ * @0x048: load address
+ * @0x04c: launch address (entry point)
+ * @0x1fc: "NSIH" magic
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifdef CONFIG_ARM64
+ b reset // jump over the header
+ .space 0x3c // fast forward to 0x40
+#else
+_start:
+ ARM_VECTORS
+ .space 0x20 // fill up from 0x20 till 0x40
+#endif
+ .word 0 // device "address" (device ID)
+ .word (_end - _start) + 32768 // binary size + space for .dtb
+ .word CONFIG_SYS_TEXT_BASE // load address
+ .word CONFIG_SYS_TEXT_BASE // launch address
+ .space 0x1ac // fast forward till 0x1fc
+ .word 0x4849534e // "NSIH" magic
+
+ // In case someone enters right after the header:
+#ifdef CONFIG_ARM64
+ b reset
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 08/13] arm: nexell: add ARM64 MMU regions
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (6 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 07/13] arm: nexell: embed NSIH header Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 09/13] arm: nexell: add UART support Andre Przywara
` (5 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
From: Amit Singh Tomar <amittomer25@gmail.com>
ARMv8 boards require a struct describing the memory regions for the
mandatory MMU setup.
Add the respective data for the Nexell S5P6818 SoC.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/mach-nexell/Makefile | 1 +
arch/arm/mach-nexell/mmu-arm64.c | 39 +++++++++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
create mode 100644 arch/arm/mach-nexell/mmu-arm64.c
diff --git a/arch/arm/mach-nexell/Makefile b/arch/arm/mach-nexell/Makefile
index bf103480bb..c4c8293cbc 100644
--- a/arch/arm/mach-nexell/Makefile
+++ b/arch/arm/mach-nexell/Makefile
@@ -5,3 +5,4 @@
#
obj-y := board.o
+obj-$(CONFIG_ARM64) += mmu-arm64.o
diff --git a/arch/arm/mach-nexell/mmu-arm64.c b/arch/arm/mach-nexell/mmu-arm64.c
new file mode 100644
index 0000000000..e7b4479c65
--- /dev/null
+++ b/arch/arm/mach-nexell/mmu-arm64.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2017 Amit Singh Tomar <amittomer25@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct mm_region nexell_s5p6818_mem_map[] = {
+ {
+ .virt = 0xc0000000UL,
+ .phys = 0xc0000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0xFFFF0000ULL,
+ .phys = 0xFFFF0000ULL,
+ .size = 0x00010000ULL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_INNER_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ },
+};
+
+struct mm_region *mem_map = nexell_s5p6818_mem_map;
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 09/13] arm: nexell: add UART support
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (7 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 08/13] arm: nexell: add ARM64 MMU regions Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 10/13] arm: nexell: add timer support Andre Przywara
` (4 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
The Nexell S5P6818 SoC uses a UART very similar to those used in the
Samsung S5P SoCs.
Enable the driver in the config and add the necessary glue headers
and clock functions to make the S5P driver happy.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/Kconfig | 3 ++
arch/arm/include/asm/arch-nexell/clk.h | 13 +++++++++
arch/arm/mach-nexell/board.c | 50 ++++++++++++++++++++++++++++++++++
3 files changed, 66 insertions(+)
create mode 100644 arch/arm/include/asm/arch-nexell/clk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b0f3ee7289..9c317ddf3f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -656,6 +656,9 @@ config ARCH_NEXELL
bool "Nexell S5P support"
select ARM64
select ENABLE_ARM_SOC_BOOT0_HOOK
+ select DM
+ select DM_SERIAL
+ select SAMSUNG_UART
config ARCH_QEMU
bool "QEMU Virtual Platform"
diff --git a/arch/arm/include/asm/arch-nexell/clk.h b/arch/arm/include/asm/arch-nexell/clk.h
new file mode 100644
index 0000000000..bfd145f555
--- /dev/null
+++ b/arch/arm/include/asm/arch-nexell/clk.h
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2017 ARM Ltd.
+ * Andre Przywara <andre.przywara@arm.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLK_H_
+#define __ASM_ARCH_CLK_H_
+
+unsigned long get_uart_clk(int dev_index);
+
+#endif
diff --git a/arch/arm/mach-nexell/board.c b/arch/arm/mach-nexell/board.c
index f0d258b71c..54a9d8c1f5 100644
--- a/arch/arm/mach-nexell/board.c
+++ b/arch/arm/mach-nexell/board.c
@@ -5,9 +5,14 @@
*/
#include <common.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
+#define NEXELL_PLLSETREG0 0xc0010008UL
+
+#define OSC_FREQ 24000000
+
/* TODO: dummy implementation for now, add proper reset code */
void reset_cpu(ulong addr)
{
@@ -35,6 +40,51 @@ ulong get_tbclk(void)
return CONFIG_SYS_HZ;
}
+static unsigned long get_pll_freq(int pll_index)
+{
+ uint32_t reg;
+ unsigned int pdiv, mdiv, sdiv, plloutdiv;
+ unsigned int multfreq;
+
+ if (pll_index < 0 || pll_index > 3)
+ return 0;
+
+ reg = readl(NEXELL_PLLSETREG0 + pll_index * 4);
+ sdiv = reg & 0xff;
+ mdiv = (reg >> 8) & 0x3ff;
+ pdiv = (reg >> 18) & 0x3f;
+ plloutdiv = ((reg >> 24) & 0xf) + 1;
+
+ multfreq = (OSC_FREQ / 1000) * mdiv;
+ return (1000 * (multfreq / (pdiv * 2 * sdiv))) / plloutdiv;
+}
+
+static unsigned long get_level1_clk_freq(uintptr_t base_addr)
+{
+ uint32_t reg;
+ unsigned int pll_index, div;
+
+ reg = readl(base_addr + 0x4);
+ pll_index = (reg >> 2) & 0x7;
+ if (pll_index > 3)
+ return -1UL;
+
+ div = ((reg >> 5) & 0xff) + 1;
+
+ return get_pll_freq(pll_index) / div;
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+ uintptr_t clock_ofs[6] = {0xc00a9000, 0xc00a8000, 0xc00aa000,
+ 0xc00ab000, 0xc006e000, 0xc0084000};
+
+ if (dev_index < 0 || dev_index > 5)
+ return 0;
+
+ return get_level1_clk_freq(clock_ofs[dev_index]);
+}
+
int board_init(void)
{
return 0;
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 10/13] arm: nexell: add timer support
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (8 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 09/13] arm: nexell: add UART support Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 11/13] arm: nexell: add preliminary S5P6818 SoC device tree Andre Przywara
` (3 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
From: Amit Singh Tomar <amittomer25@gmail.com>
Nexell based SoCs (S5P4414 and S5P6818) contain the same timer block as
present on Samsungs SoCs.
Add this timer code when compiling for Nexell SoC and provide the
necessary glue functions to make the Samsung timer driver happy.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/include/asm/arch-nexell/clk.h | 1 +
arch/arm/include/asm/arch-nexell/pwm.h | 62 ++++++++++++++++++++++++++++++++++
arch/arm/mach-nexell/Makefile | 2 ++
arch/arm/mach-nexell/board.c | 37 +++++++++++++++++---
4 files changed, 97 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/include/asm/arch-nexell/pwm.h
diff --git a/arch/arm/include/asm/arch-nexell/clk.h b/arch/arm/include/asm/arch-nexell/clk.h
index bfd145f555..8cf56ef52c 100644
--- a/arch/arm/include/asm/arch-nexell/clk.h
+++ b/arch/arm/include/asm/arch-nexell/clk.h
@@ -9,5 +9,6 @@
#define __ASM_ARCH_CLK_H_
unsigned long get_uart_clk(int dev_index);
+unsigned long get_pwm_clk(void);
#endif
diff --git a/arch/arm/include/asm/arch-nexell/pwm.h b/arch/arm/include/asm/arch-nexell/pwm.h
new file mode 100644
index 0000000000..7290c61366
--- /dev/null
+++ b/arch/arm/include/asm/arch-nexell/pwm.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
+#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1 0 /* 1/1 period */
+#define MUX_DIV_2 1 /* 1/2 period */
+#define MUX_DIV_4 2 /* 1/4 period */
+#define MUX_DIV_8 3 /* 1/8 period */
+#define MUX_DIV_16 4 /* 1/16 period */
+
+#define MUX_DIV_SHIFT(x) (x * 4)
+
+#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
+
+#define TCON_START(x) (1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
+#define TCON4_AUTO_RELOAD (1 << 22)
+
+#define NEXELL_TIMER_BASE 0xc0017000
+
+#ifndef __ASSEMBLY__
+struct s5p_timer {
+ unsigned int tcfg0;
+ unsigned int tcfg1;
+ unsigned int tcon;
+ unsigned int tcntb0;
+ unsigned int tcmpb0;
+ unsigned int tcnto0;
+ unsigned int tcntb1;
+ unsigned int tcmpb1;
+ unsigned int tcnto1;
+ unsigned int tcntb2;
+ unsigned int tcmpb2;
+ unsigned int tcnto2;
+ unsigned int tcntb3;
+ unsigned int tcmpb3;
+ unsigned int tcnto3;
+ unsigned int tcntb4;
+ unsigned int tcnto4;
+ unsigned int tintcstat;
+};
+#endif /* __ASSEMBLY__ */
+
+static inline unsigned long samsung_get_base_timer(void)
+{
+ return NEXELL_TIMER_BASE;
+}
+
+#endif
diff --git a/arch/arm/mach-nexell/Makefile b/arch/arm/mach-nexell/Makefile
index c4c8293cbc..c59ad631e6 100644
--- a/arch/arm/mach-nexell/Makefile
+++ b/arch/arm/mach-nexell/Makefile
@@ -6,3 +6,5 @@
obj-y := board.o
obj-$(CONFIG_ARM64) += mmu-arm64.o
+obj-y += ../cpu/armv7/s5p-common/timer.o
+obj-y += ../cpu/armv7/s5p-common/pwm.o
diff --git a/arch/arm/mach-nexell/board.c b/arch/arm/mach-nexell/board.c
index 54a9d8c1f5..e9b4f94630 100644
--- a/arch/arm/mach-nexell/board.c
+++ b/arch/arm/mach-nexell/board.c
@@ -10,9 +10,27 @@
DECLARE_GLOBAL_DATA_PTR;
#define NEXELL_PLLSETREG0 0xc0010008UL
+#define NEXELL_CLKDIVREG1 0xc0010024UL
+#define IP_RESET1 0xc0012004UL
#define OSC_FREQ 24000000
+int arch_cpu_init(void)
+{
+ u32 val;
+
+ /*
+ * Reset timer block #4.
+ * Ideally this should be done through the reset driver, but
+ * unfortunately our timer driver is not DM driven.
+ */
+ val = readl(IP_RESET1);
+ val |= BIT(4);
+ writel(val, IP_RESET1);
+
+ return 0;
+}
+
/* TODO: dummy implementation for now, add proper reset code */
void reset_cpu(ulong addr)
{
@@ -35,11 +53,6 @@ int dram_init(void)
return 0;
}
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
-
static unsigned long get_pll_freq(int pll_index)
{
uint32_t reg;
@@ -85,6 +98,20 @@ unsigned long get_uart_clk(int dev_index)
return get_level1_clk_freq(clock_ofs[dev_index]);
}
+/* This is reading the PCLK frequency, which drives the PWM timer. */
+unsigned long get_pwm_clk(void)
+{
+ uint32_t reg;
+ unsigned int pll_index, div;
+
+ reg = readl(NEXELL_CLKDIVREG1);
+ pll_index = reg & 0x7;
+ div = ((reg >> 3) & 0x3f) + 1; /* BCLK divider */
+ div *= ((reg >> 9) & 0x3f) + 1; /* PCLK divider */
+
+ return get_pll_freq(pll_index) / div;
+}
+
int board_init(void)
{
return 0;
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 11/13] arm: nexell: add preliminary S5P6818 SoC device tree
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (9 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 10/13] arm: nexell: add timer support Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 12/13] arm: add NanoPi M3 board support Andre Przywara
` (2 subsequent siblings)
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
The Nexell S5P6818 SoC is an octa-core SoC with ARM Cortex-A53 cores.
The chip contains the usual peripherals for an smartphone/tablet/set-top
box SoC.
Add the .dtsi file describing the peripherals supported so far, but
keep them still disabled.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/Kconfig | 1 +
arch/arm/dts/s5p6818.dtsi | 196 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 197 insertions(+)
create mode 100644 arch/arm/dts/s5p6818.dtsi
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9c317ddf3f..56f6179fe3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -656,6 +656,7 @@ config ARCH_NEXELL
bool "Nexell S5P support"
select ARM64
select ENABLE_ARM_SOC_BOOT0_HOOK
+ select OF_CONTROL
select DM
select DM_SERIAL
select SAMSUNG_UART
diff --git a/arch/arm/dts/s5p6818.dtsi b/arch/arm/dts/s5p6818.dtsi
new file mode 100644
index 0000000000..dcb90dc8ea
--- /dev/null
+++ b/arch/arm/dts/s5p6818.dtsi
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2017 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0x80000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0>;
+ };
+ };
+
+ gic: interrupt-controller at c0090000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xc0090000 0x1000>,
+ <0xc00a0000 0x2000>;
+ };
+
+ reset: reset at c0012000 {
+ reg = <0xc0012000 0x0c>;
+ compatible = "nexell,s5p6818-reset", "generic-reset";
+ #reset-cells = <1>;
+ num-resets = <68>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll0: pll0_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&osc24M>;
+ clock-mult = <200>;
+ clock-div = <6>;
+ clock-output-names = "pll_periph";
+ };
+
+ pll1: pll1_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&osc24M>;
+ clock-mult = <200>;
+ clock-div = <6>;
+ clock-output-names = "pll_cpu";
+ };
+
+ pll2: pll2_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&osc24M>;
+ clock-mult = <102>;
+ clock-div = <4>;
+ clock-output-names = "pll_spare";
+ };
+
+ pll3: pll3_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&osc24M>;
+ clock-mult = <200>;
+ clock-div = <6>;
+ clock-output-names = "pll_dram";
+ };
+
+ bclk: bus_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-mult = <1>;
+ clock-div = <2>;
+ clock-output-names = "bclk";
+ clocks = <&pll0>;
+ };
+
+ pclk: apb_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-mult = <1>;
+ clock-div = <2>;
+ clock-output-names = "pclk";
+ clocks = <&bclk>;
+ };
+
+ uart0_clk: uart0_clk at c00a9000 {
+ compatible = "nexell,clkgen-level1";
+ #clock-cells = <1>;
+ reg = <0xc00a9000 8>;
+ clocks = <&bclk>, <&pll0>, <&pll1>, <&pll2>;
+ clock-output-names = "uart0_bclk", "uart0_clock";
+
+ assigned-clocks = <&uart0_clk 1>;
+ assigned-clock-parents = <&pll0>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ serial_0: serial at c00a1000 {
+ compatible = "nexell,s5p6818-uart",
+ "samsung,exynos4210-uart";
+ reg = <0xc00a1000 0x1000>;
+ interrupts = <0 7 0>;
+ clocks = <&uart0_clk 0>, <&uart0_clk 1>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ mmc_0: mmc at c0062000 {
+ compatible = "nexell,s5p6818-dw-mshc";
+ reg = <0xc0062000 0x2000>;
+ interrupts = <0 43 0>;
+ bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fifo-depth = <32>;
+ resets = <&reset 39>;
+ reset-names = "mmc";
+ status = "disabled";
+ };
+ };
+};
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 12/13] arm: add NanoPi M3 board support
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (10 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 11/13] arm: nexell: add preliminary S5P6818 SoC device tree Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 13/13] arm: nexell: switch to 32-bit Andre Przywara
2017-11-30 10:01 ` [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Lukasz Majewski
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
The NanoPi M3 is a single board computer containing a
Nexell S5P6818 SoC (with 8 ARMv8 Cortex-A53 cores).
Add the respective defconfig and a (preliminary) device tree listing
the devices that we support so far.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/Kconfig | 6 ++++++
arch/arm/dts/s5p6818-nanopi-m3.dts | 30 ++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-nexell/clk.h | 1 +
arch/arm/mach-nexell/board.c | 10 ++++++++++
configs/nanopi_m3_defconfig | 12 ++++++++++++
include/configs/s5p6818.h | 2 ++
6 files changed, 61 insertions(+)
create mode 100644 arch/arm/dts/s5p6818-nanopi-m3.dts
create mode 100644 configs/nanopi_m3_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 56f6179fe3..5c52344ca6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -660,6 +660,12 @@ config ARCH_NEXELL
select DM
select DM_SERIAL
select SAMSUNG_UART
+ select DM_RESET
+ select GENERIC_RESET
+ select DM_MMC
+ select DM_MMC_OPS
+ select MMC_DW
+ select MMC_DW_NEXELL
config ARCH_QEMU
bool "QEMU Virtual Platform"
diff --git a/arch/arm/dts/s5p6818-nanopi-m3.dts b/arch/arm/dts/s5p6818-nanopi-m3.dts
new file mode 100644
index 0000000000..c95c40120e
--- /dev/null
+++ b/arch/arm/dts/s5p6818-nanopi-m3.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+
+#include "s5p6818.dtsi"
+
+/ {
+ model = "Nano Pi M3";
+ compatible = "FriendlyARM,NanoPi-M3";
+
+ chosen {
+ stdout-path = "serial0:115200";
+ bootargs = "console=ttySAC0,115200n8 earlycon=s5pv210,0xc00a1000";
+ };
+
+ aliases {
+ mmc0 = &mmc_0;
+ serial0 = &serial_0;
+ };
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+};
+
+&serial_0 {
+ status = "okay";
+};
+
+&mmc_0 {
+ status = "okay";
+};
diff --git a/arch/arm/include/asm/arch-nexell/clk.h b/arch/arm/include/asm/arch-nexell/clk.h
index 8cf56ef52c..792aabfffb 100644
--- a/arch/arm/include/asm/arch-nexell/clk.h
+++ b/arch/arm/include/asm/arch-nexell/clk.h
@@ -9,6 +9,7 @@
#define __ASM_ARCH_CLK_H_
unsigned long get_uart_clk(int dev_index);
+unsigned long get_mmc_clk(int dev_index);
unsigned long get_pwm_clk(void);
#endif
diff --git a/arch/arm/mach-nexell/board.c b/arch/arm/mach-nexell/board.c
index e9b4f94630..a968863e14 100644
--- a/arch/arm/mach-nexell/board.c
+++ b/arch/arm/mach-nexell/board.c
@@ -112,6 +112,16 @@ unsigned long get_pwm_clk(void)
return get_pll_freq(pll_index) / div;
}
+unsigned long get_mmc_clk(int dev_index)
+{
+ uintptr_t clock_ofs[3] = {0xc00c5000, 0xc00cc000, 0xc00cd000};
+
+ if (dev_index < 0 || dev_index >= 3)
+ return 0;
+
+ return get_level1_clk_freq(clock_ofs[dev_index]);
+}
+
int board_init(void)
{
return 0;
diff --git a/configs/nanopi_m3_defconfig b/configs/nanopi_m3_defconfig
new file mode 100644
index 0000000000..148ff1a8b9
--- /dev/null
+++ b/configs/nanopi_m3_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_NEXELL=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SYS_ARCH_TIMER is not set
+CONFIG_DEFAULT_DEVICE_TREE="s5p6818-nanopi-m3"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
diff --git a/include/configs/s5p6818.h b/include/configs/s5p6818.h
index 4d394dbec9..dff4736e20 100644
--- a/include/configs/s5p6818.h
+++ b/include/configs/s5p6818.h
@@ -30,4 +30,6 @@
#define CONFIG_SYS_TIMER_COUNTER 0xc0017040 /* TCNTO4 */
+#define CONFIG_BOUNCE_BUFFER
+
#endif /* __CONFIG_H */
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 13/13] arm: nexell: switch to 32-bit
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (11 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 12/13] arm: add NanoPi M3 board support Andre Przywara
@ 2017-11-30 1:25 ` Andre Przywara
2017-12-02 3:32 ` Simon Glass
2017-11-30 10:01 ` [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Lukasz Majewski
13 siblings, 1 reply; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 1:25 UTC (permalink / raw)
To: u-boot
The vendor provided SPL blob (called "secondboot") runs completely in
AArch32, so expects U-Boot to be AArch32 as well.
Also the lack of a working arch timer limits Linux to 32-bits, as the
mainline arm64 kernel heavily relies on the arch timer.
This commit switches the NanoPiM3 board over to generate an ARM(32) binary,
to allow easy testing for now. Also this adds a README file to describe
the generation of a bootable SD card image.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-nexell/README | 49 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-nexell/README
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5c52344ca6..3b72528019 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -654,7 +654,7 @@ config ARCH_MX5
config ARCH_NEXELL
bool "Nexell S5P support"
- select ARM64
+ select CPU_V7
select ENABLE_ARM_SOC_BOOT0_HOOK
select OF_CONTROL
select DM
diff --git a/arch/arm/mach-nexell/README b/arch/arm/mach-nexell/README
new file mode 100644
index 0000000000..52bdb19b6b
--- /dev/null
+++ b/arch/arm/mach-nexell/README
@@ -0,0 +1,49 @@
+Booting
+-------
+
+U-Boot can be build as either a 32-bit binary (capable of loading 32-bit
+ARM OS kernels) or as a 64-bit binary, to launch 64-bit AArch64 kernels.
+The only difference in U-Boot is the selection of either CONFIG_ARM64
+or CONFIG_CPU_V7 in the ARCH_NEXELL Kconfig stanza in arch/arm/Kconfig.
+
+At the moment the U-Boot port does not support an SPL, so we need to rely
+on external loaders to initialize the DRAM and load U-Boot proper.
+
+Quick start
+-----------
+
+Download a GPLed version of the boot loader and compile it:
+$ git clone https://github.com/rafaello7/bl1-nanopi-m3.git
+$ cd bl1-nanopi-m3
+(edit config.mak to set OPMODE to "aarch32")
+$ make
+Make sure you have a 32-bit ARM (cross-)compiler installed, change the
+triplet name in config.mak if necessary.
+
+Then copy the resulting binary to an SD card, starting at the second sector:
+$ sudo dd if=out/bl1-nanopi.bin of=/dev/sdX bs=512 seek=1
+
+Now configure and build U-Boot, then copy the binary to sector 64:
+$ make nanopi_m3_defconfig
+$ make
+$ sudo dd if=u-boot.bin of=/dev/sdX bs=512 seek=64
+
+This will build a 32-bit AArch64 version of both the bootloader and U-Boot.
+
+To load 64-bit kernels, change config.mak in the bl1-nanopi-m3 repository
+to set the variable OPMODE back to "aarch64", then re-compile with an Aarch64
+cross compiler. To build a 64-bit version of U-Boot, revert the patch that
+switches the Nexell port to 32-bit. That selects CONFIG_ARM64 instead
+of CONFIG_CPU_V7. Then rebuild as "dd" to the SD card as described above.
+
+"secondboot"
+------------
+There is an official, but proprietary loader ("secondboot"), provided by
+Nexell. It can be found in "official" images, starting from sector 2
+(behind the MBR) and ranging until at most 32KB, though most versions seem
+to be shorter. This loader only supports 32-bit payloads. Also the boot
+protocol differs slightly, as the NSIH header (the first 512 byte of the
+U-Boot image) is cut off and the actual payload is loaded to the load address.
+This breaks U-Boot's assumption about its start address and will fail to boot.
+Interested people might add 512 to the the launch and load address in boot0.h
+to be able to use that boot loader.
--
2.14.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
` (12 preceding siblings ...)
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 13/13] arm: nexell: switch to 32-bit Andre Przywara
@ 2017-11-30 10:01 ` Lukasz Majewski
2017-11-30 10:22 ` Lukasz Majewski
13 siblings, 1 reply; 34+ messages in thread
From: Lukasz Majewski @ 2017-11-30 10:01 UTC (permalink / raw)
To: u-boot
Hi Andre,
> Hi,
>
> this is a first draft of the things Amit and I have been working on in
> the last months. It introduces support for an SoC called "Nexell
> S5P6818". This is an Octa-core ARMv8 SoC with Cortex-A53 cores, which
> apparently is closely related to (older) Samsung SoCs. Many
> peripherals are compatible to Samsung IP (UART, MMC, Ethernet,
> timers, ...), but some core peripherals like the clocks and the pin
> controller seem to be completely different. We used the NanoPi M3
> board [1] for testing, which uses this SoC along with the usual
> suspects of on-board components and connectors. This port is done
> completely from scratch, by just looking at the manual. This allows a
> much cleaner and modern U-Boot support than the BSP code.
>
> The ARM Generic Timer (aka. arch timer) does not seem to work on this
> SoC. Ideally there would be some (hidden?) register enabling the
> right clock source, though we haven't found one (yet). But as also
> other code for this SoC out there on the net does not seem to be able
> to use the arch timer, I am not too hopeful here. While this does not
> impose a real problem to U-Boot (patch 3/13 takes care of that), it
> is a showstopper for mainline arm64 Linux, which heavily relies on
> the arch timer (since it's a mandatory part of the ARMv8
> architecture). There is only a very small chance that the arch timer
> ever becomes optional in the mainline arm64 kernel. However our
> arm(32) kernel ports works quite nicely so far, also a (hacked) arm64
> kernel boots to the prompt. We will submit Linux patches at a later
> time.
>
> We would be grateful to get some comments on the patches.
> The first five patches adapt existing code to simplify support for
> this SoC. The following six patches then successively enable and add
> SoC support, culmulating in the addition of a nanopi_m3_defconfig
> file in patch 11/13. The SoC support code is actually architecture
> agnostic, though up until the last patch it generates an AArch64
> binary. To overcome the problems with the arch timer mentioned above,
> the final patch switches the port over to AArch32, which can more
> naturally launch arm kernels.
>
> This code so far does not include an SPL, instead it relies on some
> vendor provided code to initialise the DRAM and load U-Boot proper.
> The original BSP code provided a binary blob for that (called
> "secondboot"), although there is some GPLed version of that available
> on github([2]). We can load a 32-bit U-Boot with both the vendor blob
> and Rafaello's GPL version, the 64-bit version is only usable with
> the GPL code. Instruction on how to create a bootable SD card are
> contained in the arch/arm/mach-nexell/README file.
>
> We would be very grateful to get some first feedback on those patches
> and the approach in general taken here.
Just to ask - why it is not possible to add this to:
/arch/arm/mach-exynos ? And start new mach-nexell ?
As fair as I remember, many Samsung SoCs (especially S5P) share IP
blocks, so maybe there is a place for unification?
Also, it would be quite challenging to support first armv8 Samsung soc
in the current directory structure.....
+CC Jaehoon - who may have some comments here.
>
> Cheers,
> Andre.
>
> [1] http://nanopi.io/nanopi-m3.html
> [2] https://github.com/rafaello7/bl1-nanopi-m3
>
> Amit Singh Tomar (4):
> reset: add driver for generic reset controllers
> mmc: add MMC (glue) driver for Nexell SoCs
> arm: nexell: add ARM64 MMU regions
> arm: nexell: add timer support
>
> Andre Przywara (9):
> serial: s5p: rework Samsung UART driver to get rid of uart.h
> serial: S5P/Samsung: refactor and Kconfig-ize UART selection
> arm: move SYS_ARCH_TIMER to KConfig
> arm: add basic framework for Nexell S5P6818 support
> arm: nexell: embed NSIH header
> arm: nexell: add UART support
> arm: nexell: add preliminary S5P6818 SoC device tree
> arm: add NanoPi M3 board support
> arm: nexell: switch to 32-bit
>
> arch/arm/Kconfig | 29 +++++
> arch/arm/Makefile | 1 +
> arch/arm/cpu/armv8/Makefile | 2 +-
> arch/arm/dts/s5p6818-nanopi-m3.dts | 30 +++++
> arch/arm/dts/s5p6818.dtsi | 196
> ++++++++++++++++++++++++++++++
> arch/arm/dts/s5pc1xx-goni.dts | 2 +-
> arch/arm/dts/s5pc1xx-smdkc100.dts | 2 +-
> arch/arm/include/asm/arch-nexell/boot0.h | 35 ++++++
> arch/arm/include/asm/arch-nexell/clk.h | 15 +++
> arch/arm/include/asm/arch-nexell/pwm.h | 62 ++++++++++
> arch/arm/mach-exynos/include/mach/uart.h | 44 -------
> arch/arm/mach-imx/mx7ulp/Kconfig | 1 +
> arch/arm/mach-nexell/Kconfig | 9 ++
> arch/arm/mach-nexell/Makefile | 10 ++
> arch/arm/mach-nexell/README | 49 ++++++++
> arch/arm/mach-nexell/board.c | 128 +++++++++++++++++++
> arch/arm/mach-nexell/mmu-arm64.c | 39 ++++++
> arch/arm/mach-s5pc1xx/Kconfig | 2 +
> arch/arm/mach-s5pc1xx/include/mach/uart.h | 44 -------
> configs/nanopi_m3_defconfig | 12 ++
> drivers/mmc/Kconfig | 8 ++
> drivers/mmc/Makefile | 1 +
> drivers/mmc/nexell_dw_mmc.c | 159
> ++++++++++++++++++++++++ drivers/reset/Kconfig
> | 6 + drivers/reset/Makefile | 1 +
> drivers/reset/reset-generic.c | 111 +++++++++++++++++
> drivers/serial/Kconfig | 6 +
> drivers/serial/Makefile | 2 +-
> drivers/serial/serial_s5p.c | 45 ++++++-
> include/configs/mx7ulp_evk.h | 1 -
> include/configs/s5p6818.h | 35 ++++++
> include/configs/ti_armv7_keystone2.h | 1 -
> scripts/config_whitelist.txt | 1 - 33 files changed,
> 989 insertions(+), 100 deletions(-) create mode 100644
> arch/arm/dts/s5p6818-nanopi-m3.dts create mode 100644
> arch/arm/dts/s5p6818.dtsi create mode 100644
> arch/arm/include/asm/arch-nexell/boot0.h create mode 100644
> arch/arm/include/asm/arch-nexell/clk.h create mode 100644
> arch/arm/include/asm/arch-nexell/pwm.h delete mode 100644
> arch/arm/mach-exynos/include/mach/uart.h create mode 100644
> arch/arm/mach-nexell/Kconfig create mode 100644
> arch/arm/mach-nexell/Makefile create mode 100644
> arch/arm/mach-nexell/README create mode 100644
> arch/arm/mach-nexell/board.c create mode 100644
> arch/arm/mach-nexell/mmu-arm64.c delete mode 100644
> arch/arm/mach-s5pc1xx/include/mach/uart.h create mode 100644
> configs/nanopi_m3_defconfig create mode 100644
> drivers/mmc/nexell_dw_mmc.c create mode 100644
> drivers/reset/reset-generic.c create mode 100644
> include/configs/s5p6818.h
>
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support
2017-11-30 10:01 ` [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Lukasz Majewski
@ 2017-11-30 10:22 ` Lukasz Majewski
2017-11-30 10:52 ` Andre Przywara
0 siblings, 1 reply; 34+ messages in thread
From: Lukasz Majewski @ 2017-11-30 10:22 UTC (permalink / raw)
To: u-boot
Hi,
> Hi Andre,
>
> > Hi,
> >
> > this is a first draft of the things Amit and I have been working on
> > in the last months. It introduces support for an SoC called "Nexell
> > S5P6818". This is an Octa-core ARMv8 SoC with Cortex-A53 cores,
> > which apparently is closely related to (older) Samsung SoCs. Many
> > peripherals are compatible to Samsung IP (UART, MMC, Ethernet,
> > timers, ...), but some core peripherals like the clocks and the pin
> > controller seem to be completely different. We used the NanoPi M3
> > board [1] for testing, which uses this SoC along with the usual
> > suspects of on-board components and connectors. This port is done
> > completely from scratch, by just looking at the manual. This allows
> > a much cleaner and modern U-Boot support than the BSP code.
> >
> > The ARM Generic Timer (aka. arch timer) does not seem to work on
> > this SoC. Ideally there would be some (hidden?) register enabling
> > the right clock source, though we haven't found one (yet). But as
> > also other code for this SoC out there on the net does not seem to
> > be able to use the arch timer, I am not too hopeful here. While
> > this does not impose a real problem to U-Boot (patch 3/13 takes
> > care of that), it is a showstopper for mainline arm64 Linux, which
> > heavily relies on the arch timer (since it's a mandatory part of
> > the ARMv8 architecture). There is only a very small chance that the
> > arch timer ever becomes optional in the mainline arm64 kernel.
> > However our arm(32) kernel ports works quite nicely so far, also a
> > (hacked) arm64 kernel boots to the prompt. We will submit Linux
> > patches at a later time.
> >
> > We would be grateful to get some comments on the patches.
> > The first five patches adapt existing code to simplify support for
> > this SoC. The following six patches then successively enable and add
> > SoC support, culmulating in the addition of a nanopi_m3_defconfig
> > file in patch 11/13. The SoC support code is actually architecture
> > agnostic, though up until the last patch it generates an AArch64
> > binary. To overcome the problems with the arch timer mentioned
> > above, the final patch switches the port over to AArch32, which can
> > more naturally launch arm kernels.
> >
> > This code so far does not include an SPL, instead it relies on some
> > vendor provided code to initialise the DRAM and load U-Boot proper.
> > The original BSP code provided a binary blob for that (called
> > "secondboot"), although there is some GPLed version of that
> > available on github([2]). We can load a 32-bit U-Boot with both the
> > vendor blob and Rafaello's GPL version, the 64-bit version is only
> > usable with the GPL code. Instruction on how to create a bootable
> > SD card are contained in the arch/arm/mach-nexell/README file.
> >
> > We would be very grateful to get some first feedback on those
> > patches and the approach in general taken here.
>
> Just to ask - why it is not possible to add this to:
>
> /arch/arm/mach-exynos ? And start new mach-nexell ?
Ok. I was too fast :-)
Nexell is a separate company - also from Korea - so mach-nexell is a
correct approach.
Sorry.
>
> As fair as I remember, many Samsung SoCs (especially S5P) share IP
> blocks, so maybe there is a place for unification?
But unification if possible is more than welcome - as it was done in
this patch set with uart code.
>
> Also, it would be quite challenging to support first armv8 Samsung soc
> in the current directory structure.....
Considering above - mach-nexell is probably the way to go.
>
>
> +CC Jaehoon - who may have some comments here.
>
> >
> > Cheers,
> > Andre.
> >
> > [1] http://nanopi.io/nanopi-m3.html
> > [2] https://github.com/rafaello7/bl1-nanopi-m3
> >
> > Amit Singh Tomar (4):
> > reset: add driver for generic reset controllers
> > mmc: add MMC (glue) driver for Nexell SoCs
> > arm: nexell: add ARM64 MMU regions
> > arm: nexell: add timer support
> >
> > Andre Przywara (9):
> > serial: s5p: rework Samsung UART driver to get rid of uart.h
> > serial: S5P/Samsung: refactor and Kconfig-ize UART selection
> > arm: move SYS_ARCH_TIMER to KConfig
> > arm: add basic framework for Nexell S5P6818 support
> > arm: nexell: embed NSIH header
> > arm: nexell: add UART support
> > arm: nexell: add preliminary S5P6818 SoC device tree
> > arm: add NanoPi M3 board support
> > arm: nexell: switch to 32-bit
> >
> > arch/arm/Kconfig | 29 +++++
> > arch/arm/Makefile | 1 +
> > arch/arm/cpu/armv8/Makefile | 2 +-
> > arch/arm/dts/s5p6818-nanopi-m3.dts | 30 +++++
> > arch/arm/dts/s5p6818.dtsi | 196
> > ++++++++++++++++++++++++++++++
> > arch/arm/dts/s5pc1xx-goni.dts | 2 +-
> > arch/arm/dts/s5pc1xx-smdkc100.dts | 2 +-
> > arch/arm/include/asm/arch-nexell/boot0.h | 35 ++++++
> > arch/arm/include/asm/arch-nexell/clk.h | 15 +++
> > arch/arm/include/asm/arch-nexell/pwm.h | 62 ++++++++++
> > arch/arm/mach-exynos/include/mach/uart.h | 44 -------
> > arch/arm/mach-imx/mx7ulp/Kconfig | 1 +
> > arch/arm/mach-nexell/Kconfig | 9 ++
> > arch/arm/mach-nexell/Makefile | 10 ++
> > arch/arm/mach-nexell/README | 49 ++++++++
> > arch/arm/mach-nexell/board.c | 128 +++++++++++++++++++
> > arch/arm/mach-nexell/mmu-arm64.c | 39 ++++++
> > arch/arm/mach-s5pc1xx/Kconfig | 2 +
> > arch/arm/mach-s5pc1xx/include/mach/uart.h | 44 -------
> > configs/nanopi_m3_defconfig | 12 ++
> > drivers/mmc/Kconfig | 8 ++
> > drivers/mmc/Makefile | 1 +
> > drivers/mmc/nexell_dw_mmc.c | 159
> > ++++++++++++++++++++++++ drivers/reset/Kconfig
> > | 6 + drivers/reset/Makefile | 1 +
> > drivers/reset/reset-generic.c | 111 +++++++++++++++++
> > drivers/serial/Kconfig | 6 +
> > drivers/serial/Makefile | 2 +-
> > drivers/serial/serial_s5p.c | 45 ++++++-
> > include/configs/mx7ulp_evk.h | 1 -
> > include/configs/s5p6818.h | 35 ++++++
> > include/configs/ti_armv7_keystone2.h | 1 -
> > scripts/config_whitelist.txt | 1 - 33 files changed,
> > 989 insertions(+), 100 deletions(-) create mode 100644
> > arch/arm/dts/s5p6818-nanopi-m3.dts create mode 100644
> > arch/arm/dts/s5p6818.dtsi create mode 100644
> > arch/arm/include/asm/arch-nexell/boot0.h create mode 100644
> > arch/arm/include/asm/arch-nexell/clk.h create mode 100644
> > arch/arm/include/asm/arch-nexell/pwm.h delete mode 100644
> > arch/arm/mach-exynos/include/mach/uart.h create mode 100644
> > arch/arm/mach-nexell/Kconfig create mode 100644
> > arch/arm/mach-nexell/Makefile create mode 100644
> > arch/arm/mach-nexell/README create mode 100644
> > arch/arm/mach-nexell/board.c create mode 100644
> > arch/arm/mach-nexell/mmu-arm64.c delete mode 100644
> > arch/arm/mach-s5pc1xx/include/mach/uart.h create mode 100644
> > configs/nanopi_m3_defconfig create mode 100644
> > drivers/mmc/nexell_dw_mmc.c create mode 100644
> > drivers/reset/reset-generic.c create mode 100644
> > include/configs/s5p6818.h
> >
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support
2017-11-30 10:22 ` Lukasz Majewski
@ 2017-11-30 10:52 ` Andre Przywara
0 siblings, 0 replies; 34+ messages in thread
From: Andre Przywara @ 2017-11-30 10:52 UTC (permalink / raw)
To: u-boot
Hi Lukasz,
thanks for having a look!
On 30/11/17 10:22, Lukasz Majewski wrote:
> Hi,
>
>> Hi Andre,
>>
>>> Hi,
>>>
>>> this is a first draft of the things Amit and I have been working on
>>> in the last months. It introduces support for an SoC called "Nexell
>>> S5P6818". This is an Octa-core ARMv8 SoC with Cortex-A53 cores,
>>> which apparently is closely related to (older) Samsung SoCs. Many
>>> peripherals are compatible to Samsung IP (UART, MMC, Ethernet,
>>> timers, ...), but some core peripherals like the clocks and the pin
>>> controller seem to be completely different. We used the NanoPi M3
>>> board [1] for testing, which uses this SoC along with the usual
>>> suspects of on-board components and connectors. This port is done
>>> completely from scratch, by just looking at the manual. This allows
>>> a much cleaner and modern U-Boot support than the BSP code.
>>>
>>> The ARM Generic Timer (aka. arch timer) does not seem to work on
>>> this SoC. Ideally there would be some (hidden?) register enabling
>>> the right clock source, though we haven't found one (yet). But as
>>> also other code for this SoC out there on the net does not seem to
>>> be able to use the arch timer, I am not too hopeful here. While
>>> this does not impose a real problem to U-Boot (patch 3/13 takes
>>> care of that), it is a showstopper for mainline arm64 Linux, which
>>> heavily relies on the arch timer (since it's a mandatory part of
>>> the ARMv8 architecture). There is only a very small chance that the
>>> arch timer ever becomes optional in the mainline arm64 kernel.
>>> However our arm(32) kernel ports works quite nicely so far, also a
>>> (hacked) arm64 kernel boots to the prompt. We will submit Linux
>>> patches at a later time.
>>>
>>> We would be grateful to get some comments on the patches.
>>> The first five patches adapt existing code to simplify support for
>>> this SoC. The following six patches then successively enable and add
>>> SoC support, culmulating in the addition of a nanopi_m3_defconfig
>>> file in patch 11/13. The SoC support code is actually architecture
>>> agnostic, though up until the last patch it generates an AArch64
>>> binary. To overcome the problems with the arch timer mentioned
>>> above, the final patch switches the port over to AArch32, which can
>>> more naturally launch arm kernels.
>>>
>>> This code so far does not include an SPL, instead it relies on some
>>> vendor provided code to initialise the DRAM and load U-Boot proper.
>>> The original BSP code provided a binary blob for that (called
>>> "secondboot"), although there is some GPLed version of that
>>> available on github([2]). We can load a 32-bit U-Boot with both the
>>> vendor blob and Rafaello's GPL version, the 64-bit version is only
>>> usable with the GPL code. Instruction on how to create a bootable
>>> SD card are contained in the arch/arm/mach-nexell/README file.
>>>
>>> We would be very grateful to get some first feedback on those
>>> patches and the approach in general taken here.
>>
>> Just to ask - why it is not possible to add this to:
>>
>> /arch/arm/mach-exynos ? And start new mach-nexell ?
>
> Ok. I was too fast :-)
>
> Nexell is a separate company - also from Korea - so mach-nexell is a
> correct approach.
Yes, I was thinking the same. Though the companies seem to be somewhat
related, but I couldn't find any more information about that. My best
guess is that either Nexell licensed some (older?) IP from Samsung or
it's some kind of spin-off or contractor for Samsung.
But apart from that company relationship I think we should look at the
hardware. And here we have the core peripherals (pinctrl, clocks) and
the system boot and bringup sequence being actually different from
Samsung, so I found a new directory the way to go.
> Sorry.
No worries, this isn't really obvious.
>>
>> As fair as I remember, many Samsung SoCs (especially S5P) share IP
>> blocks, so maybe there is a place for unification?
>
> But unification if possible is more than welcome - as it was done in
> this patch set with uart code.
Indeed, I think we should do it for the timer as well, I just didn't get
around it yet and wanted to have some feedback early.
>> Also, it would be quite challenging to support first armv8 Samsung soc
>> in the current directory structure.....
>
> Considering above - mach-nexell is probably the way to go.
In the long run I want to keep this directory as empty as possible.
Right now we do some clock setup for instance in board.c, which could be
moved somewhere else. But this is something for the future.
If this directory turns out to be only sparsely populated, I am open to
merging the code somewhere else.
Cheers,
Andre.
>>
>> +CC Jaehoon - who may have some comments here.
>>
>>>
>>> Cheers,
>>> Andre.
>>>
>>> [1] http://nanopi.io/nanopi-m3.html
>>> [2] https://github.com/rafaello7/bl1-nanopi-m3
>>>
>>> Amit Singh Tomar (4):
>>> reset: add driver for generic reset controllers
>>> mmc: add MMC (glue) driver for Nexell SoCs
>>> arm: nexell: add ARM64 MMU regions
>>> arm: nexell: add timer support
>>>
>>> Andre Przywara (9):
>>> serial: s5p: rework Samsung UART driver to get rid of uart.h
>>> serial: S5P/Samsung: refactor and Kconfig-ize UART selection
>>> arm: move SYS_ARCH_TIMER to KConfig
>>> arm: add basic framework for Nexell S5P6818 support
>>> arm: nexell: embed NSIH header
>>> arm: nexell: add UART support
>>> arm: nexell: add preliminary S5P6818 SoC device tree
>>> arm: add NanoPi M3 board support
>>> arm: nexell: switch to 32-bit
>>>
>>> arch/arm/Kconfig | 29 +++++
>>> arch/arm/Makefile | 1 +
>>> arch/arm/cpu/armv8/Makefile | 2 +-
>>> arch/arm/dts/s5p6818-nanopi-m3.dts | 30 +++++
>>> arch/arm/dts/s5p6818.dtsi | 196
>>> ++++++++++++++++++++++++++++++
>>> arch/arm/dts/s5pc1xx-goni.dts | 2 +-
>>> arch/arm/dts/s5pc1xx-smdkc100.dts | 2 +-
>>> arch/arm/include/asm/arch-nexell/boot0.h | 35 ++++++
>>> arch/arm/include/asm/arch-nexell/clk.h | 15 +++
>>> arch/arm/include/asm/arch-nexell/pwm.h | 62 ++++++++++
>>> arch/arm/mach-exynos/include/mach/uart.h | 44 -------
>>> arch/arm/mach-imx/mx7ulp/Kconfig | 1 +
>>> arch/arm/mach-nexell/Kconfig | 9 ++
>>> arch/arm/mach-nexell/Makefile | 10 ++
>>> arch/arm/mach-nexell/README | 49 ++++++++
>>> arch/arm/mach-nexell/board.c | 128 +++++++++++++++++++
>>> arch/arm/mach-nexell/mmu-arm64.c | 39 ++++++
>>> arch/arm/mach-s5pc1xx/Kconfig | 2 +
>>> arch/arm/mach-s5pc1xx/include/mach/uart.h | 44 -------
>>> configs/nanopi_m3_defconfig | 12 ++
>>> drivers/mmc/Kconfig | 8 ++
>>> drivers/mmc/Makefile | 1 +
>>> drivers/mmc/nexell_dw_mmc.c | 159
>>> ++++++++++++++++++++++++ drivers/reset/Kconfig
>>> | 6 + drivers/reset/Makefile | 1 +
>>> drivers/reset/reset-generic.c | 111 +++++++++++++++++
>>> drivers/serial/Kconfig | 6 +
>>> drivers/serial/Makefile | 2 +-
>>> drivers/serial/serial_s5p.c | 45 ++++++-
>>> include/configs/mx7ulp_evk.h | 1 -
>>> include/configs/s5p6818.h | 35 ++++++
>>> include/configs/ti_armv7_keystone2.h | 1 -
>>> scripts/config_whitelist.txt | 1 - 33 files changed,
>>> 989 insertions(+), 100 deletions(-) create mode 100644
>>> arch/arm/dts/s5p6818-nanopi-m3.dts create mode 100644
>>> arch/arm/dts/s5p6818.dtsi create mode 100644
>>> arch/arm/include/asm/arch-nexell/boot0.h create mode 100644
>>> arch/arm/include/asm/arch-nexell/clk.h create mode 100644
>>> arch/arm/include/asm/arch-nexell/pwm.h delete mode 100644
>>> arch/arm/mach-exynos/include/mach/uart.h create mode 100644
>>> arch/arm/mach-nexell/Kconfig create mode 100644
>>> arch/arm/mach-nexell/Makefile create mode 100644
>>> arch/arm/mach-nexell/README create mode 100644
>>> arch/arm/mach-nexell/board.c create mode 100644
>>> arch/arm/mach-nexell/mmu-arm64.c delete mode 100644
>>> arch/arm/mach-s5pc1xx/include/mach/uart.h create mode 100644
>>> configs/nanopi_m3_defconfig create mode 100644
>>> drivers/mmc/nexell_dw_mmc.c create mode 100644
>>> drivers/reset/reset-generic.c create mode 100644
>>> include/configs/s5p6818.h
>>>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 01/13] serial: s5p: rework Samsung UART driver to get rid of uart.h
2017-11-30 1:24 ` [U-Boot] [RFC PATCH 01/13] serial: s5p: rework Samsung UART driver to get rid of uart.h Andre Przywara
@ 2017-12-02 3:30 ` Simon Glass
2017-12-04 10:21 ` Andre Przywara
0 siblings, 1 reply; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:30 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:24, Andre Przywara <andre.przywara@arm.com> wrote:
> At the moment the serial_s5p driver takes care of both Exynos UARTs
> as well as those from older Samsung SoCs (s3c/s5p series).
> Looking more closely the only difference between those two groups is
> how the fractional baud rate is programmed: via a "divslot" (s3c) or as
> a proper fractional value (Exynos).
> Instead of intricately expressing this via a special header file (which
> is otherwise identical), let's use the blessings of DT to tackle this:
> The S5P series of SoCs use their own compatible string, in line with
> what the official DTs from the Linux kernel do. We then switch between
> divslot and fractional value based on the compatible string used.
> This allows us to get rid of the uart.h header files and make the
> driver more flexible.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/dts/s5pc1xx-goni.dts | 2 +-
> arch/arm/dts/s5pc1xx-smdkc100.dts | 2 +-
> arch/arm/mach-exynos/include/mach/uart.h | 44 ------------------------------
> arch/arm/mach-s5pc1xx/include/mach/uart.h | 44 ------------------------------
> drivers/serial/serial_s5p.c | 45 +++++++++++++++++++++++++++----
> 5 files changed, 42 insertions(+), 95 deletions(-)
> delete mode 100644 arch/arm/mach-exynos/include/mach/uart.h
> delete mode 100644 arch/arm/mach-s5pc1xx/include/mach/uart.h
>
> diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts
> index 182325a091..964c7a6b67 100644
> --- a/arch/arm/dts/s5pc1xx-goni.dts
> +++ b/arch/arm/dts/s5pc1xx-goni.dts
> @@ -28,7 +28,7 @@
> };
>
> serial at e2900800 {
> - compatible = "samsung,exynos4210-uart";
> + compatible = "samsung,s5pv210-uart";
Does this match linux?
Apart from that:
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 02/13] serial: S5P/Samsung: refactor and Kconfig-ize UART selection
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 02/13] serial: S5P/Samsung: refactor and Kconfig-ize UART selection Andre Przywara
@ 2017-12-02 3:30 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:30 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> Currently the UART used by some Samsung SoCs is selected by the
> generic CONFIG_S5P define. This makes it hard to re-use that UART
> without pulling in the whole of the S5P code. Also the Exynos SoCs
> use this driver, which is in fact a generic Samsung UART driver.
>
> So create a new Kconfig symbol CONFIG_SAMSUNG_UART to reflect this and
> change the existing boards to use this symbol.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/mach-s5pc1xx/Kconfig | 2 ++
> drivers/serial/Kconfig | 6 ++++++
> drivers/serial/Makefile | 2 +-
> 4 files changed, 10 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig Andre Przywara
@ 2017-12-02 3:30 ` Simon Glass
2017-12-08 6:21 ` Tuomas Tynkkynen
2018-04-12 1:27 ` Tuomas Tynkkynen
2 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:30 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch
> timer) in U-Boot.
> At the moment it is mandatory for ARMv8 and used by two ARMv7 boards.
> Add a proper Kconfig symbol to express this dependency properly,
> allowing certain board configuration to later disable arch timer in case
> there are any problems with it.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/Kconfig | 11 +++++++++++
> arch/arm/cpu/armv8/Makefile | 2 +-
> arch/arm/mach-imx/mx7ulp/Kconfig | 1 +
> include/configs/mx7ulp_evk.h | 1 -
> include/configs/ti_armv7_keystone2.h | 1 -
> scripts/config_whitelist.txt | 1 -
> 6 files changed, 13 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 04/13] reset: add driver for generic reset controllers
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 04/13] reset: add driver for generic reset controllers Andre Przywara
@ 2017-12-02 3:30 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:30 UTC (permalink / raw)
To: u-boot
Hi Andre,
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> From: Amit Singh Tomar <amittomer25@gmail.com>
>
> The simplest and most generic form of a reset controller just exposes
> multiple MMIO registers, where each bit toggles a separate reset line.
> Add a generic driver to describe this kind of reset controller.
>
> This is used on the Nexell S5P6818, for instance, but also by other
> SoCs.
>
> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
> [Andre: make more generic, let it cover multiple registers, slight rework]
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> drivers/reset/Kconfig | 6 +++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-generic.c | 111 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 118 insertions(+)
> create mode 100644 drivers/reset/reset-generic.c
Reviewed-by: Simon Glass <sjg@chromium.org>
Is there a DT binding for this?
Also please see below.
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index ce46e2752c..3032b0064c 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -12,6 +12,12 @@ config DM_RESET
> although driving such reset isgnals using GPIOs may be more
> appropriate in this case.
>
> +config GENERIC_RESET
> + bool "Generic Reset controller driver"
> + depends on DM_RESET
> + help
> + Support Generic reset controller.
What is this? This help needs to be expanded with details.
> +
> config SANDBOX_RESET
> bool "Enable the sandbox reset test driver"
> depends on DM_MAILBOX && SANDBOX
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 252cefeed5..81680837ef 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -12,3 +12,4 @@ obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
> obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
> obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
> +obj-$(CONFIG_GENERIC_RESET) += reset-generic.o
> diff --git a/drivers/reset/reset-generic.c b/drivers/reset/reset-generic.c
> new file mode 100644
> index 0000000000..0a7740202d
> --- /dev/null
> +++ b/drivers/reset/reset-generic.c
> @@ -0,0 +1,111 @@
> +/*
> + * Copyright (C) 2017 Amit Singh Tomar <amittomer25@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <reset-uclass.h>
> +#include <linux/bitops.h>
> +#include <linux/io.h>
> +#include <linux/sizes.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct generic_reset_priv {
> + void __iomem *membase;
> + int max_reset;
comment
> +};
> +
> +#define BITS_PER_BYTE 8
blank line here
> +static int generic_reset_toggle(struct reset_ctl *rst, bool assert)
> +{
> + struct generic_reset_priv *priv = dev_get_priv(rst->dev);
> + int reg_width = sizeof(u32);
> + int bank, offset;
> + u32 reg;
> +
> + if (rst->id >= priv->max_reset)
> + return -EINVAL;
> +
> + bank = rst->id / (reg_width * BITS_PER_BYTE);
> + offset = rst->id % (reg_width * BITS_PER_BYTE);
> +
> + reg = readl(priv->membase + (bank * reg_width));
Can you put that expression in a local var?
> + if (assert)
> + writel(reg & ~BIT(offset), priv->membase + (bank * reg_width));
> + else
> + writel(reg | BIT(offset), priv->membase + (bank * reg_width));
> +
> + return 0;
> +}
> +
> +static int generic_reset_assert(struct reset_ctl *rst)
> +{
> + return generic_reset_toggle(rst, true);
> +}
> +
> +static int generic_reset_deassert(struct reset_ctl *rst)
> +{
> + return generic_reset_toggle(rst, false);
> +}
> +
> +static int generic_reset_free(struct reset_ctl *rst)
> +{
> + return 0;
> +}
> +
> +static int generic_reset_request(struct reset_ctl *rst)
> +{
> + struct generic_reset_priv *priv = dev_get_priv(rst->dev);
> +
> + if (rst->id >= priv->max_reset)
> + return -EINVAL;
OK I suppose. How about -ENOENT?
> +
> + return generic_reset_assert(rst);
> +}
> +
> +struct reset_ops generic_reset_reset_ops = {
> + .free = generic_reset_free,
> + .request = generic_reset_request,
> + .rst_assert = generic_reset_assert,
> + .rst_deassert = generic_reset_deassert,
> +};
> +
> +static const struct udevice_id generic_reset_ids[] = {
> + { .compatible = "generic-reset" },
> + { .compatible = "nexell,s5p6818-reset" },
> + { }
> +};
> +
> +static int generic_reset_probe(struct udevice *dev)
> +{
> + struct generic_reset_priv *priv = dev_get_priv(dev);
> + fdt_addr_t addr;
> + fdt_size_t size;
> +
> + addr = devfdt_get_addr_size_index(dev, 0, &size);
Can we use dev_read_... here?
> + if (addr == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + priv->max_reset = dev_read_u32_default(dev, "num-resets", -1);
> + if (priv->max_reset == -1)
> + priv->max_reset = size * BITS_PER_BYTE;
> +
> + priv->membase = devm_ioremap(dev, addr, size);
> + if (!priv->membase)
> + return -EFAULT;
> +
> + return 0;
> +}
> +
> +U_BOOT_DRIVER(generic_reset) = {
> + .name = "generic_reset",
> + .id = UCLASS_RESET,
> + .of_match = generic_reset_ids,
> + .ops = &generic_reset_reset_ops,
> + .probe = generic_reset_probe,
> + .priv_auto_alloc_size = sizeof(struct generic_reset_priv),
> +};
> --
> 2.14.1
>
Regards,
Simon
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 05/13] mmc: add MMC (glue) driver for Nexell SoCs
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 05/13] mmc: add MMC (glue) driver for Nexell SoCs Andre Przywara
@ 2017-12-02 3:30 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:30 UTC (permalink / raw)
To: u-boot
Hi Andre,
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> From: Amit Singh Tomar <amittomer25@gmail.com>
>
> The Nexell SoCs contain multiple MMC devices, which can be driven by
> U-Boot's DesignWare MMC driver, if supported by the required glue driver
> file.
> Provide that file along with the Makefile/Kconfig changes.
>
> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> drivers/mmc/Kconfig | 8 +++
> drivers/mmc/Makefile | 1 +
> drivers/mmc/nexell_dw_mmc.c | 159 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 168 insertions(+)
> create mode 100644 drivers/mmc/nexell_dw_mmc.c
>
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 62ce0af7d3..243878aa65 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -91,6 +91,14 @@ config MMC_DW_K3
> Synopsys DesignWare Memory Card Interface driver. Select this option
> for platforms based on Hisilicon K3 SoC's.
>
> +config MMC_DW_NEXELL
> + bool "NEXELL SD/MMC controller support"
> + depends on ARCH_NEXELL && DM_MMC && OF_CONTROL
> + depends on MMC_DW
> + help
> + This enables support for the Nexell SD/MMM controller, which is
> + based on Designware IP.
> +
> config MMC_DW_ROCKCHIP
> bool "Rockchip SD/MMC controller support"
> depends on DM_MMC && OF_CONTROL
> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> index d505f37f01..0fb6eb7803 100644
> --- a/drivers/mmc/Makefile
> +++ b/drivers/mmc/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_MMC_DAVINCI) += davinci_mmc.o
> obj-$(CONFIG_MMC_DW) += dw_mmc.o
> obj-$(CONFIG_MMC_DW_EXYNOS) += exynos_dw_mmc.o
> obj-$(CONFIG_MMC_DW_K3) += hi6220_dw_mmc.o
> +obj-$(CONFIG_MMC_DW_NEXELL) += nexell_dw_mmc.o
> obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
> obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
> obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
> diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c
> new file mode 100644
> index 0000000000..e96395cdaf
> --- /dev/null
> +++ b/drivers/mmc/nexell_dw_mmc.c
> @@ -0,0 +1,159 @@
> +/*
> + * Copyright (C) 2017 Amit Singh Tomar <amittomer25@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <dt-structs.h>
> +#include <dwmmc.h>
> +#include <errno.h>
> +#include <mapmem.h>
> +#include <linux/err.h>
> +#include <reset.h>
> +#include <asm/arch/clk.h>
> +
> +#define SDMMCCLKENB 0xC00C5000
> +#define SDMMCCLKGEN0L 0xC00C5004
> +#define PLL_SEL_MASK GENMASK(4, 2)
> +#define CLK_DIV_MASK GENMASK(12, 5)
> +#define PLLSEL_SHIFT 0x2
> +#define PLL0_SEL 0
> +#define PLL1_SEL 1
> +#define PLL2_SEL 2
> +#define SDMMC_CLK_ENB 0xc /* Magic bit to enable/generate SDMMC clock */
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct nexell_mmc_plat {
> + struct mmc_config cfg;
> + struct mmc mmc;
> +};
> +
> +struct nexell_dwmmc_priv {
> + struct clk clk;
> + struct dwmci_host host;
> + struct reset_ctl reset_ctl;
> + int fifo_depth;
> + bool fifo_mode;
comments
> +};
> +
> +/* Should this be done from CCF ? */
> +static void nexell_dwmci_clksel(struct dwmci_host *host)
> +{
> + u32 val;
> +
> + /* Enable SDMMC clock */
> + val = readl(SDMMCCLKENB);
> + val |= SDMMC_CLK_ENB;
> + writel(val, SDMMCCLKENB);
How about using setbits_le32() ?
> +
> + /* Select PLL1 as clock source */
> + val = readl(SDMMCCLKGEN0L);
> + val = val & ~(PLL_SEL_MASK);
> + val |= (PLL1_SEL << PLLSEL_SHIFT) & PLL_SEL_MASK;
> + writel(val, SDMMCCLKGEN0L);
clrsetbits_le32
> +}
> +
> +static int nexell_dwmmc_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct nexell_dwmmc_priv *priv = dev_get_priv(dev);
> + struct dwmci_host *host = &priv->host;
> + int fifo_depth, ret;
> +
> + ret = reset_get_by_name(dev, "mmc", &priv->reset_ctl);
> + if (ret) {
> + printf("reset_get_by_name(rst) failed: %d", ret);
debug() ? And below
> + return ret;
> + }
> +
> + fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
> + "fifo-depth", 0);
dev_read_...()
and below
> + if (fifo_depth < 0) {
> + printf("DWMMC: Can't get FIFO depth\n");
> + return -EINVAL;
> + }
> +
> + host->name = dev->name;
> + host->ioaddr = (void *)devfdt_get_addr(dev);
> + host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
> + "bus-width", 4);
> +
> + ret = reset_assert(&priv->reset_ctl);
> + if (ret)
> + return ret;
> +
> + host->clksel = nexell_dwmci_clksel;
> +
> + ret = reset_deassert(&priv->reset_ctl);
> + if (ret)
> + return ret;
> +
> + host->dev_index = 0;
> + host->bus_hz = get_mmc_clk(host->dev_index);
> + host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) |
> + TX_WMARK(fifo_depth / 2);
> + host->priv = priv;
> +
> + return 0;
> +}
> +
> +static int nexell_dwmmc_probe(struct udevice *dev)
> +{
> +#ifdef CONFIG_BLK
Do we need to support non-BLK? It is going away in March anyway.
> + struct nexell_mmc_plat *plat = dev_get_platdata(dev);
> +#endif
> + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
> + struct nexell_dwmmc_priv *priv = dev_get_priv(dev);
> + struct dwmci_host *host = &priv->host;
> +
> +#ifdef CONFIG_BLK
> + dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
> + host->mmc = &plat->mmc;
> +#else
> + int ret;
> +
> + ret = add_dwmci(host, host->bus_hz, 400000);
> + if (ret)
> + return ret;
> +#endif
> +
> + host->mmc->priv = &priv->host;
> + upriv->mmc = host->mmc;
> + host->mmc->dev = dev;
> +
> + return 0;
> +}
> +
> +static int nexell_dwmmc_bind(struct udevice *dev)
> +{
> +#ifdef CONFIG_BLK
> + struct nexell_mmc_plat *plat = dev_get_platdata(dev);
> + int ret;
> +
> + ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
> + if (ret)
> + return ret;
> +#endif
> +
> + return 0;
> +}
> +
> +static const struct udevice_id nexell_dwmmc_ids[] = {
> + { .compatible = "nexell,s5p6818-dw-mshc" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(nexell_dwmmc_drv) = {
> + .name = "nexell_s5p6818_dw_mshc",
> + .id = UCLASS_MMC,
> + .of_match = nexell_dwmmc_ids,
> + .ops = &dm_dwmci_ops,
> + .ofdata_to_platdata = nexell_dwmmc_ofdata_to_platdata,
> + .bind = nexell_dwmmc_bind,
> + .probe = nexell_dwmmc_probe,
> + .priv_auto_alloc_size = sizeof(struct nexell_dwmmc_priv),
> + .platdata_auto_alloc_size = sizeof(struct nexell_mmc_plat),
> +};
> --
> 2.14.1
>
Regards,
Simon
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 06/13] arm: add basic framework for Nexell S5P6818 support
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 06/13] arm: add basic framework for Nexell S5P6818 support Andre Przywara
@ 2017-12-02 3:30 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:30 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> The Nexell S5P6818 is a typical SoC with ARM Cortex-A53 cores.
> It has many peripherals derived from Samsung SoCs (MMC, serial, I2C,
> Ethernet, ...).
> Add the required files to introduce this new SoC (family?) to U-Boot.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/Kconfig | 6 ++++++
> arch/arm/Makefile | 1 +
> arch/arm/mach-nexell/Kconfig | 9 +++++++++
> arch/arm/mach-nexell/Makefile | 7 +++++++
> arch/arm/mach-nexell/board.c | 41 +++++++++++++++++++++++++++++++++++++++++
> include/configs/s5p6818.h | 33 +++++++++++++++++++++++++++++++++
> 6 files changed, 97 insertions(+)
> create mode 100644 arch/arm/mach-nexell/Kconfig
> create mode 100644 arch/arm/mach-nexell/Makefile
> create mode 100644 arch/arm/mach-nexell/board.c
> create mode 100644 include/configs/s5p6818.h
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 07/13] arm: nexell: embed NSIH header
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 07/13] arm: nexell: embed NSIH header Andre Przywara
@ 2017-12-02 3:30 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:30 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> The primary boot loaders provided by the SoC vendor or derived from that
> use an image format called "NSIH" to learn the load address and size of
> the boot payload. This header occupies 512 bytes, but contains only a
> few essential words of information.
> Use the boot0 feature to prepend this header before the actual U-Boot
> proper. We automatically fill it with the required information, also
> add a branch instruction to be able to enter at the beginning of the
> header.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/include/asm/arch-nexell/boot0.h | 35 ++++++++++++++++++++++++++++++++
> 2 files changed, 36 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-nexell/boot0.h
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 08/13] arm: nexell: add ARM64 MMU regions
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 08/13] arm: nexell: add ARM64 MMU regions Andre Przywara
@ 2017-12-02 3:31 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:31 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> From: Amit Singh Tomar <amittomer25@gmail.com>
>
> ARMv8 boards require a struct describing the memory regions for the
> mandatory MMU setup.
> Add the respective data for the Nexell S5P6818 SoC.
>
> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/mach-nexell/Makefile | 1 +
> arch/arm/mach-nexell/mmu-arm64.c | 39 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 40 insertions(+)
> create mode 100644 arch/arm/mach-nexell/mmu-arm64.c
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 09/13] arm: nexell: add UART support
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 09/13] arm: nexell: add UART support Andre Przywara
@ 2017-12-02 3:31 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:31 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> The Nexell S5P6818 SoC uses a UART very similar to those used in the
> Samsung S5P SoCs.
> Enable the driver in the config and add the necessary glue headers
> and clock functions to make the S5P driver happy.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/Kconfig | 3 ++
> arch/arm/include/asm/arch-nexell/clk.h | 13 +++++++++
> arch/arm/mach-nexell/board.c | 50 ++++++++++++++++++++++++++++++++++
> 3 files changed, 66 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-nexell/clk.h
Reviewed-by: Simon Glass <sjg@chromium.org>
Q below
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index b0f3ee7289..9c317ddf3f 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -656,6 +656,9 @@ config ARCH_NEXELL
> bool "Nexell S5P support"
> select ARM64
> select ENABLE_ARM_SOC_BOOT0_HOOK
> + select DM
> + select DM_SERIAL
> + select SAMSUNG_UART
>
> config ARCH_QEMU
> bool "QEMU Virtual Platform"
> diff --git a/arch/arm/include/asm/arch-nexell/clk.h b/arch/arm/include/asm/arch-nexell/clk.h
> new file mode 100644
> index 0000000000..bfd145f555
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-nexell/clk.h
> @@ -0,0 +1,13 @@
> +/*
> + * (C) Copyright 2017 ARM Ltd.
> + * Andre Przywara <andre.przywara@arm.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_ARCH_CLK_H_
> +#define __ASM_ARCH_CLK_H_
> +
> +unsigned long get_uart_clk(int dev_index);
> +
> +#endif
> diff --git a/arch/arm/mach-nexell/board.c b/arch/arm/mach-nexell/board.c
> index f0d258b71c..54a9d8c1f5 100644
> --- a/arch/arm/mach-nexell/board.c
> +++ b/arch/arm/mach-nexell/board.c
> @@ -5,9 +5,14 @@
> */
>
> #include <common.h>
> +#include <asm/io.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#define NEXELL_PLLSETREG0 0xc0010008UL
Is this not in the DT?
Do you need the UL?
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 10/13] arm: nexell: add timer support
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 10/13] arm: nexell: add timer support Andre Przywara
@ 2017-12-02 3:31 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:31 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> From: Amit Singh Tomar <amittomer25@gmail.com>
>
> Nexell based SoCs (S5P4414 and S5P6818) contain the same timer block as
> present on Samsungs SoCs.
>
> Add this timer code when compiling for Nexell SoC and provide the
> necessary glue functions to make the Samsung timer driver happy.
>
> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/include/asm/arch-nexell/clk.h | 1 +
> arch/arm/include/asm/arch-nexell/pwm.h | 62 ++++++++++++++++++++++++++++++++++
> arch/arm/mach-nexell/Makefile | 2 ++
> arch/arm/mach-nexell/board.c | 37 +++++++++++++++++---
> 4 files changed, 97 insertions(+), 5 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-nexell/pwm.h
Reviewed-by: Simon Glass <sjg@chromium.org>
But I encourage use of setclrbits_le32()
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 11/13] arm: nexell: add preliminary S5P6818 SoC device tree
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 11/13] arm: nexell: add preliminary S5P6818 SoC device tree Andre Przywara
@ 2017-12-02 3:31 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:31 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> The Nexell S5P6818 SoC is an octa-core SoC with ARM Cortex-A53 cores.
> The chip contains the usual peripherals for an smartphone/tablet/set-top
> box SoC.
> Add the .dtsi file describing the peripherals supported so far, but
> keep them still disabled.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/dts/s5p6818.dtsi | 196 ++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 197 insertions(+)
> create mode 100644 arch/arm/dts/s5p6818.dtsi
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 12/13] arm: add NanoPi M3 board support
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 12/13] arm: add NanoPi M3 board support Andre Przywara
@ 2017-12-02 3:31 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:31 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> The NanoPi M3 is a single board computer containing a
> Nexell S5P6818 SoC (with 8 ARMv8 Cortex-A53 cores).
> Add the respective defconfig and a (preliminary) device tree listing
> the devices that we support so far.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/Kconfig | 6 ++++++
> arch/arm/dts/s5p6818-nanopi-m3.dts | 30 ++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-nexell/clk.h | 1 +
> arch/arm/mach-nexell/board.c | 10 ++++++++++
> configs/nanopi_m3_defconfig | 12 ++++++++++++
> include/configs/s5p6818.h | 2 ++
> 6 files changed, 61 insertions(+)
> create mode 100644 arch/arm/dts/s5p6818-nanopi-m3.dts
> create mode 100644 configs/nanopi_m3_defconfig
Reviewed-by: Simon Glass <sjg@chromium.org>
I think this needs a clock driver.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 13/13] arm: nexell: switch to 32-bit
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 13/13] arm: nexell: switch to 32-bit Andre Przywara
@ 2017-12-02 3:32 ` Simon Glass
0 siblings, 0 replies; 34+ messages in thread
From: Simon Glass @ 2017-12-02 3:32 UTC (permalink / raw)
To: u-boot
On 29 November 2017 at 18:25, Andre Przywara <andre.przywara@arm.com> wrote:
> The vendor provided SPL blob (called "secondboot") runs completely in
> AArch32, so expects U-Boot to be AArch32 as well.
> Also the lack of a working arch timer limits Linux to 32-bits, as the
> mainline arm64 kernel heavily relies on the arch timer.
>
> This commit switches the NanoPiM3 board over to generate an ARM(32) binary,
> to allow easy testing for now. Also this adds a README file to describe
> the generation of a bootable SD card image.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/Kconfig | 2 +-
> arch/arm/mach-nexell/README | 49 +++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 50 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/mach-nexell/README
Reviewed-by: Simon Glass <sjg@chromium.org>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 01/13] serial: s5p: rework Samsung UART driver to get rid of uart.h
2017-12-02 3:30 ` Simon Glass
@ 2017-12-04 10:21 ` Andre Przywara
0 siblings, 0 replies; 34+ messages in thread
From: Andre Przywara @ 2017-12-04 10:21 UTC (permalink / raw)
To: u-boot
Hi Simon,
On 02/12/17 03:30, Simon Glass wrote:
> On 29 November 2017 at 18:24, Andre Przywara <andre.przywara@arm.com> wrote:
>> At the moment the serial_s5p driver takes care of both Exynos UARTs
>> as well as those from older Samsung SoCs (s3c/s5p series).
>> Looking more closely the only difference between those two groups is
>> how the fractional baud rate is programmed: via a "divslot" (s3c) or as
>> a proper fractional value (Exynos).
>> Instead of intricately expressing this via a special header file (which
>> is otherwise identical), let's use the blessings of DT to tackle this:
>> The S5P series of SoCs use their own compatible string, in line with
>> what the official DTs from the Linux kernel do. We then switch between
>> divslot and fractional value based on the compatible string used.
>> This allows us to get rid of the uart.h header files and make the
>> driver more flexible.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> arch/arm/dts/s5pc1xx-goni.dts | 2 +-
>> arch/arm/dts/s5pc1xx-smdkc100.dts | 2 +-
>> arch/arm/mach-exynos/include/mach/uart.h | 44 ------------------------------
>> arch/arm/mach-s5pc1xx/include/mach/uart.h | 44 ------------------------------
>> drivers/serial/serial_s5p.c | 45 +++++++++++++++++++++++++++----
>> 5 files changed, 42 insertions(+), 95 deletions(-)
>> delete mode 100644 arch/arm/mach-exynos/include/mach/uart.h
>> delete mode 100644 arch/arm/mach-s5pc1xx/include/mach/uart.h
>>
>> diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts
>> index 182325a091..964c7a6b67 100644
>> --- a/arch/arm/dts/s5pc1xx-goni.dts
>> +++ b/arch/arm/dts/s5pc1xx-goni.dts
>> @@ -28,7 +28,7 @@
>> };
>>
>> serial at e2900800 {
>> - compatible = "samsung,exynos4210-uart";
>> + compatible = "samsung,s5pv210-uart";
>
> Does this match linux?
Yes, this is where I got the compatible from:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/s5pv210.dtsi#n331
And s5pv210.dtsi is included by s5pv210-goni.dts.
> Apart from that:
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
Thanks a ton for the complete review! This is much appreciated!
Cheers,
Andre.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig Andre Przywara
2017-12-02 3:30 ` Simon Glass
@ 2017-12-08 6:21 ` Tuomas Tynkkynen
2017-12-08 8:50 ` Andre Przywara
2018-04-12 1:27 ` Tuomas Tynkkynen
2 siblings, 1 reply; 34+ messages in thread
From: Tuomas Tynkkynen @ 2017-12-08 6:21 UTC (permalink / raw)
To: u-boot
Hi Andre,
On 11/30/2017 03:25 AM, Andre Przywara wrote:
> SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch
> timer) in U-Boot.
> At the moment it is mandatory for ARMv8 and used by two ARMv7 boards.
> Add a proper Kconfig symbol to express this dependency properly,
> allowing certain board configuration to later disable arch timer in case
> there are any problems with it.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> arch/arm/Kconfig | 11 +++++++++++
> arch/arm/cpu/armv8/Makefile | 2 +-
> arch/arm/mach-imx/mx7ulp/Kconfig | 1 +
> include/configs/mx7ulp_evk.h | 1 -
> include/configs/ti_armv7_keystone2.h | 1 -
> scripts/config_whitelist.txt | 1 -
> 6 files changed, 13 insertions(+), 4 deletions(-)
This patch needs refreshing, as on master there are more usages of the
symbol that need conversion:
include/configs/qemu-arm.h:#define CONFIG_SYS_ARCH_TIMER
include/configs/stm32h743-disco.h:#define CONFIG_SYS_ARCH_TIMER
include/configs/stm32h743-eval.h:#define CONFIG_SYS_ARCH_TIMER
Otherwise looks good.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig
2017-12-08 6:21 ` Tuomas Tynkkynen
@ 2017-12-08 8:50 ` Andre Przywara
0 siblings, 0 replies; 34+ messages in thread
From: Andre Przywara @ 2017-12-08 8:50 UTC (permalink / raw)
To: u-boot
Hi Tuomas,
On 08/12/17 06:21, Tuomas Tynkkynen wrote:
> Hi Andre,
>
> On 11/30/2017 03:25 AM, Andre Przywara wrote:
>> SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch
>> timer) in U-Boot.
>> At the moment it is mandatory for ARMv8 and used by two ARMv7 boards.
>> Add a proper Kconfig symbol to express this dependency properly,
>> allowing certain board configuration to later disable arch timer in case
>> there are any problems with it.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> arch/arm/Kconfig | 11 +++++++++++
>> arch/arm/cpu/armv8/Makefile | 2 +-
>> arch/arm/mach-imx/mx7ulp/Kconfig | 1 +
>> include/configs/mx7ulp_evk.h | 1 -
>> include/configs/ti_armv7_keystone2.h | 1 -
>> scripts/config_whitelist.txt | 1 -
>> 6 files changed, 13 insertions(+), 4 deletions(-)
>
> This patch needs refreshing, as on master there are more usages of the
> symbol that need conversion:
>
> include/configs/qemu-arm.h:#define CONFIG_SYS_ARCH_TIMER
> include/configs/stm32h743-disco.h:#define CONFIG_SYS_ARCH_TIMER
> include/configs/stm32h743-eval.h:#define CONFIG_SYS_ARCH_TIMER
>
> Otherwise looks good.
Thanks for the heads up!
Will include this in the next version.
Cheers,
Andre.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-12-08 6:21 ` Tuomas Tynkkynen
@ 2018-04-12 1:27 ` Tuomas Tynkkynen
2 siblings, 0 replies; 34+ messages in thread
From: Tuomas Tynkkynen @ 2018-04-12 1:27 UTC (permalink / raw)
To: u-boot
Hi,
On Thu, 30 Nov 2017 01:25:01 +0000
Andre Przywara <andre.przywara@arm.com> wrote:
> SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch
> timer) in U-Boot.
> At the moment it is mandatory for ARMv8 and used by two ARMv7 boards.
> Add a proper Kconfig symbol to express this dependency properly,
> allowing certain board configuration to later disable arch timer in case
> there are any problems with it.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
I was doing some SYS_ARCH_TIMER related cleanup to qemu-arm, so I took
the opportunity to test + send a rebased + resynced version of this patch
at the same time. Hope that it doesn't conflict or cause any problems
with upgrading this Nexell patchset.
- Tuomas
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2018-04-12 1:27 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-30 1:24 [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Andre Przywara
2017-11-30 1:24 ` [U-Boot] [RFC PATCH 01/13] serial: s5p: rework Samsung UART driver to get rid of uart.h Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-12-04 10:21 ` Andre Przywara
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 02/13] serial: S5P/Samsung: refactor and Kconfig-ize UART selection Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 03/13] arm: move SYS_ARCH_TIMER to KConfig Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-12-08 6:21 ` Tuomas Tynkkynen
2017-12-08 8:50 ` Andre Przywara
2018-04-12 1:27 ` Tuomas Tynkkynen
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 04/13] reset: add driver for generic reset controllers Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 05/13] mmc: add MMC (glue) driver for Nexell SoCs Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 06/13] arm: add basic framework for Nexell S5P6818 support Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 07/13] arm: nexell: embed NSIH header Andre Przywara
2017-12-02 3:30 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 08/13] arm: nexell: add ARM64 MMU regions Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 09/13] arm: nexell: add UART support Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 10/13] arm: nexell: add timer support Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 11/13] arm: nexell: add preliminary S5P6818 SoC device tree Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 12/13] arm: add NanoPi M3 board support Andre Przywara
2017-12-02 3:31 ` Simon Glass
2017-11-30 1:25 ` [U-Boot] [RFC PATCH 13/13] arm: nexell: switch to 32-bit Andre Przywara
2017-12-02 3:32 ` Simon Glass
2017-11-30 10:01 ` [U-Boot] [RFC PATCH 00/13] Nexell S5P6818 SoC support Lukasz Majewski
2017-11-30 10:22 ` Lukasz Majewski
2017-11-30 10:52 ` Andre Przywara
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