* MIPS: io: Add barrier after register read in readX()
@ 2018-04-13 2:30 Sinan Kaya
0 siblings, 0 replies; 3+ messages in thread
From: Sinan Kaya @ 2018-04-13 2:30 UTC (permalink / raw)
From: Sinan Kaya <okaya@codeaurora.org>
[ Upstream commit a1cc7034e33d12dc17d13fbcd7d597d552889097 ]
While a barrier is present in the writeX() functions before the register
write, a similar barrier is missing in the readX() functions after the
register read. This could allow memory accesses following readX() to
observe stale data.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/19069/
[jhogan@kernel.org: Tidy commit message]
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/include/asm/io.h | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const
BUG(); \
} \
\
+ /* prevent prefetching of coherent DMA data prematurely */ \
+ rmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
Patches currently in stable-queue which might be from okaya@codeaurora.org are
queue-4.14/mips-io-add-barrier-after-register-read-in-readx.patch
queue-4.14/mips-io-prevent-compiler-reordering-writex.patch
^ permalink raw reply [flat|nested] 3+ messages in thread
* MIPS: io: Add barrier after register read in readX()
@ 2018-04-13 2:30 Sinan Kaya
0 siblings, 0 replies; 3+ messages in thread
From: Sinan Kaya @ 2018-04-13 2:30 UTC (permalink / raw)
From: Sinan Kaya <okaya@codeaurora.org>
[ Upstream commit a1cc7034e33d12dc17d13fbcd7d597d552889097 ]
While a barrier is present in the writeX() functions before the register
write, a similar barrier is missing in the readX() functions after the
register read. This could allow memory accesses following readX() to
observe stale data.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/19069/
[jhogan@kernel.org: Tidy commit message]
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/include/asm/io.h | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -375,6 +375,8 @@ static inline type pfx##read##bwlq(const
BUG(); \
} \
\
+ /* prevent prefetching of coherent DMA data prematurely */ \
+ rmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
Patches currently in stable-queue which might be from okaya@codeaurora.org are
queue-3.18/mips-io-add-barrier-after-register-read-in-readx.patch
^ permalink raw reply [flat|nested] 3+ messages in thread
* MIPS: io: Add barrier after register read in readX()
@ 2018-04-13 2:30 Sinan Kaya
0 siblings, 0 replies; 3+ messages in thread
From: Sinan Kaya @ 2018-04-13 2:30 UTC (permalink / raw)
From: Sinan Kaya <okaya@codeaurora.org>
[ Upstream commit a1cc7034e33d12dc17d13fbcd7d597d552889097 ]
While a barrier is present in the writeX() functions before the register
write, a similar barrier is missing in the readX() functions after the
register read. This could allow memory accesses following readX() to
observe stale data.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/19069/
[jhogan@kernel.org: Tidy commit message]
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/mips/include/asm/io.h | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const
BUG(); \
} \
\
+ /* prevent prefetching of coherent DMA data prematurely */ \
+ rmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
Patches currently in stable-queue which might be from okaya@codeaurora.org are
queue-4.16/mips-io-add-barrier-after-register-read-in-readx.patch
queue-4.16/mips-io-prevent-compiler-reordering-writex.patch
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-04-13 2:30 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-13 2:30 MIPS: io: Add barrier after register read in readX() Sinan Kaya
-- strict thread matches above, loose matches on Subject: below --
2018-04-13 2:30 Sinan Kaya
2018-04-13 2:30 Sinan Kaya
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.