From: "Mylène Josserand" <mylene.josserand@bootlin.com> To: linux@armlinux.org.uk, maxime.ripard@bootlin.com, wens@csie.org, marc.zyngier@arm.com, mark.rutland@arm.com, robh+dt@kernel.org, horms@verge.net.au, geert@linux-m68k.org, magnus.damm@gmail.com Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, clabbe.montjoie@gmail.com, quentin.schulz@bootlin.com, thomas.petazzoni@bootlin.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mylene.josserand@bootlin.com Subject: [PATCH v6 04/11] ARM: dts: sun8i: a83t: Add CCI-400 node Date: Mon, 16 Apr 2018 23:50:25 +0200 [thread overview] Message-ID: <20180416215032.5023-5-mylene.josserand@bootlin.com> (raw) In-Reply-To: <20180416215032.5023-1-mylene.josserand@bootlin.com> Add CCI-400 node and control-port on CPUs needed by SMP bringup. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 7974eaba57a7..42539267e329 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -66,6 +66,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; reg = <0>; }; @@ -73,6 +74,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; reg = <1>; }; @@ -80,6 +82,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; reg = <2>; }; @@ -87,6 +90,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; reg = <3>; }; @@ -96,6 +100,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; reg = <0x100>; }; @@ -103,6 +108,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; reg = <0x101>; }; @@ -110,6 +116,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; reg = <0x102>; }; @@ -117,6 +124,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; reg = <0x103>; }; }; @@ -354,6 +362,39 @@ reg = <0x01700000 0x400>; }; + cci@1790000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01790000 0x10000>; + ranges = <0x0 0x01790000 0x10000>; + + cci_control0: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + syscon: syscon@1c00000 { compatible = "allwinner,sun8i-a83t-system-controller", "syscon"; -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: mylene.josserand@bootlin.com (Mylène Josserand) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 04/11] ARM: dts: sun8i: a83t: Add CCI-400 node Date: Mon, 16 Apr 2018 23:50:25 +0200 [thread overview] Message-ID: <20180416215032.5023-5-mylene.josserand@bootlin.com> (raw) In-Reply-To: <20180416215032.5023-1-mylene.josserand@bootlin.com> Add CCI-400 node and control-port on CPUs needed by SMP bringup. Signed-off-by: Myl?ne Josserand <mylene.josserand@bootlin.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 7974eaba57a7..42539267e329 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -66,6 +66,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; reg = <0>; }; @@ -73,6 +74,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; reg = <1>; }; @@ -80,6 +82,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; reg = <2>; }; @@ -87,6 +90,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu0_opp_table>; + cci-control-port = <&cci_control0>; reg = <3>; }; @@ -96,6 +100,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; reg = <0x100>; }; @@ -103,6 +108,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; reg = <0x101>; }; @@ -110,6 +116,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; reg = <0x102>; }; @@ -117,6 +124,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; operating-points-v2 = <&cpu1_opp_table>; + cci-control-port = <&cci_control1>; reg = <0x103>; }; }; @@ -354,6 +362,39 @@ reg = <0x01700000 0x400>; }; + cci at 1790000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01790000 0x10000>; + ranges = <0x0 0x01790000 0x10000>; + + cci_control0: slave-if at 4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control1: slave-if at 5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu at 9000 { + compatible = "arm,cci-400-pmu,r1"; + reg = <0x9000 0x5000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + syscon: syscon at 1c00000 { compatible = "allwinner,sun8i-a83t-system-controller", "syscon"; -- 2.11.0
next prev parent reply other threads:[~2018-04-16 21:51 UTC|newest] Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-04-16 21:50 [PATCH v6 00/11] Sunxi: Add SMP support on A83T Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-16 21:50 ` [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-17 3:12 ` Chen-Yu Tsai 2018-04-17 3:12 ` Chen-Yu Tsai 2018-04-17 11:17 ` Maxime Ripard 2018-04-17 11:17 ` Maxime Ripard 2018-04-17 11:25 ` Chen-Yu Tsai 2018-04-17 11:25 ` Chen-Yu Tsai 2018-04-18 8:45 ` Maxime Ripard 2018-04-18 8:45 ` Maxime Ripard 2018-04-18 10:05 ` Chen-Yu Tsai 2018-04-18 10:05 ` Chen-Yu Tsai 2018-04-19 6:53 ` Mylène Josserand 2018-04-19 6:53 ` Mylène Josserand 2018-04-17 6:36 ` kbuild test robot 2018-04-17 6:36 ` kbuild test robot 2018-04-17 6:36 ` kbuild test robot 2018-04-17 6:36 ` kbuild test robot 2018-04-17 10:46 ` kbuild test robot 2018-04-17 10:46 ` kbuild test robot 2018-04-17 10:46 ` kbuild test robot 2018-04-17 10:46 ` kbuild test robot 2018-04-16 21:50 ` [PATCH v6 02/11] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-16 21:50 ` [PATCH v6 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the " Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-17 3:13 ` Chen-Yu Tsai 2018-04-17 3:13 ` Chen-Yu Tsai 2018-04-16 21:50 ` Mylène Josserand [this message] 2018-04-16 21:50 ` [PATCH v6 04/11] ARM: dts: sun8i: a83t: Add CCI-400 node Mylène Josserand 2018-04-16 21:50 ` [PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-18 9:30 ` Geert Uytterhoeven 2018-04-18 9:30 ` Geert Uytterhoeven 2018-04-18 10:01 ` Mylène Josserand 2018-04-18 10:01 ` Mylène Josserand 2018-04-16 21:50 ` [PATCH v6 06/11] ARM: sunxi: " Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-16 21:50 ` [PATCH v6 07/11] ARM: sun9i: smp: Rename clusters's power-off Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-17 8:21 ` Sergei Shtylyov 2018-04-17 8:21 ` Sergei Shtylyov 2018-04-17 8:21 ` Sergei Shtylyov 2018-04-18 5:51 ` Mylène Josserand 2018-04-18 5:51 ` Mylène Josserand 2018-04-16 21:50 ` [PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-17 7:52 ` Maxime Ripard 2018-04-17 7:52 ` Maxime Ripard 2018-04-17 7:57 ` Chen-Yu Tsai 2018-04-17 7:57 ` Chen-Yu Tsai 2018-04-17 11:19 ` Maxime Ripard 2018-04-17 11:19 ` Maxime Ripard 2018-04-16 21:50 ` [PATCH v6 09/11] ARM: sun8i: smp: Add support for A83T Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-17 11:20 ` Maxime Ripard 2018-04-17 11:20 ` Maxime Ripard 2018-04-18 5:46 ` Mylène Josserand 2018-04-18 5:46 ` Mylène Josserand 2018-04-16 21:50 ` [PATCH v6 10/11] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-16 21:50 ` [PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff Mylène Josserand 2018-04-16 21:50 ` Mylène Josserand 2018-04-18 9:36 ` Geert Uytterhoeven 2018-04-18 9:36 ` Geert Uytterhoeven 2018-04-18 10:03 ` Mylène Josserand 2018-04-18 10:03 ` Mylène Josserand 2018-04-18 13:48 ` Simon Horman 2018-04-18 13:48 ` Simon Horman 2018-04-19 6:40 ` Mylène Josserand 2018-04-19 6:40 ` Mylène Josserand 2018-04-17 2:15 ` [PATCH v6 00/11] Sunxi: Add SMP support on A83T Ondřej Jirman 2018-04-17 2:15 ` Ondřej Jirman 2018-04-17 2:15 ` Ondřej Jirman 2018-04-17 2:15 ` Ondřej Jirman 2018-04-18 5:50 ` Mylène Josserand 2018-04-18 5:50 ` Mylène Josserand
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