* [PATCH] drm/i915/psr: vbt change for psr @ 2018-04-19 7:42 vathsala nagaraju 2018-04-19 8:08 ` ✓ Fi.CI.BAT: success for drm/i915/psr: vbt change for psr (rev3) Patchwork ` (2 more replies) 0 siblings, 3 replies; 6+ messages in thread From: vathsala nagaraju @ 2018-04-19 7:42 UTC (permalink / raw) To: rodrigo.vivi, jani.nikula, intel-gfx Cc: Puthikorn Voravootivat, Maulik V Vaghela From: Vathsala Nagaraju <vathsala.nagaraju@intel.com> For psr block #9, the vbt description has moved to options [0-3] for TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt structure. Since spec does not mention from which VBT version this change was added to vbt.bsf file, we cannot depend on bdb->version check to change for all the platforms. There is RCR inplace for GOP team to provide the version number to make generic change. Since Kabylake with bdb version 209 is having this change, limiting this change to kbl and version 209+ to unblock google. Tested on skl(bdb version 203,without options) and kabylake(bdb version 209,212) having new options. bspec 20131 v2: (Jani and Rodrigo) move the 165 version check to intel_bios.c v3: Jani move the abstraction to intel_bios Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> CC: Puthikorn Voravootivat <puthik@chromium.org> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> --- drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/intel_psr.c | 26 ++++++++++++------------- 2 files changed, 50 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 702d3fa..8913dc8 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, } } +static bool +is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) +{ + if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) + return true; + else + return false; +} + static void parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) { @@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, DRM_DEBUG_KMS("No PSR BDB found.\n"); return; } - psr_table = &psr->psr_table[panel_type]; dev_priv->vbt.psr.full_link = psr_table->full_link; @@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, break; } - dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; - dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; + /* new psr options old decimal value interpretation + * 0 [500 us] > 1 [500 us ] + * 1 [100 us] > 0 [100 us ] + * 2 [2.5 ms] > 5 [2.5 ms ] + * 3 [0 us] = 0 [0 us ] + */ + if (!is_psr_options(dev_priv, bdb)) { + if (psr_table->tp1_wakeup_time > 5) + dev_priv->vbt.psr.tp1_wakeup_time = 2; + else if (psr_table->tp1_wakeup_time > 1) + dev_priv->vbt.psr.tp1_wakeup_time = 0; + else if (psr_table->tp1_wakeup_time > 0) + dev_priv->vbt.psr.tp1_wakeup_time = 1; + else + dev_priv->vbt.psr.tp1_wakeup_time = 3; + + if (psr_table->tp2_tp3_wakeup_time > 5) + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2; + else if (psr_table->tp2_tp3_wakeup_time > 1) + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0; + else if (psr_table->tp1_wakeup_time > 0) + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1; + else + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3; + } else { + dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; + dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; + } } static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 69a5b27..95658ad 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) if (dev_priv->psr.link_standby) val |= EDP_PSR_LINK_STANDBY; - if (dev_priv->vbt.psr.tp1_wakeup_time > 5) - val |= EDP_PSR_TP1_TIME_2500us; - else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) + if (dev_priv->vbt.psr.tp1_wakeup_time == 0) val |= EDP_PSR_TP1_TIME_500us; - else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) + else if (dev_priv->vbt.psr.tp1_wakeup_time == 1) val |= EDP_PSR_TP1_TIME_100us; + else if (dev_priv->vbt.psr.tp1_wakeup_time == 2) + val |= EDP_PSR_TP1_TIME_2500us; else val |= EDP_PSR_TP1_TIME_0us; - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) - val |= EDP_PSR_TP2_TP3_TIME_2500us; - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) - val |= EDP_PSR_TP2_TP3_TIME_500us; - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) + val |= EDP_PSR_TP2_TP3_TIME_500us; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) val |= EDP_PSR_TP2_TP3_TIME_100us; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) + val |= EDP_PSR_TP2_TP3_TIME_2500us; else val |= EDP_PSR_TP2_TP3_TIME_0us; @@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) - val |= EDP_PSR2_TP2_TIME_2500; - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) val |= EDP_PSR2_TP2_TIME_500; - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) val |= EDP_PSR2_TP2_TIME_100; + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) + val |= EDP_PSR2_TP2_TIME_2500; else val |= EDP_PSR2_TP2_TIME_50; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: vbt change for psr (rev3) 2018-04-19 7:42 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju @ 2018-04-19 8:08 ` Patchwork 2018-04-19 9:13 ` ✓ Fi.CI.IGT: " Patchwork 2018-04-19 13:35 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-04-19 8:08 UTC (permalink / raw) To: vathsala nagaraju; +Cc: intel-gfx == Series Details == Series: drm/i915/psr: vbt change for psr (rev3) URL : https://patchwork.freedesktop.org/series/41289/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4067 -> Patchwork_8746 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/41289/revisions/3/mbox/ == Known issues == Here are the changes found in Patchwork_8746 that come from known issues: === IGT changes === ==== Issues hit ==== igt@debugfs_test@read_all_entries: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@gem_exec_suspend@basic-s3: fi-ivb-3520m: PASS -> DMESG-WARN (fdo#106084) +1 igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#103928) ==== Possible fixes ==== igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-ivb-3520m: DMESG-WARN (fdo#106084) -> PASS fi-skl-guc: FAIL (fdo#103191) -> PASS fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084 == Participating hosts (34 -> 30) == Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-bxt-dsi fi-skl-6700hq == Build changes == * Linux: CI_DRM_4067 -> Patchwork_8746 CI_DRM_4067: 1c7ccdf37b04bedb10e2191d34dfbba62beb79ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4441: 83ba5b7d3bde48b383df41792fc9c955a5a23bdb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_8746: ba3c1f70aef21b925872e3da8e35ec82edfe72a0 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4441: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit == Linux commits == ba3c1f70aef2 drm/i915/psr: vbt change for psr == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8746/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/psr: vbt change for psr (rev3) 2018-04-19 7:42 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju 2018-04-19 8:08 ` ✓ Fi.CI.BAT: success for drm/i915/psr: vbt change for psr (rev3) Patchwork @ 2018-04-19 9:13 ` Patchwork 2018-04-19 13:35 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula 2 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-04-19 9:13 UTC (permalink / raw) To: vathsala nagaraju; +Cc: intel-gfx == Series Details == Series: drm/i915/psr: vbt change for psr (rev3) URL : https://patchwork.freedesktop.org/series/41289/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4067_full -> Patchwork_8746_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_8746_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_8746_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/41289/revisions/3/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_8746_full: === IGT changes === ==== Warnings ==== igt@gem_exec_schedule@deep-bsd1: shard-kbl: PASS -> SKIP igt@gem_exec_schedule@deep-bsd2: shard-kbl: SKIP -> PASS +3 == Known issues == Here are the changes found in Patchwork_8746_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_suspend@forcewake: shard-kbl: PASS -> INCOMPLETE (fdo#103665) igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665) igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-hsw: PASS -> FAIL (fdo#103928) igt@kms_rotation_crc@primary-rotation-180: shard-hsw: PASS -> FAIL (fdo#103925) igt@kms_sysfs_edid_timing: shard-apl: PASS -> WARN (fdo#100047) igt@kms_vblank@pipe-c-accuracy-idle: shard-hsw: PASS -> FAIL (fdo#102583) ==== Possible fixes ==== igt@kms_flip@wf_vblank-ts-check-interruptible: shard-apl: FAIL (fdo#100368) -> PASS fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 == Participating hosts (6 -> 4) == Missing (2): shard-glk shard-glkb == Build changes == * Linux: CI_DRM_4067 -> Patchwork_8746 CI_DRM_4067: 1c7ccdf37b04bedb10e2191d34dfbba62beb79ea @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4441: 83ba5b7d3bde48b383df41792fc9c955a5a23bdb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_8746: ba3c1f70aef21b925872e3da8e35ec82edfe72a0 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4441: e60d247eb359f044caf0c09904da14e39d7adca1 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8746/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/psr: vbt change for psr 2018-04-19 7:42 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju 2018-04-19 8:08 ` ✓ Fi.CI.BAT: success for drm/i915/psr: vbt change for psr (rev3) Patchwork 2018-04-19 9:13 ` ✓ Fi.CI.IGT: " Patchwork @ 2018-04-19 13:35 ` Jani Nikula 2018-04-20 6:30 ` vathsala nagaraju 2 siblings, 1 reply; 6+ messages in thread From: Jani Nikula @ 2018-04-19 13:35 UTC (permalink / raw) To: vathsala nagaraju, rodrigo.vivi, intel-gfx Cc: Puthikorn Voravootivat, Maulik V Vaghela On Thu, 19 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote: > From: Vathsala Nagaraju <vathsala.nagaraju@intel.com> > > For psr block #9, the vbt description has moved to options [0-3] for > TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt > structure. Since spec does not mention from which VBT version this > change was added to vbt.bsf file, we cannot depend on bdb->version check > to change for all the platforms. > > There is RCR inplace for GOP team to provide the version number > to make generic change. Since Kabylake with bdb version 209 is having this > change, limiting this change to kbl and version 209+ to unblock google. This is an incredible mess. > Tested on skl(bdb version 203,without options) and > kabylake(bdb version 209,212) having new options. > > bspec 20131 > > v2: (Jani and Rodrigo) > move the 165 version check to intel_bios.c > v3: Jani > move the abstraction to intel_bios > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > CC: Puthikorn Voravootivat <puthik@chromium.org> > > Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> > --- > drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++--- > drivers/gpu/drm/i915/intel_psr.c | 26 ++++++++++++------------- > 2 files changed, 50 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c > index 702d3fa..8913dc8 100644 > --- a/drivers/gpu/drm/i915/intel_bios.c > +++ b/drivers/gpu/drm/i915/intel_bios.c > @@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, > } > } > > +static bool > +is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) > +{ > + if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) > + return true; > + else > + return false; > +} > + > static void > parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) > { > @@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, > DRM_DEBUG_KMS("No PSR BDB found.\n"); > return; > } > - > psr_table = &psr->psr_table[panel_type]; > > dev_priv->vbt.psr.full_link = psr_table->full_link; > @@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, > break; > } > > - dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; > - dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; > + /* new psr options old decimal value interpretation > + * 0 [500 us] > 1 [500 us ] > + * 1 [100 us] > 0 [100 us ] > + * 2 [2.5 ms] > 5 [2.5 ms ] > + * 3 [0 us] = 0 [0 us ] The old decimal value stuff was wake up time in multiples of 100 us. > + */ > + if (!is_psr_options(dev_priv, bdb)) { You only use is_psr_options here once, please just open code the condition. Also reverse order to not need !something in the condition. > + if (psr_table->tp1_wakeup_time > 5) > + dev_priv->vbt.psr.tp1_wakeup_time = 2; > + else if (psr_table->tp1_wakeup_time > 1) > + dev_priv->vbt.psr.tp1_wakeup_time = 0; > + else if (psr_table->tp1_wakeup_time > 0) > + dev_priv->vbt.psr.tp1_wakeup_time = 1; > + else > + dev_priv->vbt.psr.tp1_wakeup_time = 3; > + > + if (psr_table->tp2_tp3_wakeup_time > 5) > + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2; > + else if (psr_table->tp2_tp3_wakeup_time > 1) > + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0; > + else if (psr_table->tp1_wakeup_time > 0) > + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1; > + else > + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3; > + } else { > + dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; > + dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; > + } > } Please rename dev_priv->vbt.psr tp1_wakeup_time and tp2_tp3_wakeup_time to have _us suffix, and actually assign the wakeup time in us there. Hide all the hideous, hideous VBT stuff behind that, and doesn't use magic numbers all over the place. The old format becomes wakeup_time_us = vbt_value * 100. The code should handle mismatches between the value and what the hardware can do (see below). The new format should just be a switch-case mapping values to us, whining about values other than 0..3 and defaulting to max in that case. > > static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv, > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 69a5b27..95658ad 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) > if (dev_priv->psr.link_standby) > val |= EDP_PSR_LINK_STANDBY; > > - if (dev_priv->vbt.psr.tp1_wakeup_time > 5) > - val |= EDP_PSR_TP1_TIME_2500us; > - else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) > + if (dev_priv->vbt.psr.tp1_wakeup_time == 0) > val |= EDP_PSR_TP1_TIME_500us; > - else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) > + else if (dev_priv->vbt.psr.tp1_wakeup_time == 1) > val |= EDP_PSR_TP1_TIME_100us; > + else if (dev_priv->vbt.psr.tp1_wakeup_time == 2) > + val |= EDP_PSR_TP1_TIME_2500us; > else > val |= EDP_PSR_TP1_TIME_0us; > > - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) > - val |= EDP_PSR_TP2_TP3_TIME_2500us; > - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) > - val |= EDP_PSR_TP2_TP3_TIME_500us; > - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) > + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) > + val |= EDP_PSR_TP2_TP3_TIME_500us; > + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) > val |= EDP_PSR_TP2_TP3_TIME_100us; > + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) > + val |= EDP_PSR_TP2_TP3_TIME_2500us; > else > val |= EDP_PSR_TP2_TP3_TIME_0us; Rewrite these to round up the longer wait: if (wakeup_time_us == 0) val |= EDP_PSR_TP2_TP3_TIME_0us; else if (wakeup_time_us <= 100) val |= EDP_PSR_TP2_TP3_TIME_100us; else if (wakeup_time_us <= 500) val |= EDP_PSR_TP2_TP3_TIME_500us; else val |= EDP_PSR_TP2_TP3_TIME_2500us; > > @@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > > val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); > > - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) > - val |= EDP_PSR2_TP2_TIME_2500; > - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) > + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) > val |= EDP_PSR2_TP2_TIME_500; > - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) > + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) > val |= EDP_PSR2_TP2_TIME_100; > + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) > + val |= EDP_PSR2_TP2_TIME_2500; > else > val |= EDP_PSR2_TP2_TIME_50; Same here. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/psr: vbt change for psr 2018-04-19 13:35 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula @ 2018-04-20 6:30 ` vathsala nagaraju 2018-04-27 7:52 ` Jani Nikula 0 siblings, 1 reply; 6+ messages in thread From: vathsala nagaraju @ 2018-04-20 6:30 UTC (permalink / raw) To: Jani Nikula, rodrigo.vivi, intel-gfx Cc: Puthikorn Voravootivat, Maulik V Vaghela On Thursday 19 April 2018 07:05 PM, Jani Nikula wrote: > On Thu, 19 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote: >> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com> >> >> For psr block #9, the vbt description has moved to options [0-3] for >> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt >> structure. Since spec does not mention from which VBT version this >> change was added to vbt.bsf file, we cannot depend on bdb->version check >> to change for all the platforms. >> >> There is RCR inplace for GOP team to provide the version number >> to make generic change. Since Kabylake with bdb version 209 is having this >> change, limiting this change to kbl and version 209+ to unblock google. > This is an incredible mess. > >> Tested on skl(bdb version 203,without options) and >> kabylake(bdb version 209,212) having new options. >> >> bspec 20131 >> >> v2: (Jani and Rodrigo) >> move the 165 version check to intel_bios.c >> v3: Jani >> move the abstraction to intel_bios >> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >> CC: Puthikorn Voravootivat <puthik@chromium.org> >> >> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> >> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> >> --- >> drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++--- >> drivers/gpu/drm/i915/intel_psr.c | 26 ++++++++++++------------- >> 2 files changed, 50 insertions(+), 16 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c >> index 702d3fa..8913dc8 100644 >> --- a/drivers/gpu/drm/i915/intel_bios.c >> +++ b/drivers/gpu/drm/i915/intel_bios.c >> @@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, >> } >> } >> >> +static bool >> +is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) >> +{ >> + if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) >> + return true; >> + else >> + return false; >> +} >> + >> static void >> parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) >> { >> @@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, >> DRM_DEBUG_KMS("No PSR BDB found.\n"); >> return; >> } >> - >> psr_table = &psr->psr_table[panel_type]; >> >> dev_priv->vbt.psr.full_link = psr_table->full_link; >> @@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, >> break; >> } >> >> - dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; >> - dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; >> + /* new psr options old decimal value interpretation >> + * 0 [500 us] > 1 [500 us ] >> + * 1 [100 us] > 0 [100 us ] >> + * 2 [2.5 ms] > 5 [2.5 ms ] >> + * 3 [0 us] = 0 [0 us ] > The old decimal value stuff was wake up time in multiples of 100 us. > >> + */ >> + if (!is_psr_options(dev_priv, bdb)) { > You only use is_psr_options here once, please just open code the > condition. Also reverse order to not need !something in the condition. > >> + if (psr_table->tp1_wakeup_time > 5) >> + dev_priv->vbt.psr.tp1_wakeup_time = 2; >> + else if (psr_table->tp1_wakeup_time > 1) >> + dev_priv->vbt.psr.tp1_wakeup_time = 0; >> + else if (psr_table->tp1_wakeup_time > 0) >> + dev_priv->vbt.psr.tp1_wakeup_time = 1; >> + else >> + dev_priv->vbt.psr.tp1_wakeup_time = 3; >> + >> + if (psr_table->tp2_tp3_wakeup_time > 5) >> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2; >> + else if (psr_table->tp2_tp3_wakeup_time > 1) >> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0; >> + else if (psr_table->tp1_wakeup_time > 0) >> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1; >> + else >> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3; >> + } else { >> + dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; >> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; >> + } >> } > Please rename dev_priv->vbt.psr tp1_wakeup_time and tp2_tp3_wakeup_time > to have _us suffix, and actually assign the wakeup time in us > there. Hide all the hideous, hideous VBT stuff behind that, and doesn't > use magic numbers all over the place. > > The old format becomes wakeup_time_us = vbt_value * 100. The code should > handle mismatches between the value and what the hardware can do (see > below). > > The new format should just be a switch-case mapping values to us, > whining about values other than 0..3 and defaulting to max in that case. if we don't set anything in SRD_CTL/PSR2_CTL reg for those bits , by default it's 0 [which is 500 us] instead of defaulting to max value which is 3[0us], should we just default to 0[500us] >> >> static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv, >> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c >> index 69a5b27..95658ad 100644 >> --- a/drivers/gpu/drm/i915/intel_psr.c >> +++ b/drivers/gpu/drm/i915/intel_psr.c >> @@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) >> if (dev_priv->psr.link_standby) >> val |= EDP_PSR_LINK_STANDBY; >> >> - if (dev_priv->vbt.psr.tp1_wakeup_time > 5) >> - val |= EDP_PSR_TP1_TIME_2500us; >> - else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) >> + if (dev_priv->vbt.psr.tp1_wakeup_time == 0) >> val |= EDP_PSR_TP1_TIME_500us; >> - else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) >> + else if (dev_priv->vbt.psr.tp1_wakeup_time == 1) >> val |= EDP_PSR_TP1_TIME_100us; >> + else if (dev_priv->vbt.psr.tp1_wakeup_time == 2) >> + val |= EDP_PSR_TP1_TIME_2500us; >> else >> val |= EDP_PSR_TP1_TIME_0us; >> >> - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) >> - val |= EDP_PSR_TP2_TP3_TIME_2500us; >> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) >> - val |= EDP_PSR_TP2_TP3_TIME_500us; >> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) >> + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) >> + val |= EDP_PSR_TP2_TP3_TIME_500us; >> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) >> val |= EDP_PSR_TP2_TP3_TIME_100us; >> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) >> + val |= EDP_PSR_TP2_TP3_TIME_2500us; >> else >> val |= EDP_PSR_TP2_TP3_TIME_0us; > Rewrite these to round up the longer wait: > > if (wakeup_time_us == 0) > val |= EDP_PSR_TP2_TP3_TIME_0us; > else if (wakeup_time_us <= 100) > val |= EDP_PSR_TP2_TP3_TIME_100us; > else if (wakeup_time_us <= 500) > val |= EDP_PSR_TP2_TP3_TIME_500us; > else > val |= EDP_PSR_TP2_TP3_TIME_2500us; > >> >> @@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) >> >> val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); >> >> - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) >> - val |= EDP_PSR2_TP2_TIME_2500; >> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) >> + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) >> val |= EDP_PSR2_TP2_TIME_500; >> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) >> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) >> val |= EDP_PSR2_TP2_TIME_100; >> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) >> + val |= EDP_PSR2_TP2_TIME_2500; >> else >> val |= EDP_PSR2_TP2_TIME_50; > Same here. > > BR, > Jani. > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915/psr: vbt change for psr 2018-04-20 6:30 ` vathsala nagaraju @ 2018-04-27 7:52 ` Jani Nikula 0 siblings, 0 replies; 6+ messages in thread From: Jani Nikula @ 2018-04-27 7:52 UTC (permalink / raw) To: vathsala nagaraju, rodrigo.vivi, intel-gfx Cc: Puthikorn Voravootivat, Maulik V Vaghela On Fri, 20 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote: > On Thursday 19 April 2018 07:05 PM, Jani Nikula wrote: >> On Thu, 19 Apr 2018, vathsala nagaraju <vathsala.nagaraju@intel.com> wrote: >>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com> >>> >>> For psr block #9, the vbt description has moved to options [0-3] for >>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt >>> structure. Since spec does not mention from which VBT version this >>> change was added to vbt.bsf file, we cannot depend on bdb->version check >>> to change for all the platforms. >>> >>> There is RCR inplace for GOP team to provide the version number >>> to make generic change. Since Kabylake with bdb version 209 is having this >>> change, limiting this change to kbl and version 209+ to unblock google. >> This is an incredible mess. >> >>> Tested on skl(bdb version 203,without options) and >>> kabylake(bdb version 209,212) having new options. >>> >>> bspec 20131 >>> >>> v2: (Jani and Rodrigo) >>> move the 165 version check to intel_bios.c >>> v3: Jani >>> move the abstraction to intel_bios >>> >>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> >>> CC: Puthikorn Voravootivat <puthik@chromium.org> >>> >>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> >>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> >>> --- >>> drivers/gpu/drm/i915/intel_bios.c | 40 ++++++++++++++++++++++++++++++++++++--- >>> drivers/gpu/drm/i915/intel_psr.c | 26 ++++++++++++------------- >>> 2 files changed, 50 insertions(+), 16 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c >>> index 702d3fa..8913dc8 100644 >>> --- a/drivers/gpu/drm/i915/intel_bios.c >>> +++ b/drivers/gpu/drm/i915/intel_bios.c >>> @@ -646,6 +646,15 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, >>> } >>> } >>> >>> +static bool >>> +is_psr_options(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) >>> +{ >>> + if (bdb->version >= 209 && IS_KABYLAKE(dev_priv)) >>> + return true; >>> + else >>> + return false; >>> +} >>> + >>> static void >>> parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) >>> { >>> @@ -658,7 +667,6 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, >>> DRM_DEBUG_KMS("No PSR BDB found.\n"); >>> return; >>> } >>> - >>> psr_table = &psr->psr_table[panel_type]; >>> >>> dev_priv->vbt.psr.full_link = psr_table->full_link; >>> @@ -687,8 +695,34 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, >>> break; >>> } >>> >>> - dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; >>> - dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; >>> + /* new psr options old decimal value interpretation >>> + * 0 [500 us] > 1 [500 us ] >>> + * 1 [100 us] > 0 [100 us ] >>> + * 2 [2.5 ms] > 5 [2.5 ms ] >>> + * 3 [0 us] = 0 [0 us ] >> The old decimal value stuff was wake up time in multiples of 100 us. >> >>> + */ >>> + if (!is_psr_options(dev_priv, bdb)) { >> You only use is_psr_options here once, please just open code the >> condition. Also reverse order to not need !something in the condition. >> >>> + if (psr_table->tp1_wakeup_time > 5) >>> + dev_priv->vbt.psr.tp1_wakeup_time = 2; >>> + else if (psr_table->tp1_wakeup_time > 1) >>> + dev_priv->vbt.psr.tp1_wakeup_time = 0; >>> + else if (psr_table->tp1_wakeup_time > 0) >>> + dev_priv->vbt.psr.tp1_wakeup_time = 1; >>> + else >>> + dev_priv->vbt.psr.tp1_wakeup_time = 3; >>> + >>> + if (psr_table->tp2_tp3_wakeup_time > 5) >>> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 2; >>> + else if (psr_table->tp2_tp3_wakeup_time > 1) >>> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 0; >>> + else if (psr_table->tp1_wakeup_time > 0) >>> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 1; >>> + else >>> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = 3; >>> + } else { >>> + dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; >>> + dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; >>> + } >>> } >> Please rename dev_priv->vbt.psr tp1_wakeup_time and tp2_tp3_wakeup_time >> to have _us suffix, and actually assign the wakeup time in us >> there. Hide all the hideous, hideous VBT stuff behind that, and doesn't >> use magic numbers all over the place. >> >> The old format becomes wakeup_time_us = vbt_value * 100. The code should >> handle mismatches between the value and what the hardware can do (see >> below). >> >> The new format should just be a switch-case mapping values to us, >> whining about values other than 0..3 and defaulting to max in that case. > if we don't set anything in SRD_CTL/PSR2_CTL reg for those bits , by > default it's 0 [which is 500 us] > instead of defaulting to max value which is 3[0us], should we just > default to 0[500us] Like I said, if we think the VBT has the new format, and it has values in range 0..3, map those to corresponding delays in us. 0 -> 500 us, 1 -> 100 us, 2 -> 2500 us, 3 -> 0 us. If the value is not in range 0..3, *then* default to max i.e. 2500 us. BR, Jani. >>> >>> static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv, >>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c >>> index 69a5b27..95658ad 100644 >>> --- a/drivers/gpu/drm/i915/intel_psr.c >>> +++ b/drivers/gpu/drm/i915/intel_psr.c >>> @@ -353,21 +353,21 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) >>> if (dev_priv->psr.link_standby) >>> val |= EDP_PSR_LINK_STANDBY; >>> >>> - if (dev_priv->vbt.psr.tp1_wakeup_time > 5) >>> - val |= EDP_PSR_TP1_TIME_2500us; >>> - else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) >>> + if (dev_priv->vbt.psr.tp1_wakeup_time == 0) >>> val |= EDP_PSR_TP1_TIME_500us; >>> - else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) >>> + else if (dev_priv->vbt.psr.tp1_wakeup_time == 1) >>> val |= EDP_PSR_TP1_TIME_100us; >>> + else if (dev_priv->vbt.psr.tp1_wakeup_time == 2) >>> + val |= EDP_PSR_TP1_TIME_2500us; >>> else >>> val |= EDP_PSR_TP1_TIME_0us; >>> >>> - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) >>> - val |= EDP_PSR_TP2_TP3_TIME_2500us; >>> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) >>> - val |= EDP_PSR_TP2_TP3_TIME_500us; >>> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) >>> + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) >>> + val |= EDP_PSR_TP2_TP3_TIME_500us; >>> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) >>> val |= EDP_PSR_TP2_TP3_TIME_100us; >>> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) >>> + val |= EDP_PSR_TP2_TP3_TIME_2500us; >>> else >>> val |= EDP_PSR_TP2_TP3_TIME_0us; >> Rewrite these to round up the longer wait: >> >> if (wakeup_time_us == 0) >> val |= EDP_PSR_TP2_TP3_TIME_0us; >> else if (wakeup_time_us <= 100) >> val |= EDP_PSR_TP2_TP3_TIME_100us; >> else if (wakeup_time_us <= 500) >> val |= EDP_PSR_TP2_TP3_TIME_500us; >> else >> val |= EDP_PSR_TP2_TP3_TIME_2500us; >> >>> >>> @@ -406,12 +406,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) >>> >>> val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); >>> >>> - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) >>> - val |= EDP_PSR2_TP2_TIME_2500; >>> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) >>> + if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0) >>> val |= EDP_PSR2_TP2_TIME_500; >>> - else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) >>> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1) >>> val |= EDP_PSR2_TP2_TIME_100; >>> + else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2) >>> + val |= EDP_PSR2_TP2_TIME_2500; >>> else >>> val |= EDP_PSR2_TP2_TIME_50; >> Same here. >> >> BR, >> Jani. >> > -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-04-27 7:52 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-04-19 7:42 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju 2018-04-19 8:08 ` ✓ Fi.CI.BAT: success for drm/i915/psr: vbt change for psr (rev3) Patchwork 2018-04-19 9:13 ` ✓ Fi.CI.IGT: " Patchwork 2018-04-19 13:35 ` [PATCH] drm/i915/psr: vbt change for psr Jani Nikula 2018-04-20 6:30 ` vathsala nagaraju 2018-04-27 7:52 ` Jani Nikula
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