* [PATCH 0/3] Add R8A77980/Condor PFC support
@ 2018-03-09 12:04 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:04 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Hello!
Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
These patches depend on the R8A77980 PFC support in order to work properly.
[1/3] arm64: dts: renesas: r8a77980: add PFC support
[2/3] arm64: dts: renesas: condor: add SCIF0 pins
[3/3] arm64: dts: renesas: condor: add EtherAVB pins
WBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 0/3] Add R8A77980/Condor PFC support
@ 2018-03-09 12:04 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:04 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Hello!
Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
These patches depend on the R8A77980 PFC support in order to work properly.
[1/3] arm64: dts: renesas: r8a77980: add PFC support
[2/3] arm64: dts: renesas: condor: add SCIF0 pins
[3/3] arm64: dts: renesas: condor: add EtherAVB pins
WBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 0/3] Add R8A77980/Condor PFC support
@ 2018-03-09 12:04 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:04 UTC (permalink / raw)
To: linux-arm-kernel
Hello!
Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
These patches depend on the R8A77980 PFC support in order to work properly.
[1/3] arm64: dts: renesas: r8a77980: add PFC support
[2/3] arm64: dts: renesas: condor: add SCIF0 pins
[3/3] arm64: dts: renesas: condor: add EtherAVB pins
WBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 1/3] arm64: dts: renesas: r8a77980: add PFC support
2018-03-09 12:04 ` Sergei Shtylyov
(?)
@ 2018-03-09 12:06 ` Sergei Shtylyov
-1 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:06 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Define the generic R8A77980 part of the PFC device node.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 5 +++++
1 file changed, 5 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -71,6 +71,11 @@
#size-cells = <2>;
ranges;
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a77980";
+ reg = <0 0xe6060000 0 0x50c>;
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77980-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 1/3] arm64: dts: renesas: r8a77980: add PFC support
@ 2018-03-09 12:06 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:06 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Define the generic R8A77980 part of the PFC device node.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 5 +++++
1 file changed, 5 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -71,6 +71,11 @@
#size-cells = <2>;
ranges;
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a77980";
+ reg = <0 0xe6060000 0 0x50c>;
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77980-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 1/3] arm64: dts: renesas: r8a77980: add PFC support
@ 2018-03-09 12:06 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:06 UTC (permalink / raw)
To: linux-arm-kernel
Define the generic R8A77980 part of the PFC device node.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 5 +++++
1 file changed, 5 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -71,6 +71,11 @@
#size-cells = <2>;
ranges;
+ pfc: pin-controller at e6060000 {
+ compatible = "renesas,pfc-r8a77980";
+ reg = <0 0xe6060000 0 0x50c>;
+ };
+
cpg: clock-controller at e6150000 {
compatible = "renesas,r8a77980-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 2/3] arm64: dts: renesas: condor: add SCIF0 pins
2018-03-09 12:04 ` Sergei Shtylyov
(?)
@ 2018-03-09 12:07 ` Sergei Shtylyov
-1 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:07 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Add the (previously omitted) SCIF0 pin data to the Condor board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -49,7 +49,22 @@
clock-frequency = <32768>;
};
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
+};
+
&scif0 {
+ pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 2/3] arm64: dts: renesas: condor: add SCIF0 pins
@ 2018-03-09 12:07 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:07 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Add the (previously omitted) SCIF0 pin data to the Condor board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -49,7 +49,22 @@
clock-frequency = <32768>;
};
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
+};
+
&scif0 {
+ pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 2/3] arm64: dts: renesas: condor: add SCIF0 pins
@ 2018-03-09 12:07 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:07 UTC (permalink / raw)
To: linux-arm-kernel
Add the (previously omitted) SCIF0 pin data to the Condor board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -49,7 +49,22 @@
clock-frequency = <32768>;
};
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
+};
+
&scif0 {
+ pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins
2018-03-09 12:04 ` Sergei Shtylyov
(?)
@ 2018-03-09 12:09 ` Sergei Shtylyov
-1 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:09 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Add the (previously omitted) EtherAVB pin data to the Condor board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 8 ++++++++
1 file changed, 8 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -30,6 +30,9 @@
};
&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
@@ -50,6 +53,11 @@
};
&pfc {
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_rgmii";
+ function = "avb";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins
@ 2018-03-09 12:09 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:09 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
Add the (previously omitted) EtherAVB pin data to the Condor board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 8 ++++++++
1 file changed, 8 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -30,6 +30,9 @@
};
&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
@@ -50,6 +53,11 @@
};
&pfc {
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_rgmii";
+ function = "avb";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins
@ 2018-03-09 12:09 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 12:09 UTC (permalink / raw)
To: linux-arm-kernel
Add the (previously omitted) EtherAVB pin data to the Condor board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 8 ++++++++
1 file changed, 8 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -30,6 +30,9 @@
};
&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
@@ -50,6 +53,11 @@
};
&pfc {
+ avb_pins: avb {
+ groups = "avb_mdio", "avb_rgmii";
+ function = "avb";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 1/3] arm64: dts: renesas: r8a77980: add PFC support
2018-03-09 12:06 ` Sergei Shtylyov
(?)
@ 2018-03-09 12:36 ` Geert Uytterhoeven
-1 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2018-03-09 12:36 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, Linux ARM
On Fri, Mar 9, 2018 at 1:06 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the generic R8A77980 part of the PFC device node.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -71,6 +71,11 @@
> #size-cells = <2>;
> ranges;
>
> + pfc: pin-controller@e6060000 {
> + compatible = "renesas,pfc-r8a77980";
> + reg = <0 0xe6060000 0 0x50c>;
0x50c is an odd number, given the last register is at offset 0x500, just like
on V3M ;-)
> + };
> +
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 1/3] arm64: dts: renesas: r8a77980: add PFC support
@ 2018-03-09 12:36 ` Geert Uytterhoeven
0 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2018-03-09 12:36 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland, Linux ARM
On Fri, Mar 9, 2018 at 1:06 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the generic R8A77980 part of the PFC device node.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -71,6 +71,11 @@
> #size-cells = <2>;
> ranges;
>
> + pfc: pin-controller@e6060000 {
> + compatible = "renesas,pfc-r8a77980";
> + reg = <0 0xe6060000 0 0x50c>;
0x50c is an odd number, given the last register is at offset 0x500, just like
on V3M ;-)
> + };
> +
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 1/3] arm64: dts: renesas: r8a77980: add PFC support
@ 2018-03-09 12:36 ` Geert Uytterhoeven
0 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2018-03-09 12:36 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Mar 9, 2018 at 1:06 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the generic R8A77980 part of the PFC device node.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -71,6 +71,11 @@
> #size-cells = <2>;
> ranges;
>
> + pfc: pin-controller at e6060000 {
> + compatible = "renesas,pfc-r8a77980";
> + reg = <0 0xe6060000 0 0x50c>;
0x50c is an odd number, given the last register is at offset 0x500, just like
on V3M ;-)
> + };
> +
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 2/3] arm64: dts: renesas: condor: add SCIF0 pins
2018-03-09 12:07 ` Sergei Shtylyov
(?)
@ 2018-03-09 12:39 ` Geert Uytterhoeven
-1 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2018-03-09 12:39 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, Linux ARM
Hi Sergei,
On Fri, Mar 9, 2018 at 1:07 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the (previously omitted) SCIF0 pin data to the Condor board's
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 2/3] arm64: dts: renesas: condor: add SCIF0 pins
@ 2018-03-09 12:39 ` Geert Uytterhoeven
0 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2018-03-09 12:39 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland, Linux ARM
Hi Sergei,
On Fri, Mar 9, 2018 at 1:07 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the (previously omitted) SCIF0 pin data to the Condor board's
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 2/3] arm64: dts: renesas: condor: add SCIF0 pins
@ 2018-03-09 12:39 ` Geert Uytterhoeven
0 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2018-03-09 12:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sergei,
On Fri, Mar 9, 2018 at 1:07 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the (previously omitted) SCIF0 pin data to the Condor board's
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins
2018-03-09 12:09 ` Sergei Shtylyov
(?)
@ 2018-03-09 12:44 ` Geert Uytterhoeven
-1 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2018-03-09 12:44 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, Linux ARM
Hi Sergei,
On Fri, Mar 9, 2018 at 1:09 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the (previously omitted) EtherAVB pin data to the Condor board's
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
According to the Condor schematics, the KSZ9031RNXVB is wired to
GEther by default. So I guess you are using a modified board?
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -30,6 +30,9 @@
> };
>
> &avb {
> + pinctrl-0 = <&avb_pins>;
> + pinctrl-names = "default";
> +
> phy-mode = "rgmii-id";
> phy-handle = <&phy0>;
> renesas,no-ether-link;
> @@ -50,6 +53,11 @@
> };
>
> &pfc {
> + avb_pins: avb {
> + groups = "avb_mdio", "avb_rgmii";
> + function = "avb";
> + };
> +
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins
@ 2018-03-09 12:44 ` Geert Uytterhoeven
0 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2018-03-09 12:44 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland, Linux ARM
Hi Sergei,
On Fri, Mar 9, 2018 at 1:09 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the (previously omitted) EtherAVB pin data to the Condor board's
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
According to the Condor schematics, the KSZ9031RNXVB is wired to
GEther by default. So I guess you are using a modified board?
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -30,6 +30,9 @@
> };
>
> &avb {
> + pinctrl-0 = <&avb_pins>;
> + pinctrl-names = "default";
> +
> phy-mode = "rgmii-id";
> phy-handle = <&phy0>;
> renesas,no-ether-link;
> @@ -50,6 +53,11 @@
> };
>
> &pfc {
> + avb_pins: avb {
> + groups = "avb_mdio", "avb_rgmii";
> + function = "avb";
> + };
> +
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins
@ 2018-03-09 12:44 ` Geert Uytterhoeven
0 siblings, 0 replies; 33+ messages in thread
From: Geert Uytterhoeven @ 2018-03-09 12:44 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sergei,
On Fri, Mar 9, 2018 at 1:09 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the (previously omitted) EtherAVB pin data to the Condor board's
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
According to the Condor schematics, the KSZ9031RNXVB is wired to
GEther by default. So I guess you are using a modified board?
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -30,6 +30,9 @@
> };
>
> &avb {
> + pinctrl-0 = <&avb_pins>;
> + pinctrl-names = "default";
> +
> phy-mode = "rgmii-id";
> phy-handle = <&phy0>;
> renesas,no-ether-link;
> @@ -50,6 +53,11 @@
> };
>
> &pfc {
> + avb_pins: avb {
> + groups = "avb_mdio", "avb_rgmii";
> + function = "avb";
> + };
> +
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins
2018-03-09 12:44 ` Geert Uytterhoeven
(?)
@ 2018-03-09 17:26 ` Sergei Shtylyov
-1 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 17:26 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, Linux ARM
Hello!
On 03/09/2018 03:44 PM, Geert Uytterhoeven wrote:
>> Add the (previously omitted) EtherAVB pin data to the Condor board's
>> device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> According to the Condor schematics, the KSZ9031RNXVB is wired to
> GEther by default. So I guess you are using a modified board?
Artemy told me they haven't been able to bring up the GEther (due to wrong
base address?), so they resoldered the reisitors. He also told me there are now
versions of the board that wire the PHY to EtherAVB. Go figure...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins
@ 2018-03-09 17:26 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 17:26 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Mark Rutland, Linux ARM
Hello!
On 03/09/2018 03:44 PM, Geert Uytterhoeven wrote:
>> Add the (previously omitted) EtherAVB pin data to the Condor board's
>> device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> According to the Condor schematics, the KSZ9031RNXVB is wired to
> GEther by default. So I guess you are using a modified board?
Artemy told me they haven't been able to bring up the GEther (due to wrong
base address?), so they resoldered the reisitors. He also told me there are now
versions of the board that wire the PHY to EtherAVB. Go figure...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins
@ 2018-03-09 17:26 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-03-09 17:26 UTC (permalink / raw)
To: linux-arm-kernel
Hello!
On 03/09/2018 03:44 PM, Geert Uytterhoeven wrote:
>> Add the (previously omitted) EtherAVB pin data to the Condor board's
>> device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> According to the Condor schematics, the KSZ9031RNXVB is wired to
> GEther by default. So I guess you are using a modified board?
Artemy told me they haven't been able to bring up the GEther (due to wrong
base address?), so they resoldered the reisitors. He also told me there are now
versions of the board that wire the PHY to EtherAVB. Go figure...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 0/3] Add R8A77980/Condor PFC support
2018-03-09 12:04 ` Sergei Shtylyov
(?)
@ 2018-03-13 18:46 ` Simon Horman
-1 siblings, 0 replies; 33+ messages in thread
From: Simon Horman @ 2018-03-13 18:46 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Fri, Mar 09, 2018 at 03:04:56PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
> and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> These patches depend on the R8A77980 PFC support in order to work properly.
I have marked these patches as Deferred. Please repost or ping me
once the dependencies are in an RC release. If looser dependency handling
is appropriate please let me know.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 0/3] Add R8A77980/Condor PFC support
@ 2018-03-13 18:46 ` Simon Horman
0 siblings, 0 replies; 33+ messages in thread
From: Simon Horman @ 2018-03-13 18:46 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, Catalin Marinas, Will Deacon, linux-renesas-soc,
devicetree, Magnus Damm, Mark Rutland, linux-arm-kernel
On Fri, Mar 09, 2018 at 03:04:56PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
> and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> These patches depend on the R8A77980 PFC support in order to work properly.
I have marked these patches as Deferred. Please repost or ping me
once the dependencies are in an RC release. If looser dependency handling
is appropriate please let me know.
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 0/3] Add R8A77980/Condor PFC support
@ 2018-03-13 18:46 ` Simon Horman
0 siblings, 0 replies; 33+ messages in thread
From: Simon Horman @ 2018-03-13 18:46 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Mar 09, 2018 at 03:04:56PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
> and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> These patches depend on the R8A77980 PFC support in order to work properly.
I have marked these patches as Deferred. Please repost or ping me
once the dependencies are in an RC release. If looser dependency handling
is appropriate please let me know.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 0/3] Add R8A77980/Condor PFC support
2018-03-09 12:04 ` Sergei Shtylyov
(?)
@ 2018-04-20 17:33 ` Sergei Shtylyov
-1 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-04-20 17:33 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
On 03/09/2018 03:04 PM, Sergei Shtylyov wrote:
> Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
> and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> These patches depend on the R8A77980 PFC support in order to work properly.
... and their time has finally come! Please merge.
> [1/3] arm64: dts: renesas: r8a77980: add PFC support
> [2/3] arm64: dts: renesas: condor: add SCIF0 pins
> [3/3] arm64: dts: renesas: condor: add EtherAVB pins
WBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 0/3] Add R8A77980/Condor PFC support
@ 2018-04-20 17:33 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-04-20 17:33 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Magnus Damm, Mark Rutland, linux-arm-kernel
On 03/09/2018 03:04 PM, Sergei Shtylyov wrote:
> Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
> and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> These patches depend on the R8A77980 PFC support in order to work properly.
... and their time has finally come! Please merge.
> [1/3] arm64: dts: renesas: r8a77980: add PFC support
> [2/3] arm64: dts: renesas: condor: add SCIF0 pins
> [3/3] arm64: dts: renesas: condor: add EtherAVB pins
WBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 0/3] Add R8A77980/Condor PFC support
@ 2018-04-20 17:33 ` Sergei Shtylyov
0 siblings, 0 replies; 33+ messages in thread
From: Sergei Shtylyov @ 2018-04-20 17:33 UTC (permalink / raw)
To: linux-arm-kernel
On 03/09/2018 03:04 PM, Sergei Shtylyov wrote:
> Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
> and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> These patches depend on the R8A77980 PFC support in order to work properly.
... and their time has finally come! Please merge.
> [1/3] arm64: dts: renesas: r8a77980: add PFC support
> [2/3] arm64: dts: renesas: condor: add SCIF0 pins
> [3/3] arm64: dts: renesas: condor: add EtherAVB pins
WBR, Sergei
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 0/3] Add R8A77980/Condor PFC support
2018-04-20 17:33 ` Sergei Shtylyov
(?)
@ 2018-04-24 9:20 ` Simon Horman
-1 siblings, 0 replies; 33+ messages in thread
From: Simon Horman @ 2018-04-24 9:20 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Fri, Apr 20, 2018 at 08:33:20PM +0300, Sergei Shtylyov wrote:
> On 03/09/2018 03:04 PM, Sergei Shtylyov wrote:
>
> > Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> > 'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
> > and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> > These patches depend on the R8A77980 PFC support in order to work properly.
>
> ... and their time has finally come! Please merge.
>
> > [1/3] arm64: dts: renesas: r8a77980: add PFC support
> > [2/3] arm64: dts: renesas: condor: add SCIF0 pins
> > [3/3] arm64: dts: renesas: condor: add EtherAVB pins
Thanks, applied.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH 0/3] Add R8A77980/Condor PFC support
@ 2018-04-24 9:20 ` Simon Horman
0 siblings, 0 replies; 33+ messages in thread
From: Simon Horman @ 2018-04-24 9:20 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Rob Herring, Catalin Marinas, Will Deacon, linux-renesas-soc,
devicetree, Magnus Damm, Mark Rutland, linux-arm-kernel
On Fri, Apr 20, 2018 at 08:33:20PM +0300, Sergei Shtylyov wrote:
> On 03/09/2018 03:04 PM, Sergei Shtylyov wrote:
>
> > Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> > 'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
> > and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> > These patches depend on the R8A77980 PFC support in order to work properly.
>
> ... and their time has finally come! Please merge.
>
> > [1/3] arm64: dts: renesas: r8a77980: add PFC support
> > [2/3] arm64: dts: renesas: condor: add SCIF0 pins
> > [3/3] arm64: dts: renesas: condor: add EtherAVB pins
Thanks, applied.
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH 0/3] Add R8A77980/Condor PFC support
@ 2018-04-24 9:20 ` Simon Horman
0 siblings, 0 replies; 33+ messages in thread
From: Simon Horman @ 2018-04-24 9:20 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Apr 20, 2018 at 08:33:20PM +0300, Sergei Shtylyov wrote:
> On 03/09/2018 03:04 PM, Sergei Shtylyov wrote:
>
> > Here's the set of 3 patches against Simon Horman's 'renesas.git' repo's
> > 'renesas-devel-20180308-v4.16-rc4' tag. We're adding the R8A77980 PFC node
> > and then describing the pins for SCIF0 and EtherAVB devices declared earlier.
> > These patches depend on the R8A77980 PFC support in order to work properly.
>
> ... and their time has finally come! Please merge.
>
> > [1/3] arm64: dts: renesas: r8a77980: add PFC support
> > [2/3] arm64: dts: renesas: condor: add SCIF0 pins
> > [3/3] arm64: dts: renesas: condor: add EtherAVB pins
Thanks, applied.
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2018-04-24 9:20 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-09 12:04 [PATCH 0/3] Add R8A77980/Condor PFC support Sergei Shtylyov
2018-03-09 12:04 ` Sergei Shtylyov
2018-03-09 12:04 ` Sergei Shtylyov
2018-03-09 12:06 ` [PATCH 1/3] arm64: dts: renesas: r8a77980: add " Sergei Shtylyov
2018-03-09 12:06 ` Sergei Shtylyov
2018-03-09 12:06 ` Sergei Shtylyov
2018-03-09 12:36 ` Geert Uytterhoeven
2018-03-09 12:36 ` Geert Uytterhoeven
2018-03-09 12:36 ` Geert Uytterhoeven
2018-03-09 12:07 ` [PATCH 2/3] arm64: dts: renesas: condor: add SCIF0 pins Sergei Shtylyov
2018-03-09 12:07 ` Sergei Shtylyov
2018-03-09 12:07 ` Sergei Shtylyov
2018-03-09 12:39 ` Geert Uytterhoeven
2018-03-09 12:39 ` Geert Uytterhoeven
2018-03-09 12:39 ` Geert Uytterhoeven
2018-03-09 12:09 ` [PATCH 3/3] arm64: dts: renesas: condor: add EtherAVB pins Sergei Shtylyov
2018-03-09 12:09 ` Sergei Shtylyov
2018-03-09 12:09 ` Sergei Shtylyov
2018-03-09 12:44 ` Geert Uytterhoeven
2018-03-09 12:44 ` Geert Uytterhoeven
2018-03-09 12:44 ` Geert Uytterhoeven
2018-03-09 17:26 ` Sergei Shtylyov
2018-03-09 17:26 ` Sergei Shtylyov
2018-03-09 17:26 ` Sergei Shtylyov
2018-03-13 18:46 ` [PATCH 0/3] Add R8A77980/Condor PFC support Simon Horman
2018-03-13 18:46 ` Simon Horman
2018-03-13 18:46 ` Simon Horman
2018-04-20 17:33 ` Sergei Shtylyov
2018-04-20 17:33 ` Sergei Shtylyov
2018-04-20 17:33 ` Sergei Shtylyov
2018-04-24 9:20 ` Simon Horman
2018-04-24 9:20 ` Simon Horman
2018-04-24 9:20 ` Simon Horman
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