* [PATCH] perf vendor events intel: Fix double words "are are" in cache.json
@ 2018-04-24 15:02 Masanari Iida
2018-04-24 16:01 ` Andi Kleen
0 siblings, 1 reply; 2+ messages in thread
From: Masanari Iida @ 2018-04-24 15:02 UTC (permalink / raw)
To: linux-kernel, ak, acme, peterz, mingo; +Cc: Masanari Iida
This patch fix double words "are are".
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
---
tools/perf/pmu-events/arch/x86/silvermont/cache.json | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/perf/pmu-events/arch/x86/silvermont/cache.json
index 82be7d1b8b81..d961a8cb8215 100644
--- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json
+++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json
@@ -641,7 +641,7 @@
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"SampleAfterValue": "100007",
- "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
"Offcore": "1"
},
{
@@ -696,7 +696,7 @@
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING",
"MSRIndex": "0x1a6",
"SampleAfterValue": "100007",
- "BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "BriefDescription": "Counts demand and DCU prefetch RFOs that are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
"Offcore": "1"
},
{
@@ -751,7 +751,7 @@
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING",
"MSRIndex": "0x1a6",
"SampleAfterValue": "100007",
- "BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
+ "BriefDescription": "Counts demand and DCU prefetch data read that are outstanding, per cycle, from the time of the L2 miss to when any response is received.",
"Offcore": "1"
},
{
@@ -809,4 +809,4 @@
"BriefDescription": "Counts demand and DCU prefetch data read that have any response type.",
"Offcore": "1"
}
-]
\ No newline at end of file
+]
--
2.17.0.140.g0b0cc9f86731
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] perf vendor events intel: Fix double words "are are" in cache.json
2018-04-24 15:02 [PATCH] perf vendor events intel: Fix double words "are are" in cache.json Masanari Iida
@ 2018-04-24 16:01 ` Andi Kleen
0 siblings, 0 replies; 2+ messages in thread
From: Andi Kleen @ 2018-04-24 16:01 UTC (permalink / raw)
To: Masanari Iida; +Cc: linux-kernel, acme, peterz, mingo
On Wed, Apr 25, 2018 at 12:02:49AM +0900, Masanari Iida wrote:
> This patch fix double words "are are".
These files are auto generated from another source. I don't think
it makes much sense to do a lot of editing on the Linux copies.
I will pass it on to the owners of the original files.
-Andi
^ permalink raw reply [flat|nested] 2+ messages in thread
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2018-04-24 15:02 [PATCH] perf vendor events intel: Fix double words "are are" in cache.json Masanari Iida
2018-04-24 16:01 ` Andi Kleen
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