* [PATCH 1/4] ARM: dts: r8a77470: Add SYS-DMAC support
2018-04-20 15:27 [PATCH 0/4] Add SYS-DMAC, IRQC and SCIF to SoC dtsi Biju Das
@ 2018-04-20 15:27 ` Biju Das
2018-04-24 6:52 ` Simon Horman
2018-04-24 14:38 ` Geert Uytterhoeven
2018-04-20 15:27 ` [PATCH 2/4] ARM: dts: r8a77470: Add IRQC support Biju Das
` (2 subsequent siblings)
3 siblings, 2 replies; 18+ messages in thread
From: Biju Das @ 2018-04-20 15:27 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
Describe SYS-DMAC0/1 in the R8A77470 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a77470.dtsi | 66 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 4578582..c39aceb 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -104,6 +104,72 @@
reg = <0 0xe6300000 0 0x20000>;
};
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a77470",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a77470",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 1/4] ARM: dts: r8a77470: Add SYS-DMAC support
2018-04-20 15:27 ` [PATCH 1/4] ARM: dts: r8a77470: Add SYS-DMAC support Biju Das
@ 2018-04-24 6:52 ` Simon Horman
2018-04-24 14:38 ` Geert Uytterhoeven
1 sibling, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-04-24 6:52 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro, devicetree, linux-renesas-soc
On Fri, Apr 20, 2018 at 04:27:06PM +0100, Biju Das wrote:
> Describe SYS-DMAC0/1 in the R8A77470 device tree.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Thanks, applied.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/4] ARM: dts: r8a77470: Add SYS-DMAC support
2018-04-20 15:27 ` [PATCH 1/4] ARM: dts: r8a77470: Add SYS-DMAC support Biju Das
2018-04-24 6:52 ` Simon Horman
@ 2018-04-24 14:38 ` Geert Uytterhoeven
2018-04-25 6:08 ` Simon Horman
1 sibling, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2018-04-24 14:38 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Chris Paterson, Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
On Fri, Apr 20, 2018 at 5:27 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> Describe SYS-DMAC0/1 in the R8A77470 device tree.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 1/4] ARM: dts: r8a77470: Add SYS-DMAC support
2018-04-24 14:38 ` Geert Uytterhoeven
@ 2018-04-25 6:08 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-04-25 6:08 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
On Tue, Apr 24, 2018 at 04:38:22PM +0200, Geert Uytterhoeven wrote:
> On Fri, Apr 20, 2018 at 5:27 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > Describe SYS-DMAC0/1 in the R8A77470 device tree.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, tag added.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/4] ARM: dts: r8a77470: Add IRQC support
2018-04-20 15:27 [PATCH 0/4] Add SYS-DMAC, IRQC and SCIF to SoC dtsi Biju Das
2018-04-20 15:27 ` [PATCH 1/4] ARM: dts: r8a77470: Add SYS-DMAC support Biju Das
@ 2018-04-20 15:27 ` Biju Das
2018-04-24 6:56 ` Simon Horman
2018-04-24 14:34 ` Geert Uytterhoeven
2018-04-20 15:27 ` [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support Biju Das
2018-04-20 15:27 ` [PATCH 4/4] ARM: dts: r8a77470: Add SCIF DMA support Biju Das
3 siblings, 2 replies; 18+ messages in thread
From: Biju Das @ 2018-04-20 15:27 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
Describe the IRQC interrupt controller in the R8A77470 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a77470.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index c39aceb..2f89f33 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -81,6 +81,26 @@
#power-domain-cells = <1>;
};
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a77470", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 407>;
+ };
+
icram0: sram@e63a0000 {
compatible = "mmio-sram";
reg = <0 0xe63a0000 0 0x12000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 2/4] ARM: dts: r8a77470: Add IRQC support
2018-04-20 15:27 ` [PATCH 2/4] ARM: dts: r8a77470: Add IRQC support Biju Das
@ 2018-04-24 6:56 ` Simon Horman
2018-04-24 14:34 ` Geert Uytterhoeven
1 sibling, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-04-24 6:56 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro, devicetree, linux-renesas-soc
On Fri, Apr 20, 2018 at 04:27:07PM +0100, Biju Das wrote:
> Describe the IRQC interrupt controller in the R8A77470 device tree.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Thanks, applied.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/4] ARM: dts: r8a77470: Add IRQC support
2018-04-20 15:27 ` [PATCH 2/4] ARM: dts: r8a77470: Add IRQC support Biju Das
2018-04-24 6:56 ` Simon Horman
@ 2018-04-24 14:34 ` Geert Uytterhoeven
2018-04-25 6:08 ` Simon Horman
1 sibling, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2018-04-24 14:34 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Chris Paterson, Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
On Fri, Apr 20, 2018 at 5:27 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> Describe the IRQC interrupt controller in the R8A77470 device tree.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 2/4] ARM: dts: r8a77470: Add IRQC support
2018-04-24 14:34 ` Geert Uytterhoeven
@ 2018-04-25 6:08 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-04-25 6:08 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
On Tue, Apr 24, 2018 at 04:34:19PM +0200, Geert Uytterhoeven wrote:
> On Fri, Apr 20, 2018 at 5:27 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > Describe the IRQC interrupt controller in the R8A77470 device tree.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, tag added.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support
2018-04-20 15:27 [PATCH 0/4] Add SYS-DMAC, IRQC and SCIF to SoC dtsi Biju Das
2018-04-20 15:27 ` [PATCH 1/4] ARM: dts: r8a77470: Add SYS-DMAC support Biju Das
2018-04-20 15:27 ` [PATCH 2/4] ARM: dts: r8a77470: Add IRQC support Biju Das
@ 2018-04-20 15:27 ` Biju Das
2018-04-24 7:08 ` Simon Horman
2018-04-20 15:27 ` [PATCH 4/4] ARM: dts: r8a77470: Add SCIF DMA support Biju Das
3 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2018-04-20 15:27 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
Describe SCIF ports in the R8A77470 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a77470.dtsi | 69 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 67 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 2f89f33..39549f2 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -190,19 +190,84 @@
dma-channels = <15>;
};
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a77470",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE 5>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 721>;
+ status = "disabled";
+ };
+
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a77470",
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 0x40>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 720>,
- <&cpg CPG_CORE 6>, <&scif_clk>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc 32>;
resets = <&cpg 720>;
status = "disabled";
};
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a77470",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 0x40>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>,
+ <&cpg CPG_CORE 5>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 719>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a77470",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>,
+ <&cpg CPG_CORE 5>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 718>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a77470",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 0x40>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>,
+ <&cpg CPG_CORE 5>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 715>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a77470",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 0x40>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>,
+ <&cpg CPG_CORE 5>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&sysc 32>;
+ resets = <&cpg 714>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support
2018-04-20 15:27 ` [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support Biju Das
@ 2018-04-24 7:08 ` Simon Horman
2018-04-24 7:19 ` Geert Uytterhoeven
0 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2018-04-24 7:08 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro, devicetree, linux-renesas-soc
On Fri, Apr 20, 2018 at 04:27:08PM +0100, Biju Das wrote:
> Describe SCIF ports in the R8A77470 device tree.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---
> arch/arm/boot/dts/r8a77470.dtsi | 69 +++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 67 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> index 2f89f33..39549f2 100644
> --- a/arch/arm/boot/dts/r8a77470.dtsi
> +++ b/arch/arm/boot/dts/r8a77470.dtsi
> @@ -190,19 +190,84 @@
> dma-channels = <15>;
> };
>
> + scif0: serial@e6e60000 {
> + compatible = "renesas,scif-r8a77470",
> + "renesas,rcar-gen2-scif", "renesas,scif";
> + reg = <0 0xe6e60000 0 0x40>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 721>,
> + <&cpg CPG_CORE 5>, <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc 32>;
> + resets = <&cpg 721>;
> + status = "disabled";
> + };
> +
> scif1: serial@e6e68000 {
> compatible = "renesas,scif-r8a77470",
> "renesas,rcar-gen2-scif", "renesas,scif";
> reg = <0 0xe6e68000 0 0x40>;
> interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&cpg CPG_MOD 720>,
> - <&cpg CPG_CORE 6>, <&scif_clk>;
> + clocks = <&cpg CPG_MOD 720>,
> + <&cpg CPG_CORE 5>, <&scif_clk>;
I am a little unclear why the CPG clock is changed from 6 (ZS?) to 5 (ZX?).
Could you clarify this for me?
> clock-names = "fck", "brg_int", "scif_clk";
> power-domains = <&sysc 32>;
> resets = <&cpg 720>;
> status = "disabled";
> };
>
> + scif2: serial@e6e58000 {
> + compatible = "renesas,scif-r8a77470",
> + "renesas,rcar-gen2-scif", "renesas,scif";
> + reg = <0 0xe6e58000 0 0x40>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 719>,
> + <&cpg CPG_CORE 5>, <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc 32>;
> + resets = <&cpg 719>;
> + status = "disabled";
> + };
> +
> + scif3: serial@e6ea8000 {
> + compatible = "renesas,scif-r8a77470",
> + "renesas,rcar-gen2-scif", "renesas,scif";
> + reg = <0 0xe6ea8000 0 0x40>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 718>,
> + <&cpg CPG_CORE 5>, <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc 32>;
> + resets = <&cpg 718>;
> + status = "disabled";
> + };
> +
> + scif4: serial@e6ee0000 {
> + compatible = "renesas,scif-r8a77470",
> + "renesas,rcar-gen2-scif", "renesas,scif";
> + reg = <0 0xe6ee0000 0 0x40>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 715>,
> + <&cpg CPG_CORE 5>, <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc 32>;
> + resets = <&cpg 715>;
> + status = "disabled";
> + };
> +
> + scif5: serial@e6ee8000 {
> + compatible = "renesas,scif-r8a77470",
> + "renesas,rcar-gen2-scif", "renesas,scif";
> + reg = <0 0xe6ee8000 0 0x40>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 714>,
> + <&cpg CPG_CORE 5>, <&scif_clk>;
> + clock-names = "fck", "brg_int", "scif_clk";
> + power-domains = <&sysc 32>;
> + resets = <&cpg 714>;
> + status = "disabled";
> + };
> +
> gic: interrupt-controller@f1001000 {
> compatible = "arm,gic-400";
> #interrupt-cells = <3>;
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support
2018-04-24 7:08 ` Simon Horman
@ 2018-04-24 7:19 ` Geert Uytterhoeven
2018-04-24 8:14 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2018-04-24 7:19 UTC (permalink / raw)
To: Simon Horman
Cc: Biju Das, Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
Hi Simon,
On Tue, Apr 24, 2018 at 9:08 AM, Simon Horman <horms@verge.net.au> wrote:
> On Fri, Apr 20, 2018 at 04:27:08PM +0100, Biju Das wrote:
>> Describe SCIF ports in the R8A77470 device tree.
>>
>> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>> ---
>> arch/arm/boot/dts/r8a77470.dtsi | 69 +++++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 67 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
>> index 2f89f33..39549f2 100644
>> --- a/arch/arm/boot/dts/r8a77470.dtsi
>> +++ b/arch/arm/boot/dts/r8a77470.dtsi
>> @@ -190,19 +190,84 @@
>> dma-channels = <15>;
>> };
>>
>> + scif0: serial@e6e60000 {
>> + compatible = "renesas,scif-r8a77470",
>> + "renesas,rcar-gen2-scif", "renesas,scif";
>> + reg = <0 0xe6e60000 0 0x40>;
>> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 721>,
>> + <&cpg CPG_CORE 5>, <&scif_clk>;
>> + clock-names = "fck", "brg_int", "scif_clk";
>> + power-domains = <&sysc 32>;
>> + resets = <&cpg 721>;
>> + status = "disabled";
>> + };
>> +
>> scif1: serial@e6e68000 {
>> compatible = "renesas,scif-r8a77470",
>> "renesas,rcar-gen2-scif", "renesas,scif";
>> reg = <0 0xe6e68000 0 0x40>;
>> interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&cpg CPG_MOD 720>,
>> - <&cpg CPG_CORE 6>, <&scif_clk>;
>> + clocks = <&cpg CPG_MOD 720>,
>> + <&cpg CPG_CORE 5>, <&scif_clk>;
>
> I am a little unclear why the CPG clock is changed from 6 (ZS?) to 5 (ZX?).
> Could you clarify this for me?
#define R8A77470_CLK_ZS 5
I guess you queued up the initial .dtsi before the error in
include/dt-bindings/clock/r8a77470-cpg-mssr.h was detected?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support
2018-04-24 7:19 ` Geert Uytterhoeven
@ 2018-04-24 8:14 ` Simon Horman
2018-04-24 8:20 ` Biju Das
0 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2018-04-24 8:14 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
On Tue, Apr 24, 2018 at 09:19:39AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Tue, Apr 24, 2018 at 9:08 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Fri, Apr 20, 2018 at 04:27:08PM +0100, Biju Das wrote:
> >> Describe SCIF ports in the R8A77470 device tree.
> >>
> >> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> >> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >> ---
> >> arch/arm/boot/dts/r8a77470.dtsi | 69 +++++++++++++++++++++++++++++++++++++++--
> >> 1 file changed, 67 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> >> index 2f89f33..39549f2 100644
> >> --- a/arch/arm/boot/dts/r8a77470.dtsi
> >> +++ b/arch/arm/boot/dts/r8a77470.dtsi
> >> @@ -190,19 +190,84 @@
> >> dma-channels = <15>;
> >> };
> >>
> >> + scif0: serial@e6e60000 {
> >> + compatible = "renesas,scif-r8a77470",
> >> + "renesas,rcar-gen2-scif", "renesas,scif";
> >> + reg = <0 0xe6e60000 0 0x40>;
> >> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 721>,
> >> + <&cpg CPG_CORE 5>, <&scif_clk>;
> >> + clock-names = "fck", "brg_int", "scif_clk";
> >> + power-domains = <&sysc 32>;
> >> + resets = <&cpg 721>;
> >> + status = "disabled";
> >> + };
> >> +
> >> scif1: serial@e6e68000 {
> >> compatible = "renesas,scif-r8a77470",
> >> "renesas,rcar-gen2-scif", "renesas,scif";
> >> reg = <0 0xe6e68000 0 0x40>;
> >> interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> >> - clocks = <&cpg CPG_MOD 720>,
> >> - <&cpg CPG_CORE 6>, <&scif_clk>;
> >> + clocks = <&cpg CPG_MOD 720>,
> >> + <&cpg CPG_CORE 5>, <&scif_clk>;
> >
> > I am a little unclear why the CPG clock is changed from 6 (ZS?) to 5 (ZX?).
> > Could you clarify this for me?
>
> #define R8A77470_CLK_ZS 5
>
> I guess you queued up the initial .dtsi before the error in
> include/dt-bindings/clock/r8a77470-cpg-mssr.h was detected?
Thanks, I see that ZS is 5 in renesas-drivers,
but when looking at an earlier version of the patch to add the
indexes it was 6.
I think that explains things. But could we add an explanation to the
changelog?
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support
2018-04-24 8:14 ` Simon Horman
@ 2018-04-24 8:20 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2018-04-24 8:20 UTC (permalink / raw)
To: Simon Horman, Geert Uytterhoeven
Cc: Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
<devicetree@vger.kernel.org>,
Linux-Renesas
Hi Simon and Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support
>
> On Tue, Apr 24, 2018 at 09:19:39AM +0200, Geert Uytterhoeven wrote:
> > Hi Simon,
> >
> > On Tue, Apr 24, 2018 at 9:08 AM, Simon Horman <horms@verge.net.au>
> wrote:
> > > On Fri, Apr 20, 2018 at 04:27:08PM +0100, Biju Das wrote:
> > >> Describe SCIF ports in the R8A77470 device tree.
> > >>
> > >> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > >> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >> ---
> > >> arch/arm/boot/dts/r8a77470.dtsi | 69
> > >> +++++++++++++++++++++++++++++++++++++++--
> > >> 1 file changed, 67 insertions(+), 2 deletions(-)
> > >>
> > >> diff --git a/arch/arm/boot/dts/r8a77470.dtsi
> > >> b/arch/arm/boot/dts/r8a77470.dtsi index 2f89f33..39549f2 100644
> > >> --- a/arch/arm/boot/dts/r8a77470.dtsi
> > >> +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > >> @@ -190,19 +190,84 @@
> > >> dma-channels = <15>;
> > >> };
> > >>
> > >> + scif0: serial@e6e60000 {
> > >> + compatible = "renesas,scif-r8a77470",
> > >> + "renesas,rcar-gen2-scif", "renesas,scif";
> > >> + reg = <0 0xe6e60000 0 0x40>;
> > >> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> > >> + clocks = <&cpg CPG_MOD 721>,
> > >> + <&cpg CPG_CORE 5>, <&scif_clk>;
> > >> + clock-names = "fck", "brg_int", "scif_clk";
> > >> + power-domains = <&sysc 32>;
> > >> + resets = <&cpg 721>;
> > >> + status = "disabled";
> > >> + };
> > >> +
> > >> scif1: serial@e6e68000 {
> > >> compatible = "renesas,scif-r8a77470",
> > >> "renesas,rcar-gen2-scif", "renesas,scif";
> > >> reg = <0 0xe6e68000 0 0x40>;
> > >> interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> > >> - clocks = <&cpg CPG_MOD 720>,
> > >> - <&cpg CPG_CORE 6>, <&scif_clk>;
> > >> + clocks = <&cpg CPG_MOD 720>,
> > >> + <&cpg CPG_CORE 5>, <&scif_clk>;
> > >
> > > I am a little unclear why the CPG clock is changed from 6 (ZS?) to 5 (ZX?).
> > > Could you clarify this for me?
> >
> > #define R8A77470_CLK_ZS 5
> >
> > I guess you queued up the initial .dtsi before the error in
> > include/dt-bindings/clock/r8a77470-cpg-mssr.h was detected?
>
> Thanks, I see that ZS is 5 in renesas-drivers, but when looking at an earlier
> version of the patch to add the indexes it was 6.
Yes, I took this value from renesas-drivers.
> I think that explains things. But could we add an explanation to the
> changelog?
OK. I will add the explanation to the change log.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support
@ 2018-04-24 8:20 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2018-04-24 8:20 UTC (permalink / raw)
To: Simon Horman, Geert Uytterhoeven
Cc: Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
Hi Simon and Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support
>
> On Tue, Apr 24, 2018 at 09:19:39AM +0200, Geert Uytterhoeven wrote:
> > Hi Simon,
> >
> > On Tue, Apr 24, 2018 at 9:08 AM, Simon Horman <horms@verge.net.au>
> wrote:
> > > On Fri, Apr 20, 2018 at 04:27:08PM +0100, Biju Das wrote:
> > >> Describe SCIF ports in the R8A77470 device tree.
> > >>
> > >> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > >> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >> ---
> > >> arch/arm/boot/dts/r8a77470.dtsi | 69
> > >> +++++++++++++++++++++++++++++++++++++++--
> > >> 1 file changed, 67 insertions(+), 2 deletions(-)
> > >>
> > >> diff --git a/arch/arm/boot/dts/r8a77470.dtsi
> > >> b/arch/arm/boot/dts/r8a77470.dtsi index 2f89f33..39549f2 100644
> > >> --- a/arch/arm/boot/dts/r8a77470.dtsi
> > >> +++ b/arch/arm/boot/dts/r8a77470.dtsi
> > >> @@ -190,19 +190,84 @@
> > >> dma-channels = <15>;
> > >> };
> > >>
> > >> + scif0: serial@e6e60000 {
> > >> + compatible = "renesas,scif-r8a77470",
> > >> + "renesas,rcar-gen2-scif", "renesas,scif";
> > >> + reg = <0 0xe6e60000 0 0x40>;
> > >> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> > >> + clocks = <&cpg CPG_MOD 721>,
> > >> + <&cpg CPG_CORE 5>, <&scif_clk>;
> > >> + clock-names = "fck", "brg_int", "scif_clk";
> > >> + power-domains = <&sysc 32>;
> > >> + resets = <&cpg 721>;
> > >> + status = "disabled";
> > >> + };
> > >> +
> > >> scif1: serial@e6e68000 {
> > >> compatible = "renesas,scif-r8a77470",
> > >> "renesas,rcar-gen2-scif", "renesas,scif";
> > >> reg = <0 0xe6e68000 0 0x40>;
> > >> interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> > >> - clocks = <&cpg CPG_MOD 720>,
> > >> - <&cpg CPG_CORE 6>, <&scif_clk>;
> > >> + clocks = <&cpg CPG_MOD 720>,
> > >> + <&cpg CPG_CORE 5>, <&scif_clk>;
> > >
> > > I am a little unclear why the CPG clock is changed from 6 (ZS?) to 5 (ZX?).
> > > Could you clarify this for me?
> >
> > #define R8A77470_CLK_ZS 5
> >
> > I guess you queued up the initial .dtsi before the error in
> > include/dt-bindings/clock/r8a77470-cpg-mssr.h was detected?
>
> Thanks, I see that ZS is 5 in renesas-drivers, but when looking at an earlier
> version of the patch to add the indexes it was 6.
Yes, I took this value from renesas-drivers.
> I think that explains things. But could we add an explanation to the
> changelog?
OK. I will add the explanation to the change log.
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] ARM: dts: r8a77470: Add SCIF DMA support
2018-04-20 15:27 [PATCH 0/4] Add SYS-DMAC, IRQC and SCIF to SoC dtsi Biju Das
` (2 preceding siblings ...)
2018-04-20 15:27 ` [PATCH 3/4] ARM: dts: r8a77470: Add SCIF support Biju Das
@ 2018-04-20 15:27 ` Biju Das
2018-04-24 14:44 ` Geert Uytterhoeven
3 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2018-04-20 15:27 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Simon Horman, Magnus Damm, Chris Paterson, Fabrizio Castro,
devicetree, linux-renesas-soc, Biju Das
Add SCIF DMA support for R8A77470 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm/boot/dts/r8a77470.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 39549f2..baec3ca 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -198,6 +198,9 @@
clocks = <&cpg CPG_MOD 721>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 721>;
status = "disabled";
@@ -211,6 +214,9 @@
clocks = <&cpg CPG_MOD 720>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 720>;
status = "disabled";
@@ -224,6 +230,9 @@
clocks = <&cpg CPG_MOD 719>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 719>;
status = "disabled";
@@ -237,6 +246,9 @@
clocks = <&cpg CPG_MOD 718>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 718>;
status = "disabled";
@@ -250,6 +262,9 @@
clocks = <&cpg CPG_MOD 715>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 715>;
status = "disabled";
@@ -263,6 +278,9 @@
clocks = <&cpg CPG_MOD 714>,
<&cpg CPG_CORE 5>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 714>;
status = "disabled";
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 4/4] ARM: dts: r8a77470: Add SCIF DMA support
2018-04-20 15:27 ` [PATCH 4/4] ARM: dts: r8a77470: Add SCIF DMA support Biju Das
@ 2018-04-24 14:44 ` Geert Uytterhoeven
2018-04-25 6:08 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2018-04-24 14:44 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Magnus Damm,
Chris Paterson, Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
On Fri, Apr 20, 2018 at 5:27 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> Add SCIF DMA support for R8A77470 SoC.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 4/4] ARM: dts: r8a77470: Add SCIF DMA support
2018-04-24 14:44 ` Geert Uytterhoeven
@ 2018-04-25 6:08 ` Simon Horman
0 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2018-04-25 6:08 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Rob Herring, Mark Rutland, Magnus Damm, Chris Paterson,
Fabrizio Castro,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
On Tue, Apr 24, 2018 at 04:44:17PM +0200, Geert Uytterhoeven wrote:
> On Fri, Apr 20, 2018 at 5:27 PM, Biju Das <biju.das@bp.renesas.com> wrote:
> > Add SCIF DMA support for R8A77470 SoC.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, tag added.
^ permalink raw reply [flat|nested] 18+ messages in thread