* [U-Boot] [PATCH v6 04/34] musb: sunxi: Add fifo config
@ 2018-04-26 10:20 Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6 06/34] musb: sunxi: Add OTG device clkgate and reset for H3/H5 Jagan Teki
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Jagan Teki @ 2018-04-26 10:20 UTC (permalink / raw)
To: u-boot
Unlike other Allwinner SOC's H3/H5/V3s OTG support 4 endpoints
with relevant fifo configs, rest all have 5 endpoints.
So add the fifo configs and defer them based on driver_data.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v6:
- Create private config for passing through driver_data instead
directly passing musb_config. This make room for adding new
configs in coming patches.
drivers/usb/musb-new/sunxi.c | 70 ++++++++++++++++++++++++++++++++++++++++----
1 file changed, 65 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 637e8b9b52..af0dbc5a20 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -76,9 +76,14 @@
* From usbc/usbc.c
******************************************************************************/
+struct sunxi_musb_config {
+ struct musb_hdrc_config *config;
+};
+
struct sunxi_glue {
struct musb_host_data mdata;
struct sunxi_ccm_reg *ccm;
+ struct sunxi_musb_config *cfg;
struct device dev;
};
#define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev)
@@ -301,13 +306,52 @@ static const struct musb_platform_ops sunxi_musb_ops = {
#define SUNXI_MUSB_MAX_EP_NUM 6
#define SUNXI_MUSB_RAM_BITS 11
+static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
+ MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
+ MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
+ MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
+ MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
+ MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
+ MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
+ MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
+ MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
+ MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
+ MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
+};
+
+/* H3/V3s OTG supports only 4 endpoints */
+#define SUNXI_MUSB_MAX_EP_NUM_H3 5
+
+static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
+ MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
+ MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
+ MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
+ MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
+ MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
+ MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
+ MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
+ MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
+};
+
static struct musb_hdrc_config musb_config = {
+ .fifo_cfg = sunxi_musb_mode_cfg,
+ .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
.multipoint = true,
.dyn_fifo = true,
.num_eps = SUNXI_MUSB_MAX_EP_NUM,
.ram_bits = SUNXI_MUSB_RAM_BITS,
};
+static struct musb_hdrc_config musb_config_h3 = {
+ .fifo_cfg = sunxi_musb_mode_cfg_h3,
+ .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
+ .multipoint = true,
+ .dyn_fifo = true,
+ .soft_con = true,
+ .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
+ .ram_bits = SUNXI_MUSB_RAM_BITS,
+};
+
static int musb_usb_probe(struct udevice *dev)
{
struct sunxi_glue *glue = dev_get_priv(dev);
@@ -320,6 +364,10 @@ static int musb_usb_probe(struct udevice *dev)
if (!base)
return -EINVAL;
+ glue->cfg = (struct sunxi_musb_config *)dev_get_driver_data(dev);
+ if (!glue->cfg)
+ return -EINVAL;
+
glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (IS_ERR(glue->ccm))
return PTR_ERR(glue->ccm);
@@ -329,7 +377,7 @@ static int musb_usb_probe(struct udevice *dev)
memset(&pdata, 0, sizeof(pdata));
pdata.power = 250;
pdata.platform_ops = &sunxi_musb_ops;
- pdata.config = &musb_config;
+ pdata.config = glue->cfg->config;
#ifdef CONFIG_USB_MUSB_HOST
pdata.mode = MUSB_HOST;
@@ -369,11 +417,23 @@ static int musb_usb_remove(struct udevice *dev)
return 0;
}
+static const struct sunxi_musb_config sun4i_a10_cfg = {
+ .config = &musb_config,
+};
+
+static const struct sunxi_musb_config sun8i_h3_cfg = {
+ .config = &musb_config_h3,
+};
+
static const struct udevice_id sunxi_musb_ids[] = {
- { .compatible = "allwinner,sun4i-a10-musb" },
- { .compatible = "allwinner,sun6i-a31-musb" },
- { .compatible = "allwinner,sun8i-a33-musb" },
- { .compatible = "allwinner,sun8i-h3-musb" },
+ { .compatible = "allwinner,sun4i-a10-musb",
+ .data = (ulong)&sun4i_a10_cfg },
+ { .compatible = "allwinner,sun6i-a31-musb",
+ .data = (ulong)&sun4i_a10_cfg },
+ { .compatible = "allwinner,sun8i-a33-musb",
+ .data = (ulong)&sun4i_a10_cfg },
+ { .compatible = "allwinner,sun8i-h3-musb",
+ .data = (ulong)&sun8i_h3_cfg },
{ }
};
--
2.14.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v6 06/34] musb: sunxi: Add OTG device clkgate and reset for H3/H5
2018-04-26 10:20 [U-Boot] [PATCH v6 04/34] musb: sunxi: Add fifo config Jagan Teki
@ 2018-04-26 10:20 ` Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6] musb: sunxi: Use BIT instead of numerical shift Jagan Teki
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Jagan Teki @ 2018-04-26 10:20 UTC (permalink / raw)
To: u-boot
Add OTG device clkgate and reset for H3/H5 through driver_data.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v6:
- split previous version patch and add only relevant changes.
drivers/usb/musb-new/sunxi.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index af0dbc5a20..e79d7a2774 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -78,6 +78,8 @@
struct sunxi_musb_config {
struct musb_hdrc_config *config;
+ u8 rst_bit;
+ u8 clkgate_bit;
};
struct sunxi_glue {
@@ -275,9 +277,16 @@ static int sunxi_musb_init(struct musb *musb)
musb->isr = sunxi_musb_interrupt;
setbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+ if (glue->cfg->clkgate_bit)
+ setbits_le32(&glue->ccm->ahb_gate0,
+ 1 << glue->cfg->clkgate_bit);
#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+ if (glue->cfg->rst_bit)
+ setbits_le32(&glue->ccm->ahb_reset0_cfg,
+ 1 << glue->cfg->rst_bit);
#endif
+
sunxi_usb_phy_init(0);
USBC_ConfigFIFO_Base();
@@ -408,8 +417,14 @@ static int musb_usb_remove(struct udevice *dev)
sunxi_usb_phy_exit(0);
#ifdef CONFIG_SUNXI_GEN_SUN6I
clrbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+ if (glue->cfg->rst_bit)
+ clrbits_le32(&glue->ccm->ahb_reset0_cfg,
+ 1 << glue->cfg->rst_bit);
#endif
clrbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+ if (glue->cfg->clkgate_bit)
+ clrbits_le32(&glue->ccm->ahb_gate0,
+ 1 << glue->cfg->clkgate_bit);
free(host->host);
host->host = NULL;
@@ -423,6 +438,8 @@ static const struct sunxi_musb_config sun4i_a10_cfg = {
static const struct sunxi_musb_config sun8i_h3_cfg = {
.config = &musb_config_h3,
+ .rst_bit = 23,
+ .clkgate_bit = 23,
};
static const struct udevice_id sunxi_musb_ids[] = {
--
2.14.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v6] musb: sunxi: Use BIT instead of numerical shift
2018-04-26 10:20 [U-Boot] [PATCH v6 04/34] musb: sunxi: Add fifo config Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6 06/34] musb: sunxi: Add OTG device clkgate and reset for H3/H5 Jagan Teki
@ 2018-04-26 10:20 ` Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6 03/34] musb: sunxi: Use simple way to fill musb_hdrc pdata Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6 07/34] sunxi: clock: Fix OHCI clock gating for H3/H5 Jagan Teki
3 siblings, 0 replies; 5+ messages in thread
From: Jagan Teki @ 2018-04-26 10:20 UTC (permalink / raw)
To: u-boot
Use BIT is possible areas instead of numerical shift.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v6:
- new patch on top of sunxi PHY series
drivers/usb/musb-new/sunxi.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index e79d7a2774..16551c7cf8 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -94,9 +94,9 @@ static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
{
u32 temp = reg_val;
- temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
- temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
- temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
+ temp &= ~BIT(USBC_BP_ISCR_VBUS_CHANGE_DETECT);
+ temp &= ~BIT(USBC_BP_ISCR_ID_CHANGE_DETECT);
+ temp &= ~BIT(USBC_BP_ISCR_DPDM_CHANGE_DETECT);
return temp;
}
@@ -106,7 +106,7 @@ static void USBC_EnableIdPullUp(__iomem void *base)
u32 reg_val;
reg_val = musb_readl(base, USBC_REG_o_ISCR);
- reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
+ reg_val |= BIT(USBC_BP_ISCR_ID_PULLUP_EN);
reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
musb_writel(base, USBC_REG_o_ISCR, reg_val);
}
@@ -116,7 +116,7 @@ static void USBC_EnableDpDmPullUp(__iomem void *base)
u32 reg_val;
reg_val = musb_readl(base, USBC_REG_o_ISCR);
- reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
+ reg_val |= BIT(USBC_BP_ISCR_DPDM_PULLUP_EN);
reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
musb_writel(base, USBC_REG_o_ISCR, reg_val);
}
@@ -172,7 +172,7 @@ static void USBC_ConfigFIFO_Base(void)
/* config usb fifo, 8kb mode */
reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
reg_value &= ~(0x03 << 0);
- reg_value |= (1 << 0);
+ reg_value |= BIT(0);
writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
}
@@ -276,15 +276,15 @@ static int sunxi_musb_init(struct musb *musb)
musb->isr = sunxi_musb_interrupt;
- setbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+ setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
if (glue->cfg->clkgate_bit)
setbits_le32(&glue->ccm->ahb_gate0,
- 1 << glue->cfg->clkgate_bit);
+ BIT(glue->cfg->clkgate_bit));
#ifdef CONFIG_SUNXI_GEN_SUN6I
- setbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+ setbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
if (glue->cfg->rst_bit)
setbits_le32(&glue->ccm->ahb_reset0_cfg,
- 1 << glue->cfg->rst_bit);
+ BIT(glue->cfg->rst_bit));
#endif
sunxi_usb_phy_init(0);
@@ -416,15 +416,15 @@ static int musb_usb_remove(struct udevice *dev)
sunxi_usb_phy_exit(0);
#ifdef CONFIG_SUNXI_GEN_SUN6I
- clrbits_le32(&glue->ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+ clrbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0));
if (glue->cfg->rst_bit)
clrbits_le32(&glue->ccm->ahb_reset0_cfg,
- 1 << glue->cfg->rst_bit);
+ BIT(glue->cfg->rst_bit));
#endif
- clrbits_le32(&glue->ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+ clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
if (glue->cfg->clkgate_bit)
clrbits_le32(&glue->ccm->ahb_gate0,
- 1 << glue->cfg->clkgate_bit);
+ BIT(glue->cfg->clkgate_bit));
free(host->host);
host->host = NULL;
--
2.14.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v6 03/34] musb: sunxi: Use simple way to fill musb_hdrc pdata
2018-04-26 10:20 [U-Boot] [PATCH v6 04/34] musb: sunxi: Add fifo config Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6 06/34] musb: sunxi: Add OTG device clkgate and reset for H3/H5 Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6] musb: sunxi: Use BIT instead of numerical shift Jagan Teki
@ 2018-04-26 10:20 ` Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6 07/34] sunxi: clock: Fix OHCI clock gating for H3/H5 Jagan Teki
3 siblings, 0 replies; 5+ messages in thread
From: Jagan Teki @ 2018-04-26 10:20 UTC (permalink / raw)
To: u-boot
Filling musb_hdrc pdata using structure will unnecessary
add extra ifdefs, so fill them inside probe call for
better code understanding and get rid ifdefs using
devicetree compatible.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v6:
- memset to pdata
drivers/usb/musb-new/sunxi.c | 23 ++++++++++-------------
1 file changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 3f3b89886a..637e8b9b52 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -308,22 +308,12 @@ static struct musb_hdrc_config musb_config = {
.ram_bits = SUNXI_MUSB_RAM_BITS,
};
-static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_HOST)
- .mode = MUSB_HOST,
-#else
- .mode = MUSB_PERIPHERAL,
-#endif
- .config = &musb_config,
- .power = 250,
- .platform_ops = &sunxi_musb_ops,
-};
-
static int musb_usb_probe(struct udevice *dev)
{
struct sunxi_glue *glue = dev_get_priv(dev);
struct musb_host_data *host = &glue->mdata;
struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
+ struct musb_hdrc_platform_data pdata;
void *base = dev_read_addr_ptr(dev);
int ret;
@@ -336,8 +326,14 @@ static int musb_usb_probe(struct udevice *dev)
priv->desc_before_addr = true;
+ memset(&pdata, 0, sizeof(pdata));
+ pdata.power = 250;
+ pdata.platform_ops = &sunxi_musb_ops;
+ pdata.config = &musb_config;
+
#ifdef CONFIG_USB_MUSB_HOST
- host->host = musb_init_controller(&musb_plat, &glue->dev, base);
+ pdata.mode = MUSB_HOST;
+ host->host = musb_init_controller(&pdata, &glue->dev, base);
if (!host->host)
return -EIO;
@@ -345,7 +341,8 @@ static int musb_usb_probe(struct udevice *dev)
if (!ret)
printf("Allwinner mUSB OTG (Host)\n");
#else
- ret = musb_register(&musb_plat, &glue->dev, base);
+ pdata.mode = MUSB_PERIPHERAL;
+ ret = musb_register(&pdata, &glue->dev, base);
if (!ret)
printf("Allwinner mUSB OTG (Peripheral)\n");
#endif
--
2.14.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH v6 07/34] sunxi: clock: Fix OHCI clock gating for H3/H5
2018-04-26 10:20 [U-Boot] [PATCH v6 04/34] musb: sunxi: Add fifo config Jagan Teki
` (2 preceding siblings ...)
2018-04-26 10:20 ` [U-Boot] [PATCH v6 03/34] musb: sunxi: Use simple way to fill musb_hdrc pdata Jagan Teki
@ 2018-04-26 10:20 ` Jagan Teki
3 siblings, 0 replies; 5+ messages in thread
From: Jagan Teki @ 2018-04-26 10:20 UTC (permalink / raw)
To: u-boot
From: Chen-Yu Tsai <wens@csie.org>
Clock gating bits on H43/H5 were wrong, fix them.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v6:
- Add SoB
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index c5dea45985..6fa6cf40ee 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -351,13 +351,10 @@ struct sunxi_ccm_reg {
#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
#ifdef CONFIG_MACH_SUNXI_H3_H5
-/*
- * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
- * them 0 - 2 like they were called on older SoCs.
- */
-#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
-#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
-#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
#else
#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
--
2.14.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-04-26 10:20 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-26 10:20 [U-Boot] [PATCH v6 04/34] musb: sunxi: Add fifo config Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6 06/34] musb: sunxi: Add OTG device clkgate and reset for H3/H5 Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6] musb: sunxi: Use BIT instead of numerical shift Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6 03/34] musb: sunxi: Use simple way to fill musb_hdrc pdata Jagan Teki
2018-04-26 10:20 ` [U-Boot] [PATCH v6 07/34] sunxi: clock: Fix OHCI clock gating for H3/H5 Jagan Teki
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