* [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427
@ 2018-04-27 9:20 David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 01/49] uninorth: trivial style fixups David Gibson
` (50 more replies)
0 siblings, 51 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
The following changes since commit ca92651697bdb2f15b36d347a498fbc31f4a4893:
Merge remote-tracking branch 'remotes/iwj/tags/for-upstream.depriv-2' into staging (2018-04-26 19:22:09 +0100)
are available in the Git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.13-20180427
for you to fetch changes up to 6233b679cae8741890f981c9dd6570d47715141e:
Clear mem_path if we fall back to anonymous RAM allocation (2018-04-27 18:05:23 +1000)
----------------------------------------------------------------
ppc patch queue 2018-04-27
Here's the first batch of ppc patches for 2.13. This has a lot of
stuff that's accumulated during the 2.12 freeze. Highlights are:
* Many improvements for the Uninorth PCI host bridge for Mac
machine types
* Preliminary helpers improve handling of multiple backing
pagesizes (not strictly ppc related, but have acks and aimed to
allow future ppc changes)
* Cleanups to pseries cpu initialization
* Cleanups to hash64 MMU handling
* Assorted bugfixes and improvements
----------------------------------------------------------------
BALATON Zoltan (1):
target/ppc: Fix reserved bit mask of dstst instruction
Bharata B Rao (1):
spapr: Support ibm,dynamic-memory-v2 property
David Gibson (19):
spapr: Introduce pseries-2.13 machine type
Make qemu_mempath_getpagesize() accept NULL
Add host_memory_backend_pagesize() helper
target/ppc: Standardize instance_init and realize function names
target/ppc: Simplify cpu valid check in ppc_cpu_realize
target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
target/ppc: Remove fallback 64k pagesize information
target/ppc: Move page size setup to helper function
target/ppc: Split page size information into a separate allocation
target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
target/ppc: Move 1T segment and AMR options to PPCHash64Options
target/ppc: Fold ci_large_pages flag into PPCHash64Options
target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
target/ppc: Get rid of POWERPC_MMU_VER() macros
target/ppc: Fold slb_nr into PPCHash64Options
target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr()
spapr: Set compatibility mode before the rest of spapr_cpu_reset()
Clear mem_path if we fall back to anonymous RAM allocation
Greg Kurz (2):
spapr: drop useless sanity check in spapr_irq_alloc*()
spapr: drop useless dynamic sysbus device sanity check
Igor Mammedov (1):
ppc: e500: switch E500 based machines to full machine definition
Mark Cave-Ayland (22):
uninorth: trivial style fixups
uninorth: remove second set of uninorth token registers
uninorth: QOMify PCI and AGP host bridges
uninorth: remove stray PCIBus realize from mac_newworld.c
uninorth: move uninorth definitions into uninorth.h
uninorth: alter pci_pmac_init() and pci_pmac_u3_init() to return uninorth device
heathrow: remove obsolete heathow_init() function
grackle: general tidy-up and QOMify
grackle: remove deprecated pci_grackle_init() function
grackle: move PCI IO (ISA) memory region into the grackle device
mac_oldworld: remove pics IRQ array and wire up macio to heathrow directly
mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize()
uninorth: move PCI mmio memory region initialisation into init function
uninorth: introduce temporary pic_irqs device property
uninorth: move PCI host bridge bus initialisation into device realize
uninorth: fix PCI and AGP bus mixup
uninorth: enable internal PCI host bridge
uninorth: remove obsolete pci_pmac_init() function
uninorth: remove obsolete pci_pmac_u3_init() function
uninorth: use object link to pass OpenPIC object to uninorth
uninorth: move PCI IO (ISA) memory region into the uninorth device
uninorth: rename UNINState to UNINHostState
Michael Matz (1):
ppc: Fix size of ppc64 xer register
Serhii Popovych (2):
Revert "spapr: Don't allow memory hotplug to memory less nodes"
spapr: Add ibm,max-associativity-domains property
backends/hostmem.c | 18 ++
docs/specs/ppc-spapr-hotplug.txt | 19 +++
exec.c | 20 +--
hw/intc/heathrow_pic.c | 23 +--
hw/misc/macio/macio.c | 37 ++--
hw/pci-host/grackle.c | 103 +++++------
hw/pci-host/uninorth.c | 357 ++++++++++++++++++++-------------------
hw/ppc/e500.c | 119 +++++++------
hw/ppc/e500.h | 29 +++-
hw/ppc/e500plat.c | 64 ++++---
hw/ppc/fdt.c | 7 +-
hw/ppc/mac.h | 27 +--
hw/ppc/mac_newworld.c | 68 ++++++--
hw/ppc/mac_oldworld.c | 51 +++---
hw/ppc/mpc8544ds.c | 47 ++++--
hw/ppc/pnv.c | 9 +-
hw/ppc/spapr.c | 330 +++++++++++++++++++++++++-----------
hw/ppc/spapr_cpu_core.c | 11 +-
include/hw/compat.h | 2 +
include/hw/intc/heathrow_pic.h | 2 +-
include/hw/misc/macio/macio.h | 1 -
include/hw/pci-host/uninorth.h | 56 ++++++
include/hw/ppc/fdt.h | 2 +-
include/hw/ppc/spapr_ovec.h | 1 +
include/sysemu/hostmem.h | 2 +
numa.c | 1 +
target/ppc/cpu-qom.h | 27 +--
target/ppc/cpu.h | 30 +---
target/ppc/gdbstub.c | 14 +-
target/ppc/kvm.c | 41 ++---
target/ppc/machine.c | 23 ++-
target/ppc/mmu-hash64.c | 152 ++++++++++++-----
target/ppc/mmu-hash64.h | 48 +++++-
target/ppc/mmu_helper.c | 24 +--
target/ppc/translate.c | 14 +-
target/ppc/translate_init.c | 137 ++++-----------
util/mmap-alloc.c | 26 +--
37 files changed, 1132 insertions(+), 810 deletions(-)
create mode 100644 include/hw/pci-host/uninorth.h
^ permalink raw reply [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 01/49] uninorth: trivial style fixups
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 02/49] uninorth: remove second set of uninorth token registers David Gibson
` (49 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This makes sure we keep patchew/checkpatch happy during the remainder of this
patchset.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 29 +++++++++++++++++++----------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 66991da975..710818e355 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -272,7 +272,6 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
UNINState *d;
/* Uninorth AGP bus */
-
dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
@@ -302,16 +301,23 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
- d->config[0x0C] = 0x08; // cache_line_size
- d->config[0x0D] = 0x10; // latency_timer
- d->config[0x34] = 0x00; // capabilities_pointer
+ /* cache_line_size */
+ d->config[0x0C] = 0x08;
+ /* latency_timer */
+ d->config[0x0D] = 0x10;
+ /* capabilities_pointer */
+ d->config[0x34] = 0x00;
}
static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
- d->config[0x0C] = 0x08; // cache_line_size
- d->config[0x0D] = 0x10; // latency_timer
- // d->config[0x34] = 0x80; // capabilities_pointer
+ /* cache_line_size */
+ d->config[0x0C] = 0x08;
+ /* latency_timer */
+ d->config[0x0D] = 0x10;
+ /* capabilities_pointer
+ d->config[0x34] = 0x80; */
+
/*
* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
* memory space with base 0x80000000, size 0x10000000 for Apple's
@@ -333,9 +339,12 @@ static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
{
- d->config[0x0C] = 0x08; // cache_line_size
- d->config[0x0D] = 0x10; // latency_timer
- d->config[0x34] = 0x00; // capabilities_pointer
+ /* cache_line_size */
+ d->config[0x0C] = 0x08;
+ /* latency_timer */
+ d->config[0x0D] = 0x10;
+ /* capabilities_pointer */
+ d->config[0x34] = 0x00;
}
static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 02/49] uninorth: remove second set of uninorth token registers
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 01/49] uninorth: trivial style fixups David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 03/49] uninorth: QOMify PCI and AGP host bridges David Gibson
` (48 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Commit 593c181160: "PPC: Newworld: Add second uninorth control register set"
added a second set of uninorth registers at 0xf3000000.
Testing MacOS 9.2 to MacOS X 10.4 reveals no accesses to this address and I
can't find any reference to it in Apple's Core99.cpp source so I'm assuming
that this was the result of another bug that has now been fixed.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/mac_newworld.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 2f5b6f651a..39944203a4 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -147,7 +147,6 @@ static void ppc_core99_init(MachineState *machine)
qemu_irq *pic, **openpic_irqs;
MemoryRegion *isa = g_new(MemoryRegion, 1);
MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
- MemoryRegion *unin2_memory = g_new(MemoryRegion, 1);
int linux_boot, i, j, k;
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
hwaddr kernel_base, initrd_base, cmdline_base = 0;
@@ -282,9 +281,6 @@ static void ppc_core99_init(MachineState *machine)
memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000);
memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
- memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000);
- memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory);
-
openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
openpic_irqs[0] =
g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 03/49] uninorth: QOMify PCI and AGP host bridges
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 01/49] uninorth: trivial style fixups David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 02/49] uninorth: remove second set of uninorth token registers David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 04/49] uninorth: remove stray PCIBus realize from mac_newworld.c David Gibson
` (47 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 79 ++++++++++++++++++++------------------------------
1 file changed, 32 insertions(+), 47 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 710818e355..1d4d3f5705 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -129,72 +129,61 @@ static const MemoryRegionOps unin_data_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static int pci_unin_main_init_device(SysBusDevice *dev)
+static void pci_unin_main_init(Object *obj)
{
- PCIHostState *h;
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ PCIHostState *h = PCI_HOST_BRIDGE(obj);
/* Use values found on a real PowerMac */
/* Uninorth main bus */
- h = PCI_HOST_BRIDGE(dev);
-
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- dev, "pci-conf-idx", 0x1000);
- memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
+ obj, "pci-conf-idx", 0x1000);
+ memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
"pci-conf-data", 0x1000);
- sysbus_init_mmio(dev, &h->conf_mem);
- sysbus_init_mmio(dev, &h->data_mem);
-
- return 0;
+ sysbus_init_mmio(sbd, &h->conf_mem);
+ sysbus_init_mmio(sbd, &h->data_mem);
}
-
-static int pci_u3_agp_init_device(SysBusDevice *dev)
+static void pci_u3_agp_init(Object *obj)
{
- PCIHostState *h;
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ PCIHostState *h = PCI_HOST_BRIDGE(obj);
/* Uninorth U3 AGP bus */
- h = PCI_HOST_BRIDGE(dev);
-
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- dev, "pci-conf-idx", 0x1000);
- memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, dev,
+ obj, "pci-conf-idx", 0x1000);
+ memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
"pci-conf-data", 0x1000);
- sysbus_init_mmio(dev, &h->conf_mem);
- sysbus_init_mmio(dev, &h->data_mem);
-
- return 0;
+ sysbus_init_mmio(sbd, &h->conf_mem);
+ sysbus_init_mmio(sbd, &h->data_mem);
}
-static int pci_unin_agp_init_device(SysBusDevice *dev)
+static void pci_unin_agp_init(Object *obj)
{
- PCIHostState *h;
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ PCIHostState *h = PCI_HOST_BRIDGE(obj);
/* Uninorth AGP bus */
- h = PCI_HOST_BRIDGE(dev);
-
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- dev, "pci-conf-idx", 0x1000);
+ obj, "pci-conf-idx", 0x1000);
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
- dev, "pci-conf-data", 0x1000);
- sysbus_init_mmio(dev, &h->conf_mem);
- sysbus_init_mmio(dev, &h->data_mem);
- return 0;
+ obj, "pci-conf-data", 0x1000);
+ sysbus_init_mmio(sbd, &h->conf_mem);
+ sysbus_init_mmio(sbd, &h->data_mem);
}
-static int pci_unin_internal_init_device(SysBusDevice *dev)
+static void pci_unin_internal_init(Object *obj)
{
- PCIHostState *h;
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ PCIHostState *h = PCI_HOST_BRIDGE(obj);
/* Uninorth internal bus */
- h = PCI_HOST_BRIDGE(dev);
-
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- dev, "pci-conf-idx", 0x1000);
+ obj, "pci-conf-idx", 0x1000);
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
- dev, "pci-conf-data", 0x1000);
- sysbus_init_mmio(dev, &h->conf_mem);
- sysbus_init_mmio(dev, &h->data_mem);
- return 0;
+ obj, "pci-conf-data", 0x1000);
+ sysbus_init_mmio(sbd, &h->conf_mem);
+ sysbus_init_mmio(sbd, &h->data_mem);
}
PCIBus *pci_pmac_init(qemu_irq *pic,
@@ -461,10 +450,8 @@ static const TypeInfo unin_internal_pci_host_info = {
static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- sbc->init = pci_unin_main_init_device;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -472,15 +459,14 @@ static const TypeInfo pci_unin_main_info = {
.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(UNINState),
+ .instance_init = pci_unin_main_init,
.class_init = pci_unin_main_class_init,
};
static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- sbc->init = pci_u3_agp_init_device;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -488,15 +474,14 @@ static const TypeInfo pci_u3_agp_info = {
.name = TYPE_U3_AGP_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(UNINState),
+ .instance_init = pci_u3_agp_init,
.class_init = pci_u3_agp_class_init,
};
static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- sbc->init = pci_unin_agp_init_device;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -504,15 +489,14 @@ static const TypeInfo pci_unin_agp_info = {
.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(UNINState),
+ .instance_init = pci_unin_agp_init,
.class_init = pci_unin_agp_class_init,
};
static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- sbc->init = pci_unin_internal_init_device;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -520,6 +504,7 @@ static const TypeInfo pci_unin_internal_info = {
.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(UNINState),
+ .instance_init = pci_unin_internal_init,
.class_init = pci_unin_internal_class_init,
};
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 04/49] uninorth: remove stray PCIBus realize from mac_newworld.c
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (2 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 03/49] uninorth: QOMify PCI and AGP host bridges David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 05/49] uninorth: move uninorth definitions into uninorth.h David Gibson
` (46 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
After QOMification this is clearly no longer needed (and possibly hasn't been
for some time).
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/mac_newworld.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 39944203a4..4ff1c293a8 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -350,7 +350,6 @@ static void ppc_core99_init(MachineState *machine)
pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
machine_arch = ARCH_MAC99;
}
- object_property_set_bool(OBJECT(pci_bus), true, "realized", &error_abort);
machine->usb |= defaults_enabled() && !machine->usb_disabled;
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 05/49] uninorth: move uninorth definitions into uninorth.h
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (3 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 04/49] uninorth: remove stray PCIBus realize from mac_newworld.c David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 06/49] uninorth: alter pci_pmac_init() and pci_pmac_u3_init() to return uninorth device David Gibson
` (45 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
[dwg: Added hw/hw.h #include as suggested by Philippe Mathieu-Daudé]
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 22 +-----------------
include/hw/pci-host/uninorth.h | 51 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+), 21 deletions(-)
create mode 100644 include/hw/pci-host/uninorth.h
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 1d4d3f5705..600d675573 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -26,31 +26,11 @@
#include "hw/ppc/mac.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
+#include "hw/pci-host/uninorth.h"
#include "trace.h"
static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
-#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
-#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
-#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
-#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
-
-#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
-#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
-#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
-#define U3_AGP_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
-
-typedef struct UNINState {
- PCIHostState parent_obj;
-
- MemoryRegion pci_mmio;
- MemoryRegion pci_hole;
-} UNINState;
-
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 3;
diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h
new file mode 100644
index 0000000000..0366376a3b
--- /dev/null
+++ b/include/hw/pci-host/uninorth.h
@@ -0,0 +1,51 @@
+/*
+ * QEMU Uninorth PCI host (for all Mac99 and newer machines)
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef UNINORTH_H
+#define UNINORTH_H
+
+#include "hw/hw.h"
+
+#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
+#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
+#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
+#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
+
+#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
+ OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
+#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
+ OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
+#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
+ OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
+#define U3_AGP_HOST_BRIDGE(obj) \
+ OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
+
+typedef struct UNINState {
+ PCIHostState parent_obj;
+
+ MemoryRegion pci_mmio;
+ MemoryRegion pci_hole;
+} UNINState;
+
+#endif /* UNINORTH_H */
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 06/49] uninorth: alter pci_pmac_init() and pci_pmac_u3_init() to return uninorth device
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (4 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 05/49] uninorth: move uninorth definitions into uninorth.h David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 07/49] heathrow: remove obsolete heathow_init() function David Gibson
` (44 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This is in preparation for moving the device wiring into the New World machine.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 16 ++++++++--------
hw/ppc/mac.h | 10 ++++++----
hw/ppc/mac_newworld.c | 10 ++++++++--
3 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 600d675573..b081e3c153 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -166,9 +166,9 @@ static void pci_unin_internal_init(Object *obj)
sysbus_init_mmio(sbd, &h->data_mem);
}
-PCIBus *pci_pmac_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io)
+UNINState *pci_pmac_init(qemu_irq *pic,
+ MemoryRegion *address_space_mem,
+ MemoryRegion *address_space_io)
{
DeviceState *dev;
SysBusDevice *s;
@@ -228,12 +228,12 @@ PCIBus *pci_pmac_init(qemu_irq *pic,
sysbus_mmio_map(s, 1, 0xf4c00000);
#endif
- return h->bus;
+ return d;
}
-PCIBus *pci_pmac_u3_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io)
+UNINState *pci_pmac_u3_init(qemu_irq *pic,
+ MemoryRegion *address_space_mem,
+ MemoryRegion *address_space_io)
{
DeviceState *dev;
SysBusDevice *s;
@@ -265,7 +265,7 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
pci_create_simple(h->bus, 11 << 3, "u3-agp");
- return h->bus;
+ return d;
}
static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index a02f797598..fcf13cb757 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -31,6 +31,8 @@
#include "hw/ide/internal.h"
#include "hw/input/adb.h"
#include "hw/misc/mos6522.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci-host/uninorth.h"
/* SMP is not enabled, for now */
#define MAX_CPUS 1
@@ -86,12 +88,12 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
MemoryRegion *address_space_io);
/* UniNorth PCI */
-PCIBus *pci_pmac_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io);
-PCIBus *pci_pmac_u3_init(qemu_irq *pic,
+UNINState *pci_pmac_init(qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io);
+UNINState *pci_pmac_u3_init(qemu_irq *pic,
+ MemoryRegion *address_space_mem,
+ MemoryRegion *address_space_io);
/* Mac NVRAM */
#define TYPE_MACIO_NVRAM "macio-nvram"
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 4ff1c293a8..ccf34ee36c 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -151,6 +151,7 @@ static void ppc_core99_init(MachineState *machine)
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
hwaddr kernel_base, initrd_base, cmdline_base = 0;
long kernel_size, initrd_size;
+ UNINState *uninorth_pci;
PCIBus *pci_bus;
NewWorldMacIOState *macio;
MACIOIDEState *macio_ide;
@@ -344,10 +345,12 @@ static void ppc_core99_init(MachineState *machine)
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
- pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
+ uninorth_pci = pci_pmac_u3_init(pic, get_system_memory(),
+ get_system_io());
machine_arch = ARCH_MAC99_U3;
} else {
- pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
+ uninorth_pci = pci_pmac_init(pic, get_system_memory(),
+ get_system_io());
machine_arch = ARCH_MAC99;
}
@@ -360,6 +363,9 @@ static void ppc_core99_init(MachineState *machine)
tbfreq = TBFREQ;
}
+ /* init basic PC hardware */
+ pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus;
+
/* MacIO */
macio = NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO));
dev = DEVICE(macio);
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 07/49] heathrow: remove obsolete heathow_init() function
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (5 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 06/49] uninorth: alter pci_pmac_init() and pci_pmac_u3_init() to return uninorth device David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 08/49] grackle: general tidy-up and QOMify David Gibson
` (43 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Instead wire up heathrow to the CPU and grackle PCI host using qdev GPIOs.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/intc/heathrow_pic.c | 23 +++++------------------
hw/ppc/mac.h | 4 ----
hw/ppc/mac_oldworld.c | 20 ++++++++++++--------
include/hw/intc/heathrow_pic.h | 2 +-
4 files changed, 18 insertions(+), 31 deletions(-)
diff --git a/hw/intc/heathrow_pic.c b/hw/intc/heathrow_pic.c
index 393fdd7326..b8b997deca 100644
--- a/hw/intc/heathrow_pic.c
+++ b/hw/intc/heathrow_pic.c
@@ -172,27 +172,14 @@ static void heathrow_init(Object *obj)
HeathrowState *s = HEATHROW(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
- memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s,
- "heathrow-pic", 0x1000);
- sysbus_init_mmio(sbd, &s->mem);
-}
-
-DeviceState *heathrow_pic_init(int nb_cpus, qemu_irq **irqs,
- qemu_irq **pic_irqs)
-{
- DeviceState *d;
- HeathrowState *s;
-
- d = qdev_create(NULL, TYPE_HEATHROW);
- qdev_init_nofail(d);
-
- s = HEATHROW(d);
/* only 1 CPU */
- s->irqs = irqs[0];
+ qdev_init_gpio_out(DEVICE(obj), s->irqs, 1);
- *pic_irqs = qemu_allocate_irqs(heathrow_set_irq, s, HEATHROW_NUM_IRQS);
+ qdev_init_gpio_in(DEVICE(obj), heathrow_set_irq, HEATHROW_NUM_IRQS);
- return d;
+ memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s,
+ "heathrow-pic", 0x1000);
+ sysbus_init_mmio(sbd, &s->mem);
}
static void heathrow_class_init(ObjectClass *oc, void *data)
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index fcf13cb757..d661515e9d 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -77,10 +77,6 @@ void macio_ide_register_dma(MACIOIDEState *ide);
void macio_init(PCIDevice *dev,
MemoryRegion *pic_mem);
-/* Heathrow PIC */
-DeviceState *heathrow_pic_init(int nb_cpus, qemu_irq **irqs,
- qemu_irq **pic_irqs);
-
/* Grackle PCI */
#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 10e291ca22..9bd4ece16d 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -84,7 +84,7 @@ static void ppc_heathrow_init(MachineState *machine)
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
- qemu_irq *pic, **heathrow_irqs;
+ qemu_irq *pic;
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
@@ -227,16 +227,15 @@ static void ppc_heathrow_init(MachineState *machine)
memory_region_add_subregion(sysmem, 0xfe000000, isa);
/* XXX: we register only 1 output pin for heathrow PIC */
- heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
- heathrow_irqs[0] =
- g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
+ pic_dev = qdev_create(NULL, TYPE_HEATHROW);
+ qdev_init_nofail(pic_dev);
+
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
- heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
- heathrow_irqs[i][0] =
- ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
+ qdev_connect_gpio_out(pic_dev, 0,
+ ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
break;
default:
error_report("Bus model not supported on OldWorld Mac machine");
@@ -244,6 +243,11 @@ static void ppc_heathrow_init(MachineState *machine)
}
}
+ pic = g_new0(qemu_irq, HEATHROW_NUM_IRQS);
+ for (i = 0; i < HEATHROW_NUM_IRQS; i++) {
+ pic[i] = qdev_get_gpio_in(pic_dev, i);
+ }
+
/* Timebase Frequency */
if (kvm_enabled()) {
tbfreq = kvmppc_get_tbfreq();
@@ -256,7 +260,7 @@ static void ppc_heathrow_init(MachineState *machine)
error_report("Only 6xx bus is supported on heathrow machine");
exit(1);
}
- pic_dev = heathrow_pic_init(1, heathrow_irqs, &pic);
+
pci_bus = pci_grackle_init(0xfec00000, pic,
get_system_memory(),
get_system_io());
diff --git a/include/hw/intc/heathrow_pic.h b/include/hw/intc/heathrow_pic.h
index bc3ffaab87..56c2ef339f 100644
--- a/include/hw/intc/heathrow_pic.h
+++ b/include/hw/intc/heathrow_pic.h
@@ -41,7 +41,7 @@ typedef struct HeathrowState {
MemoryRegion mem;
HeathrowPICState pics[2];
- qemu_irq *irqs;
+ qemu_irq irqs[1];
} HeathrowState;
#define HEATHROW_NUM_IRQS 64
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 08/49] grackle: general tidy-up and QOMify
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (6 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 07/49] heathrow: remove obsolete heathow_init() function David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 09/49] grackle: remove deprecated pci_grackle_init() function David Gibson
` (42 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This is the first step towards removing the old-style pci_grackle_init()
function. Following on from the previous commit we can now pass the heathrow
device as an object link and wire up the heathrow IRQs via qdev GPIOs.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/grackle.c | 96 +++++++++++++++++++++++++++++++++------------------
hw/ppc/mac.h | 2 +-
hw/ppc/mac_oldworld.c | 2 +-
3 files changed, 64 insertions(+), 36 deletions(-)
diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c
index 033588b7d2..f8935246c3 100644
--- a/hw/pci-host/grackle.c
+++ b/hw/pci-host/grackle.c
@@ -27,6 +27,8 @@
#include "hw/pci/pci_host.h"
#include "hw/ppc/mac.h"
#include "hw/pci/pci.h"
+#include "hw/intc/heathrow_pic.h"
+#include "qapi/error.h"
#include "trace.h"
#define GRACKLE_PCI_HOST_BRIDGE(obj) \
@@ -35,6 +37,8 @@
typedef struct GrackleState {
PCIHostState parent_obj;
+ HeathrowState *pic;
+ qemu_irq irqs[4];
MemoryRegion pci_mmio;
MemoryRegion pci_hole;
} GrackleState;
@@ -47,13 +51,22 @@ static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
{
- qemu_irq *pic = opaque;
+ GrackleState *s = opaque;
trace_grackle_set_irq(irq_num, level);
- qemu_set_irq(pic[irq_num + 0x15], level);
+ qemu_set_irq(s->irqs[irq_num], level);
}
-PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
+static void grackle_init_irqs(GrackleState *s)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
+ s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), 0x15 + i);
+ }
+}
+
+PCIBus *pci_grackle_init(uint32_t base, DeviceState *pic_dev,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io)
{
@@ -63,60 +76,75 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
GrackleState *d;
dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE);
+ object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
+ &error_abort);
+ qdev_init_nofail(dev);
+
s = SYS_BUS_DEVICE(dev);
phb = PCI_HOST_BRIDGE(dev);
d = GRACKLE_PCI_HOST_BRIDGE(dev);
- memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
- memory_region_init_alias(&d->pci_hole, OBJECT(s), "pci-hole", &d->pci_mmio,
- 0x80000000ULL, 0x7e000000ULL);
memory_region_add_subregion(address_space_mem, 0x80000000ULL,
&d->pci_hole);
+ sysbus_mmio_map(s, 0, base);
+ sysbus_mmio_map(s, 1, base + 0x00200000);
+
+ return phb->bus;
+}
+
+static void grackle_realize(DeviceState *dev, Error **errp)
+{
+ GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
+ PCIHostState *phb = PCI_HOST_BRIDGE(dev);
+
phb->bus = pci_register_root_bus(dev, NULL,
pci_grackle_set_irq,
pci_grackle_map_irq,
- pic,
- &d->pci_mmio,
- address_space_io,
+ s,
+ &s->pci_mmio,
+ get_system_io(),
0, 4, TYPE_PCI_BUS);
pci_create_simple(phb->bus, 0, "grackle");
- qdev_init_nofail(dev);
-
- sysbus_mmio_map(s, 0, base);
- sysbus_mmio_map(s, 1, base + 0x00200000);
-
- return phb->bus;
+ grackle_init_irqs(s);
}
-static int pci_grackle_init_device(SysBusDevice *dev)
+static void grackle_init(Object *obj)
{
- PCIHostState *phb;
+ GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ PCIHostState *phb = PCI_HOST_BRIDGE(obj);
- phb = PCI_HOST_BRIDGE(dev);
+ memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
+ memory_region_init_alias(&s->pci_hole, OBJECT(s), "pci-hole", &s->pci_mmio,
+ 0x80000000ULL, 0x7e000000ULL);
- memory_region_init_io(&phb->conf_mem, OBJECT(dev), &pci_host_conf_le_ops,
- dev, "pci-conf-idx", 0x1000);
- memory_region_init_io(&phb->data_mem, OBJECT(dev), &pci_host_data_le_ops,
- dev, "pci-data-idx", 0x1000);
- sysbus_init_mmio(dev, &phb->conf_mem);
- sysbus_init_mmio(dev, &phb->data_mem);
+ memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops,
+ DEVICE(obj), "pci-conf-idx", 0x1000);
+ memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops,
+ DEVICE(obj), "pci-data-idx", 0x1000);
- return 0;
+ object_property_add_link(obj, "pic", TYPE_HEATHROW,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+
+ sysbus_init_mmio(sbd, &phb->conf_mem);
+ sysbus_init_mmio(sbd, &phb->data_mem);
}
-static void grackle_pci_host_realize(PCIDevice *d, Error **errp)
+static void grackle_pci_realize(PCIDevice *d, Error **errp)
{
d->config[0x09] = 0x01;
}
static void grackle_pci_class_init(ObjectClass *klass, void *data)
{
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
- k->realize = grackle_pci_host_realize;
+ k->realize = grackle_pci_realize;
k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106;
k->revision = 0x00;
@@ -139,26 +167,26 @@ static const TypeInfo grackle_pci_info = {
},
};
-static void pci_grackle_class_init(ObjectClass *klass, void *data)
+static void grackle_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
- k->init = pci_grackle_init_device;
+ dc->realize = grackle_realize;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
-static const TypeInfo grackle_pci_host_info = {
+static const TypeInfo grackle_host_info = {
.name = TYPE_GRACKLE_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(GrackleState),
- .class_init = pci_grackle_class_init,
+ .instance_init = grackle_init,
+ .class_init = grackle_class_init,
};
static void grackle_register_types(void)
{
type_register_static(&grackle_pci_info);
- type_register_static(&grackle_pci_host_info);
+ type_register_static(&grackle_host_info);
}
type_init(grackle_register_types)
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index d661515e9d..695557b8bf 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -79,7 +79,7 @@ void macio_init(PCIDevice *dev,
/* Grackle PCI */
#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
-PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
+PCIBus *pci_grackle_init(uint32_t base, DeviceState *pic_dev,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io);
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 9bd4ece16d..d48abfef07 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -261,7 +261,7 @@ static void ppc_heathrow_init(MachineState *machine)
exit(1);
}
- pci_bus = pci_grackle_init(0xfec00000, pic,
+ pci_bus = pci_grackle_init(0xfec00000, pic_dev,
get_system_memory(),
get_system_io());
pci_vga_init(pci_bus);
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 09/49] grackle: remove deprecated pci_grackle_init() function
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (7 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 08/49] grackle: general tidy-up and QOMify David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 10/49] grackle: move PCI IO (ISA) memory region into the grackle device David Gibson
` (41 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Instead wire up the grackle device inside the Mac Old World machine.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/grackle.c | 28 +---------------------------
hw/ppc/mac.h | 3 ---
hw/ppc/mac_oldworld.c | 21 ++++++++++++++++++---
3 files changed, 19 insertions(+), 33 deletions(-)
diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c
index f8935246c3..e4583d493b 100644
--- a/hw/pci-host/grackle.c
+++ b/hw/pci-host/grackle.c
@@ -66,33 +66,6 @@ static void grackle_init_irqs(GrackleState *s)
}
}
-PCIBus *pci_grackle_init(uint32_t base, DeviceState *pic_dev,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io)
-{
- DeviceState *dev;
- SysBusDevice *s;
- PCIHostState *phb;
- GrackleState *d;
-
- dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE);
- object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
- &error_abort);
- qdev_init_nofail(dev);
-
- s = SYS_BUS_DEVICE(dev);
- phb = PCI_HOST_BRIDGE(dev);
- d = GRACKLE_PCI_HOST_BRIDGE(dev);
-
- memory_region_add_subregion(address_space_mem, 0x80000000ULL,
- &d->pci_hole);
-
- sysbus_mmio_map(s, 0, base);
- sysbus_mmio_map(s, 1, base + 0x00200000);
-
- return phb->bus;
-}
-
static void grackle_realize(DeviceState *dev, Error **errp)
{
GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
@@ -132,6 +105,7 @@ static void grackle_init(Object *obj)
sysbus_init_mmio(sbd, &phb->conf_mem);
sysbus_init_mmio(sbd, &phb->data_mem);
+ sysbus_init_mmio(sbd, &s->pci_hole);
}
static void grackle_pci_realize(PCIDevice *d, Error **errp)
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index 695557b8bf..93f25d7acb 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -79,9 +79,6 @@ void macio_init(PCIDevice *dev,
/* Grackle PCI */
#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
-PCIBus *pci_grackle_init(uint32_t base, DeviceState *pic_dev,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io);
/* UniNorth PCI */
UNINState *pci_pmac_init(qemu_irq *pic,
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index d48abfef07..f0246f43d3 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -34,6 +34,7 @@
#include "net/net.h"
#include "hw/isa/isa.h"
#include "hw/pci/pci.h"
+#include "hw/pci/pci_host.h"
#include "hw/boards.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/char/escc.h"
@@ -55,6 +56,8 @@
#define NDRV_VGA_FILENAME "qemu_vga.ndrv"
+#define GRACKLE_BASE 0xfec00000
+
static void fw_cfg_boot_set(void *opaque, const char *boot_device,
Error **errp)
{
@@ -94,6 +97,7 @@ static void ppc_heathrow_init(MachineState *machine)
PCIBus *pci_bus;
OldWorldMacIOState *macio;
MACIOIDEState *macio_ide;
+ SysBusDevice *s;
DeviceState *dev, *pic_dev;
BusState *adb_bus;
int bios_size, ndrv_size;
@@ -261,9 +265,20 @@ static void ppc_heathrow_init(MachineState *machine)
exit(1);
}
- pci_bus = pci_grackle_init(0xfec00000, pic_dev,
- get_system_memory(),
- get_system_io());
+ /* Grackle PCI host bridge */
+ dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE);
+ object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
+ &error_abort);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(s, 0, GRACKLE_BASE);
+ sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
+ /* PCI hole */
+ memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
+ sysbus_mmio_get_region(s, 2));
+
+ pci_bus = PCI_HOST_BRIDGE(dev)->bus;
+
pci_vga_init(pci_bus);
for (i = 0; i < nb_nics; i++) {
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 10/49] grackle: move PCI IO (ISA) memory region into the grackle device
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (8 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 09/49] grackle: remove deprecated pci_grackle_init() function David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 11/49] mac_oldworld: remove pics IRQ array and wire up macio to heathrow directly David Gibson
` (40 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This simplifies the Old World machine to simply mapping the ISA memory region
into the main address space.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/grackle.c | 7 ++++++-
hw/ppc/mac_oldworld.c | 9 +++------
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c
index e4583d493b..4810a4de79 100644
--- a/hw/pci-host/grackle.c
+++ b/hw/pci-host/grackle.c
@@ -41,6 +41,7 @@ typedef struct GrackleState {
qemu_irq irqs[4];
MemoryRegion pci_mmio;
MemoryRegion pci_hole;
+ MemoryRegion pci_io;
} GrackleState;
/* Don't know if this matches real hardware, but it agrees with OHW. */
@@ -76,7 +77,7 @@ static void grackle_realize(DeviceState *dev, Error **errp)
pci_grackle_map_irq,
s,
&s->pci_mmio,
- get_system_io(),
+ &s->pci_io,
0, 4, TYPE_PCI_BUS);
pci_create_simple(phb->bus, 0, "grackle");
@@ -90,6 +91,9 @@ static void grackle_init(Object *obj)
PCIHostState *phb = PCI_HOST_BRIDGE(obj);
memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
+ memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
+ "pci-isa-mmio", 0x00200000);
+
memory_region_init_alias(&s->pci_hole, OBJECT(s), "pci-hole", &s->pci_mmio,
0x80000000ULL, 0x7e000000ULL);
@@ -106,6 +110,7 @@ static void grackle_init(Object *obj)
sysbus_init_mmio(sbd, &phb->conf_mem);
sysbus_init_mmio(sbd, &phb->data_mem);
sysbus_init_mmio(sbd, &s->pci_hole);
+ sysbus_init_mmio(sbd, &s->pci_io);
}
static void grackle_pci_realize(PCIDevice *d, Error **errp)
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index f0246f43d3..f9e63b8d83 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -91,7 +91,6 @@ static void ppc_heathrow_init(MachineState *machine)
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
- MemoryRegion *isa = g_new(MemoryRegion, 1);
uint32_t kernel_base, initrd_base, cmdline_base = 0;
int32_t kernel_size, initrd_size;
PCIBus *pci_bus;
@@ -225,11 +224,6 @@ static void ppc_heathrow_init(MachineState *machine)
}
}
- /* Register 2 MB of ISA IO space */
- memory_region_init_alias(isa, NULL, "isa_mmio",
- get_system_io(), 0, 0x00200000);
- memory_region_add_subregion(sysmem, 0xfe000000, isa);
-
/* XXX: we register only 1 output pin for heathrow PIC */
pic_dev = qdev_create(NULL, TYPE_HEATHROW);
qdev_init_nofail(pic_dev);
@@ -276,6 +270,9 @@ static void ppc_heathrow_init(MachineState *machine)
/* PCI hole */
memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
sysbus_mmio_get_region(s, 2));
+ /* Register 2 MB of ISA IO space */
+ memory_region_add_subregion(get_system_memory(), 0xfe000000,
+ sysbus_mmio_get_region(s, 3));
pci_bus = PCI_HOST_BRIDGE(dev)->bus;
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 11/49] mac_oldworld: remove pics IRQ array and wire up macio to heathrow directly
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (9 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 10/49] grackle: move PCI IO (ISA) memory region into the grackle device David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 12/49] mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize() David Gibson
` (39 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Introduce constants for the pre-defined Old World IRQs to help keep things
readable.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/mac.h | 8 ++++++++
hw/ppc/mac_oldworld.c | 27 ++++++++++++++-------------
2 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index 93f25d7acb..c5a33e96cb 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -47,6 +47,14 @@
#define ESCC_CLOCK 3686400
+/* Old World IRQs */
+#define OLDWORLD_CUDA_IRQ 0x12
+#define OLDWORLD_ESCCB_IRQ 0x10
+#define OLDWORLD_ESCCA_IRQ 0xf
+#define OLDWORLD_IDE0_IRQ 0xd
+#define OLDWORLD_IDE0_DMA_IRQ 0x2
+#define OLDWORLD_IDE1_IRQ 0xe
+#define OLDWORLD_IDE1_DMA_IRQ 0x3
/* MacIO */
#define TYPE_MACIO_IDE "macio-ide"
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index f9e63b8d83..2bbcefa076 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -87,7 +87,6 @@ static void ppc_heathrow_init(MachineState *machine)
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
- qemu_irq *pic;
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
@@ -241,11 +240,6 @@ static void ppc_heathrow_init(MachineState *machine)
}
}
- pic = g_new0(qemu_irq, HEATHROW_NUM_IRQS);
- for (i = 0; i < HEATHROW_NUM_IRQS; i++) {
- pic[i] = qdev_get_gpio_in(pic_dev, i);
- }
-
/* Timebase Frequency */
if (kvm_enabled()) {
tbfreq = kvmppc_get_tbfreq();
@@ -287,13 +281,20 @@ static void ppc_heathrow_init(MachineState *machine)
/* MacIO */
macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO));
dev = DEVICE(macio);
- qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
- qdev_connect_gpio_out(dev, 1, pic[0x10]); /* ESCC-B */
- qdev_connect_gpio_out(dev, 2, pic[0x0F]); /* ESCC-A */
- qdev_connect_gpio_out(dev, 3, pic[0x0D]); /* IDE-0 */
- qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE-0 DMA */
- qdev_connect_gpio_out(dev, 5, pic[0x0E]); /* IDE-1 */
- qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE-1 DMA */
+ qdev_connect_gpio_out(dev, 0,
+ qdev_get_gpio_in(pic_dev, OLDWORLD_CUDA_IRQ));
+ qdev_connect_gpio_out(dev, 1,
+ qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCB_IRQ));
+ qdev_connect_gpio_out(dev, 2,
+ qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCA_IRQ));
+ qdev_connect_gpio_out(dev, 3,
+ qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ));
+ qdev_connect_gpio_out(dev, 4,
+ qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ));
+ qdev_connect_gpio_out(dev, 5,
+ qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ));
+ qdev_connect_gpio_out(dev, 6,
+ qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ));
qdev_prop_set_uint64(dev, "frequency", tbfreq);
object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
&error_abort);
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 12/49] mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize()
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (10 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 11/49] mac_oldworld: remove pics IRQ array and wire up macio to heathrow directly David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 13/49] uninorth: move PCI mmio memory region initialisation into init function David Gibson
` (38 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Since the macio device has a link to the PIC device, we can now wire up the
IRQs directly via qdev GPIOs rather than having to use an intermediate array.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/misc/macio/macio.c | 37 ++++++++++++++++++++++---------------
hw/ppc/mac_oldworld.c | 14 --------------
include/hw/misc/macio/macio.h | 1 -
3 files changed, 22 insertions(+), 30 deletions(-)
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index a0cefe5719..dac7bcd15e 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -152,10 +152,9 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
{
MacIOState *s = MACIO(d);
OldWorldMacIOState *os = OLDWORLD_MACIO(d);
+ DeviceState *pic_dev = DEVICE(os->pic);
Error *err = NULL;
SysBusDevice *sysbus_dev;
- int i;
- int cur_irq = 0;
macio_common_realize(d, &err);
if (err) {
@@ -164,11 +163,14 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
}
sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
- sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]);
+ sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
+ OLDWORLD_CUDA_IRQ));
sysbus_dev = SYS_BUS_DEVICE(&s->escc);
- sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]);
- sysbus_connect_irq(sysbus_dev, 1, os->irqs[cur_irq++]);
+ sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev,
+ OLDWORLD_ESCCB_IRQ));
+ sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev,
+ OLDWORLD_ESCCA_IRQ));
object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err);
if (err) {
@@ -186,15 +188,22 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp)
sysbus_mmio_get_region(sysbus_dev, 0));
/* IDE buses */
- for (i = 0; i < ARRAY_SIZE(os->ide); i++) {
- qemu_irq irq0 = os->irqs[cur_irq++];
- qemu_irq irq1 = os->irqs[cur_irq++];
+ macio_realize_ide(s, &os->ide[0],
+ qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ),
+ qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ),
+ 0x16, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
- macio_realize_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4), &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
+ macio_realize_ide(s, &os->ide[1],
+ qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ),
+ qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ),
+ 0x1a, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
}
}
@@ -219,8 +228,6 @@ static void macio_oldworld_init(Object *obj)
DeviceState *dev;
int i;
- qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs));
-
object_property_add_link(obj, "pic", TYPE_HEATHROW,
(Object **) &os->pic,
qdev_prop_allow_set_link_before_realize,
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 2bbcefa076..4608bab014 100644
--- a/hw/ppc/mac_oldworld.c
+++ b/hw/ppc/mac_oldworld.c
@@ -281,20 +281,6 @@ static void ppc_heathrow_init(MachineState *machine)
/* MacIO */
macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO));
dev = DEVICE(macio);
- qdev_connect_gpio_out(dev, 0,
- qdev_get_gpio_in(pic_dev, OLDWORLD_CUDA_IRQ));
- qdev_connect_gpio_out(dev, 1,
- qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCB_IRQ));
- qdev_connect_gpio_out(dev, 2,
- qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCA_IRQ));
- qdev_connect_gpio_out(dev, 3,
- qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ));
- qdev_connect_gpio_out(dev, 4,
- qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ));
- qdev_connect_gpio_out(dev, 5,
- qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ));
- qdev_connect_gpio_out(dev, 6,
- qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ));
qdev_prop_set_uint64(dev, "frequency", tbfreq);
object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
&error_abort);
diff --git a/include/hw/misc/macio/macio.h b/include/hw/misc/macio/macio.h
index 4528282b36..64a2584a77 100644
--- a/include/hw/misc/macio/macio.h
+++ b/include/hw/misc/macio/macio.h
@@ -56,7 +56,6 @@ typedef struct OldWorldMacIOState {
/*< public >*/
HeathrowState *pic;
- qemu_irq irqs[7];
MacIONVRAMState nvram;
MACIOIDEState ide[2];
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 13/49] uninorth: move PCI mmio memory region initialisation into init function
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (11 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 12/49] mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize() David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 14/49] uninorth: introduce temporary pic_irqs device property David Gibson
` (37 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Whilst we are here, rename the memory regions to better reflect whether they
belong to either a PCI or an AGP bus.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index b081e3c153..5b8fc3aa16 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -111,29 +111,39 @@ static const MemoryRegionOps unin_data_ops = {
static void pci_unin_main_init(Object *obj)
{
+ UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
/* Use values found on a real PowerMac */
/* Uninorth main bus */
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- obj, "pci-conf-idx", 0x1000);
+ obj, "unin-pci-conf-idx", 0x1000);
memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
- "pci-conf-data", 0x1000);
+ "unin-pci-conf-data", 0x1000);
+
+ memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
+ 0x100000000ULL);
+
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
}
static void pci_u3_agp_init(Object *obj)
{
+ UNINState *s = U3_AGP_HOST_BRIDGE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
/* Uninorth U3 AGP bus */
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- obj, "pci-conf-idx", 0x1000);
+ obj, "unin-pci-conf-idx", 0x1000);
memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
- "pci-conf-data", 0x1000);
+ "unin-pci-conf-data", 0x1000);
+
+ memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
+ 0x100000000ULL);
+
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
}
@@ -145,9 +155,9 @@ static void pci_unin_agp_init(Object *obj)
/* Uninorth AGP bus */
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- obj, "pci-conf-idx", 0x1000);
+ obj, "unin-agp-conf-idx", 0x1000);
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
- obj, "pci-conf-data", 0x1000);
+ obj, "unin-agp-conf-data", 0x1000);
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
}
@@ -159,9 +169,9 @@ static void pci_unin_internal_init(Object *obj)
/* Uninorth internal bus */
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
- obj, "pci-conf-idx", 0x1000);
+ obj, "unin-pci-conf-idx", 0x1000);
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
- obj, "pci-conf-data", 0x1000);
+ obj, "unin-pci-conf-data", 0x1000);
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
}
@@ -182,7 +192,6 @@ UNINState *pci_pmac_init(qemu_irq *pic,
s = SYS_BUS_DEVICE(dev);
h = PCI_HOST_BRIDGE(s);
d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
- memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
0x80000000ULL, 0x10000000ULL);
memory_region_add_subregion(address_space_mem, 0x80000000ULL,
@@ -247,7 +256,6 @@ UNINState *pci_pmac_u3_init(qemu_irq *pic,
h = PCI_HOST_BRIDGE(dev);
d = U3_AGP_HOST_BRIDGE(dev);
- memory_region_init(&d->pci_mmio, OBJECT(d), "pci-mmio", 0x100000000ULL);
memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
0x80000000ULL, 0x70000000ULL);
memory_region_add_subregion(address_space_mem, 0x80000000ULL,
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 14/49] uninorth: introduce temporary pic_irqs device property
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (12 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 13/49] uninorth: move PCI mmio memory region initialisation into init function David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 15/49] uninorth: move PCI host bridge bus initialisation into device realize David Gibson
` (36 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This is in preparation for moving the PCI bus wiring inside the uninorth
host bridge devices. In the future it will be possible to remove this once the
PICs have been switched to use qdev GPIOs.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 25 +++++++++++++++++++++++--
include/hw/pci-host/uninorth.h | 1 +
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 5b8fc3aa16..fc59698f06 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -188,6 +188,7 @@ UNINState *pci_pmac_init(qemu_irq *pic,
/* Use values found on a real PowerMac */
/* Uninorth main bus */
dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
+ qdev_prop_set_ptr(dev, "pic-irqs", pic);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
h = PCI_HOST_BRIDGE(s);
@@ -199,7 +200,7 @@ UNINState *pci_pmac_init(qemu_irq *pic,
h->bus = pci_register_root_bus(dev, NULL,
pci_unin_set_irq, pci_unin_map_irq,
- pic,
+ d->pic_irqs,
&d->pci_mmio,
address_space_io,
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
@@ -220,6 +221,7 @@ UNINState *pci_pmac_init(qemu_irq *pic,
/* Uninorth AGP bus */
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
+ qdev_prop_set_ptr(dev, "pic-irqs", pic);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0xf0800000);
@@ -251,6 +253,7 @@ UNINState *pci_pmac_u3_init(qemu_irq *pic,
/* Uninorth AGP bus */
dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
+ qdev_prop_set_ptr(dev, "pic-irqs", pic);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
h = PCI_HOST_BRIDGE(dev);
@@ -263,7 +266,7 @@ UNINState *pci_pmac_u3_init(qemu_irq *pic,
h->bus = pci_register_root_bus(dev, NULL,
pci_unin_set_irq, pci_unin_map_irq,
- pic,
+ d->pic_irqs,
&d->pci_mmio,
address_space_io,
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
@@ -436,10 +439,16 @@ static const TypeInfo unin_internal_pci_host_info = {
},
};
+static Property pci_unin_main_properties[] = {
+ DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->props = pci_unin_main_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -451,10 +460,16 @@ static const TypeInfo pci_unin_main_info = {
.class_init = pci_unin_main_class_init,
};
+static Property pci_u3_agp_properties[] = {
+ DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->props = pci_u3_agp_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -466,10 +481,16 @@ static const TypeInfo pci_u3_agp_info = {
.class_init = pci_u3_agp_class_init,
};
+static Property pci_unin_agp_class_properties[] = {
+ DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->props = pci_unin_agp_class_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h
index 0366376a3b..e4fa11c145 100644
--- a/include/hw/pci-host/uninorth.h
+++ b/include/hw/pci-host/uninorth.h
@@ -44,6 +44,7 @@
typedef struct UNINState {
PCIHostState parent_obj;
+ void *pic_irqs;
MemoryRegion pci_mmio;
MemoryRegion pci_hole;
} UNINState;
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 15/49] uninorth: move PCI host bridge bus initialisation into device realize
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (13 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 14/49] uninorth: introduce temporary pic_irqs device property David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 16/49] uninorth: fix PCI and AGP bus mixup David Gibson
` (35 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Since the IO address space is fixed to use the standard system IO address
space then we can also use the opportunity to remove the address_space_io
parameter from pci_pmac_init() and pci_pmac_u3_init().
Note we also move the default mac99 PCI bus to the end of the initialisation
list so that it becomes the default destination for any devices specified
via -device without an explicit PCI bus provided.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 117 ++++++++++++++++++++++++++++---------------------
hw/ppc/mac.h | 6 +--
hw/ppc/mac_newworld.c | 6 +--
3 files changed, 72 insertions(+), 57 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index fc59698f06..426b3c4e33 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -109,6 +109,27 @@ static const MemoryRegionOps unin_data_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
+static void pci_unin_main_realize(DeviceState *dev, Error **errp)
+{
+ UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
+
+ h->bus = pci_register_root_bus(dev, NULL,
+ pci_unin_set_irq, pci_unin_map_irq,
+ s->pic_irqs,
+ &s->pci_mmio,
+ get_system_io(),
+ PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
+
+ pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
+
+ /* DEC 21154 bridge */
+#if 0
+ /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
+ pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
+#endif
+}
+
static void pci_unin_main_init(Object *obj)
{
UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
@@ -129,6 +150,21 @@ static void pci_unin_main_init(Object *obj)
sysbus_init_mmio(sbd, &h->data_mem);
}
+static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
+{
+ UNINState *s = U3_AGP_HOST_BRIDGE(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
+
+ h->bus = pci_register_root_bus(dev, NULL,
+ pci_unin_set_irq, pci_unin_map_irq,
+ s->pic_irqs,
+ &s->pci_mmio,
+ get_system_io(),
+ PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
+
+ pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
+}
+
static void pci_u3_agp_init(Object *obj)
{
UNINState *s = U3_AGP_HOST_BRIDGE(obj);
@@ -148,6 +184,19 @@ static void pci_u3_agp_init(Object *obj)
sysbus_init_mmio(sbd, &h->data_mem);
}
+static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
+{
+ UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
+
+ h->bus = pci_register_root_bus(dev, NULL,
+ pci_unin_set_irq, pci_unin_map_irq,
+ s->pic_irqs,
+ &s->pci_mmio,
+ get_system_io(),
+ PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
+}
+
static void pci_unin_agp_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
@@ -177,49 +226,14 @@ static void pci_unin_internal_init(Object *obj)
}
UNINState *pci_pmac_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io)
+ MemoryRegion *address_space_mem)
{
DeviceState *dev;
SysBusDevice *s;
- PCIHostState *h;
UNINState *d;
/* Use values found on a real PowerMac */
- /* Uninorth main bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
- qdev_prop_set_ptr(dev, "pic-irqs", pic);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- h = PCI_HOST_BRIDGE(s);
- d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
- memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
- 0x80000000ULL, 0x10000000ULL);
- memory_region_add_subregion(address_space_mem, 0x80000000ULL,
- &d->pci_hole);
-
- h->bus = pci_register_root_bus(dev, NULL,
- pci_unin_set_irq, pci_unin_map_irq,
- d->pic_irqs,
- &d->pci_mmio,
- address_space_io,
- PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
-
-#if 0
- pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
-#endif
-
- sysbus_mmio_map(s, 0, 0xf2800000);
- sysbus_mmio_map(s, 1, 0xf2c00000);
-
- /* DEC 21154 bridge */
-#if 0
- /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
- pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
-#endif
-
/* Uninorth AGP bus */
- pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
qdev_prop_set_ptr(dev, "pic-irqs", pic);
qdev_init_nofail(dev);
@@ -239,16 +253,28 @@ UNINState *pci_pmac_init(qemu_irq *pic,
sysbus_mmio_map(s, 1, 0xf4c00000);
#endif
+ /* Uninorth main bus */
+ dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
+ qdev_prop_set_ptr(dev, "pic-irqs", pic);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+ d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
+ memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
+ 0x80000000ULL, 0x10000000ULL);
+ memory_region_add_subregion(address_space_mem, 0x80000000ULL,
+ &d->pci_hole);
+
+ sysbus_mmio_map(s, 0, 0xf2800000);
+ sysbus_mmio_map(s, 1, 0xf2c00000);
+
return d;
}
UNINState *pci_pmac_u3_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io)
+ MemoryRegion *address_space_mem)
{
DeviceState *dev;
SysBusDevice *s;
- PCIHostState *h;
UNINState *d;
/* Uninorth AGP bus */
@@ -256,7 +282,6 @@ UNINState *pci_pmac_u3_init(qemu_irq *pic,
qdev_prop_set_ptr(dev, "pic-irqs", pic);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
- h = PCI_HOST_BRIDGE(dev);
d = U3_AGP_HOST_BRIDGE(dev);
memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
@@ -264,18 +289,9 @@ UNINState *pci_pmac_u3_init(qemu_irq *pic,
memory_region_add_subregion(address_space_mem, 0x80000000ULL,
&d->pci_hole);
- h->bus = pci_register_root_bus(dev, NULL,
- pci_unin_set_irq, pci_unin_map_irq,
- d->pic_irqs,
- &d->pci_mmio,
- address_space_io,
- PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
-
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
- pci_create_simple(h->bus, 11 << 3, "u3-agp");
-
return d;
}
@@ -448,6 +464,7 @@ static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = pci_unin_main_realize;
dc->props = pci_unin_main_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -469,6 +486,7 @@ static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = pci_u3_agp_realize;
dc->props = pci_u3_agp_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -490,6 +508,7 @@ static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = pci_unin_agp_realize;
dc->props = pci_unin_agp_class_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index c5a33e96cb..1ab2a3b354 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -90,11 +90,9 @@ void macio_init(PCIDevice *dev,
/* UniNorth PCI */
UNINState *pci_pmac_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io);
+ MemoryRegion *address_space_mem);
UNINState *pci_pmac_u3_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io);
+ MemoryRegion *address_space_mem);
/* Mac NVRAM */
#define TYPE_MACIO_NVRAM "macio-nvram"
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index ccf34ee36c..3367d7bb93 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -345,12 +345,10 @@ static void ppc_core99_init(MachineState *machine)
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
- uninorth_pci = pci_pmac_u3_init(pic, get_system_memory(),
- get_system_io());
+ uninorth_pci = pci_pmac_u3_init(pic, get_system_memory());
machine_arch = ARCH_MAC99_U3;
} else {
- uninorth_pci = pci_pmac_init(pic, get_system_memory(),
- get_system_io());
+ uninorth_pci = pci_pmac_init(pic, get_system_memory());
machine_arch = ARCH_MAC99;
}
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 16/49] uninorth: fix PCI and AGP bus mixup
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (14 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 15/49] uninorth: move PCI host bridge bus initialisation into device realize David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 17/49] uninorth: enable internal PCI host bridge David Gibson
` (34 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Somewhere in the history of time, the initialisation of the PCI buses for the
AGP and PCI host bridges got mixed up in that the PCI host bridge was
creating an instance of the AGP PCI bus, and the AGP PCI bus was missing.
Swap the PCI host bridge over to use the correct PCI bus (including setting
the kMacRISCPCIAddressSelect register used by MacOS X) and add the missing
reference to the AGP PCI bus.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 426b3c4e33..1f6752c294 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -121,7 +121,7 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp)
get_system_io(),
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
- pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
+ pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
/* DEC 21154 bridge */
#if 0
@@ -195,6 +195,8 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
&s->pci_mmio,
get_system_io(),
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
+
+ pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
}
static void pci_unin_agp_init(Object *obj)
@@ -303,16 +305,6 @@ static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
d->config[0x0D] = 0x10;
/* capabilities_pointer */
d->config[0x34] = 0x00;
-}
-
-static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
-{
- /* cache_line_size */
- d->config[0x0C] = 0x08;
- /* latency_timer */
- d->config[0x0D] = 0x10;
- /* capabilities_pointer
- d->config[0x34] = 0x80; */
/*
* Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
@@ -325,6 +317,16 @@ static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
d->config[0x4b] = 0x1;
}
+static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
+{
+ /* cache_line_size */
+ d->config[0x0C] = 0x08;
+ /* latency_timer */
+ d->config[0x0D] = 0x10;
+ /* capabilities_pointer
+ d->config[0x34] = 0x80; */
+}
+
static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
{
/* cache line size */
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 17/49] uninorth: enable internal PCI host bridge
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (15 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 16/49] uninorth: fix PCI and AGP bus mixup David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 18/49] uninorth: remove obsolete pci_pmac_init() function David Gibson
` (33 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 1f6752c294..ccde332fa9 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -213,6 +213,21 @@ static void pci_unin_agp_init(Object *obj)
sysbus_init_mmio(sbd, &h->data_mem);
}
+static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
+{
+ UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
+
+ h->bus = pci_register_root_bus(dev, NULL,
+ pci_unin_set_irq, pci_unin_map_irq,
+ s->pic_irqs,
+ &s->pci_mmio,
+ get_system_io(),
+ PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
+
+ pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
+}
+
static void pci_unin_internal_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
@@ -244,16 +259,12 @@ UNINState *pci_pmac_init(qemu_irq *pic,
sysbus_mmio_map(s, 1, 0xf0c00000);
/* Uninorth internal bus */
-#if 0
- /* XXX: not needed for now */
- pci_create_simple(h->bus, PCI_DEVFN(14, 0),
- "uni-north-internal-pci");
dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
+ qdev_prop_set_ptr(dev, "pic-irqs", pic);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0xf4800000);
sysbus_mmio_map(s, 1, 0xf4c00000);
-#endif
/* Uninorth main bus */
dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
@@ -523,10 +534,17 @@ static const TypeInfo pci_unin_agp_info = {
.class_init = pci_unin_agp_class_init,
};
+static Property pci_unin_internal_class_properties[] = {
+ DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = pci_unin_internal_realize;
+ dc->props = pci_unin_internal_class_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 18/49] uninorth: remove obsolete pci_pmac_init() function
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (16 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 17/49] uninorth: enable internal PCI host bridge David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 19/49] uninorth: remove obsolete pci_pmac_u3_init() function David Gibson
` (32 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Instead wire up the PCI/AGP host bridges in mac_newworld.c. Now this is complete
it is possible to move the initialisation of the PCI hole alias into
pci_unin_main_init().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 46 +++++-----------------------------------------
hw/ppc/mac_newworld.c | 30 +++++++++++++++++++++++++++++-
2 files changed, 34 insertions(+), 42 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index ccde332fa9..8e4e9b3d35 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -146,8 +146,13 @@ static void pci_unin_main_init(Object *obj)
memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
0x100000000ULL);
+ memory_region_init_alias(&s->pci_hole, OBJECT(s),
+ "unin-pci-hole", &s->pci_mmio,
+ 0x80000000ULL, 0x10000000ULL);
+
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
+ sysbus_init_mmio(sbd, &s->pci_hole);
}
static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
@@ -242,47 +247,6 @@ static void pci_unin_internal_init(Object *obj)
sysbus_init_mmio(sbd, &h->data_mem);
}
-UNINState *pci_pmac_init(qemu_irq *pic,
- MemoryRegion *address_space_mem)
-{
- DeviceState *dev;
- SysBusDevice *s;
- UNINState *d;
-
- /* Use values found on a real PowerMac */
- /* Uninorth AGP bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
- qdev_prop_set_ptr(dev, "pic-irqs", pic);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- sysbus_mmio_map(s, 0, 0xf0800000);
- sysbus_mmio_map(s, 1, 0xf0c00000);
-
- /* Uninorth internal bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
- qdev_prop_set_ptr(dev, "pic-irqs", pic);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- sysbus_mmio_map(s, 0, 0xf4800000);
- sysbus_mmio_map(s, 1, 0xf4c00000);
-
- /* Uninorth main bus */
- dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
- qdev_prop_set_ptr(dev, "pic-irqs", pic);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
- memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
- 0x80000000ULL, 0x10000000ULL);
- memory_region_add_subregion(address_space_mem, 0x80000000ULL,
- &d->pci_hole);
-
- sysbus_mmio_map(s, 0, 0xf2800000);
- sysbus_mmio_map(s, 1, 0xf2c00000);
-
- return d;
-}
-
UNINState *pci_pmac_u3_init(qemu_irq *pic,
MemoryRegion *address_space_mem)
{
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 3367d7bb93..3033fc0d7e 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -348,7 +348,35 @@ static void ppc_core99_init(MachineState *machine)
uninorth_pci = pci_pmac_u3_init(pic, get_system_memory());
machine_arch = ARCH_MAC99_U3;
} else {
- uninorth_pci = pci_pmac_init(pic, get_system_memory());
+ /* Use values found on a real PowerMac */
+ /* Uninorth AGP bus */
+ dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
+ qdev_prop_set_ptr(dev, "pic-irqs", pic);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(s, 0, 0xf0800000);
+ sysbus_mmio_map(s, 1, 0xf0c00000);
+
+ /* Uninorth internal bus */
+ dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
+ qdev_prop_set_ptr(dev, "pic-irqs", pic);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(s, 0, 0xf4800000);
+ sysbus_mmio_map(s, 1, 0xf4c00000);
+
+ /* Uninorth main bus */
+ dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
+ qdev_prop_set_ptr(dev, "pic-irqs", pic);
+ qdev_init_nofail(dev);
+ uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
+ s = SYS_BUS_DEVICE(dev);
+ /* PCI hole */
+ memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
+ sysbus_mmio_get_region(s, 2));
+ sysbus_mmio_map(s, 0, 0xf2800000);
+ sysbus_mmio_map(s, 1, 0xf2c00000);
+
machine_arch = ARCH_MAC99;
}
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 19/49] uninorth: remove obsolete pci_pmac_u3_init() function
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (17 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 18/49] uninorth: remove obsolete pci_pmac_init() function David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 20/49] uninorth: use object link to pass OpenPIC object to uninorth David Gibson
` (31 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Instead wire up the PCI/AGP host bridges in mac_newworld.c. Now this is complete
it is possible to move the initialisation of the PCI hole alias into
pci_u3_agp_init().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 30 +++++-------------------------
hw/ppc/mac_newworld.c | 13 ++++++++++++-
2 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 8e4e9b3d35..ec6e529d66 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -185,8 +185,13 @@ static void pci_u3_agp_init(Object *obj)
memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
0x100000000ULL);
+ memory_region_init_alias(&s->pci_hole, OBJECT(s),
+ "unin-pci-hole", &s->pci_mmio,
+ 0x80000000ULL, 0x70000000ULL);
+
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
+ sysbus_init_mmio(sbd, &s->pci_hole);
}
static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
@@ -247,31 +252,6 @@ static void pci_unin_internal_init(Object *obj)
sysbus_init_mmio(sbd, &h->data_mem);
}
-UNINState *pci_pmac_u3_init(qemu_irq *pic,
- MemoryRegion *address_space_mem)
-{
- DeviceState *dev;
- SysBusDevice *s;
- UNINState *d;
-
- /* Uninorth AGP bus */
- dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
- qdev_prop_set_ptr(dev, "pic-irqs", pic);
- qdev_init_nofail(dev);
- s = SYS_BUS_DEVICE(dev);
- d = U3_AGP_HOST_BRIDGE(dev);
-
- memory_region_init_alias(&d->pci_hole, OBJECT(d), "pci-hole", &d->pci_mmio,
- 0x80000000ULL, 0x70000000ULL);
- memory_region_add_subregion(address_space_mem, 0x80000000ULL,
- &d->pci_hole);
-
- sysbus_mmio_map(s, 0, 0xf0800000);
- sysbus_mmio_map(s, 1, 0xf0c00000);
-
- return d;
-}
-
static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
{
/* cache_line_size */
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 3033fc0d7e..2360b24a12 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -345,7 +345,18 @@ static void ppc_core99_init(MachineState *machine)
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
- uninorth_pci = pci_pmac_u3_init(pic, get_system_memory());
+ /* Uninorth AGP bus */
+ dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
+ qdev_prop_set_ptr(dev, "pic-irqs", pic);
+ qdev_init_nofail(dev);
+ uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
+ s = SYS_BUS_DEVICE(dev);
+ /* PCI hole */
+ memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
+ sysbus_mmio_get_region(s, 2));
+ sysbus_mmio_map(s, 0, 0xf0800000);
+ sysbus_mmio_map(s, 1, 0xf0c00000);
+
machine_arch = ARCH_MAC99_U3;
} else {
/* Use values found on a real PowerMac */
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 20/49] uninorth: use object link to pass OpenPIC object to uninorth
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (18 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 19/49] uninorth: remove obsolete pci_pmac_u3_init() function David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 21/49] uninorth: move PCI IO (ISA) memory region into the uninorth device David Gibson
` (30 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Now that the OpenPIC is wired up via the board, we can now remove our temporary
PIC qdev pointer property and replace it with an object link instead.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 73 +++++++++++++++++++++++++-----------------
hw/ppc/mac_newworld.c | 12 ++++---
include/hw/pci-host/uninorth.h | 5 ++-
3 files changed, 55 insertions(+), 35 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index ec6e529d66..e2278fd0f0 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -38,10 +38,10 @@ static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
- qemu_irq *pic = opaque;
+ UNINState *s = opaque;
trace_unin_set_irq(unin_irq_line[irq_num], level);
- qemu_set_irq(pic[unin_irq_line[irq_num]], level);
+ qemu_set_irq(s->irqs[irq_num], level);
}
static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
@@ -109,6 +109,15 @@ static const MemoryRegionOps unin_data_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
+static void pci_unin_init_irqs(UNINState *s)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
+ s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
+ }
+}
+
static void pci_unin_main_realize(DeviceState *dev, Error **errp)
{
UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
@@ -116,12 +125,13 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp)
h->bus = pci_register_root_bus(dev, NULL,
pci_unin_set_irq, pci_unin_map_irq,
- s->pic_irqs,
+ s,
&s->pci_mmio,
get_system_io(),
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
+ pci_unin_init_irqs(s);
/* DEC 21154 bridge */
#if 0
@@ -150,6 +160,11 @@ static void pci_unin_main_init(Object *obj)
"unin-pci-hole", &s->pci_mmio,
0x80000000ULL, 0x10000000ULL);
+ object_property_add_link(obj, "pic", TYPE_OPENPIC,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
sysbus_init_mmio(sbd, &s->pci_hole);
@@ -162,12 +177,13 @@ static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
h->bus = pci_register_root_bus(dev, NULL,
pci_unin_set_irq, pci_unin_map_irq,
- s->pic_irqs,
+ s,
&s->pci_mmio,
get_system_io(),
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
+ pci_unin_init_irqs(s);
}
static void pci_u3_agp_init(Object *obj)
@@ -189,6 +205,11 @@ static void pci_u3_agp_init(Object *obj)
"unin-pci-hole", &s->pci_mmio,
0x80000000ULL, 0x70000000ULL);
+ object_property_add_link(obj, "pic", TYPE_OPENPIC,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
sysbus_init_mmio(sbd, &s->pci_hole);
@@ -201,16 +222,18 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
h->bus = pci_register_root_bus(dev, NULL,
pci_unin_set_irq, pci_unin_map_irq,
- s->pic_irqs,
+ s,
&s->pci_mmio,
get_system_io(),
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
+ pci_unin_init_irqs(s);
}
static void pci_unin_agp_init(Object *obj)
{
+ UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
@@ -219,6 +242,12 @@ static void pci_unin_agp_init(Object *obj)
obj, "unin-agp-conf-idx", 0x1000);
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
obj, "unin-agp-conf-data", 0x1000);
+
+ object_property_add_link(obj, "pic", TYPE_OPENPIC,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
}
@@ -230,16 +259,18 @@ static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
h->bus = pci_register_root_bus(dev, NULL,
pci_unin_set_irq, pci_unin_map_irq,
- s->pic_irqs,
+ s,
&s->pci_mmio,
get_system_io(),
PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
+ pci_unin_init_irqs(s);
}
static void pci_unin_internal_init(Object *obj)
{
+ UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
@@ -248,6 +279,12 @@ static void pci_unin_internal_init(Object *obj)
obj, "unin-pci-conf-idx", 0x1000);
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
obj, "unin-pci-conf-data", 0x1000);
+
+ object_property_add_link(obj, "pic", TYPE_OPENPIC,
+ (Object **) &s->pic,
+ qdev_prop_allow_set_link_before_realize,
+ 0, NULL);
+
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
}
@@ -412,17 +449,11 @@ static const TypeInfo unin_internal_pci_host_info = {
},
};
-static Property pci_unin_main_properties[] = {
- DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void pci_unin_main_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pci_unin_main_realize;
- dc->props = pci_unin_main_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -434,17 +465,11 @@ static const TypeInfo pci_unin_main_info = {
.class_init = pci_unin_main_class_init,
};
-static Property pci_u3_agp_properties[] = {
- DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pci_u3_agp_realize;
- dc->props = pci_u3_agp_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -456,17 +481,11 @@ static const TypeInfo pci_u3_agp_info = {
.class_init = pci_u3_agp_class_init,
};
-static Property pci_unin_agp_class_properties[] = {
- DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pci_unin_agp_realize;
- dc->props = pci_unin_agp_class_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
@@ -478,17 +497,11 @@ static const TypeInfo pci_unin_agp_info = {
.class_init = pci_unin_agp_class_init,
};
-static Property pci_unin_internal_class_properties[] = {
- DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = pci_unin_internal_realize;
- dc->props = pci_unin_internal_class_properties;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index 2360b24a12..e05aa26c3d 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -347,7 +347,8 @@ static void ppc_core99_init(MachineState *machine)
/* 970 gets a U3 bus */
/* Uninorth AGP bus */
dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
- qdev_prop_set_ptr(dev, "pic-irqs", pic);
+ object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
+ &error_abort);
qdev_init_nofail(dev);
uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
@@ -362,7 +363,8 @@ static void ppc_core99_init(MachineState *machine)
/* Use values found on a real PowerMac */
/* Uninorth AGP bus */
dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
- qdev_prop_set_ptr(dev, "pic-irqs", pic);
+ object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
+ &error_abort);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0xf0800000);
@@ -370,7 +372,8 @@ static void ppc_core99_init(MachineState *machine)
/* Uninorth internal bus */
dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
- qdev_prop_set_ptr(dev, "pic-irqs", pic);
+ object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
+ &error_abort);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, 0xf4800000);
@@ -378,7 +381,8 @@ static void ppc_core99_init(MachineState *machine)
/* Uninorth main bus */
dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
- qdev_prop_set_ptr(dev, "pic-irqs", pic);
+ object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
+ &error_abort);
qdev_init_nofail(dev);
uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
s = SYS_BUS_DEVICE(dev);
diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h
index e4fa11c145..e048fd56e8 100644
--- a/include/hw/pci-host/uninorth.h
+++ b/include/hw/pci-host/uninorth.h
@@ -27,6 +27,8 @@
#include "hw/hw.h"
+#include "hw/ppc/openpic.h"
+
#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
@@ -44,7 +46,8 @@
typedef struct UNINState {
PCIHostState parent_obj;
- void *pic_irqs;
+ OpenPICState *pic;
+ qemu_irq irqs[4];
MemoryRegion pci_mmio;
MemoryRegion pci_hole;
} UNINState;
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 21/49] uninorth: move PCI IO (ISA) memory region into the uninorth device
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (19 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 20/49] uninorth: use object link to pass OpenPIC object to uninorth David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 22/49] uninorth: rename UNINState to UNINHostState David Gibson
` (29 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Do this for both the uninorth main and uninorth u3 AGP buses, using the main
PCI bus for each machine (this ensures the IO addresses still match those
used by OpenBIOS).
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 14 ++++++++++----
hw/ppc/mac_newworld.c | 12 ++++++------
include/hw/pci-host/uninorth.h | 1 +
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index e2278fd0f0..3a29a4410e 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -127,7 +127,7 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp)
pci_unin_set_irq, pci_unin_map_irq,
s,
&s->pci_mmio,
- get_system_io(),
+ &s->pci_io,
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
@@ -155,6 +155,8 @@ static void pci_unin_main_init(Object *obj)
memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
0x100000000ULL);
+ memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
+ "unin-pci-isa-mmio", 0x00800000);
memory_region_init_alias(&s->pci_hole, OBJECT(s),
"unin-pci-hole", &s->pci_mmio,
@@ -168,6 +170,7 @@ static void pci_unin_main_init(Object *obj)
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
sysbus_init_mmio(sbd, &s->pci_hole);
+ sysbus_init_mmio(sbd, &s->pci_io);
}
static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
@@ -179,7 +182,7 @@ static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
pci_unin_set_irq, pci_unin_map_irq,
s,
&s->pci_mmio,
- get_system_io(),
+ &s->pci_io,
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
@@ -200,6 +203,8 @@ static void pci_u3_agp_init(Object *obj)
memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
0x100000000ULL);
+ memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
+ "unin-pci-isa-mmio", 0x00800000);
memory_region_init_alias(&s->pci_hole, OBJECT(s),
"unin-pci-hole", &s->pci_mmio,
@@ -213,6 +218,7 @@ static void pci_u3_agp_init(Object *obj)
sysbus_init_mmio(sbd, &h->conf_mem);
sysbus_init_mmio(sbd, &h->data_mem);
sysbus_init_mmio(sbd, &s->pci_hole);
+ sysbus_init_mmio(sbd, &s->pci_io);
}
static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
@@ -224,7 +230,7 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
pci_unin_set_irq, pci_unin_map_irq,
s,
&s->pci_mmio,
- get_system_io(),
+ &s->pci_io,
PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
@@ -261,7 +267,7 @@ static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
pci_unin_set_irq, pci_unin_map_irq,
s,
&s->pci_mmio,
- get_system_io(),
+ &s->pci_io,
PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index e05aa26c3d..bd7ffdb0fb 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -145,7 +145,6 @@ static void ppc_core99_init(MachineState *machine)
CPUPPCState *env = NULL;
char *filename;
qemu_irq *pic, **openpic_irqs;
- MemoryRegion *isa = g_new(MemoryRegion, 1);
MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
int linux_boot, i, j, k;
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
@@ -273,11 +272,6 @@ static void ppc_core99_init(MachineState *machine)
}
}
- /* Register 8 MB of ISA IO space */
- memory_region_init_alias(isa, NULL, "isa_mmio",
- get_system_io(), 0, 0x00800000);
- memory_region_add_subregion(get_system_memory(), 0xf2000000, isa);
-
/* UniN init: XXX should be a real device */
memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000);
memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
@@ -355,6 +349,9 @@ static void ppc_core99_init(MachineState *machine)
/* PCI hole */
memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
sysbus_mmio_get_region(s, 2));
+ /* Register 8 MB of ISA IO space */
+ memory_region_add_subregion(get_system_memory(), 0xf2000000,
+ sysbus_mmio_get_region(s, 3));
sysbus_mmio_map(s, 0, 0xf0800000);
sysbus_mmio_map(s, 1, 0xf0c00000);
@@ -389,6 +386,9 @@ static void ppc_core99_init(MachineState *machine)
/* PCI hole */
memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
sysbus_mmio_get_region(s, 2));
+ /* Register 8 MB of ISA IO space */
+ memory_region_add_subregion(get_system_memory(), 0xf2000000,
+ sysbus_mmio_get_region(s, 3));
sysbus_mmio_map(s, 0, 0xf2800000);
sysbus_mmio_map(s, 1, 0xf2c00000);
diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h
index e048fd56e8..a953b5e9b1 100644
--- a/include/hw/pci-host/uninorth.h
+++ b/include/hw/pci-host/uninorth.h
@@ -50,6 +50,7 @@ typedef struct UNINState {
qemu_irq irqs[4];
MemoryRegion pci_mmio;
MemoryRegion pci_hole;
+ MemoryRegion pci_io;
} UNINState;
#endif /* UNINORTH_H */
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 22/49] uninorth: rename UNINState to UNINHostState
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (20 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 21/49] uninorth: move PCI IO (ISA) memory region into the uninorth device David Gibson
@ 2018-04-27 9:20 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 23/49] ppc: Fix size of ppc64 xer register David Gibson
` (28 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:20 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Mark Cave-Ayland, David Gibson
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
The existing UNINState actually represents the PCI/AGP host bridge stage so
rename it accordingly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/pci-host/uninorth.c | 32 ++++++++++++++++----------------
hw/ppc/mac.h | 8 ++++----
hw/ppc/mac_newworld.c | 2 +-
include/hw/pci-host/uninorth.h | 12 ++++++------
4 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 3a29a4410e..fada0ffd5f 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -38,7 +38,7 @@ static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
- UNINState *s = opaque;
+ UNINHostState *s = opaque;
trace_unin_set_irq(unin_irq_line[irq_num], level);
qemu_set_irq(s->irqs[irq_num], level);
@@ -81,7 +81,7 @@ static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
static void unin_data_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
- UNINState *s = opaque;
+ UNINHostState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
trace_unin_data_write(addr, len, val);
pci_data_write(phb->bus,
@@ -92,7 +92,7 @@ static void unin_data_write(void *opaque, hwaddr addr,
static uint64_t unin_data_read(void *opaque, hwaddr addr,
unsigned len)
{
- UNINState *s = opaque;
+ UNINHostState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t val;
@@ -109,7 +109,7 @@ static const MemoryRegionOps unin_data_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void pci_unin_init_irqs(UNINState *s)
+static void pci_unin_init_irqs(UNINHostState *s)
{
int i;
@@ -120,7 +120,7 @@ static void pci_unin_init_irqs(UNINState *s)
static void pci_unin_main_realize(DeviceState *dev, Error **errp)
{
- UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
+ UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
PCIHostState *h = PCI_HOST_BRIDGE(dev);
h->bus = pci_register_root_bus(dev, NULL,
@@ -142,7 +142,7 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp)
static void pci_unin_main_init(Object *obj)
{
- UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
+ UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
@@ -175,7 +175,7 @@ static void pci_unin_main_init(Object *obj)
static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
{
- UNINState *s = U3_AGP_HOST_BRIDGE(dev);
+ UNINHostState *s = U3_AGP_HOST_BRIDGE(dev);
PCIHostState *h = PCI_HOST_BRIDGE(dev);
h->bus = pci_register_root_bus(dev, NULL,
@@ -191,7 +191,7 @@ static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
static void pci_u3_agp_init(Object *obj)
{
- UNINState *s = U3_AGP_HOST_BRIDGE(obj);
+ UNINHostState *s = U3_AGP_HOST_BRIDGE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
@@ -223,7 +223,7 @@ static void pci_u3_agp_init(Object *obj)
static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
{
- UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
+ UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
PCIHostState *h = PCI_HOST_BRIDGE(dev);
h->bus = pci_register_root_bus(dev, NULL,
@@ -239,7 +239,7 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
static void pci_unin_agp_init(Object *obj)
{
- UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj);
+ UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
@@ -260,7 +260,7 @@ static void pci_unin_agp_init(Object *obj)
static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
{
- UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev);
+ UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev);
PCIHostState *h = PCI_HOST_BRIDGE(dev);
h->bus = pci_register_root_bus(dev, NULL,
@@ -276,7 +276,7 @@ static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
static void pci_unin_internal_init(Object *obj)
{
- UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj);
+ UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
PCIHostState *h = PCI_HOST_BRIDGE(obj);
@@ -466,7 +466,7 @@ static void pci_unin_main_class_init(ObjectClass *klass, void *data)
static const TypeInfo pci_unin_main_info = {
.name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(UNINState),
+ .instance_size = sizeof(UNINHostState),
.instance_init = pci_unin_main_init,
.class_init = pci_unin_main_class_init,
};
@@ -482,7 +482,7 @@ static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
static const TypeInfo pci_u3_agp_info = {
.name = TYPE_U3_AGP_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(UNINState),
+ .instance_size = sizeof(UNINHostState),
.instance_init = pci_u3_agp_init,
.class_init = pci_u3_agp_class_init,
};
@@ -498,7 +498,7 @@ static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
static const TypeInfo pci_unin_agp_info = {
.name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(UNINState),
+ .instance_size = sizeof(UNINHostState),
.instance_init = pci_unin_agp_init,
.class_init = pci_unin_agp_class_init,
};
@@ -514,7 +514,7 @@ static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
static const TypeInfo pci_unin_internal_info = {
.name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
.parent = TYPE_PCI_HOST_BRIDGE,
- .instance_size = sizeof(UNINState),
+ .instance_size = sizeof(UNINHostState),
.instance_init = pci_unin_internal_init,
.class_init = pci_unin_internal_class_init,
};
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index 1ab2a3b354..892dd03789 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -89,10 +89,10 @@ void macio_init(PCIDevice *dev,
#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
/* UniNorth PCI */
-UNINState *pci_pmac_init(qemu_irq *pic,
- MemoryRegion *address_space_mem);
-UNINState *pci_pmac_u3_init(qemu_irq *pic,
- MemoryRegion *address_space_mem);
+UNINHostState *pci_pmac_init(qemu_irq *pic,
+ MemoryRegion *address_space_mem);
+UNINHostState *pci_pmac_u3_init(qemu_irq *pic,
+ MemoryRegion *address_space_mem);
/* Mac NVRAM */
#define TYPE_MACIO_NVRAM "macio-nvram"
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
index bd7ffdb0fb..29bd3838bf 100644
--- a/hw/ppc/mac_newworld.c
+++ b/hw/ppc/mac_newworld.c
@@ -150,7 +150,7 @@ static void ppc_core99_init(MachineState *machine)
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
hwaddr kernel_base, initrd_base, cmdline_base = 0;
long kernel_size, initrd_size;
- UNINState *uninorth_pci;
+ UNINHostState *uninorth_pci;
PCIBus *pci_bus;
NewWorldMacIOState *macio;
MACIOIDEState *macio_ide;
diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h
index a953b5e9b1..f0e6836c76 100644
--- a/include/hw/pci-host/uninorth.h
+++ b/include/hw/pci-host/uninorth.h
@@ -35,15 +35,15 @@
#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
+ OBJECT_CHECK(UNINHostState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
+ OBJECT_CHECK(UNINHostState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
+ OBJECT_CHECK(UNINHostState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
#define U3_AGP_HOST_BRIDGE(obj) \
- OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
+ OBJECT_CHECK(UNINHostState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
-typedef struct UNINState {
+typedef struct UNINHostState {
PCIHostState parent_obj;
OpenPICState *pic;
@@ -51,6 +51,6 @@ typedef struct UNINState {
MemoryRegion pci_mmio;
MemoryRegion pci_hole;
MemoryRegion pci_io;
-} UNINState;
+} UNINHostState;
#endif /* UNINORTH_H */
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 23/49] ppc: Fix size of ppc64 xer register
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (21 preceding siblings ...)
2018-04-27 9:20 ` [Qemu-devel] [PULL 22/49] uninorth: rename UNINState to UNINHostState David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 24/49] target/ppc: Fix reserved bit mask of dstst instruction David Gibson
` (27 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Michael Matz, David Gibson
From: Michael Matz <matz@suse.de>
The normal gdb definition of the XER registers is only 32 bit,
and that's what the current version of power64-core.xml also
says (seems copied from gdb's). But qemu's idea of the XER register
is target_ulong (in CPUPPCState, ppc_gdb_register_len and
ppc_cpu_gdb_read_register)
That mismatch leads to the following message when attaching
with gdb:
Truncated register 32 in remote 'g' packet
(and following on that qemu stops responding). The simple fix is
to say the truth in the .xml file. But the better fix is to
actually make it 32bit on the wire, as old gdbs don't support
XML files for describing registers. Also the XER state in qemu
doesn't seem to use the high 32 bits, so sending it off to gdb
doesn't seem worthwhile.
Signed-off-by: Michael Matz <matz@suse.de>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/gdbstub.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 7a338136a8..b6f6693583 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -37,10 +37,10 @@ static int ppc_gdb_register_len_apple(int n)
case 65+32: /* msr */
case 67+32: /* lr */
case 68+32: /* ctr */
- case 69+32: /* xer */
case 70+32: /* fpscr */
return 8;
case 66+32: /* cr */
+ case 69+32: /* xer */
return 4;
default:
return 0;
@@ -61,6 +61,8 @@ static int ppc_gdb_register_len(int n)
return 8;
case 66:
/* cr */
+ case 69:
+ /* xer */
return 4;
case 64:
/* nip */
@@ -70,8 +72,6 @@ static int ppc_gdb_register_len(int n)
/* lr */
case 68:
/* ctr */
- case 69:
- /* xer */
return sizeof(target_ulong);
case 70:
/* fpscr */
@@ -152,7 +152,7 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
gdb_get_regl(mem_buf, env->ctr);
break;
case 69:
- gdb_get_regl(mem_buf, env->xer);
+ gdb_get_reg32(mem_buf, env->xer);
break;
case 70:
gdb_get_reg32(mem_buf, env->fpscr);
@@ -208,7 +208,7 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
gdb_get_reg64(mem_buf, env->ctr);
break;
case 69 + 32:
- gdb_get_reg64(mem_buf, env->xer);
+ gdb_get_reg32(mem_buf, env->xer);
break;
case 70 + 32:
gdb_get_reg64(mem_buf, env->fpscr);
@@ -259,7 +259,7 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
env->ctr = ldtul_p(mem_buf);
break;
case 69:
- env->xer = ldtul_p(mem_buf);
+ env->xer = ldl_p(mem_buf);
break;
case 70:
/* fpscr */
@@ -309,7 +309,7 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
env->ctr = ldq_p(mem_buf);
break;
case 69 + 32:
- env->xer = ldq_p(mem_buf);
+ env->xer = ldl_p(mem_buf);
break;
case 70 + 32:
/* fpscr */
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 24/49] target/ppc: Fix reserved bit mask of dstst instruction
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (22 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 23/49] ppc: Fix size of ppc64 xer register David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 25/49] spapr: Introduce pseries-2.13 machine type David Gibson
` (26 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, BALATON Zoltan, David Gibson
From: BALATON Zoltan <balaton@eik.bme.hu>
According to the Vector/SIMD extension documentation bit 6 that is
currently masked is valid (listed as transient bit) but bits 7 and 8
should be reserved instead. Fix the mask to match this.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3457d29f8e..b0d79a3fb9 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6561,7 +6561,7 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
-GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
+GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 25/49] spapr: Introduce pseries-2.13 machine type
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (23 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 24/49] target/ppc: Fix reserved bit mask of dstst instruction David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 26/49] Make qemu_mempath_getpagesize() accept NULL David Gibson
` (25 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 23 +++++++++++++++++++++--
include/hw/compat.h | 2 ++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 92194a9a53..b92dad2273 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3984,19 +3984,38 @@ static const TypeInfo spapr_machine_info = {
} \
type_init(spapr_machine_register_##suffix)
+/*
+ * pseries-2.13
+ */
+static void spapr_machine_2_13_instance_options(MachineState *machine)
+{
+}
+
+static void spapr_machine_2_13_class_options(MachineClass *mc)
+{
+ /* Defaults for the latest behaviour inherited from the base class */
+}
+
+DEFINE_SPAPR_MACHINE(2_13, "2.13", true);
+
/*
* pseries-2.12
*/
+#define SPAPR_COMPAT_2_12 \
+ HW_COMPAT_2_12
+
static void spapr_machine_2_12_instance_options(MachineState *machine)
{
+ spapr_machine_2_13_instance_options(machine);
}
static void spapr_machine_2_12_class_options(MachineClass *mc)
{
- /* Defaults for the latest behaviour inherited from the base class */
+ spapr_machine_2_13_class_options(mc);
+ SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12);
}
-DEFINE_SPAPR_MACHINE(2_12, "2.12", true);
+DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine)
{
diff --git a/include/hw/compat.h b/include/hw/compat.h
index 13242b831a..4681c2719a 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -1,6 +1,8 @@
#ifndef HW_COMPAT_H
#define HW_COMPAT_H
+#define HW_COMPAT_2_12
+
#define HW_COMPAT_2_11 \
{\
.driver = "hpet",\
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 26/49] Make qemu_mempath_getpagesize() accept NULL
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (24 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 25/49] spapr: Introduce pseries-2.13 machine type David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 27/49] Add host_memory_backend_pagesize() helper David Gibson
` (24 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
qemu_mempath_getpagesize() gets the effective (host side) page size for
a block of memory backed by an mmap()ed file on the host. It requires
the mem_path parameter to be non-NULL.
This ends up meaning all the callers need a different case for handling
anonymous memory (for memory-backend-ram or default memory with -mem-path
is not specified).
We can make all those callers a little simpler by having
qemu_mempath_getpagesize() accept NULL, and treat that as the anonymous
memory case.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
---
exec.c | 21 ++++++---------------
target/ppc/kvm.c | 8 ++------
util/mmap-alloc.c | 26 ++++++++++++++------------
3 files changed, 22 insertions(+), 33 deletions(-)
diff --git a/exec.c b/exec.c
index 02b1efebb7..b38b004563 100644
--- a/exec.c
+++ b/exec.c
@@ -1488,19 +1488,14 @@ void ram_block_dump(Monitor *mon)
*/
static int find_max_supported_pagesize(Object *obj, void *opaque)
{
- char *mem_path;
long *hpsize_min = opaque;
if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
- mem_path = object_property_get_str(obj, "mem-path", NULL);
- if (mem_path) {
- long hpsize = qemu_mempath_getpagesize(mem_path);
- g_free(mem_path);
- if (hpsize < *hpsize_min) {
- *hpsize_min = hpsize;
- }
- } else {
- *hpsize_min = getpagesize();
+ char *mem_path = object_property_get_str(obj, "mem-path", NULL);
+ long hpsize = qemu_mempath_getpagesize(mem_path);
+ g_free(mem_path);
+ if (hpsize < *hpsize_min) {
+ *hpsize_min = hpsize;
}
}
@@ -1513,11 +1508,7 @@ long qemu_getrampagesize(void)
long mainrampagesize;
Object *memdev_root;
- if (mem_path) {
- mainrampagesize = qemu_mempath_getpagesize(mem_path);
- } else {
- mainrampagesize = getpagesize();
- }
+ mainrampagesize = qemu_mempath_getpagesize(mem_path);
/* it's possible we have memory-backend objects with
* hugepage-backed RAM. these may get mapped into system
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 79a436a384..e24fa50dc9 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -499,12 +499,8 @@ bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
char *mempath = object_property_get_str(mem_obj, "mem-path", NULL);
long pagesize;
- if (mempath) {
- pagesize = qemu_mempath_getpagesize(mempath);
- g_free(mempath);
- } else {
- pagesize = getpagesize();
- }
+ pagesize = qemu_mempath_getpagesize(mempath);
+ g_free(mempath);
return pagesize >= max_cpu_page_size;
}
diff --git a/util/mmap-alloc.c b/util/mmap-alloc.c
index 2fd8cbcc6f..fd329eccd8 100644
--- a/util/mmap-alloc.c
+++ b/util/mmap-alloc.c
@@ -50,19 +50,21 @@ size_t qemu_mempath_getpagesize(const char *mem_path)
struct statfs fs;
int ret;
- do {
- ret = statfs(mem_path, &fs);
- } while (ret != 0 && errno == EINTR);
-
- if (ret != 0) {
- fprintf(stderr, "Couldn't statfs() memory path: %s\n",
- strerror(errno));
- exit(1);
- }
+ if (mem_path) {
+ do {
+ ret = statfs(mem_path, &fs);
+ } while (ret != 0 && errno == EINTR);
- if (fs.f_type == HUGETLBFS_MAGIC) {
- /* It's hugepage, return the huge page size */
- return fs.f_bsize;
+ if (ret != 0) {
+ fprintf(stderr, "Couldn't statfs() memory path: %s\n",
+ strerror(errno));
+ exit(1);
+ }
+
+ if (fs.f_type == HUGETLBFS_MAGIC) {
+ /* It's hugepage, return the huge page size */
+ return fs.f_bsize;
+ }
}
#ifdef __sparc__
/* SPARC Linux needs greater alignment than the pagesize */
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 27/49] Add host_memory_backend_pagesize() helper
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (25 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 26/49] Make qemu_mempath_getpagesize() accept NULL David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 28/49] spapr: drop useless sanity check in spapr_irq_alloc*() David Gibson
` (23 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
There are a couple places (one generic, one target specific) where we need
to get the host page size associated with a particular memory backend. I
have some upcoming code which will add another place which wants this. So,
for convenience, add a helper function to calculate this.
host_memory_backend_pagesize() returns the host pagesize for a given
HostMemoryBackend object.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
---
backends/hostmem.c | 18 ++++++++++++++++++
exec.c | 5 ++---
include/sysemu/hostmem.h | 2 ++
target/ppc/kvm.c | 6 +-----
4 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/backends/hostmem.c b/backends/hostmem.c
index f61093654e..6a0c474222 100644
--- a/backends/hostmem.c
+++ b/backends/hostmem.c
@@ -18,6 +18,7 @@
#include "qapi/visitor.h"
#include "qemu/config-file.h"
#include "qom/object_interfaces.h"
+#include "qemu/mmap-alloc.h"
#ifdef CONFIG_NUMA
#include <numaif.h>
@@ -262,6 +263,23 @@ bool host_memory_backend_is_mapped(HostMemoryBackend *backend)
return backend->is_mapped;
}
+#ifdef __linux__
+size_t host_memory_backend_pagesize(HostMemoryBackend *memdev)
+{
+ Object *obj = OBJECT(memdev);
+ char *path = object_property_get_str(obj, "mem-path", NULL);
+ size_t pagesize = qemu_mempath_getpagesize(path);
+
+ g_free(path);
+ return pagesize;
+}
+#else
+size_t host_memory_backend_pagesize(HostMemoryBackend *memdev)
+{
+ return getpagesize();
+}
+#endif
+
static void
host_memory_backend_memory_complete(UserCreatable *uc, Error **errp)
{
diff --git a/exec.c b/exec.c
index b38b004563..c7fcefa851 100644
--- a/exec.c
+++ b/exec.c
@@ -1491,9 +1491,8 @@ static int find_max_supported_pagesize(Object *obj, void *opaque)
long *hpsize_min = opaque;
if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) {
- char *mem_path = object_property_get_str(obj, "mem-path", NULL);
- long hpsize = qemu_mempath_getpagesize(mem_path);
- g_free(mem_path);
+ long hpsize = host_memory_backend_pagesize(MEMORY_BACKEND(obj));
+
if (hpsize < *hpsize_min) {
*hpsize_min = hpsize;
}
diff --git a/include/sysemu/hostmem.h b/include/sysemu/hostmem.h
index 47bc9846ac..bc36899bb8 100644
--- a/include/sysemu/hostmem.h
+++ b/include/sysemu/hostmem.h
@@ -68,4 +68,6 @@ MemoryRegion *host_memory_backend_get_memory(HostMemoryBackend *backend,
void host_memory_backend_set_mapped(HostMemoryBackend *backend, bool mapped);
bool host_memory_backend_is_mapped(HostMemoryBackend *backend);
+size_t host_memory_backend_pagesize(HostMemoryBackend *memdev);
+
#endif
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index e24fa50dc9..f62f7ac288 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -496,11 +496,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
{
Object *mem_obj = object_resolve_path(obj_path, NULL);
- char *mempath = object_property_get_str(mem_obj, "mem-path", NULL);
- long pagesize;
-
- pagesize = qemu_mempath_getpagesize(mempath);
- g_free(mempath);
+ long pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(mem_obj));
return pagesize >= max_cpu_page_size;
}
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 28/49] spapr: drop useless sanity check in spapr_irq_alloc*()
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (26 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 27/49] Add host_memory_backend_pagesize() helper David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 29/49] Revert "spapr: Don't allow memory hotplug to memory less nodes" David Gibson
` (22 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
From: Greg Kurz <groug@kaod.org>
Both spapr_irq_alloc() and spapr_irq_alloc_block() have an errp
parameter, but they don't use it if XICS hasn't been initialized
yet.
This is doubly wrong:
- all callers do pass a non-null Error **, ie, they expect an error
to be propagated in case of failure
- XICS obviously needs to be initialized before anything starts allocating
IRQs
So this patch turns the check into an assert.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b92dad2273..5a1c1e25e1 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3719,9 +3719,8 @@ int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
ICSState *ics = spapr->ics;
int irq;
- if (!ics) {
- return -1;
- }
+ assert(ics);
+
if (irq_hint) {
if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
@@ -3753,9 +3752,7 @@ int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
ICSState *ics = spapr->ics;
int i, first = -1;
- if (!ics) {
- return -1;
- }
+ assert(ics);
/*
* MSIMesage::data is used for storing VIRQ so
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 29/49] Revert "spapr: Don't allow memory hotplug to memory less nodes"
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (27 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 28/49] spapr: drop useless sanity check in spapr_irq_alloc*() David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 30/49] spapr: drop useless dynamic sysbus device sanity check David Gibson
` (21 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Serhii Popovych, David Gibson
From: Serhii Popovych <spopovyc@redhat.com>
This reverts commit b556854bd8524c26b8be98ab1bfdf0826831e793.
Leave change @node type from uint32_t to to int from reverted commit
because node < 0 is always false.
Note that implementing capability or some trick to detect if guest
kernel does not support hot-add to memory: this returns previous
behavour where memory added to first non-empty node.
Signed-off-by: Serhii Popovych <spopovyc@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 22 ----------------------
1 file changed, 22 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 5a1c1e25e1..fc86ba6934 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -3478,28 +3478,6 @@ static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
return;
}
- /*
- * Currently PowerPC kernel doesn't allow hot-adding memory to
- * memory-less node, but instead will silently add the memory
- * to the first node that has some memory. This causes two
- * unexpected behaviours for the user.
- *
- * - Memory gets hotplugged to a different node than what the user
- * specified.
- * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
- * to memory-less node, a reboot will set things accordingly
- * and the previously hotplugged memory now ends in the right node.
- * This appears as if some memory moved from one node to another.
- *
- * So until kernel starts supporting memory hotplug to memory-less
- * nodes, just prevent such attempts upfront in QEMU.
- */
- if (nb_numa_nodes && !numa_info[node].node_mem) {
- error_setg(errp, "Can't hotplug memory to memory-less node %d",
- node);
- return;
- }
-
spapr_memory_plug(hotplug_dev, dev, node, errp);
} else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
spapr_core_plug(hotplug_dev, dev, errp);
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 30/49] spapr: drop useless dynamic sysbus device sanity check
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (28 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 29/49] Revert "spapr: Don't allow memory hotplug to memory less nodes" David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 31/49] target/ppc: Standardize instance_init and realize function names David Gibson
` (20 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
From: Greg Kurz <groug@kaod.org>
Since commit 7da79a167aa11, the machine class init function registers
dynamic sysbus device types it supports. Passing an unsupported device
type on the command line causes QEMU to exit with an error message
just after machine init.
It is hence not needed to do the same sanity check at machine reset.
Signed-off-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index fc86ba6934..d35a88ca80 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1440,21 +1440,6 @@ void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
}
}
-static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
-{
- bool matched = false;
-
- if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
- matched = true;
- }
-
- if (!matched) {
- error_report("Device %s is not supported by this machine yet.",
- qdev_fw_name(DEVICE(sbdev)));
- exit(1);
- }
-}
-
static int spapr_reset_drcs(Object *child, void *opaque)
{
sPAPRDRConnector *drc =
@@ -1478,9 +1463,6 @@ static void spapr_machine_reset(void)
void *fdt;
int rc;
- /* Check for unknown sysbus devices */
- foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
-
spapr_caps_reset(spapr);
first_ppc_cpu = POWERPC_CPU(first_cpu);
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 31/49] target/ppc: Standardize instance_init and realize function names
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (29 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 30/49] spapr: drop useless dynamic sysbus device sanity check David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 32/49] target/ppc: Simplify cpu valid check in ppc_cpu_realize David Gibson
` (19 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
Because of the various hooks called some variant on "init" - and the rather
greater number that used to exist, I'm always wondering when a function
called simply "*_init" or "*_initfn" will be called.
To make it easier on myself, and maybe others, rename the instance_init
hooks for ppc cpus to *_instance_init(). While we're at it rename the
realize time hooks to *_realize() (from *_realizefn()) which seems to be
the more common current convention.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
target/ppc/translate_init.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 391b94b97d..56b80a204a 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9726,7 +9726,7 @@ static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
#endif
}
-static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
+static void ppc_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
PowerPCCPU *cpu = POWERPC_CPU(dev);
@@ -9952,7 +9952,7 @@ unrealize:
cpu_exec_unrealizefn(cs);
}
-static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
+static void ppc_cpu_unrealize(DeviceState *dev, Error **errp)
{
PowerPCCPU *cpu = POWERPC_CPU(dev);
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
@@ -10438,7 +10438,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
}
#endif
-static void ppc_cpu_initfn(Object *obj)
+static void ppc_cpu_instance_init(Object *obj)
{
CPUState *cs = CPU(obj);
PowerPCCPU *cpu = POWERPC_CPU(obj);
@@ -10561,9 +10561,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
DeviceClass *dc = DEVICE_CLASS(oc);
- device_class_set_parent_realize(dc, ppc_cpu_realizefn,
+ device_class_set_parent_realize(dc, ppc_cpu_realize,
&pcc->parent_realize);
- device_class_set_parent_unrealize(dc, ppc_cpu_unrealizefn,
+ device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
&pcc->parent_unrealize);
pcc->pvr_match = ppc_pvr_match_default;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
@@ -10623,7 +10623,7 @@ static const TypeInfo ppc_cpu_type_info = {
.name = TYPE_POWERPC_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(PowerPCCPU),
- .instance_init = ppc_cpu_initfn,
+ .instance_init = ppc_cpu_instance_init,
.abstract = true,
.class_size = sizeof(PowerPCCPUClass),
.class_init = ppc_cpu_class_init,
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 32/49] target/ppc: Simplify cpu valid check in ppc_cpu_realize
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (30 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 31/49] target/ppc: Standardize instance_init and realize function names David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 33/49] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() David Gibson
` (18 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
The #if isn't necessary, because there's a suitable one inside
ppc_cpu_is_valid(). We've already filtered for suitable cpu models in the
functions that search and register them. So by the time we get to realize
having an invalid one indicates a code error, not a user error, so an
assert() is more appropriate than error_setg().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
target/ppc/translate_init.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 56b80a204a..2ae718242a 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9749,14 +9749,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
}
}
-#if defined(TARGET_PPCEMB)
- if (!ppc_cpu_is_valid(pcc)) {
- error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
- "Please use qemu-system-ppc or qemu-system-ppc64 instead "
- "or choose another CPU model.");
- goto unrealize;
- }
-#endif
+ assert(ppc_cpu_is_valid(pcc));
create_ppc_opcodes(cpu, &local_err);
if (local_err != NULL) {
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 33/49] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (31 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 32/49] target/ppc: Simplify cpu valid check in ppc_cpu_realize David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 34/49] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions David Gibson
` (17 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this
change will make some things simpler later on.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/fdt.c | 5 +++--
hw/ppc/pnv.c | 4 ++--
hw/ppc/spapr.c | 4 ++--
include/hw/ppc/fdt.h | 2 +-
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c
index 2ffc5866e4..2721603ffa 100644
--- a/hw/ppc/fdt.c
+++ b/hw/ppc/fdt.c
@@ -13,9 +13,10 @@
#include "hw/ppc/fdt.h"
#if defined(TARGET_PPC64)
-size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
- size_t maxsize)
+size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
+ size_t maxsize)
{
+ CPUPPCState *env = &cpu->env;
size_t maxcells = maxsize / sizeof(uint32_t);
int i, j, count;
uint32_t *p = prop;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 549cfccdcb..3220ef8f79 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -209,8 +209,8 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
_FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
}
- page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
- sizeof(page_sizes_prop));
+ page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
+ sizeof(page_sizes_prop));
if (page_sizes_prop_size) {
_FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
page_sizes_prop, page_sizes_prop_size)));
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index d35a88ca80..a4b3722656 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -581,8 +581,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
_FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
}
- page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
- sizeof(page_sizes_prop));
+ page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
+ sizeof(page_sizes_prop));
if (page_sizes_prop_size) {
_FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
page_sizes_prop, page_sizes_prop_size)));
diff --git a/include/hw/ppc/fdt.h b/include/hw/ppc/fdt.h
index bd5b0a8c3d..a8cd85069f 100644
--- a/include/hw/ppc/fdt.h
+++ b/include/hw/ppc/fdt.h
@@ -23,7 +23,7 @@
} \
} while (0)
-size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
+size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
size_t maxsize);
#endif /* PPC_FDT_H */
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 34/49] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (32 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 33/49] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 35/49] target/ppc: Remove fallback 64k pagesize information David Gibson
` (16 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
In most cases we prefer to pass a PowerPCCPU rather than the (embedded)
CPUPPCState.
For ppc_hash64_update_{rmls,vrma}() change to take "cpu" instead of "env".
For ppc_hash64_set_{dsi,isi}() remove the redundant "env" parameter.
In theory this makes more work for the functions, but since "cs", "cpu"
and "env" are related by at most constant offsets, the compiler should be
able to optimize out the difference at effectively zero cost.
helper_*() functions are left alone - since they're more closely tied to
the TCG generated code, passing "env" is still the standard there.
While we're there, fix an incorrect indentation.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/mmu-hash64.c | 35 +++++++++++++++++++----------------
target/ppc/mmu-hash64.h | 4 ++--
target/ppc/translate_init.c | 4 ++--
3 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index c9b72b7429..a87fa7c83f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -633,9 +633,9 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
return 0;
}
-static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
- uint64_t error_code)
+static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code)
{
+ CPUPPCState *env = &POWERPC_CPU(cs)->env;
bool vpm;
if (msr_ir) {
@@ -659,9 +659,9 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
env->error_code = error_code;
}
-static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
- uint64_t dsisr)
+static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr)
{
+ CPUPPCState *env = &POWERPC_CPU(cs)->env;
bool vpm;
if (msr_dr) {
@@ -741,13 +741,13 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
} else {
/* The access failed, generate the approriate interrupt */
if (rwx == 2) {
- ppc_hash64_set_isi(cs, env, SRR1_PROTFAULT);
+ ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
} else {
int dsisr = DSISR_PROTFAULT;
if (rwx == 1) {
dsisr |= DSISR_ISSTORE;
}
- ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
+ ppc_hash64_set_dsi(cs, eaddr, dsisr);
}
return 1;
}
@@ -783,7 +783,7 @@ skip_slb_search:
/* 3. Check for segment level no-execute violation */
if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
- ppc_hash64_set_isi(cs, env, SRR1_NOEXEC_GUARD);
+ ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD);
return 1;
}
@@ -791,13 +791,13 @@ skip_slb_search:
ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
if (ptex == -1) {
if (rwx == 2) {
- ppc_hash64_set_isi(cs, env, SRR1_NOPTE);
+ ppc_hash64_set_isi(cs, SRR1_NOPTE);
} else {
int dsisr = DSISR_NOPTE;
if (rwx == 1) {
dsisr |= DSISR_ISSTORE;
}
- ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
+ ppc_hash64_set_dsi(cs, eaddr, dsisr);
}
return 1;
}
@@ -824,7 +824,7 @@ skip_slb_search:
if (PAGE_EXEC & ~amr_prot) {
srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */
}
- ppc_hash64_set_isi(cs, env, srr1);
+ ppc_hash64_set_isi(cs, srr1);
} else {
int dsisr = 0;
if (need_prot[rwx] & ~pp_prot) {
@@ -836,7 +836,7 @@ skip_slb_search:
if (need_prot[rwx] & ~amr_prot) {
dsisr |= DSISR_AMR;
}
- ppc_hash64_set_dsi(cs, env, eaddr, dsisr);
+ ppc_hash64_set_dsi(cs, eaddr, dsisr);
}
return 1;
}
@@ -942,8 +942,9 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
}
-void ppc_hash64_update_rmls(CPUPPCState *env)
+void ppc_hash64_update_rmls(PowerPCCPU *cpu)
{
+ CPUPPCState *env = &cpu->env;
uint64_t lpcr = env->spr[SPR_LPCR];
/*
@@ -976,8 +977,9 @@ void ppc_hash64_update_rmls(CPUPPCState *env)
}
}
-void ppc_hash64_update_vrma(CPUPPCState *env)
+void ppc_hash64_update_vrma(PowerPCCPU *cpu)
{
+ CPUPPCState *env = &cpu->env;
const struct ppc_one_seg_page_size *sps = NULL;
target_ulong esid, vsid, lpcr;
ppc_slb_t *slb = &env->vrma_slb;
@@ -1002,7 +1004,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env)
vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
esid = SLB_ESID_V;
- for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
+ for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
if (!sps1->page_shift) {
@@ -1028,6 +1030,7 @@ void ppc_hash64_update_vrma(CPUPPCState *env)
void helper_store_lpcr(CPUPPCState *env, target_ulong val)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
uint64_t lpcr = 0;
/* Filter out bits */
@@ -1089,6 +1092,6 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
;
}
env->spr[SPR_LPCR] = lpcr;
- ppc_hash64_update_rmls(env);
- ppc_hash64_update_vrma(env);
+ ppc_hash64_update_rmls(cpu);
+ ppc_hash64_update_vrma(cpu);
}
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index d297b97d37..95a8c330d6 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -17,8 +17,8 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
target_ulong pte0, target_ulong pte1);
unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
uint64_t pte0, uint64_t pte1);
-void ppc_hash64_update_vrma(CPUPPCState *env);
-void ppc_hash64_update_rmls(CPUPPCState *env);
+void ppc_hash64_update_vrma(PowerPCCPU *cpu);
+void ppc_hash64_update_rmls(PowerPCCPU *cpu);
#endif
/*
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 2ae718242a..29bd6f3654 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8975,8 +8975,8 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
/* Update some env bits based on new LPCR value */
- ppc_hash64_update_rmls(env);
- ppc_hash64_update_vrma(env);
+ ppc_hash64_update_rmls(cpu);
+ ppc_hash64_update_vrma(cpu);
/* Tell KVM that we're in PAPR mode */
if (kvm_enabled()) {
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 35/49] target/ppc: Remove fallback 64k pagesize information
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (33 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 34/49] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 36/49] target/ppc: Move page size setup to helper function David Gibson
` (15 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
CPU definitions for cpus with the 64-bit hash MMU can include a table of
available pagesizes. If this isn't supplied ppc_cpu_instance_init() will
fill it in a fallback table based on the POWERPC_MMU_64K bit in mmu_model.
However, it turns out all the cpus which support 64K pages already include
an explicit table of page sizes, so there's no point to the fallback table
including 64k pages.
That removes the only place which tests POWERPC_MMU_64K, so we can remove
it. Which in turn allows some logic to be removed from
kvm_fixup_page_sizes().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
target/ppc/cpu-qom.h | 4 ----
target/ppc/kvm.c | 7 -------
target/ppc/translate_init.c | 20 ++------------------
3 files changed, 2 insertions(+), 29 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index deaa46a14b..9bbb05cf62 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -70,7 +70,6 @@ enum powerpc_mmu_t {
#define POWERPC_MMU_64 0x00010000
#define POWERPC_MMU_1TSEG 0x00020000
#define POWERPC_MMU_AMR 0x00040000
-#define POWERPC_MMU_64K 0x00080000
#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
@@ -78,15 +77,12 @@ enum powerpc_mmu_t {
POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
/* Architecture 2.06 variant */
POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_64K
| POWERPC_MMU_AMR | 0x00000003,
/* Architecture 2.07 variant */
POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_64K
| POWERPC_MMU_AMR | 0x00000004,
/* Architecture 3.00 variant */
POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_64K
| POWERPC_MMU_AMR | POWERPC_MMU_V3
| 0x00000005,
};
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index f62f7ac288..660467aec6 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -425,7 +425,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
static bool has_smmu_info;
CPUPPCState *env = &cpu->env;
int iq, ik, jq, jk;
- bool has_64k_pages = false;
/* We only handle page sizes for 64-bit server guests for now */
if (!(env->mmu_model & POWERPC_MMU_64)) {
@@ -471,9 +470,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
ksps->enc[jk].page_shift)) {
continue;
}
- if (ksps->enc[jk].page_shift == 16) {
- has_64k_pages = true;
- }
qsps->enc[jq].page_shift = ksps->enc[jk].page_shift;
qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc;
if (++jq >= PPC_PAGE_SIZES_MAX_SZ) {
@@ -488,9 +484,6 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
env->mmu_model &= ~POWERPC_MMU_1TSEG;
}
- if (!has_64k_pages) {
- env->mmu_model &= ~POWERPC_MMU_64K;
- }
}
bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 29bd6f3654..99be6fcd68 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10469,7 +10469,7 @@ static void ppc_cpu_instance_init(Object *obj)
env->sps = *pcc->sps;
} else if (env->mmu_model & POWERPC_MMU_64) {
/* Use default sets of page sizes. We don't support MPSS */
- static const struct ppc_segment_page_sizes defsps_4k = {
+ static const struct ppc_segment_page_sizes defsps = {
.sps = {
{ .page_shift = 12, /* 4K */
.slb_enc = 0,
@@ -10481,23 +10481,7 @@ static void ppc_cpu_instance_init(Object *obj)
},
},
};
- static const struct ppc_segment_page_sizes defsps_64k = {
- .sps = {
- { .page_shift = 12, /* 4K */
- .slb_enc = 0,
- .enc = { { .page_shift = 12, .pte_enc = 0 } }
- },
- { .page_shift = 16, /* 64K */
- .slb_enc = 0x110,
- .enc = { { .page_shift = 16, .pte_enc = 1 } }
- },
- { .page_shift = 24, /* 16M */
- .slb_enc = 0x100,
- .enc = { { .page_shift = 24, .pte_enc = 0 } }
- },
- },
- };
- env->sps = (env->mmu_model & POWERPC_MMU_64K) ? defsps_64k : defsps_4k;
+ env->sps = defsps;
}
#endif /* defined(TARGET_PPC64) */
}
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 36/49] target/ppc: Move page size setup to helper function
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (34 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 35/49] target/ppc: Remove fallback 64k pagesize information David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 37/49] target/ppc: Split page size information into a separate allocation David Gibson
` (14 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
Initialization of the env->sps structure at the end of instance_init is
specific to the 64-bit hash MMU, so move the code into a helper function
in mmu-hash64.c.
We also create a corresponding function to be called at finalize time -
it's empty for now, but we'll need it shortly.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
target/ppc/mmu-hash64.c | 29 +++++++++++++++++++++++++++++
target/ppc/mmu-hash64.h | 11 +++++++++++
target/ppc/translate_init.c | 29 +++++++++--------------------
3 files changed, 49 insertions(+), 20 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a87fa7c83f..4cb7d1cf07 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1095,3 +1095,32 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
ppc_hash64_update_rmls(cpu);
ppc_hash64_update_vrma(cpu);
}
+
+void ppc_hash64_init(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+ if (pcc->sps) {
+ env->sps = *pcc->sps;
+ } else if (env->mmu_model & POWERPC_MMU_64) {
+ /* Use default sets of page sizes. We don't support MPSS */
+ static const struct ppc_segment_page_sizes defsps = {
+ .sps = {
+ { .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 } }
+ },
+ { .page_shift = 24, /* 16M */
+ .slb_enc = 0x100,
+ .enc = { { .page_shift = 24, .pte_enc = 0 } }
+ },
+ },
+ };
+ env->sps = defsps;
+ }
+}
+
+void ppc_hash64_finalize(PowerPCCPU *cpu)
+{
+}
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 95a8c330d6..074ded4c27 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -19,6 +19,8 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
uint64_t pte0, uint64_t pte1);
void ppc_hash64_update_vrma(PowerPCCPU *cpu);
void ppc_hash64_update_rmls(PowerPCCPU *cpu);
+void ppc_hash64_init(PowerPCCPU *cpu);
+void ppc_hash64_finalize(PowerPCCPU *cpu);
#endif
/*
@@ -136,4 +138,13 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
#endif /* CONFIG_USER_ONLY */
+#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
+static inline void ppc_hash64_init(PowerPCCPU *cpu)
+{
+}
+static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
+{
+}
+#endif
+
#endif /* MMU_HASH64_H */
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 99be6fcd68..aa63a5dcb3 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10464,26 +10464,14 @@ static void ppc_cpu_instance_init(Object *obj)
env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
#endif
-#if defined(TARGET_PPC64)
- if (pcc->sps) {
- env->sps = *pcc->sps;
- } else if (env->mmu_model & POWERPC_MMU_64) {
- /* Use default sets of page sizes. We don't support MPSS */
- static const struct ppc_segment_page_sizes defsps = {
- .sps = {
- { .page_shift = 12, /* 4K */
- .slb_enc = 0,
- .enc = { { .page_shift = 12, .pte_enc = 0 } }
- },
- { .page_shift = 24, /* 16M */
- .slb_enc = 0x100,
- .enc = { { .page_shift = 24, .pte_enc = 0 } }
- },
- },
- };
- env->sps = defsps;
- }
-#endif /* defined(TARGET_PPC64) */
+ ppc_hash64_init(cpu);
+}
+
+static void ppc_cpu_instance_finalize(Object *obj)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(obj);
+
+ ppc_hash64_finalize(cpu);
}
static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
@@ -10601,6 +10589,7 @@ static const TypeInfo ppc_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(PowerPCCPU),
.instance_init = ppc_cpu_instance_init,
+ .instance_finalize = ppc_cpu_instance_finalize,
.abstract = true,
.class_size = sizeof(PowerPCCPUClass),
.class_init = ppc_cpu_class_init,
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 37/49] target/ppc: Split page size information into a separate allocation
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (35 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 36/49] target/ppc: Move page size setup to helper function David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 38/49] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs David Gibson
` (13 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
env->sps contains page size encoding information as an embedded structure.
Since this information is specific to 64-bit hash MMUs, split it out into
a separately allocated structure, to reduce the basic env size for other
cpus. Along the way we make a few other cleanups:
* Rename to PPCHash64Options which is more in line with qemu name
conventions, and reflects that we're going to merge some more hash64
mmu specific details in there in future. Also rename its
substructures to match qemu conventions.
* Move structure definitions to the mmu-hash64.[ch] files.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/fdt.c | 4 +--
target/ppc/cpu-qom.h | 4 +--
target/ppc/cpu.h | 26 +++----------------
target/ppc/kvm.c | 4 +--
target/ppc/mmu-hash64.c | 61 +++++++++++++++++++++++++++++++++------------
target/ppc/mmu-hash64.h | 22 ++++++++++++++++
target/ppc/translate_init.c | 36 +++-----------------------
7 files changed, 80 insertions(+), 77 deletions(-)
diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c
index 2721603ffa..0828ad7254 100644
--- a/hw/ppc/fdt.c
+++ b/hw/ppc/fdt.c
@@ -9,6 +9,7 @@
#include "qemu/osdep.h"
#include "target/ppc/cpu.h"
+#include "target/ppc/mmu-hash64.h"
#include "hw/ppc/fdt.h"
@@ -16,13 +17,12 @@
size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop,
size_t maxsize)
{
- CPUPPCState *env = &cpu->env;
size_t maxcells = maxsize / sizeof(uint32_t);
int i, j, count;
uint32_t *p = prop;
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
+ PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i];
if (!sps->page_shift) {
break;
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 9bbb05cf62..3e5ef7375f 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -160,7 +160,7 @@ enum powerpc_input_t {
PPC_FLAGS_INPUT_RCPU,
};
-struct ppc_segment_page_sizes;
+typedef struct PPCHash64Options PPCHash64Options;
/**
* PowerPCCPUClass:
@@ -194,7 +194,7 @@ typedef struct PowerPCCPUClass {
uint32_t flags;
int bfd_mach;
uint32_t l1_dcache_size, l1_icache_size;
- const struct ppc_segment_page_sizes *sps;
+ const PPCHash64Options *hash64_opts;
struct ppc_radix_page_info *radix_page_info;
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c621a6bd5e..1c5c33ca11 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -327,11 +327,13 @@ union ppc_tlb_t {
#define TLB_MAS 3
#endif
+typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
+
typedef struct ppc_slb_t ppc_slb_t;
struct ppc_slb_t {
uint64_t esid;
uint64_t vsid;
- const struct ppc_one_seg_page_size *sps;
+ const PPCHash64SegmentPageSizes *sps;
};
#define MAX_SLB_ENTRIES 64
@@ -948,28 +950,8 @@ enum {
#define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
-/*****************************************************************************/
-/* Segment page size information, used by recent hash MMUs
- * The format of this structure mirrors kvm_ppc_smmu_info
- */
-
#define PPC_PAGE_SIZES_MAX_SZ 8
-struct ppc_one_page_size {
- uint32_t page_shift; /* Page shift (or 0) */
- uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
-};
-
-struct ppc_one_seg_page_size {
- uint32_t page_shift; /* Base page shift of segment (or 0) */
- uint32_t slb_enc; /* SLB encoding for BookS */
- struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
-};
-
-struct ppc_segment_page_sizes {
- struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
-};
-
struct ppc_radix_page_info {
uint32_t count;
uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
@@ -1106,7 +1088,6 @@ struct CPUPPCState {
uint64_t insns_flags;
uint64_t insns_flags2;
#if defined(TARGET_PPC64)
- struct ppc_segment_page_sizes sps;
ppc_slb_t vrma_slb;
target_ulong rmls;
bool ci_large_pages;
@@ -1227,6 +1208,7 @@ struct PowerPCCPU {
PPCVirtualHypervisor *vhyp;
Object *intc;
int32_t node_id; /* NUMA node this CPU belongs to */
+ PPCHash64Options *hash64_opts;
/* Fields related to migration compatibility hacks */
bool pre_2_8_migration;
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 660467aec6..c67254acca 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -442,7 +442,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
}
/* Convert to QEMU form */
- memset(&env->sps, 0, sizeof(env->sps));
+ memset(cpu->hash64_opts->sps, 0, sizeof(*cpu->hash64_opts->sps));
/* If we have HV KVM, we need to forbid CI large pages if our
* host page size is smaller than 64K.
@@ -456,7 +456,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
* the selected CPU has with the capabilities that KVM supports.
*/
for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) {
- struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq];
+ PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik];
if (!kvm_valid_page_size(smmu_info.flags, max_cpu_page_size,
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 4cb7d1cf07..6758afd9de 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -148,7 +148,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
{
CPUPPCState *env = &cpu->env;
ppc_slb_t *slb = &env->slb[slot];
- const struct ppc_one_seg_page_size *sps = NULL;
+ const PPCHash64SegmentPageSizes *sps = NULL;
int i;
if (slot >= env->slb_nr) {
@@ -165,7 +165,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
}
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
+ const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i];
if (!sps1->page_shift) {
break;
@@ -451,8 +451,8 @@ void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
false, n * HASH_PTE_SIZE_64);
}
-static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
- uint64_t pte0, uint64_t pte1)
+static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps,
+ uint64_t pte0, uint64_t pte1)
{
int i;
@@ -466,7 +466,7 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
}
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- const struct ppc_one_page_size *ps = &sps->enc[i];
+ const PPCHash64PageSize *ps = &sps->enc[i];
uint64_t mask;
if (!ps->page_shift) {
@@ -489,7 +489,7 @@ static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps,
}
static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
- const struct ppc_one_seg_page_size *sps,
+ const PPCHash64SegmentPageSizes *sps,
target_ulong ptem,
ppc_hash_pte64_t *pte, unsigned *pshift)
{
@@ -543,7 +543,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
CPUPPCState *env = &cpu->env;
hwaddr hash, ptex;
uint64_t vsid, epnmask, epn, ptem;
- const struct ppc_one_seg_page_size *sps = slb->sps;
+ const PPCHash64SegmentPageSizes *sps = slb->sps;
/* The SLB store path should prevent any bad page size encodings
* getting in there, so: */
@@ -552,7 +552,7 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
/* If ISL is set in LPCR we need to clamp the page size to 4K */
if (env->spr[SPR_LPCR] & LPCR_ISL) {
/* We assume that when using TCG, 4k is first entry of SPS */
- sps = &env->sps.sps[0];
+ sps = &cpu->hash64_opts->sps[0];
assert(sps->page_shift == 12);
}
@@ -605,7 +605,6 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu,
unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
uint64_t pte0, uint64_t pte1)
{
- CPUPPCState *env = &cpu->env;
int i;
if (!(pte0 & HPTE64_V_LARGE)) {
@@ -617,7 +616,7 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
* this gives an unambiguous result.
*/
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
+ const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i];
unsigned shift;
if (!sps->page_shift) {
@@ -980,7 +979,7 @@ void ppc_hash64_update_rmls(PowerPCCPU *cpu)
void ppc_hash64_update_vrma(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
- const struct ppc_one_seg_page_size *sps = NULL;
+ const PPCHash64SegmentPageSizes *sps = NULL;
target_ulong esid, vsid, lpcr;
ppc_slb_t *slb = &env->vrma_slb;
uint32_t vrmasd;
@@ -1005,7 +1004,7 @@ void ppc_hash64_update_vrma(PowerPCCPU *cpu)
esid = SLB_ESID_V;
for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i];
+ const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i];
if (!sps1->page_shift) {
break;
@@ -1101,11 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu)
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- if (pcc->sps) {
- env->sps = *pcc->sps;
+ if (pcc->hash64_opts) {
+ cpu->hash64_opts = g_memdup(pcc->hash64_opts,
+ sizeof(*cpu->hash64_opts));
} else if (env->mmu_model & POWERPC_MMU_64) {
/* Use default sets of page sizes. We don't support MPSS */
- static const struct ppc_segment_page_sizes defsps = {
+ static const PPCHash64Options defopts = {
.sps = {
{ .page_shift = 12, /* 4K */
.slb_enc = 0,
@@ -1117,10 +1117,39 @@ void ppc_hash64_init(PowerPCCPU *cpu)
},
},
};
- env->sps = defsps;
+ cpu->hash64_opts = g_memdup(&defopts, sizeof(*cpu->hash64_opts));
}
}
void ppc_hash64_finalize(PowerPCCPU *cpu)
{
+ g_free(cpu->hash64_opts);
}
+
+const PPCHash64Options ppc_hash64_opts_POWER7 = {
+ .sps = {
+ {
+ .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 },
+ { .page_shift = 16, .pte_enc = 0x7 },
+ { .page_shift = 24, .pte_enc = 0x38 }, },
+ },
+ {
+ .page_shift = 16, /* 64K */
+ .slb_enc = SLB_VSID_64K,
+ .enc = { { .page_shift = 16, .pte_enc = 0x1 },
+ { .page_shift = 24, .pte_enc = 0x8 }, },
+ },
+ {
+ .page_shift = 24, /* 16M */
+ .slb_enc = SLB_VSID_16M,
+ .enc = { { .page_shift = 24, .pte_enc = 0 }, },
+ },
+ {
+ .page_shift = 34, /* 16G */
+ .slb_enc = SLB_VSID_16G,
+ .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
+ },
+ }
+};
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 074ded4c27..957bd68e33 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -136,6 +136,28 @@ static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
return ldq_p(&(hptes[i].pte1));
}
+/*
+ * MMU Options
+ */
+
+struct PPCHash64PageSize {
+ uint32_t page_shift; /* Page shift (or 0) */
+ uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
+};
+typedef struct PPCHash64PageSize PPCHash64PageSize;
+
+struct PPCHash64SegmentPageSizes {
+ uint32_t page_shift; /* Base page shift of segment (or 0) */
+ uint32_t slb_enc; /* SLB encoding for BookS */
+ PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ];
+};
+
+struct PPCHash64Options {
+ PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
+};
+
+extern const PPCHash64Options ppc_hash64_opts_POWER7;
+
#endif /* CONFIG_USER_ONLY */
#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index aa63a5dcb3..040d6fbac3 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8368,36 +8368,6 @@ static Property powerpc_servercpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
-#ifdef CONFIG_SOFTMMU
-static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
- .sps = {
- {
- .page_shift = 12, /* 4K */
- .slb_enc = 0,
- .enc = { { .page_shift = 12, .pte_enc = 0 },
- { .page_shift = 16, .pte_enc = 0x7 },
- { .page_shift = 24, .pte_enc = 0x38 }, },
- },
- {
- .page_shift = 16, /* 64K */
- .slb_enc = SLB_VSID_64K,
- .enc = { { .page_shift = 16, .pte_enc = 0x1 },
- { .page_shift = 24, .pte_enc = 0x8 }, },
- },
- {
- .page_shift = 24, /* 16M */
- .slb_enc = SLB_VSID_16M,
- .enc = { { .page_shift = 24, .pte_enc = 0 }, },
- },
- {
- .page_shift = 34, /* 16G */
- .slb_enc = SLB_VSID_16G,
- .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
- },
- }
-};
-#endif /* CONFIG_SOFTMMU */
-
static void init_proc_POWER7(CPUPPCState *env)
{
/* Common Registers */
@@ -8526,7 +8496,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
- pcc->sps = &POWER7_POWER8_sps;
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
#endif
pcc->excp_model = POWERPC_EXCP_POWER7;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
@@ -8698,7 +8668,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_07;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
- pcc->sps = &POWER7_POWER8_sps;
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
#endif
pcc->excp_model = POWERPC_EXCP_POWER8;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
@@ -8893,7 +8863,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
/* segment page size remain the same */
- pcc->sps = &POWER7_POWER8_sps;
+ pcc->hash64_opts = &ppc_hash64_opts_POWER7;
pcc->radix_page_info = &POWER9_radix_page_info;
#endif
pcc->excp_model = POWERPC_EXCP_POWER8;
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 38/49] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (36 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 37/49] target/ppc: Split page size information into a separate allocation David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 39/49] target/ppc: Move 1T segment and AMR options to PPCHash64Options David Gibson
` (12 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
Currently some cpus set the hash64_opts field in the class structure, with
specific details of their variant of the 64-bit hash mmu. For the
remaining cpus with that mmu, ppc_hash64_realize() fills in defaults.
But there are only a couple of cpus that use those fallbacks, so just have
them to set the has64_opts field instead, simplifying the logic.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
target/ppc/mmu-hash64.c | 36 ++++++++++++++++++------------------
target/ppc/mmu-hash64.h | 1 +
target/ppc/translate_init.c | 2 ++
3 files changed, 21 insertions(+), 18 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 6758afd9de..2809c31170 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1100,25 +1100,12 @@ void ppc_hash64_init(PowerPCCPU *cpu)
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- if (pcc->hash64_opts) {
- cpu->hash64_opts = g_memdup(pcc->hash64_opts,
- sizeof(*cpu->hash64_opts));
- } else if (env->mmu_model & POWERPC_MMU_64) {
- /* Use default sets of page sizes. We don't support MPSS */
- static const PPCHash64Options defopts = {
- .sps = {
- { .page_shift = 12, /* 4K */
- .slb_enc = 0,
- .enc = { { .page_shift = 12, .pte_enc = 0 } }
- },
- { .page_shift = 24, /* 16M */
- .slb_enc = 0x100,
- .enc = { { .page_shift = 24, .pte_enc = 0 } }
- },
- },
- };
- cpu->hash64_opts = g_memdup(&defopts, sizeof(*cpu->hash64_opts));
+ if (!pcc->hash64_opts) {
+ assert(!(env->mmu_model & POWERPC_MMU_64));
+ return;
}
+
+ cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts));
}
void ppc_hash64_finalize(PowerPCCPU *cpu)
@@ -1126,6 +1113,19 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
g_free(cpu->hash64_opts);
}
+const PPCHash64Options ppc_hash64_opts_basic = {
+ .sps = {
+ { .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 } }
+ },
+ { .page_shift = 24, /* 16M */
+ .slb_enc = 0x100,
+ .enc = { { .page_shift = 24, .pte_enc = 0 } }
+ },
+ },
+};
+
const PPCHash64Options ppc_hash64_opts_POWER7 = {
.sps = {
{
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 957bd68e33..341c1524c2 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -156,6 +156,7 @@ struct PPCHash64Options {
PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
};
+extern const PPCHash64Options ppc_hash64_opts_basic;
extern const PPCHash64Options ppc_hash64_opts_POWER7;
#endif /* CONFIG_USER_ONLY */
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 040d6fbac3..ae005b2a54 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8242,6 +8242,7 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_64B;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->hash64_opts = &ppc_hash64_opts_basic;
#endif
pcc->excp_model = POWERPC_EXCP_970;
pcc->bus_model = PPC_FLAGS_INPUT_970;
@@ -8319,6 +8320,7 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
pcc->mmu_model = POWERPC_MMU_2_03;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+ pcc->hash64_opts = &ppc_hash64_opts_basic;
#endif
pcc->excp_model = POWERPC_EXCP_970;
pcc->bus_model = PPC_FLAGS_INPUT_970;
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 39/49] target/ppc: Move 1T segment and AMR options to PPCHash64Options
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (37 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 38/49] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 40/49] target/ppc: Fold ci_large_pages flag into PPCHash64Options David Gibson
` (11 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
Currently env->mmu_model is a bit of an unholy mess of an enum of distinct
MMU types, with various flag bits as well. This makes which bits of the
field should be compared pretty confusing.
Make a start on cleaning that up by moving two of the flags bits -
POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit
hash MMU into a new flags field in PPCHash64Options structure.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/pnv.c | 3 ++-
hw/ppc/spapr.c | 2 +-
target/ppc/cpu-qom.h | 11 +++--------
target/ppc/kvm.c | 4 ++--
target/ppc/mmu-hash64.c | 6 ++++--
target/ppc/mmu-hash64.h | 8 ++++++++
6 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 3220ef8f79..0e49c5e9b8 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -36,6 +36,7 @@
#include "monitor/monitor.h"
#include "hw/intc/intc.h"
#include "hw/ipmi/ipmi.h"
+#include "target/ppc/mmu-hash64.h"
#include "hw/ppc/xics.h"
#include "hw/ppc/pnv_xscom.h"
@@ -187,7 +188,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
_FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
}
- if (env->mmu_model & POWERPC_MMU_1TSEG) {
+ if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
_FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
segs, sizeof(segs))));
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a4b3722656..9c26dc37e1 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -557,7 +557,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
_FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
}
- if (env->mmu_model & POWERPC_MMU_1TSEG) {
+ if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
_FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
segs, sizeof(segs))));
}
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 3e5ef7375f..2bd58b2a84 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -68,22 +68,17 @@ enum powerpc_mmu_t {
/* PowerPC 601 MMU model (specific BATs format) */
POWERPC_MMU_601 = 0x0000000A,
#define POWERPC_MMU_64 0x00010000
-#define POWERPC_MMU_1TSEG 0x00020000
-#define POWERPC_MMU_AMR 0x00040000
#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
/* Architecture 2.03 and later (has LPCR) */
POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
/* Architecture 2.06 variant */
- POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_AMR | 0x00000003,
+ POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
/* Architecture 2.07 variant */
- POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_AMR | 0x00000004,
+ POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
/* Architecture 3.00 variant */
- POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
- | POWERPC_MMU_AMR | POWERPC_MMU_V3
+ POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3
| 0x00000005,
};
#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index c67254acca..b53af75ecf 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
/* HV KVM has backing store size restrictions */
info->flags = KVM_PPC_PAGE_SIZES_REAL;
- if (env->mmu_model & POWERPC_MMU_1TSEG) {
+ if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
info->flags |= KVM_PPC_1T_SEGMENTS;
}
@@ -482,7 +482,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
}
env->slb_nr = smmu_info.slb_size;
if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
- env->mmu_model &= ~POWERPC_MMU_1TSEG;
+ cpu->hash64_opts->flags &= ~PPC_HASH64_1TSEG;
}
}
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 2809c31170..c9ee55e1ea 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
return -1; /* Bad segment size */
}
- if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
+ if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) {
return -1; /* 1T segment on MMU that doesn't support it */
}
@@ -369,7 +369,7 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte)
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
/* Only recent MMUs implement Virtual Page Class Key Protection */
- if (!(env->mmu_model & POWERPC_MMU_AMR)) {
+ if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) {
return prot;
}
@@ -1114,6 +1114,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
}
const PPCHash64Options ppc_hash64_opts_basic = {
+ .flags = 0,
.sps = {
{ .page_shift = 12, /* 4K */
.slb_enc = 0,
@@ -1127,6 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
};
const PPCHash64Options ppc_hash64_opts_POWER7 = {
+ .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
.sps = {
{
.page_shift = 12, /* 4K */
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 341c1524c2..b2b5d25238 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -153,12 +153,20 @@ struct PPCHash64SegmentPageSizes {
};
struct PPCHash64Options {
+#define PPC_HASH64_1TSEG 0x00001
+#define PPC_HASH64_AMR 0x00002
+ unsigned flags;
PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
};
extern const PPCHash64Options ppc_hash64_opts_basic;
extern const PPCHash64Options ppc_hash64_opts_POWER7;
+static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature)
+{
+ return !!(cpu->hash64_opts->flags & feature);
+}
+
#endif /* CONFIG_USER_ONLY */
#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 40/49] target/ppc: Fold ci_large_pages flag into PPCHash64Options
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (38 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 39/49] target/ppc: Move 1T segment and AMR options to PPCHash64Options David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 41/49] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model David Gibson
` (10 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
The ci_large_pages boolean in CPUPPCState is only relevant to 64-bit hash
MMU machines, indicating whether it's possible to map large (> 4kiB) pages
as cache-inhibitied (i.e. for IO, rather than memory). Fold it as another
flag into the PPCHash64Options structure.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr.c | 3 +--
target/ppc/cpu.h | 1 -
target/ppc/kvm.c | 6 +++++-
target/ppc/mmu-hash64.c | 2 +-
target/ppc/mmu-hash64.h | 1 +
target/ppc/translate_init.c | 3 ---
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 9c26dc37e1..abf38c62e8 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -263,7 +263,6 @@ static void spapr_populate_pa_features(sPAPRMachineState *spapr,
void *fdt, int offset,
bool legacy_guest)
{
- CPUPPCState *env = &cpu->env;
uint8_t pa_features_206[] = { 6, 0,
0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
uint8_t pa_features_207[] = { 24, 0,
@@ -315,7 +314,7 @@ static void spapr_populate_pa_features(sPAPRMachineState *spapr,
return;
}
- if (env->ci_large_pages) {
+ if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
/*
* Note: we keep CI large pages off by default because a 64K capable
* guest provisioned with large pages might otherwise try to map a qemu
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1c5c33ca11..c0c44fb91d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1090,7 +1090,6 @@ struct CPUPPCState {
#if defined(TARGET_PPC64)
ppc_slb_t vrma_slb;
target_ulong rmls;
- bool ci_large_pages;
#endif
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index b53af75ecf..25f93dc708 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -448,7 +448,11 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
* host page size is smaller than 64K.
*/
if (smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL) {
- env->ci_large_pages = getpagesize() >= 0x10000;
+ if (getpagesize() >= 0x10000) {
+ cpu->hash64_opts->flags |= PPC_HASH64_CI_LARGEPAGE;
+ } else {
+ cpu->hash64_opts->flags &= ~PPC_HASH64_CI_LARGEPAGE;
+ }
}
/*
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index c9ee55e1ea..f341714550 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1128,7 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
};
const PPCHash64Options ppc_hash64_opts_POWER7 = {
- .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR,
+ .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE,
.sps = {
{
.page_shift = 12, /* 4K */
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index b2b5d25238..f1babb0afc 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -155,6 +155,7 @@ struct PPCHash64SegmentPageSizes {
struct PPCHash64Options {
#define PPC_HASH64_1TSEG 0x00001
#define PPC_HASH64_AMR 0x00002
+#define PPC_HASH64_CI_LARGEPAGE 0x00004
unsigned flags;
PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
};
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index ae005b2a54..a925cf5cd3 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8392,7 +8392,6 @@ static void init_proc_POWER7(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
- env->ci_large_pages = true;
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8547,7 +8546,6 @@ static void init_proc_POWER8(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
- env->ci_large_pages = true;
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8748,7 +8746,6 @@ static void init_proc_POWER9(CPUPPCState *env)
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
- env->ci_large_pages = true;
env->dcache_line_size = 128;
env->icache_line_size = 128;
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 41/49] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (39 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 40/49] target/ppc: Fold ci_large_pages flag into PPCHash64Options David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 42/49] target/ppc: Get rid of POWERPC_MMU_VER() macros David Gibson
` (9 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
The only place we test this flag is in conjunction with
ppc64_use_proc_tbl(). That checks for the LPCR_UPRT bit, which we already
ensure can't be set except on a machine with a v3 MMU (i.e. POWER9).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
target/ppc/cpu-qom.h | 4 +---
target/ppc/mmu-hash64.c | 2 +-
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 2bd58b2a84..ef96d42cf2 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -68,7 +68,6 @@ enum powerpc_mmu_t {
/* PowerPC 601 MMU model (specific BATs format) */
POWERPC_MMU_601 = 0x0000000A,
#define POWERPC_MMU_64 0x00010000
-#define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */
/* 64 bits PowerPC MMU */
POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
/* Architecture 2.03 and later (has LPCR) */
@@ -78,8 +77,7 @@ enum powerpc_mmu_t {
/* Architecture 2.07 variant */
POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
/* Architecture 3.00 variant */
- POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3
- | 0x00000005,
+ POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
};
#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index f341714550..df26a03c15 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -761,7 +761,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
slb = slb_lookup(cpu, eaddr);
if (!slb) {
/* No entry found, check if in-memory segment tables are in use */
- if ((env->mmu_model & POWERPC_MMU_V3) && ppc64_use_proc_tbl(cpu)) {
+ if (ppc64_use_proc_tbl(cpu)) {
/* TODO - Unsupported */
error_report("Segment Table Support Unimplemented");
exit(1);
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 42/49] target/ppc: Get rid of POWERPC_MMU_VER() macros
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (40 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 41/49] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 43/49] target/ppc: Fold slb_nr into PPCHash64Options David Gibson
` (8 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
These macros were introduced to deal with the fact that the mmu_model
field has bit flags mixed in with what's otherwise an enum of various mmu
types.
We've now eliminated all those flags except for one, and that one -
POWERPC_MMU_64 - is already included/compared in the MMU_VER macros. So,
we can get rid of those macros and just directly compare mmu_model values
in the places it was used.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
target/ppc/cpu-qom.h | 6 ------
target/ppc/kvm.c | 8 ++++----
target/ppc/mmu-hash64.c | 12 ++++++------
target/ppc/mmu_helper.c | 24 ++++++++++++------------
target/ppc/translate.c | 12 ++++++------
5 files changed, 28 insertions(+), 34 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index ef96d42cf2..433a71e484 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -79,12 +79,6 @@ enum powerpc_mmu_t {
/* Architecture 3.00 variant */
POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
};
-#define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF))
-#define POWERPC_MMU_VER_64B POWERPC_MMU_VER(POWERPC_MMU_64B)
-#define POWERPC_MMU_VER_2_03 POWERPC_MMU_VER(POWERPC_MMU_2_03)
-#define POWERPC_MMU_VER_2_06 POWERPC_MMU_VER(POWERPC_MMU_2_06)
-#define POWERPC_MMU_VER_2_07 POWERPC_MMU_VER(POWERPC_MMU_2_07)
-#define POWERPC_MMU_VER_3_00 POWERPC_MMU_VER(POWERPC_MMU_3_00)
/*****************************************************************************/
/* Exception model */
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 25f93dc708..246b9eab2a 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -306,8 +306,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
info->flags |= KVM_PPC_1T_SEGMENTS;
}
- if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 ||
- POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) {
+ if (env->mmu_model == POWERPC_MMU_2_06 ||
+ env->mmu_model == POWERPC_MMU_2_07) {
info->slb_size = 32;
} else {
info->slb_size = 64;
@@ -321,8 +321,8 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu,
i++;
/* 64K on MMU 2.06 and later */
- if (POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_06 ||
- POWERPC_MMU_VER(env->mmu_model) == POWERPC_MMU_VER_2_07) {
+ if (env->mmu_model == POWERPC_MMU_2_06 ||
+ env->mmu_model == POWERPC_MMU_2_07) {
info->sps[i].page_shift = 16;
info->sps[i].slb_enc = 0x110;
info->sps[i].enc[0].page_shift = 16;
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index df26a03c15..a5570c8774 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1033,8 +1033,8 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
uint64_t lpcr = 0;
/* Filter out bits */
- switch (POWERPC_MMU_VER(env->mmu_model)) {
- case POWERPC_MMU_VER_64B: /* 970 */
+ switch (env->mmu_model) {
+ case POWERPC_MMU_64B: /* 970 */
if (val & 0x40) {
lpcr |= LPCR_LPES0;
}
@@ -1060,26 +1060,26 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
* to dig HRMOR out of HID5
*/
break;
- case POWERPC_MMU_VER_2_03: /* P5p */
+ case POWERPC_MMU_2_03: /* P5p */
lpcr = val & (LPCR_RMLS | LPCR_ILE |
LPCR_LPES0 | LPCR_LPES1 |
LPCR_RMI | LPCR_HDICE);
break;
- case POWERPC_MMU_VER_2_06: /* P7 */
+ case POWERPC_MMU_2_06: /* P7 */
lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
LPCR_MER | LPCR_TC |
LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
break;
- case POWERPC_MMU_VER_2_07: /* P8 */
+ case POWERPC_MMU_2_07: /* P8 */
lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
break;
- case POWERPC_MMU_VER_3_00: /* P9 */
+ case POWERPC_MMU_3_00: /* P9 */
lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
(LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 5568d1642b..8075b7149a 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1266,7 +1266,7 @@ static void mmu6xx_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
{
- switch (POWERPC_MMU_VER(env->mmu_model)) {
+ switch (env->mmu_model) {
case POWERPC_MMU_BOOKE:
mmubooke_dump_mmu(f, cpu_fprintf, env);
break;
@@ -1278,13 +1278,13 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
mmu6xx_dump_mmu(f, cpu_fprintf, env);
break;
#if defined(TARGET_PPC64)
- case POWERPC_MMU_VER_64B:
- case POWERPC_MMU_VER_2_03:
- case POWERPC_MMU_VER_2_06:
- case POWERPC_MMU_VER_2_07:
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_2_03:
+ case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_07:
dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
break;
- case POWERPC_MMU_VER_3_00:
+ case POWERPC_MMU_3_00:
if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
/* TODO - Unsupported */
} else {
@@ -1423,14 +1423,14 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
CPUPPCState *env = &cpu->env;
mmu_ctx_t ctx;
- switch (POWERPC_MMU_VER(env->mmu_model)) {
+ switch (env->mmu_model) {
#if defined(TARGET_PPC64)
- case POWERPC_MMU_VER_64B:
- case POWERPC_MMU_VER_2_03:
- case POWERPC_MMU_VER_2_06:
- case POWERPC_MMU_VER_2_07:
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_2_03:
+ case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_07:
return ppc_hash64_get_phys_page_debug(cpu, addr);
- case POWERPC_MMU_VER_3_00:
+ case POWERPC_MMU_3_00:
if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
return ppc_radix64_get_phys_page_debug(cpu, addr);
} else {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b0d79a3fb9..3beaa1e2f0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7121,17 +7121,17 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
if (env->spr_cb[SPR_LPCR].name)
cpu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
- switch (POWERPC_MMU_VER(env->mmu_model)) {
+ switch (env->mmu_model) {
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
#if defined(TARGET_PPC64)
- case POWERPC_MMU_VER_64B:
- case POWERPC_MMU_VER_2_03:
- case POWERPC_MMU_VER_2_06:
- case POWERPC_MMU_VER_2_07:
- case POWERPC_MMU_VER_3_00:
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_2_03:
+ case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_07:
+ case POWERPC_MMU_3_00:
#endif
if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 43/49] target/ppc: Fold slb_nr into PPCHash64Options
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (41 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 42/49] target/ppc: Get rid of POWERPC_MMU_VER() macros David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 44/49] spapr: Add ibm, max-associativity-domains property David Gibson
` (7 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
The env->slb_nr field gives the size of the SLB (Segment Lookaside Buffer).
This is another static-after-initialization parameter of the specific
version of the 64-bit hash MMU in the CPU. So, this patch folds the field
into PPCHash64Options with the other hash MMU options.
This is a bit more complicated that the things previously put in there,
because slb_nr was foolishly included in the migration stream. So we need
some of the usual dance to handle backwards compatible migration.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/pnv.c | 2 +-
hw/ppc/spapr.c | 11 ++++++++---
target/ppc/cpu.h | 3 ++-
target/ppc/kvm.c | 2 +-
target/ppc/machine.c | 23 ++++++++++++++++++++---
target/ppc/mmu-hash64.c | 15 +++++++++------
target/ppc/mmu-hash64.h | 1 +
target/ppc/translate_init.c | 17 ++---------------
8 files changed, 44 insertions(+), 30 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0e49c5e9b8..0314881316 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -180,7 +180,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
_FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
_FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
- _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
+ _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
_FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
_FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index abf38c62e8..8c2e3ccb89 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -547,8 +547,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
_FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
_FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
- _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
- _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
+ _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
+ _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
_FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
_FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
@@ -3958,7 +3958,12 @@ DEFINE_SPAPR_MACHINE(2_13, "2.13", true);
* pseries-2.12
*/
#define SPAPR_COMPAT_2_12 \
- HW_COMPAT_2_12
+ HW_COMPAT_2_12 \
+ { \
+ .driver = TYPE_POWERPC_CPU, \
+ .property = "pre-2.13-migration", \
+ .value = "on", \
+ },
static void spapr_machine_2_12_instance_options(MachineState *machine)
{
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c0c44fb91d..8c9e03f54d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1025,7 +1025,6 @@ struct CPUPPCState {
#if defined(TARGET_PPC64)
/* PowerPC 64 SLB area */
ppc_slb_t slb[MAX_SLB_ENTRIES];
- int32_t slb_nr;
/* tcg TLB needs flush (deferred slb inval instruction typically) */
#endif
/* segment registers */
@@ -1216,6 +1215,8 @@ struct PowerPCCPU {
uint64_t mig_insns_flags2;
uint32_t mig_nb_BATs;
bool pre_2_10_migration;
+ bool pre_2_13_migration;
+ int32_t mig_slb_nr;
};
static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 246b9eab2a..6de59c5b21 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -484,7 +484,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu)
break;
}
}
- env->slb_nr = smmu_info.slb_size;
+ cpu->hash64_opts->slb_size = smmu_info.slb_size;
if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
cpu->hash64_opts->flags &= ~PPC_HASH64_1TSEG;
}
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 0634cdb295..3d6434a006 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -18,6 +18,9 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
unsigned int i, j;
target_ulong sdr1;
uint32_t fpscr;
+#if defined(TARGET_PPC64)
+ int32_t slb_nr;
+#endif
target_ulong xer;
for (i = 0; i < 32; i++)
@@ -49,7 +52,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
qemu_get_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
qemu_get_betls(f, &env->spr[SPR_ASR]);
- qemu_get_sbe32s(f, &env->slb_nr);
+ qemu_get_sbe32s(f, &slb_nr);
#endif
qemu_get_betls(f, &sdr1);
for (i = 0; i < 32; i++)
@@ -146,6 +149,15 @@ static bool cpu_pre_2_8_migration(void *opaque, int version_id)
return cpu->pre_2_8_migration;
}
+#if defined(TARGET_PPC64)
+static bool cpu_pre_2_13_migration(void *opaque, int version_id)
+{
+ PowerPCCPU *cpu = opaque;
+
+ return cpu->pre_2_13_migration;
+}
+#endif
+
static int cpu_pre_save(void *opaque)
{
PowerPCCPU *cpu = opaque;
@@ -203,6 +215,11 @@ static int cpu_pre_save(void *opaque)
cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
cpu->mig_nb_BATs = env->nb_BATs;
}
+ if (cpu->pre_2_13_migration) {
+ if (cpu->hash64_opts) {
+ cpu->mig_slb_nr = cpu->hash64_opts->slb_size;
+ }
+ }
return 0;
}
@@ -478,7 +495,7 @@ static int slb_post_load(void *opaque, int version_id)
/* We've pulled in the raw esid and vsid values from the migration
* stream, but we need to recompute the page size pointers */
- for (i = 0; i < env->slb_nr; i++) {
+ for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
/* Migration source had bad values in its SLB */
return -1;
@@ -495,7 +512,7 @@ static const VMStateDescription vmstate_slb = {
.needed = slb_needed,
.post_load = slb_post_load,
.fields = (VMStateField[]) {
- VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU, NULL),
+ VMSTATE_INT32_TEST(mig_slb_nr, PowerPCCPU, cpu_pre_2_13_migration),
VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
VMSTATE_END_OF_LIST()
}
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a5570c8774..7e0adecfd9 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -52,7 +52,7 @@ static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr)
esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
- for (n = 0; n < env->slb_nr; n++) {
+ for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
ppc_slb_t *slb = &env->slb[n];
LOG_SLB("%s: slot %d %016" PRIx64 " %016"
@@ -80,7 +80,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
cpu_synchronize_state(CPU(cpu));
cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
- for (i = 0; i < env->slb_nr; i++) {
+ for (i = 0; i < cpu->hash64_opts->slb_size; i++) {
slbe = env->slb[i].esid;
slbv = env->slb[i].vsid;
if (slbe == 0 && slbv == 0) {
@@ -93,10 +93,11 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu)
void helper_slbia(CPUPPCState *env)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
int n;
/* XXX: Warning: slbia never invalidates the first segment */
- for (n = 1; n < env->slb_nr; n++) {
+ for (n = 1; n < cpu->hash64_opts->slb_size; n++) {
ppc_slb_t *slb = &env->slb[n];
if (slb->esid & SLB_ESID_V) {
@@ -151,7 +152,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
const PPCHash64SegmentPageSizes *sps = NULL;
int i;
- if (slot >= env->slb_nr) {
+ if (slot >= cpu->hash64_opts->slb_size) {
return -1; /* Bad slot number */
}
if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) {
@@ -202,7 +203,7 @@ static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
int slot = rb & 0xfff;
ppc_slb_t *slb = &env->slb[slot];
- if (slot >= env->slb_nr) {
+ if (slot >= cpu->hash64_opts->slb_size) {
return -1;
}
@@ -217,7 +218,7 @@ static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
int slot = rb & 0xfff;
ppc_slb_t *slb = &env->slb[slot];
- if (slot >= env->slb_nr) {
+ if (slot >= cpu->hash64_opts->slb_size) {
return -1;
}
@@ -1115,6 +1116,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu)
const PPCHash64Options ppc_hash64_opts_basic = {
.flags = 0,
+ .slb_size = 64,
.sps = {
{ .page_shift = 12, /* 4K */
.slb_enc = 0,
@@ -1129,6 +1131,7 @@ const PPCHash64Options ppc_hash64_opts_basic = {
const PPCHash64Options ppc_hash64_opts_POWER7 = {
.flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE,
+ .slb_size = 32,
.sps = {
{
.page_shift = 12, /* 4K */
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index f1babb0afc..d5fc03441d 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -157,6 +157,7 @@ struct PPCHash64Options {
#define PPC_HASH64_AMR 0x00002
#define PPC_HASH64_CI_LARGEPAGE 0x00004
unsigned flags;
+ unsigned slb_size;
PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
};
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index a925cf5cd3..bb79d23b50 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8195,9 +8195,6 @@ static void init_proc_970(CPUPPCState *env)
gen_spr_970_dbg(env);
/* env variables */
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 64;
-#endif
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8272,9 +8269,6 @@ static void init_proc_power5plus(CPUPPCState *env)
gen_spr_power5p_ear(env);
/* env variables */
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 64;
-#endif
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8389,9 +8383,6 @@ static void init_proc_POWER7(CPUPPCState *env)
gen_spr_power7_book4(env);
/* env variables */
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 32;
-#endif
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8543,9 +8534,6 @@ static void init_proc_POWER8(CPUPPCState *env)
gen_spr_power8_rpr(env);
/* env variables */
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 32;
-#endif
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -8743,9 +8731,6 @@ static void init_proc_POWER9(CPUPPCState *env)
KVM_REG_PPC_PSSCR, 0);
/* env variables */
-#if !defined(CONFIG_USER_ONLY)
- env->slb_nr = 32;
-#endif
env->dcache_line_size = 128;
env->icache_line_size = 128;
@@ -10486,6 +10471,8 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
false),
+ DEFINE_PROP_BOOL("pre-2.13-migration", PowerPCCPU, pre_2_13_migration,
+ false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 44/49] spapr: Add ibm, max-associativity-domains property
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (42 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 43/49] target/ppc: Fold slb_nr into PPCHash64Options David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 45/49] ppc: e500: switch E500 based machines to full machine definition David Gibson
` (6 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Serhii Popovych, David Gibson
From: Serhii Popovych <spopovyc@redhat.com>
Now recent kernels (i.e. since linux-stable commit a346137e9142
("powerpc/numa: Use ibm,max-associativity-domains to discover possible nodes")
support this property to mark initially memory-less NUMA nodes as "possible"
to allow further memory hot-add to them.
Advertise this property for pSeries machines to let guest kernels detect
maximum supported node configuration and benefit from kernel side change
when hot-add memory to specific, possibly empty before, NUMA node.
Signed-off-by: Serhii Popovych <spopovyc@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 8c2e3ccb89..2203b6f46d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -909,6 +909,13 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
cpu_to_be32(max_cpus / smp_threads),
};
+ uint32_t maxdomains[] = {
+ cpu_to_be32(4),
+ cpu_to_be32(0),
+ cpu_to_be32(0),
+ cpu_to_be32(0),
+ cpu_to_be32(nb_numa_nodes ? nb_numa_nodes - 1 : 0),
+ };
_FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
@@ -945,6 +952,9 @@ static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
_FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
refpoints, sizeof(refpoints)));
+ _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
+ maxdomains, sizeof(maxdomains)));
+
_FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
RTAS_ERROR_LOG_MAX));
_FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 45/49] ppc: e500: switch E500 based machines to full machine definition
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (43 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 44/49] spapr: Add ibm, max-associativity-domains property David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 46/49] spapr: Support ibm, dynamic-memory-v2 property David Gibson
` (5 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Igor Mammedov, David Gibson
From: Igor Mammedov <imammedo@redhat.com>
Convert PPCE500Params to PCCE500MachineClass which it essentially is,
and introduce PCCE500MachineState to keep track of E500 specific
state instead of adding global variables or extra parameters to
functions when we need to keep data beyond machine init
(i.e. make it look like typical fully defined machine).
It's pretty shallow conversion instead of currently used trivial
DEFINE_MACHINE() macro. It adds extra 60LOC of boilerplate code
of full machine definition.
The patch on top[1] will use PCCE500MachineState to keep track of
platform_bus device and add E500Plate specific machine class
to use HOTPLUG_HANDLER for explicitly initializing dynamic
sysbus devices at the time they are added instead of delaying
it to machine done time by platform_bus_init_notify() which is
being removed.
1) <1523551221-11612-3-git-send-email-imammedo@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/e500.c | 119 ++++++++++++++++++++++++++++-------------------------
hw/ppc/e500.h | 29 ++++++++++---
hw/ppc/e500plat.c | 64 +++++++++++++++++-----------
hw/ppc/mpc8544ds.c | 47 +++++++++++++--------
4 files changed, 156 insertions(+), 103 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 2ddab7ed24..3e0923cfba 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -221,14 +221,14 @@ static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
}
}
-static void platform_bus_create_devtree(PPCE500Params *params, void *fdt,
- const char *mpic)
+static void platform_bus_create_devtree(const PPCE500MachineClass *pmc,
+ void *fdt, const char *mpic)
{
- gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base);
+ gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base);
const char platcomp[] = "qemu,platform\0simple-bus";
- uint64_t addr = params->platform_bus_base;
- uint64_t size = params->platform_bus_size;
- int irq_start = params->platform_bus_first_irq;
+ uint64_t addr = pmc->platform_bus_base;
+ uint64_t size = pmc->platform_bus_size;
+ int irq_start = pmc->platform_bus_first_irq;
PlatformBusDevice *pbus;
DeviceState *dev;
@@ -265,8 +265,7 @@ static void platform_bus_create_devtree(PPCE500Params *params, void *fdt,
g_free(node);
}
-static int ppce500_load_device_tree(MachineState *machine,
- PPCE500Params *params,
+static int ppce500_load_device_tree(PPCE500MachineState *pms,
hwaddr addr,
hwaddr initrd_base,
hwaddr initrd_size,
@@ -274,6 +273,8 @@ static int ppce500_load_device_tree(MachineState *machine,
hwaddr kernel_size,
bool dry_run)
{
+ MachineState *machine = MACHINE(pms);
+ const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
CPUPPCState *env = first_cpu->env_ptr;
int ret = -1;
uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
@@ -295,12 +296,12 @@ static int ppce500_load_device_tree(MachineState *machine,
int len;
uint32_t pci_ranges[14] =
{
- 0x2000000, 0x0, params->pci_mmio_bus_base,
- params->pci_mmio_base >> 32, params->pci_mmio_base,
+ 0x2000000, 0x0, pmc->pci_mmio_bus_base,
+ pmc->pci_mmio_base >> 32, pmc->pci_mmio_base,
0x0, 0x20000000,
0x1000000, 0x0, 0x0,
- params->pci_pio_base >> 32, params->pci_pio_base,
+ pmc->pci_pio_base >> 32, pmc->pci_pio_base,
0x0, 0x10000,
};
QemuOpts *machine_opts = qemu_get_machine_opts();
@@ -391,7 +392,7 @@ static int ppce500_load_device_tree(MachineState *machine,
for (i = smp_cpus - 1; i >= 0; i--) {
CPUState *cpu;
char cpu_name[128];
- uint64_t cpu_release_addr = params->spin_base + (i * 0x20);
+ uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
cpu = qemu_get_cpu(i);
if (cpu == NULL) {
@@ -425,7 +426,7 @@ static int ppce500_load_device_tree(MachineState *machine,
qemu_fdt_add_subnode(fdt, "/aliases");
/* XXX These should go into their respective devices' code */
- snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base);
+ snprintf(soc, sizeof(soc), "/soc@%"PRIx64, pmc->ccsrbar_base);
qemu_fdt_add_subnode(fdt, soc);
qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
@@ -433,7 +434,7 @@ static int ppce500_load_device_tree(MachineState *machine,
qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
- params->ccsrbar_base >> 32, params->ccsrbar_base,
+ pmc->ccsrbar_base >> 32, pmc->ccsrbar_base,
MPC8544_CCSRBAR_SIZE);
/* XXX should contain a reasonable value */
qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
@@ -493,7 +494,7 @@ static int ppce500_load_device_tree(MachineState *machine,
qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
snprintf(pci, sizeof(pci), "/pci@%llx",
- params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
+ pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
qemu_fdt_add_subnode(fdt, pci);
qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
@@ -501,7 +502,7 @@ static int ppce500_load_device_tree(MachineState *machine,
qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
0x0, 0x7);
pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
- params->pci_first_slot, params->pci_nr_slots,
+ pmc->pci_first_slot, pmc->pci_nr_slots,
&len);
qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
@@ -513,8 +514,8 @@ static int ppce500_load_device_tree(MachineState *machine,
qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
qemu_fdt_setprop_cells(fdt, pci, "reg",
- (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
- (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
+ (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
+ (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
0, 0x1000);
qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
@@ -522,15 +523,15 @@ static int ppce500_load_device_tree(MachineState *machine,
qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
- if (params->has_mpc8xxx_gpio) {
+ if (pmc->has_mpc8xxx_gpio) {
create_dt_mpc8xxx_gpio(fdt, soc, mpic);
}
- if (params->has_platform_bus) {
- platform_bus_create_devtree(params, fdt, mpic);
+ if (pmc->has_platform_bus) {
+ platform_bus_create_devtree(pmc, fdt, mpic);
}
- params->fixup_devtree(params, fdt);
+ pmc->fixup_devtree(fdt);
if (toplevel_compat) {
qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
@@ -551,8 +552,7 @@ out:
}
typedef struct DeviceTreeParams {
- MachineState *machine;
- PPCE500Params params;
+ PPCE500MachineState *machine;
hwaddr addr;
hwaddr initrd_base;
hwaddr initrd_size;
@@ -564,7 +564,7 @@ typedef struct DeviceTreeParams {
static void ppce500_reset_device_tree(void *opaque)
{
DeviceTreeParams *p = opaque;
- ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base,
+ ppce500_load_device_tree(p->machine, p->addr, p->initrd_base,
p->initrd_size, p->kernel_base, p->kernel_size,
false);
}
@@ -575,8 +575,7 @@ static void ppce500_init_notify(Notifier *notifier, void *data)
ppce500_reset_device_tree(p);
}
-static int ppce500_prep_device_tree(MachineState *machine,
- PPCE500Params *params,
+static int ppce500_prep_device_tree(PPCE500MachineState *machine,
hwaddr addr,
hwaddr initrd_base,
hwaddr initrd_size,
@@ -585,7 +584,6 @@ static int ppce500_prep_device_tree(MachineState *machine,
{
DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
p->machine = machine;
- p->params = *params;
p->addr = addr;
p->initrd_base = initrd_base;
p->initrd_size = initrd_size;
@@ -597,9 +595,8 @@ static int ppce500_prep_device_tree(MachineState *machine,
qemu_add_machine_init_done_notifier(&p->notifier);
/* Issue the device tree loader once, so that we get the size of the blob */
- return ppce500_load_device_tree(machine, params, addr, initrd_base,
- initrd_size, kernel_base, kernel_size,
- true);
+ return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size,
+ kernel_base, kernel_size, true);
}
/* Create -kernel TLB entries for BookE. */
@@ -685,17 +682,19 @@ static void ppce500_cpu_reset(void *opaque)
mmubooke_create_initial_mapping(env);
}
-static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
+static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
qemu_irq **irqs)
{
DeviceState *dev;
SysBusDevice *s;
int i, j, k;
+ MachineState *machine = MACHINE(pms);
+ const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
dev = qdev_create(NULL, TYPE_OPENPIC);
- object_property_add_child(qdev_get_machine(), "pic", OBJECT(dev),
+ object_property_add_child(OBJECT(machine), "pic", OBJECT(dev),
&error_fatal);
- qdev_prop_set_uint32(dev, "model", params->mpic_version);
+ qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
qdev_init_nofail(dev);
@@ -711,7 +710,7 @@ static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
return dev;
}
-static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
+static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
qemu_irq **irqs, Error **errp)
{
Error *err = NULL;
@@ -719,7 +718,7 @@ static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
CPUState *cs;
dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
- qdev_prop_set_uint32(dev, "model", params->mpic_version);
+ qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
object_property_set_bool(OBJECT(dev), true, "realized", &err);
if (err) {
@@ -739,11 +738,12 @@ static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
return dev;
}
-static DeviceState *ppce500_init_mpic(MachineState *machine,
- PPCE500Params *params,
+static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
MemoryRegion *ccsr,
qemu_irq **irqs)
{
+ MachineState *machine = MACHINE(pms);
+ const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
DeviceState *dev = NULL;
SysBusDevice *s;
@@ -751,7 +751,7 @@ static DeviceState *ppce500_init_mpic(MachineState *machine,
Error *err = NULL;
if (machine_kernel_irqchip_allowed(machine)) {
- dev = ppce500_init_mpic_kvm(params, irqs, &err);
+ dev = ppce500_init_mpic_kvm(pmc, irqs, &err);
}
if (machine_kernel_irqchip_required(machine) && !dev) {
error_reportf_err(err,
@@ -761,7 +761,7 @@ static DeviceState *ppce500_init_mpic(MachineState *machine,
}
if (!dev) {
- dev = ppce500_init_mpic_qemu(params, irqs);
+ dev = ppce500_init_mpic_qemu(pms, irqs);
}
s = SYS_BUS_DEVICE(dev);
@@ -778,10 +778,12 @@ static void ppce500_power_off(void *opaque, int line, int on)
}
}
-void ppce500_init(MachineState *machine, PPCE500Params *params)
+void ppce500_init(MachineState *machine)
{
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
+ PPCE500MachineState *pms = PPCE500_MACHINE(machine);
+ const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
PCIBus *pci_bus;
CPUPPCState *env = NULL;
uint64_t loadaddr;
@@ -835,8 +837,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
- env->mpic_iack = params->ccsrbar_base +
- MPC8544_MPIC_REGS_OFFSET + 0xa0;
+ env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
@@ -869,10 +870,10 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
qdev_init_nofail(dev);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
- memory_region_add_subregion(address_space_mem, params->ccsrbar_base,
+ memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
ccsr_addr_space);
- mpicdev = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs);
+ mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs);
/* Serial */
if (serial_hd(0)) {
@@ -898,7 +899,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
dev = qdev_create(NULL, "e500-pcihost");
object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev),
&error_abort);
- qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
+ qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
@@ -921,9 +922,9 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
}
/* Register spinning region */
- sysbus_create_simple("e500-spin", params->spin_base, NULL);
+ sysbus_create_simple("e500-spin", pmc->spin_base, NULL);
- if (params->has_mpc8xxx_gpio) {
+ if (pmc->has_mpc8xxx_gpio) {
qemu_irq poweroff_irq;
dev = qdev_create(NULL, "mpc8xxx_gpio");
@@ -939,21 +940,21 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
}
/* Platform Bus Device */
- if (params->has_platform_bus) {
+ if (pmc->has_platform_bus) {
dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
dev->id = TYPE_PLATFORM_BUS_DEVICE;
- qdev_prop_set_uint32(dev, "num_irqs", params->platform_bus_num_irqs);
- qdev_prop_set_uint32(dev, "mmio_size", params->platform_bus_size);
+ qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
+ qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
- for (i = 0; i < params->platform_bus_num_irqs; i++) {
- int irqn = params->platform_bus_first_irq + i;
+ for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
+ int irqn = pmc->platform_bus_first_irq + i;
sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
}
memory_region_add_subregion(address_space_mem,
- params->platform_bus_base,
+ pmc->platform_bus_base,
sysbus_mmio_get_region(s, 0));
}
@@ -1056,7 +1057,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
exit(1);
}
- dt_size = ppce500_prep_device_tree(machine, params, dt_base,
+ dt_size = ppce500_prep_device_tree(pms, dt_base,
initrd_base, initrd_size,
kernel_base, kernel_size);
if (dt_size < 0) {
@@ -1085,9 +1086,17 @@ static const TypeInfo e500_ccsr_info = {
.instance_init = e500_ccsr_initfn,
};
+static const TypeInfo ppce500_info = {
+ .name = TYPE_PPCE500_MACHINE,
+ .parent = TYPE_MACHINE,
+ .abstract = true,
+ .class_size = sizeof(PPCE500MachineClass),
+};
+
static void e500_register_types(void)
{
type_register_static(&e500_ccsr_info);
+ type_register_static(&ppce500_info);
}
type_init(e500_register_types)
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 70ba1d8f4f..621403bd24 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -3,12 +3,21 @@
#include "hw/boards.h"
-typedef struct PPCE500Params {
- int pci_first_slot;
- int pci_nr_slots;
+typedef struct PPCE500MachineState {
+ /*< private >*/
+ MachineState parent_obj;
+
+} PPCE500MachineState;
+
+typedef struct PPCE500MachineClass {
+ /*< private >*/
+ MachineClass parent_class;
/* required -- must at least add toplevel board compatible */
- void (*fixup_devtree)(struct PPCE500Params *params, void *fdt);
+ void (*fixup_devtree)(void *fdt);
+
+ int pci_first_slot;
+ int pci_nr_slots;
int mpic_version;
bool has_mpc8xxx_gpio;
@@ -22,10 +31,18 @@ typedef struct PPCE500Params {
hwaddr pci_mmio_base;
hwaddr pci_mmio_bus_base;
hwaddr spin_base;
-} PPCE500Params;
+} PPCE500MachineClass;
-void ppce500_init(MachineState *machine, PPCE500Params *params);
+void ppce500_init(MachineState *machine);
hwaddr booke206_page_size_to_tlb(uint64_t size);
+#define TYPE_PPCE500_MACHINE "ppce500-base-machine"
+#define PPCE500_MACHINE(obj) \
+ OBJECT_CHECK(PPCE500MachineState, (obj), TYPE_PPCE500_MACHINE)
+#define PPCE500_MACHINE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(PPCE500MachineClass, obj, TYPE_PPCE500_MACHINE)
+#define PPCE500_MACHINE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(PPCE500MachineClass, klass, TYPE_PPCE500_MACHINE)
+
#endif
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 81d03e1038..f69aadb666 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -21,7 +21,7 @@
#include "hw/ppc/openpic.h"
#include "kvm_ppc.h"
-static void e500plat_fixup_devtree(PPCE500Params *params, void *fdt)
+static void e500plat_fixup_devtree(void *fdt)
{
const char model[] = "QEMU ppce500";
const char compatible[] = "fsl,qemu-e500";
@@ -33,40 +33,54 @@ static void e500plat_fixup_devtree(PPCE500Params *params, void *fdt)
static void e500plat_init(MachineState *machine)
{
- PPCE500Params params = {
- .pci_first_slot = 0x1,
- .pci_nr_slots = PCI_SLOT_MAX - 1,
- .fixup_devtree = e500plat_fixup_devtree,
- .mpic_version = OPENPIC_MODEL_FSL_MPIC_42,
- .has_mpc8xxx_gpio = true,
- .has_platform_bus = true,
- .platform_bus_base = 0xf00000000ULL,
- .platform_bus_size = (128ULL * 1024 * 1024),
- .platform_bus_first_irq = 5,
- .platform_bus_num_irqs = 10,
- .ccsrbar_base = 0xFE0000000ULL,
- .pci_pio_base = 0xFE1000000ULL,
- .pci_mmio_base = 0xC00000000ULL,
- .pci_mmio_bus_base = 0xE0000000ULL,
- .spin_base = 0xFEF000000ULL,
- };
-
+ PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
/* Older KVM versions don't support EPR which breaks guests when we announce
MPIC variants that support EPR. Revert to an older one for those */
if (kvm_enabled() && !kvmppc_has_cap_epr()) {
- params.mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
+ pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
}
- ppce500_init(machine, ¶ms);
+ ppce500_init(machine);
}
-static void e500plat_machine_init(MachineClass *mc)
+#define TYPE_E500PLAT_MACHINE MACHINE_TYPE_NAME("ppce500")
+
+static void e500plat_machine_class_init(ObjectClass *oc, void *data)
{
+ PPCE500MachineClass *pmc = PPCE500_MACHINE_CLASS(oc);
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ pmc->pci_first_slot = 0x1;
+ pmc->pci_nr_slots = PCI_SLOT_MAX - 1;
+ pmc->fixup_devtree = e500plat_fixup_devtree;
+ pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42;
+ pmc->has_mpc8xxx_gpio = true;
+ pmc->has_platform_bus = true;
+ pmc->platform_bus_base = 0xf00000000ULL;
+ pmc->platform_bus_size = (128ULL * 1024 * 1024);
+ pmc->platform_bus_first_irq = 5;
+ pmc->platform_bus_num_irqs = 10;
+ pmc->ccsrbar_base = 0xFE0000000ULL;
+ pmc->pci_pio_base = 0xFE1000000ULL;
+ pmc->pci_mmio_base = 0xC00000000ULL;
+ pmc->pci_mmio_bus_base = 0xE0000000ULL;
+ pmc->spin_base = 0xFEF000000ULL;
+
mc->desc = "generic paravirt e500 platform";
mc->init = e500plat_init;
mc->max_cpus = 32;
- machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ETSEC_COMMON);
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30");
-}
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ETSEC_COMMON);
+ }
+
+static const TypeInfo e500plat_info = {
+ .name = TYPE_E500PLAT_MACHINE,
+ .parent = TYPE_PPCE500_MACHINE,
+ .class_init = e500plat_machine_class_init,
+};
-DEFINE_MACHINE("ppce500", e500plat_machine_init)
+static void e500plat_register_types(void)
+{
+ type_register_static(&e500plat_info);
+}
+type_init(e500plat_register_types)
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index 1717953ec7..ab30a2a99e 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -18,7 +18,7 @@
#include "qemu/error-report.h"
#include "cpu.h"
-static void mpc8544ds_fixup_devtree(PPCE500Params *params, void *fdt)
+static void mpc8544ds_fixup_devtree(void *fdt)
{
const char model[] = "MPC8544DS";
const char compatible[] = "MPC8544DS\0MPC85xxDS";
@@ -30,33 +30,46 @@ static void mpc8544ds_fixup_devtree(PPCE500Params *params, void *fdt)
static void mpc8544ds_init(MachineState *machine)
{
- PPCE500Params params = {
- .pci_first_slot = 0x11,
- .pci_nr_slots = 2,
- .fixup_devtree = mpc8544ds_fixup_devtree,
- .mpic_version = OPENPIC_MODEL_FSL_MPIC_20,
- .ccsrbar_base = 0xE0000000ULL,
- .pci_mmio_base = 0xC0000000ULL,
- .pci_mmio_bus_base = 0xC0000000ULL,
- .pci_pio_base = 0xE1000000ULL,
- .spin_base = 0xEF000000ULL,
- };
-
if (machine->ram_size > 0xc0000000) {
error_report("The MPC8544DS board only supports up to 3GB of RAM");
exit(1);
}
- ppce500_init(machine, ¶ms);
+ ppce500_init(machine);
}
-
-static void ppce500_machine_init(MachineClass *mc)
+static void e500plat_machine_class_init(ObjectClass *oc, void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ PPCE500MachineClass *pmc = PPCE500_MACHINE_CLASS(oc);
+
+ pmc->pci_first_slot = 0x11;
+ pmc->pci_nr_slots = 2;
+ pmc->fixup_devtree = mpc8544ds_fixup_devtree;
+ pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20;
+ pmc->ccsrbar_base = 0xE0000000ULL;
+ pmc->pci_mmio_base = 0xC0000000ULL;
+ pmc->pci_mmio_bus_base = 0xC0000000ULL;
+ pmc->pci_pio_base = 0xE1000000ULL;
+ pmc->spin_base = 0xEF000000ULL;
+
mc->desc = "mpc8544ds";
mc->init = mpc8544ds_init;
mc->max_cpus = 15;
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30");
}
-DEFINE_MACHINE("mpc8544ds", ppce500_machine_init)
+#define TYPE_MPC8544DS_MACHINE MACHINE_TYPE_NAME("mpc8544ds")
+
+static const TypeInfo mpc8544ds_info = {
+ .name = TYPE_MPC8544DS_MACHINE,
+ .parent = TYPE_PPCE500_MACHINE,
+ .class_init = e500plat_machine_class_init,
+};
+
+static void mpc8544ds_register_types(void)
+{
+ type_register_static(&mpc8544ds_info);
+}
+
+type_init(mpc8544ds_register_types)
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 46/49] spapr: Support ibm, dynamic-memory-v2 property
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (44 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 45/49] ppc: e500: switch E500 based machines to full machine definition David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 47/49] target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr() David Gibson
` (4 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, Bharata B Rao, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
The new property ibm,dynamic-memory-v2 allows memory to be represented
in a more compact manner in device tree.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
docs/specs/ppc-spapr-hotplug.txt | 19 ++++
hw/ppc/spapr.c | 230 +++++++++++++++++++++++++++++++--------
include/hw/ppc/spapr_ovec.h | 1 +
3 files changed, 202 insertions(+), 48 deletions(-)
diff --git a/docs/specs/ppc-spapr-hotplug.txt b/docs/specs/ppc-spapr-hotplug.txt
index f57e2a09c6..cc7833108e 100644
--- a/docs/specs/ppc-spapr-hotplug.txt
+++ b/docs/specs/ppc-spapr-hotplug.txt
@@ -387,4 +387,23 @@ Each LMB list entry consists of the following elements:
- A 32bit flags word. The bit at bit position 0x00000008 defines whether
the LMB is assigned to the the partition as of boot time.
+ibm,dynamic-memory-v2
+
+This property describes the dynamically reconfigurable memory. This is
+an alternate and newer way to describe dyanamically reconfigurable memory.
+It is a property encoded array that has an integer N (the number of
+LMB set entries) followed by N LMB set entries. There is an LMB set entry
+for each sequential group of LMBs that share common attributes.
+
+Each LMB set entry consists of the following elements:
+
+- Number of sequential LMBs in the entry represented by a 32bit integer.
+- Logical address of the first LMB in the set encoded as a 64bit integer.
+- DRC index of the first LMB in the set.
+- Associativity list index that is used as an index into
+ ibm,associativity-lookup-arrays property described earlier. This
+ is used to retrieve the right associativity list to be used for all
+ the LMBs in this set.
+- A 32bit flags word that applies to all the LMBs in the set.
+
[1] http://thread.gmane.org/gmane.linux.ports.ppc.embedded/75350/focus=106867
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 2203b6f46d..b35aff5d81 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -668,63 +668,137 @@ static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
return -1;
}
-/*
- * Adds ibm,dynamic-reconfiguration-memory node.
- * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
- * of this device tree node.
- */
-static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
+struct sPAPRDrconfCellV2 {
+ uint32_t seq_lmbs;
+ uint64_t base_addr;
+ uint32_t drc_index;
+ uint32_t aa_index;
+ uint32_t flags;
+} QEMU_PACKED;
+
+typedef struct DrconfCellQueue {
+ struct sPAPRDrconfCellV2 cell;
+ QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
+} DrconfCellQueue;
+
+static DrconfCellQueue *
+spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
+ uint32_t drc_index, uint32_t aa_index,
+ uint32_t flags)
{
- MachineState *machine = MACHINE(spapr);
- int ret, i, offset;
- uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
- uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
- uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
- uint32_t nr_lmbs = (spapr->hotplug_memory.base +
- memory_region_size(&spapr->hotplug_memory.mr)) /
- lmb_size;
- uint32_t *int_buf, *cur_index, buf_len;
- int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
- MemoryDeviceInfoList *dimms = NULL;
+ DrconfCellQueue *elem;
- /*
- * Don't create the node if there is no hotpluggable memory
- */
- if (machine->ram_size == machine->maxram_size) {
- return 0;
- }
+ elem = g_malloc0(sizeof(*elem));
+ elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
+ elem->cell.base_addr = cpu_to_be64(base_addr);
+ elem->cell.drc_index = cpu_to_be32(drc_index);
+ elem->cell.aa_index = cpu_to_be32(aa_index);
+ elem->cell.flags = cpu_to_be32(flags);
- /*
- * Allocate enough buffer size to fit in ibm,dynamic-memory
- * or ibm,associativity-lookup-arrays
- */
- buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
- * sizeof(uint32_t);
- cur_index = int_buf = g_malloc0(buf_len);
+ return elem;
+}
- offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
+/* ibm,dynamic-memory-v2 */
+static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt,
+ int offset, MemoryDeviceInfoList *dimms)
+{
+ uint8_t *int_buf, *cur_index, buf_len;
+ int ret;
+ uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
+ uint64_t addr, cur_addr, size;
+ uint32_t nr_boot_lmbs = (spapr->hotplug_memory.base / lmb_size);
+ uint64_t mem_end = spapr->hotplug_memory.base +
+ memory_region_size(&spapr->hotplug_memory.mr);
+ uint32_t node, nr_entries = 0;
+ sPAPRDRConnector *drc;
+ DrconfCellQueue *elem, *next;
+ MemoryDeviceInfoList *info;
+ QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
+ = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
+
+ /* Entry to cover RAM and the gap area */
+ elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
+ SPAPR_LMB_FLAGS_RESERVED |
+ SPAPR_LMB_FLAGS_DRC_INVALID);
+ QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
+ nr_entries++;
+
+ cur_addr = spapr->hotplug_memory.base;
+ for (info = dimms; info; info = info->next) {
+ PCDIMMDeviceInfo *di = info->value->u.dimm.data;
+
+ addr = di->addr;
+ size = di->size;
+ node = di->node;
+
+ /* Entry for hot-pluggable area */
+ if (cur_addr < addr) {
+ drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
+ g_assert(drc);
+ elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
+ cur_addr, spapr_drc_index(drc), -1, 0);
+ QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
+ nr_entries++;
+ }
- ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
- sizeof(prop_lmb_size));
- if (ret < 0) {
- goto out;
+ /* Entry for DIMM */
+ drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
+ g_assert(drc);
+ elem = spapr_get_drconf_cell(size / lmb_size, addr,
+ spapr_drc_index(drc), node,
+ SPAPR_LMB_FLAGS_ASSIGNED);
+ QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
+ nr_entries++;
+ cur_addr = addr + size;
}
- ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
- if (ret < 0) {
- goto out;
+ /* Entry for remaining hotpluggable area */
+ if (cur_addr < mem_end) {
+ drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
+ g_assert(drc);
+ elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
+ cur_addr, spapr_drc_index(drc), -1, 0);
+ QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
+ nr_entries++;
}
- ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
- if (ret < 0) {
- goto out;
+ buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
+ int_buf = cur_index = g_malloc0(buf_len);
+ *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
+ cur_index += sizeof(nr_entries);
+
+ QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
+ memcpy(cur_index, &elem->cell, sizeof(elem->cell));
+ cur_index += sizeof(elem->cell);
+ QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
+ g_free(elem);
}
- if (hotplug_lmb_start) {
- dimms = qmp_pc_dimm_device_list();
+ ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
+ g_free(int_buf);
+ if (ret < 0) {
+ return -1;
}
+ return 0;
+}
+
+/* ibm,dynamic-memory */
+static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt,
+ int offset, MemoryDeviceInfoList *dimms)
+{
+ int i, ret;
+ uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
+ uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
+ uint32_t nr_lmbs = (spapr->hotplug_memory.base +
+ memory_region_size(&spapr->hotplug_memory.mr)) /
+ lmb_size;
+ uint32_t *int_buf, *cur_index, buf_len;
- /* ibm,dynamic-memory */
+ /*
+ * Allocate enough buffer size to fit in ibm,dynamic-memory
+ */
+ buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
+ cur_index = int_buf = g_malloc0(buf_len);
int_buf[0] = cpu_to_be32(nr_lmbs);
cur_index++;
for (i = 0; i < nr_lmbs; i++) {
@@ -764,13 +838,71 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
}
- qapi_free_MemoryDeviceInfoList(dimms);
ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
+ g_free(int_buf);
if (ret < 0) {
- goto out;
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * Adds ibm,dynamic-reconfiguration-memory node.
+ * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
+ * of this device tree node.
+ */
+static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
+{
+ MachineState *machine = MACHINE(spapr);
+ int ret, i, offset;
+ uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
+ uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
+ uint32_t *int_buf, *cur_index, buf_len;
+ int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
+ MemoryDeviceInfoList *dimms = NULL;
+
+ /*
+ * Don't create the node if there is no hotpluggable memory
+ */
+ if (machine->ram_size == machine->maxram_size) {
+ return 0;
+ }
+
+ offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
+
+ ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
+ sizeof(prop_lmb_size));
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
+ if (ret < 0) {
+ return ret;
+ }
+
+ ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
+ if (ret < 0) {
+ return ret;
+ }
+
+ /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
+ dimms = qmp_pc_dimm_device_list();
+ if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
+ ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
+ } else {
+ ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
+ }
+ qapi_free_MemoryDeviceInfoList(dimms);
+
+ if (ret < 0) {
+ return ret;
}
/* ibm,associativity-lookup-arrays */
+ buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
+ cur_index = int_buf = g_malloc0(buf_len);
+
cur_index = int_buf;
int_buf[0] = cpu_to_be32(nr_nodes);
int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
@@ -787,8 +919,8 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
}
ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
(cur_index - int_buf) * sizeof(uint32_t));
-out:
g_free(int_buf);
+
return ret;
}
@@ -2491,6 +2623,9 @@ static void spapr_machine_init(MachineState *machine)
spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
}
+ /* advertise support for ibm,dyamic-memory-v2 */
+ spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
+
/* init CPUs */
spapr_init_cpus(spapr);
@@ -2918,7 +3053,6 @@ static void spapr_instance_init(Object *obj)
" place of standard EPOW events when possible"
" (required for memory hot-unplug support)",
NULL);
-
ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
"Maximum permitted CPU compatibility mode",
&error_fatal);
diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h
index bf25e5d954..0f2d8d715d 100644
--- a/include/hw/ppc/spapr_ovec.h
+++ b/include/hw/ppc/spapr_ovec.h
@@ -51,6 +51,7 @@ typedef struct sPAPROptionVector sPAPROptionVector;
#define OV5_FORM1_AFFINITY OV_BIT(5, 0)
#define OV5_HP_EVT OV_BIT(6, 5)
#define OV5_HPT_RESIZE OV_BIT(6, 7)
+#define OV5_DRMEM_V2 OV_BIT(22, 0)
#define OV5_XIVE_BOTH OV_BIT(23, 0)
#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 47/49] target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr()
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (45 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 46/49] spapr: Support ibm, dynamic-memory-v2 property David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 48/49] spapr: Set compatibility mode before the rest of spapr_cpu_reset() David Gibson
` (3 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
cpu_ppc_set_papr() removes the EP and HV bits from the MSR mask. While
removing the HV bit makes sense (a cpu in PAPR mode should never be
emulated in hypervisor mode), the EP bit is just bizarre. Although it's
true that a papr mode guest shouldn't be able to change the exception
prefix, the MSR[EP] bit doesn't even exist on the cpus supported for PAPR
mode, so it's pointless to do anything with it here.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
target/ppc/translate_init.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index bb79d23b50..808f6c1a08 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8874,12 +8874,11 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
cpu->vhyp = vhyp;
- /* PAPR always has exception vectors in RAM not ROM. To ensure this,
- * MSR[IP] should never be set.
- *
- * We also disallow setting of MSR_HV
+ /*
+ * With a virtual hypervisor mode we never allow the CPU to go
+ * hypervisor mode itself
*/
- env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
+ env->msr_mask &= ~MSR_HVB;
/* Set emulated LPCR to not send interrupts to hypervisor. Note that
* under KVM, the actual HW LPCR will be set differently by KVM itself,
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 48/49] spapr: Set compatibility mode before the rest of spapr_cpu_reset()
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (46 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 47/49] target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr() David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 49/49] Clear mem_path if we fall back to anonymous RAM allocation David Gibson
` (2 subsequent siblings)
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
Although the order doesn't really matter at the moment, it's possible
other initializastions could depend on the compatiblity mode, so make sure
we set it first in spapr_cpu_reset().
While we're at it drop the test against first_cpu. Setting the compat mode
to the value it already has is redundant, but harmless, so we might as well
make a small simplification to the code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr_cpu_core.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 94afeb399e..01dbc69424 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -31,6 +31,11 @@ static void spapr_cpu_reset(void *opaque)
cpu_reset(cs);
+ /* Set compatibility mode to match the boot CPU, which was either set
+ * by the machine reset code or by CAS. This should never fail.
+ */
+ ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
+
/* All CPUs start halted. CPU0 is unhalted from the machine level
* reset code and the rest are explicitly started up by the guest
* using an RTAS call */
@@ -45,12 +50,6 @@ static void spapr_cpu_reset(void *opaque)
env->spr[SPR_LPCR] &= ~pcc->lpcr_pm;
}
- /* Set compatibility mode to match the boot CPU, which was either set
- * by the machine reset code or by CAS. This should never fail.
- */
- if (cs != first_cpu) {
- ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
- }
}
static void spapr_cpu_destroy(PowerPCCPU *cpu)
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [Qemu-devel] [PULL 49/49] Clear mem_path if we fall back to anonymous RAM allocation
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (47 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 48/49] spapr: Set compatibility mode before the rest of spapr_cpu_reset() David Gibson
@ 2018-04-27 9:21 ` David Gibson
2018-04-27 10:13 ` [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 no-reply
2018-04-27 10:39 ` Peter Maydell
50 siblings, 0 replies; 52+ messages in thread
From: David Gibson @ 2018-04-27 9:21 UTC (permalink / raw)
To: peter.maydell; +Cc: groug, qemu-devel, qemu-ppc, David Gibson
If the -mem-path option is set, we attempt to map the guest's RAM from a
file in the given path; it's usually used to back guest RAM with hugepages.
If we're unable to (e.g. not enough free hugepages) then we fall back to
allocating normal anonymous pages. This behaviour can be surprising, but a
comment in allocate_system_memory_nonnuma() suggests it's legacy behaviour
we can't change.
What really isn't ok, though, is that in this case we leave mem_path set.
That means functions which attempt to determine the pagesize of main RAM
can erroneously think it is hugepage based on the requested path, even
though it's not.
This is particular bad for the pseries machine type. KVM HV limitations
mean the guest can't use pagesizes larger than the host page size used to
back RAM. That means that such a fallback, rather than merely giving
poorer performance than expected will cause the guest to freeze up early in
boot as it attempts to use large page mappings that can't work.
This patch addresses the problem by clearing the mem_path variable when we
fall back to anonymous pages, meaning that subsequent attempts to
determine the RAM page size will get an accurate result.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
numa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/numa.c b/numa.c
index 1116c90af9..78a869e598 100644
--- a/numa.c
+++ b/numa.c
@@ -469,6 +469,7 @@ static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner,
/* Legacy behavior: if allocation failed, fall back to
* regular RAM allocation.
*/
+ mem_path = NULL;
memory_region_init_ram_nomigrate(mr, owner, name, ram_size, &error_fatal);
}
#else
--
2.14.3
^ permalink raw reply related [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (48 preceding siblings ...)
2018-04-27 9:21 ` [Qemu-devel] [PULL 49/49] Clear mem_path if we fall back to anonymous RAM allocation David Gibson
@ 2018-04-27 10:13 ` no-reply
2018-04-27 10:39 ` Peter Maydell
50 siblings, 0 replies; 52+ messages in thread
From: no-reply @ 2018-04-27 10:13 UTC (permalink / raw)
To: david; +Cc: famz, peter.maydell, qemu-ppc, groug, qemu-devel
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180427092126.24812-1-david@gibson.dropbear.id.au
Subject: [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20180427092126.24812-1-david@gibson.dropbear.id.au -> patchew/20180427092126.24812-1-david@gibson.dropbear.id.au
Switched to a new branch 'test'
626125dd6a Clear mem_path if we fall back to anonymous RAM allocation
1cb34b9657 spapr: Set compatibility mode before the rest of spapr_cpu_reset()
1a58957f3b target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr()
d6d2f6f166 spapr: Support ibm, dynamic-memory-v2 property
e3cc82abbc ppc: e500: switch E500 based machines to full machine definition
ae53594c96 spapr: Add ibm, max-associativity-domains property
afa9b64a12 target/ppc: Fold slb_nr into PPCHash64Options
29159ef8e0 target/ppc: Get rid of POWERPC_MMU_VER() macros
04a45a3cb0 target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model
98ad6b634b target/ppc: Fold ci_large_pages flag into PPCHash64Options
177121bf2a target/ppc: Move 1T segment and AMR options to PPCHash64Options
c5e9ce0454 target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs
1a1b68e40d target/ppc: Split page size information into a separate allocation
71bdec3362 target/ppc: Move page size setup to helper function
d0f975aadc target/ppc: Remove fallback 64k pagesize information
0b222ce598 target/ppc: Avoid taking "env" parameter to mmu-hash64 functions
b264b4e4ba target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()
40fca579a0 target/ppc: Simplify cpu valid check in ppc_cpu_realize
97c3a208a6 target/ppc: Standardize instance_init and realize function names
e016914097 spapr: drop useless dynamic sysbus device sanity check
bc145fe8b7 Revert "spapr: Don't allow memory hotplug to memory less nodes"
3a6337c247 spapr: drop useless sanity check in spapr_irq_alloc*()
966de6a65e Add host_memory_backend_pagesize() helper
826920ec44 Make qemu_mempath_getpagesize() accept NULL
d515ad4b89 spapr: Introduce pseries-2.13 machine type
e708833f76 target/ppc: Fix reserved bit mask of dstst instruction
798b69e16c ppc: Fix size of ppc64 xer register
c60fb4018a uninorth: rename UNINState to UNINHostState
c4782da8e3 uninorth: move PCI IO (ISA) memory region into the uninorth device
64ebeb460f uninorth: use object link to pass OpenPIC object to uninorth
72dd5354b3 uninorth: remove obsolete pci_pmac_u3_init() function
118bd490d6 uninorth: remove obsolete pci_pmac_init() function
c784d08f0e uninorth: enable internal PCI host bridge
ff57ec3e13 uninorth: fix PCI and AGP bus mixup
6c94d593a9 uninorth: move PCI host bridge bus initialisation into device realize
f9bf749e28 uninorth: introduce temporary pic_irqs device property
69b8c6a2dc uninorth: move PCI mmio memory region initialisation into init function
3a1e230e19 mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize()
1a00fb6cf0 mac_oldworld: remove pics IRQ array and wire up macio to heathrow directly
89750552a5 grackle: move PCI IO (ISA) memory region into the grackle device
39f1e52433 grackle: remove deprecated pci_grackle_init() function
875d60b543 grackle: general tidy-up and QOMify
0e29ac89fc heathrow: remove obsolete heathow_init() function
986f46a881 uninorth: alter pci_pmac_init() and pci_pmac_u3_init() to return uninorth device
a55c02b0f2 uninorth: move uninorth definitions into uninorth.h
100273f6a8 uninorth: remove stray PCIBus realize from mac_newworld.c
d8ae7f8b1d uninorth: QOMify PCI and AGP host bridges
37c17ba02d uninorth: remove second set of uninorth token registers
8afd2d170f uninorth: trivial style fixups
=== OUTPUT BEGIN ===
Checking PATCH 1/49: uninorth: trivial style fixups...
Checking PATCH 2/49: uninorth: remove second set of uninorth token registers...
Checking PATCH 3/49: uninorth: QOMify PCI and AGP host bridges...
Checking PATCH 4/49: uninorth: remove stray PCIBus realize from mac_newworld.c...
Checking PATCH 5/49: uninorth: move uninorth definitions into uninorth.h...
Checking PATCH 6/49: uninorth: alter pci_pmac_init() and pci_pmac_u3_init() to return uninorth device...
Checking PATCH 7/49: heathrow: remove obsolete heathow_init() function...
Checking PATCH 8/49: grackle: general tidy-up and QOMify...
Checking PATCH 9/49: grackle: remove deprecated pci_grackle_init() function...
Checking PATCH 10/49: grackle: move PCI IO (ISA) memory region into the grackle device...
Checking PATCH 11/49: mac_oldworld: remove pics IRQ array and wire up macio to heathrow directly...
Checking PATCH 12/49: mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize()...
Checking PATCH 13/49: uninorth: move PCI mmio memory region initialisation into init function...
Checking PATCH 14/49: uninorth: introduce temporary pic_irqs device property...
Checking PATCH 15/49: uninorth: move PCI host bridge bus initialisation into device realize...
ERROR: if this code is redundant consider removing it
#46: FILE: hw/pci-host/uninorth.c:127:
+#if 0
total: 1 errors, 0 warnings, 221 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 16/49: uninorth: fix PCI and AGP bus mixup...
Checking PATCH 17/49: uninorth: enable internal PCI host bridge...
Checking PATCH 18/49: uninorth: remove obsolete pci_pmac_init() function...
Checking PATCH 19/49: uninorth: remove obsolete pci_pmac_u3_init() function...
Checking PATCH 20/49: uninorth: use object link to pass OpenPIC object to uninorth...
Checking PATCH 21/49: uninorth: move PCI IO (ISA) memory region into the uninorth device...
Checking PATCH 22/49: uninorth: rename UNINState to UNINHostState...
Checking PATCH 23/49: ppc: Fix size of ppc64 xer register...
ERROR: spaces required around that '+' (ctx:VxV)
#40: FILE: target/ppc/gdbstub.c:43:
+ case 69+32: /* xer */
^
total: 1 errors, 0 warnings, 59 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 24/49: target/ppc: Fix reserved bit mask of dstst instruction...
Checking PATCH 25/49: spapr: Introduce pseries-2.13 machine type...
Checking PATCH 26/49: Make qemu_mempath_getpagesize() accept NULL...
Checking PATCH 27/49: Add host_memory_backend_pagesize() helper...
WARNING: architecture specific defines should be avoided
#35: FILE: backends/hostmem.c:266:
+#ifdef __linux__
total: 0 errors, 1 warnings, 59 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 28/49: spapr: drop useless sanity check in spapr_irq_alloc*()...
Checking PATCH 29/49: Revert "spapr: Don't allow memory hotplug to memory less nodes"...
Checking PATCH 30/49: spapr: drop useless dynamic sysbus device sanity check...
Checking PATCH 31/49: target/ppc: Standardize instance_init and realize function names...
Checking PATCH 32/49: target/ppc: Simplify cpu valid check in ppc_cpu_realize...
Checking PATCH 33/49: target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop()...
Checking PATCH 34/49: target/ppc: Avoid taking "env" parameter to mmu-hash64 functions...
Checking PATCH 35/49: target/ppc: Remove fallback 64k pagesize information...
Checking PATCH 36/49: target/ppc: Move page size setup to helper function...
Checking PATCH 37/49: target/ppc: Split page size information into a separate allocation...
Checking PATCH 38/49: target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs...
Checking PATCH 39/49: target/ppc: Move 1T segment and AMR options to PPCHash64Options...
Checking PATCH 40/49: target/ppc: Fold ci_large_pages flag into PPCHash64Options...
Checking PATCH 41/49: target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model...
Checking PATCH 42/49: target/ppc: Get rid of POWERPC_MMU_VER() macros...
Checking PATCH 43/49: target/ppc: Fold slb_nr into PPCHash64Options...
WARNING: line over 80 characters
#28: FILE: hw/ppc/pnv.c:183:
+ _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
WARNING: line over 80 characters
#42: FILE: hw/ppc/spapr.c:550:
+ _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
WARNING: line over 80 characters
#43: FILE: hw/ppc/spapr.c:551:
+ _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
total: 0 errors, 3 warnings, 239 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 44/49: spapr: Add ibm, max-associativity-domains property...
Checking PATCH 45/49: ppc: e500: switch E500 based machines to full machine definition...
Checking PATCH 46/49: spapr: Support ibm, dynamic-memory-v2 property...
Checking PATCH 47/49: target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr()...
Checking PATCH 48/49: spapr: Set compatibility mode before the rest of spapr_cpu_reset()...
Checking PATCH 49/49: Clear mem_path if we fall back to anonymous RAM allocation...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 52+ messages in thread
* Re: [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
` (49 preceding siblings ...)
2018-04-27 10:13 ` [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 no-reply
@ 2018-04-27 10:39 ` Peter Maydell
50 siblings, 0 replies; 52+ messages in thread
From: Peter Maydell @ 2018-04-27 10:39 UTC (permalink / raw)
To: David Gibson; +Cc: Greg Kurz, QEMU Developers, qemu-ppc
On 27 April 2018 at 10:20, David Gibson <david@gibson.dropbear.id.au> wrote:
> The following changes since commit ca92651697bdb2f15b36d347a498fbc31f4a4893:
>
> Merge remote-tracking branch 'remotes/iwj/tags/for-upstream.depriv-2' into staging (2018-04-26 19:22:09 +0100)
>
> are available in the Git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-2.13-20180427
>
> for you to fetch changes up to 6233b679cae8741890f981c9dd6570d47715141e:
>
> Clear mem_path if we fall back to anonymous RAM allocation (2018-04-27 18:05:23 +1000)
>
> ----------------------------------------------------------------
> ppc patch queue 2018-04-27
>
> Here's the first batch of ppc patches for 2.13. This has a lot of
> stuff that's accumulated during the 2.12 freeze. Highlights are:
>
> * Many improvements for the Uninorth PCI host bridge for Mac
> machine types
> * Preliminary helpers improve handling of multiple backing
> pagesizes (not strictly ppc related, but have acks and aimed to
> allow future ppc changes)
> * Cleanups to pseries cpu initialization
> * Cleanups to hash64 MMU handling
> * Assorted bugfixes and improvements
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2018-04-27 10:39 UTC | newest]
Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-27 9:20 [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 01/49] uninorth: trivial style fixups David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 02/49] uninorth: remove second set of uninorth token registers David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 03/49] uninorth: QOMify PCI and AGP host bridges David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 04/49] uninorth: remove stray PCIBus realize from mac_newworld.c David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 05/49] uninorth: move uninorth definitions into uninorth.h David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 06/49] uninorth: alter pci_pmac_init() and pci_pmac_u3_init() to return uninorth device David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 07/49] heathrow: remove obsolete heathow_init() function David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 08/49] grackle: general tidy-up and QOMify David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 09/49] grackle: remove deprecated pci_grackle_init() function David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 10/49] grackle: move PCI IO (ISA) memory region into the grackle device David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 11/49] mac_oldworld: remove pics IRQ array and wire up macio to heathrow directly David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 12/49] mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize() David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 13/49] uninorth: move PCI mmio memory region initialisation into init function David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 14/49] uninorth: introduce temporary pic_irqs device property David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 15/49] uninorth: move PCI host bridge bus initialisation into device realize David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 16/49] uninorth: fix PCI and AGP bus mixup David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 17/49] uninorth: enable internal PCI host bridge David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 18/49] uninorth: remove obsolete pci_pmac_init() function David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 19/49] uninorth: remove obsolete pci_pmac_u3_init() function David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 20/49] uninorth: use object link to pass OpenPIC object to uninorth David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 21/49] uninorth: move PCI IO (ISA) memory region into the uninorth device David Gibson
2018-04-27 9:20 ` [Qemu-devel] [PULL 22/49] uninorth: rename UNINState to UNINHostState David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 23/49] ppc: Fix size of ppc64 xer register David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 24/49] target/ppc: Fix reserved bit mask of dstst instruction David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 25/49] spapr: Introduce pseries-2.13 machine type David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 26/49] Make qemu_mempath_getpagesize() accept NULL David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 27/49] Add host_memory_backend_pagesize() helper David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 28/49] spapr: drop useless sanity check in spapr_irq_alloc*() David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 29/49] Revert "spapr: Don't allow memory hotplug to memory less nodes" David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 30/49] spapr: drop useless dynamic sysbus device sanity check David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 31/49] target/ppc: Standardize instance_init and realize function names David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 32/49] target/ppc: Simplify cpu valid check in ppc_cpu_realize David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 33/49] target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 34/49] target/ppc: Avoid taking "env" parameter to mmu-hash64 functions David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 35/49] target/ppc: Remove fallback 64k pagesize information David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 36/49] target/ppc: Move page size setup to helper function David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 37/49] target/ppc: Split page size information into a separate allocation David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 38/49] target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 39/49] target/ppc: Move 1T segment and AMR options to PPCHash64Options David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 40/49] target/ppc: Fold ci_large_pages flag into PPCHash64Options David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 41/49] target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 42/49] target/ppc: Get rid of POWERPC_MMU_VER() macros David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 43/49] target/ppc: Fold slb_nr into PPCHash64Options David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 44/49] spapr: Add ibm, max-associativity-domains property David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 45/49] ppc: e500: switch E500 based machines to full machine definition David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 46/49] spapr: Support ibm, dynamic-memory-v2 property David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 47/49] target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr() David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 48/49] spapr: Set compatibility mode before the rest of spapr_cpu_reset() David Gibson
2018-04-27 9:21 ` [Qemu-devel] [PULL 49/49] Clear mem_path if we fall back to anonymous RAM allocation David Gibson
2018-04-27 10:13 ` [Qemu-devel] [PULL 00/49] ppc-for-2.13 queue 20180427 no-reply
2018-04-27 10:39 ` Peter Maydell
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