From: Borislav Petkov <bp@alien8.de>
To: David Wang <davidwang@zhaoxin.com>
Cc: tony.luck@intel.com, tglx@linutronix.de, mingo@redhat.com,
hpa@zytor.com, gregkh@linuxfoundation.org, x86@kernel.org,
linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
brucechang@via-alliance.com, cooperyan@zhaoxin.com,
qiyuanwang@zhaoxin.com, benjaminpan@viatech.com,
lukelin@viacpu.com, timguo@zhaoxin.com
Subject: Re: [PATCH v3 2/2] x86/mce: add CMCI support for Centaur CPUs
Date: Mon, 30 Apr 2018 11:48:02 +0200 [thread overview]
Message-ID: <20180430094802.GF6509@pd.tnic> (raw)
In-Reply-To: <1524652420-17330-3-git-send-email-davidwang@zhaoxin.com>
On Wed, Apr 25, 2018 at 06:33:40PM +0800, David Wang wrote:
> Newer Centaur support CMCI mechnism, which is compatible with INTEL CMCI.
>
> Signed-off-by: David Wang <davidwang@zhaoxin.com>
> ---
> arch/x86/kernel/cpu/mcheck/mce.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
> index 38ccab8..f9a7295 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce.c
> @@ -1757,6 +1757,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
> }
> case X86_VENDOR_CENTAUR:
> mce_centaur_feature_init(c);
> + mce_intel_feature_init(c);
> + mce_adjust_timer = cmci_intel_adjust_timer;
This won't work in configs with CONFIG_X86_MCE_INTEL disabled.
You need to define CONFIG_X86_MCE_CENTAUR or so which depends on
CONFIG_CPU_SUP_CENTAUR and CONFIG_X86_MCE_INTEL and which then makes
sure the intel CMCI et al stuff is enabled.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
WARNING: multiple messages have this Message-ID (diff)
From: Borislav Petkov <bp@alien8.de>
To: David Wang <davidwang@zhaoxin.com>
Cc: tony.luck@intel.com, tglx@linutronix.de, mingo@redhat.com,
hpa@zytor.com, gregkh@linuxfoundation.org, x86@kernel.org,
linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
brucechang@via-alliance.com, cooperyan@zhaoxin.com,
qiyuanwang@zhaoxin.com, benjaminpan@viatech.com,
lukelin@viacpu.com, timguo@zhaoxin.com
Subject: [v3,2/2] x86/mce: add CMCI support for Centaur CPUs
Date: Mon, 30 Apr 2018 11:48:02 +0200 [thread overview]
Message-ID: <20180430094802.GF6509@pd.tnic> (raw)
On Wed, Apr 25, 2018 at 06:33:40PM +0800, David Wang wrote:
> Newer Centaur support CMCI mechnism, which is compatible with INTEL CMCI.
>
> Signed-off-by: David Wang <davidwang@zhaoxin.com>
> ---
> arch/x86/kernel/cpu/mcheck/mce.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
> index 38ccab8..f9a7295 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce.c
> @@ -1757,6 +1757,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
> }
> case X86_VENDOR_CENTAUR:
> mce_centaur_feature_init(c);
> + mce_intel_feature_init(c);
> + mce_adjust_timer = cmci_intel_adjust_timer;
This won't work in configs with CONFIG_X86_MCE_INTEL disabled.
You need to define CONFIG_X86_MCE_CENTAUR or so which depends on
CONFIG_CPU_SUP_CENTAUR and CONFIG_X86_MCE_INTEL and which then makes
sure the intel CMCI et al stuff is enabled.
next prev parent reply other threads:[~2018-04-30 9:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-25 10:33 [PATCH v3 0/2] MCA support for Centaur CPUs David Wang
2018-04-25 10:33 ` [PATCH v3 1/2] x86/mce: new Centaur CPU support MCE broadcasting David Wang
2018-04-25 10:33 ` [v3,1/2] " davidwang
2018-04-30 9:41 ` [PATCH v3 1/2] " Borislav Petkov
2018-04-30 9:41 ` [v3,1/2] " Borislav Petkov
2018-05-06 10:51 ` [tip:ras/core] x86/MCE: Enable MCE broadcasting on new Centaur CPUs tip-bot for David Wang
2018-05-06 10:51 ` tip-bot for Borislav Petkov
2018-04-25 10:33 ` [PATCH v3 2/2] x86/mce: add CMCI support for " David Wang
2018-04-25 10:33 ` [v3,2/2] " davidwang
2018-04-30 9:48 ` Borislav Petkov [this message]
2018-04-30 9:48 ` Borislav Petkov
2018-05-02 10:02 [PATCH v3 2/2] " David Wang
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