[PATCH] drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.

[PATCH] drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.

[Rodrigo Vivi]

I believe I finally got the platform/panel that WA1183
was targeting.

WA 1183 aims to fix the cdclk change for
"CD clock frequency 308.57 or 617.14 MHz"

I faced one case here where the desired CDCLK to 308571 kHz,
VCO 8640000 kHz doesn't stick, unless that we unconditionally
disables and re-enables dpll0 and fully apply WA 1183.

[   42.857519] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 308571 kHz, VCO 8640000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
[   42.897269] cdclk state doesn't match!
[   42.901052] WARNING: CPU: 5 PID: 1116 at drivers/gpu/drm/i915/intel_cdclk.c:2084 intel_set_cdclk+0x5d/0x110 [i915]
[   42.938004] RIP: 0010:intel_set_cdclk+0x5d/0x110 [i915]
[   43.155253] WARNING: CPU: 5 PID: 1116 at drivers/gpu/drm/i915/intel_cdclk.c:2084 intel_set_cdclk+0x5d/0x110 [i915]
[   43.170277] [drm:intel_dump_cdclk_state [i915]] [hw state] 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
[   43.182566] [drm:intel_dump_cdclk_state [i915]] [sw state] 308571 kHz, VCO 8640000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0

Fixes: 53421c2fe99c ("drm/i915: Apply Display WA #1183 on skl, kbl, and cfl")
Cc: Arthur J Runyan" <arthur.j.runyan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 32d24c69da3c..5a65a79965cd 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1026,26 +1026,21 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	if (dev_priv->cdclk.hw.vco != 0 &&
-	    dev_priv->cdclk.hw.vco != vco)
-		skl_dpll0_disable(dev_priv);
+	skl_dpll0_disable(dev_priv);
 
 	cdclk_ctl = I915_READ(CDCLK_CTL);
 
-	if (dev_priv->cdclk.hw.vco != vco) {
-		/* Wa Display #1183: skl,kbl,cfl */
-		cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
-		cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
-		I915_WRITE(CDCLK_CTL, cdclk_ctl);
-	}
+	/* Wa Display #1183: skl,kbl,cfl */
+	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
+	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
+	I915_WRITE(CDCLK_CTL, cdclk_ctl);
 
 	/* Wa Display #1183: skl,kbl,cfl */
 	cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
 	I915_WRITE(CDCLK_CTL, cdclk_ctl);
 	POSTING_READ(CDCLK_CTL);
 
-	if (dev_priv->cdclk.hw.vco != vco)
-		skl_dpll0_enable(dev_priv, vco);
+	skl_dpll0_enable(dev_priv, vco);
 
 	/* Wa Display #1183: skl,kbl,cfl */
 	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
-- 
2.13.6

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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.

[Patchwork]

== Series Details ==

Series: drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.
URL   : https://patchwork.freedesktop.org/series/42500/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f1546a78be1b drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.
-:29: WARNING:BAD_SIGN_OFF: email address 'Arthur J Runyan" <arthur.j.runyan@intel.com>' might be better as 'Arthur J Runyan <arthur.j.runyan@intel.com>'
#29: 
Cc: Arthur J Runyan" <arthur.j.runyan@intel.com>

total: 0 errors, 1 warnings, 0 checks, 32 lines checked

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✗ Fi.CI.BAT: failure for drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.

[Patchwork]

== Series Details ==

Series: drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.
URL   : https://patchwork.freedesktop.org/series/42500/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4116 -> Patchwork_8851 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8851 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8851, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42500/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8851:

  === IGT changes ===

    ==== Possible regressions ====

    igt@gem_exec_suspend@basic-s3:
      fi-skl-6770hq:      PASS -> DMESG-WARN +3
      fi-cfl-s3:          PASS -> DMESG-WARN +3
      fi-skl-gvtdvm:      PASS -> DMESG-WARN +3
      fi-cfl-u:           PASS -> DMESG-WARN +3
      fi-skl-6260u:       PASS -> DMESG-WARN +3

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-kbl-7560u:       PASS -> DMESG-WARN +3
      fi-skl-6600u:       PASS -> DMESG-WARN +3
      fi-kbl-7500u:       PASS -> DMESG-WARN +3

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-skl-6700k2:      PASS -> DMESG-WARN +4
      fi-cfl-8700k:       PASS -> DMESG-WARN +3

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-kbl-7567u:       PASS -> DMESG-WARN +3
      fi-skl-guc:         PASS -> DMESG-WARN +3

    
== Known issues ==

  Here are the changes found in Patchwork_8851 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         PASS -> FAIL (fdo#102575)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-ivb-3520m:       DMESG-WARN (fdo#106084) -> PASS
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#106084 https://bugs.freedesktop.org/show_bug.cgi?id=106084


== Participating hosts (38 -> 35) ==

  Missing    (3): fi-ctg-p8600 fi-ilk-m540 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4116 -> Patchwork_8851

  CI_DRM_4116: 7ff375cb94000d93f7a9d541cb0c8180fbea80f2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4453: 29ae12bd764e3b1876356e7628a32192b4ec9066 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8851: f1546a78be1b480ab73aab66a60ba5584a613cc7 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4453: d0a0bca2194a673c4d9a70a2256837c59213c64b @ git://anongit.freedesktop.org/piglit


== Linux commits ==

f1546a78be1b drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8851/issues.html
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Re: [PATCH] drm/i915: Unconditionally disable/enable dpll0 and apply WA1183 when changing cdclk.

[Rodrigo Vivi]

Please fully ignore this patch.

On Mon, Apr 30, 2018 at 05:57:22PM -0700, Rodrigo Vivi wrote:
> I believe I finally got the platform/panel that WA1183
> was targeting.
> 
> WA 1183 aims to fix the cdclk change for
> "CD clock frequency 308.57 or 617.14 MHz"
> 
> I faced one case here where the desired CDCLK to 308571 kHz,
> VCO 8640000 kHz doesn't stick, unless that we unconditionally
> disables and re-enables dpll0 and fully apply WA 1183.
> 
> [   42.857519] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 308571 kHz, VCO 8640000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
> [   42.897269] cdclk state doesn't match!
> [   42.901052] WARNING: CPU: 5 PID: 1116 at drivers/gpu/drm/i915/intel_cdclk.c:2084 intel_set_cdclk+0x5d/0x110 [i915]
> [   42.938004] RIP: 0010:intel_set_cdclk+0x5d/0x110 [i915]
> [   43.155253] WARNING: CPU: 5 PID: 1116 at drivers/gpu/drm/i915/intel_cdclk.c:2084 intel_set_cdclk+0x5d/0x110 [i915]
> [   43.170277] [drm:intel_dump_cdclk_state [i915]] [hw state] 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
> [   43.182566] [drm:intel_dump_cdclk_state [i915]] [sw state] 308571 kHz, VCO 8640000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
> 
> Fixes: 53421c2fe99c ("drm/i915: Apply Display WA #1183 on skl, kbl, and cfl")
> Cc: Arthur J Runyan" <arthur.j.runyan@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 17 ++++++-----------
>  1 file changed, 6 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 32d24c69da3c..5a65a79965cd 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1026,26 +1026,21 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	if (dev_priv->cdclk.hw.vco != 0 &&
> -	    dev_priv->cdclk.hw.vco != vco)
> -		skl_dpll0_disable(dev_priv);
> +	skl_dpll0_disable(dev_priv);
>  
>  	cdclk_ctl = I915_READ(CDCLK_CTL);
>  
> -	if (dev_priv->cdclk.hw.vco != vco) {
> -		/* Wa Display #1183: skl,kbl,cfl */
> -		cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> -		cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> -		I915_WRITE(CDCLK_CTL, cdclk_ctl);
> -	}
> +	/* Wa Display #1183: skl,kbl,cfl */
> +	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> +	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> +	I915_WRITE(CDCLK_CTL, cdclk_ctl);
>  
>  	/* Wa Display #1183: skl,kbl,cfl */
>  	cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
>  	I915_WRITE(CDCLK_CTL, cdclk_ctl);
>  	POSTING_READ(CDCLK_CTL);
>  
> -	if (dev_priv->cdclk.hw.vco != vco)
> -		skl_dpll0_enable(dev_priv, vco);
> +	skl_dpll0_enable(dev_priv, vco);
>  
>  	/* Wa Display #1183: skl,kbl,cfl */
>  	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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