[PATCH v2 00/22] Workarounds for Icelake

[PATCH v2 00/22] Workarounds for Icelake

[Oscar Mateo]

List of GT workarounds for Icelake that we have been carrying in internal.

Oscar Mateo (22):
  drm/i915/icl: Introduce initial Icelake Workarounds
  drm/i915/icl: Enable Sampler DFR
  drm/i915/icl: WaGAPZPriorityScheme
  drm/i915/icl: WaL3BankAddressHashing
  drm/i915/icl: WaModifyGamTlbPartitioning
  drm/i915/icl: WaDisableCleanEvicts
  drm/i915/icl: WaCL2SFHalfMaxAlloc
  drm/i915/icl: WaDisCtxReload
  drm/i915/icl: Wa_1405779004
  drm/i915/icl: Wa_1406680159
  drm/i915/icl: Wa_1604302699
  drm/i915/icl: Wa_1406838659
  drm/i915/icl: WaForwardProgressSoftReset
  drm/i915/icl: WaDisableImprovedTdlClkGating
  drm/i915/icl: WaEnableStateCacheRedirectToCS
  drm/i915/icl: Wa_2006665173
  drm/i915/icl: WaEnableFloatBlendOptimization
  drm/i915/icl: WaSendPushConstantsFromMMIO
  drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
  drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
  drm/i915/icl: WaAllowUmdWriteTRTTRootTable
  drm/i915/icl: WaAllowUMDToModifySamplerMode

 drivers/gpu/drm/i915/i915_drv.h          |   9 ++
 drivers/gpu/drm/i915/i915_gem_gtt.c      |   4 +-
 drivers/gpu/drm/i915/i915_reg.h          |  85 ++++++++++++++----
 drivers/gpu/drm/i915/intel_lrc.c         |   2 +
 drivers/gpu/drm/i915/intel_pm.c          |  11 ++-
 drivers/gpu/drm/i915/intel_uncore.c      |   7 +-
 drivers/gpu/drm/i915/intel_workarounds.c | 150 +++++++++++++++++++++++++++++++
 7 files changed, 245 insertions(+), 23 deletions(-)

-- 
1.9.1

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[PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Oscar Mateo]

Inherit workarounds from previous platforms that are still valid for
Icelake.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Since it has been fixed already in upstream, removed the TODO
    comment about WA_SET_BIT for WaInPlaceDecompressionHang.
  - Squashed with this patch:
      drm/i915/icl: add icelake_init_clock_gating()
    from Paulo Zanoni <paulo.r.zanoni@intel.com>
  - Squashed with this patch:
      drm/i915/icl: WaForceEnableNonCoherent
    from Oscar Mateo <oscar.mateo@intel.com>
  - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
    applies to B0 as well.
  - WaPipeControlBefore3DStateSamplePattern WABB was being applied
    to ICL incorrectly.
v4:
  - Wrap the commit message
  - s/dev_priv/p to please checkpatch
v5: Rebased on top of the WA refactoring
v6: Rebased on top of further whitelist registers refactoring (Michel)
v7: Added WaRsForcewakeAddDelayForAck
v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Tomasz Lis <tomasz.lis@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  9 +++++++
 drivers/gpu/drm/i915/i915_gem_gtt.c      |  4 +--
 drivers/gpu/drm/i915/i915_reg.h          |  1 +
 drivers/gpu/drm/i915/intel_lrc.c         |  2 ++
 drivers/gpu/drm/i915/intel_pm.c          |  4 ++-
 drivers/gpu/drm/i915/intel_uncore.c      |  7 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
 7 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 193176b..7a3b0b1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2466,6 +2466,15 @@ static inline unsigned int i915_sg_segment_size(void)
 #define IS_CNL_REVID(p, since, until) \
 	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
+#define ICL_REVID_A0		0x0
+#define ICL_REVID_A2		0x1
+#define ICL_REVID_B0		0x3
+#define ICL_REVID_B2		0x4
+#define ICL_REVID_C0		0x5
+
+#define IS_ICL_REVID(p, since, until) \
+	(IS_ICELAKE(p) && IS_REVID(p, since, until))
+
 /*
  * The genX designation typically refers to the render engine, so render
  * capability related checks should use IS_GEN, while display and other checks
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 21d72f6..221b873 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
-	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
+	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
 	if (IS_BROADWELL(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
 	else if (IS_CHERRYVIEW(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
-	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
+	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
 	else if (IS_GEN9_LP(dev_priv))
 		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 197c966..454009f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7238,6 +7238,7 @@ enum {
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
 #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
+#define ICL_HDC_MODE				_MMIO(0xE5F4)
 #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 513aee6..d5fab47 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1661,6 +1661,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 		return -EINVAL;
 
 	switch (INTEL_GEN(engine->i915)) {
+	case 11:
+		return 0;
 	case 10:
 		wa_bb_fn[0] = gen10_init_indirectctx_bb;
 		wa_bb_fn[1] = NULL;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4126132..9c6e48c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_CANNONLAKE(dev_priv))
+	if (IS_ICELAKE(dev_priv))
+		dev_priv->display.init_clock_gating = nop_init_clock_gating;
+	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
 	else if (IS_COFFEELAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d6e20f0..448293e 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -139,7 +139,9 @@ enum ack_type {
 	 * in the hope that the original ack will be delivered along with
 	 * the fallback ack.
 	 *
-	 * This workaround is described in HSDES #1604254524
+	 * This workaround is described in HSDES #1604254524 and it's known as:
+	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
+	 * although the name is a bit misleading.
 	 */
 
 	pass = 1;
@@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 11) {
 		int i;
 
-		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
+		dev_priv->uncore.funcs.force_wake_get =
+			fw_domains_get_with_fallback;
 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
 		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
 			       FORCEWAKE_RENDER_GEN9,
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ec9d340..9a793ac 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
+{
+	/* Wa_1604370585:icl (pre-prod)
+	 * Formerly known as WaPushConstantDereferenceHoldDisable
+	 */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+				  PUSH_CONSTANT_DEREF_DISABLE);
+
+	/* WaForceEnableNonCoherent:icl
+	 * This is not the same workaround as in early Gen9 platforms, where
+	 * lacking this could cause system hangs, but coherency performance
+	 * overhead is high and only a few compute workloads really need it
+	 * (the register is whitelisted in hardware now, so UMDs can opt in
+	 * for coherency if they have a good reason).
+	 */
+	WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
+
+	return 0;
+}
+
 int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 {
 	int err = 0;
@@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		err = cfl_ctx_workarounds_init(dev_priv);
 	else if (IS_CANNONLAKE(dev_priv))
 		err = cnl_ctx_workarounds_init(dev_priv);
+	else if (IS_ICELAKE(dev_priv))
+		err = icl_ctx_workarounds_init(dev_priv);
 	else
 		MISSING_CASE(INTEL_GEN(dev_priv));
 	if (err)
@@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
 }
 
+static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
+{
+	/* This is not an Wa. Enable for better image quality */
+	I915_WRITE(_3D_CHICKEN3,
+		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
+
+	/* WaInPlaceDecompressionHang:icl */
+	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
+
+	/* WaPipelineFlushCoherentLines:icl */
+	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+				    GEN8_LQSC_FLUSH_COHERENT_LINES));
+}
+
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 {
 	if (INTEL_GEN(dev_priv) < 8)
@@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		cfl_gt_workarounds_apply(dev_priv);
 	else if (IS_CANNONLAKE(dev_priv))
 		cnl_gt_workarounds_apply(dev_priv);
+	else if (IS_ICELAKE(dev_priv))
+		icl_gt_workarounds_apply(dev_priv);
 	else
 		MISSING_CASE(INTEL_GEN(dev_priv));
 }
@@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
 	whitelist_reg(w, GEN8_CS_CHICKEN1);
 }
 
+static void icl_whitelist_build(struct whitelist *w)
+{
+}
+
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
 					 struct whitelist *w)
 {
@@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
 		cfl_whitelist_build(w);
 	else if (IS_CANNONLAKE(i915))
 		cnl_whitelist_build(w);
+	else if (IS_ICELAKE(i915))
+		icl_whitelist_build(w);
 	else
 		MISSING_CASE(INTEL_GEN(i915));
 
-- 
1.9.1

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Re: [PATCH 01/22] drm/i915/icl: Introduce initial Icelake Workarounds

[Tvrtko Ursulin]

On 02/05/2018 21:34, Oscar Mateo wrote:
> Inherit workarounds from previous platforms that are still valid for
> Icelake.
> 
> v2: GEN7_ROW_CHICKEN2 is masked
> v3:
>    - Since it has been fixed already in upstream, removed the TODO
>      comment about WA_SET_BIT for WaInPlaceDecompressionHang.
>    - Squashed with this patch:
>        drm/i915/icl: add icelake_init_clock_gating()
>      from Paulo Zanoni <paulo.r.zanoni@intel.com>
>    - Squashed with this patch:
>        drm/i915/icl: WaForceEnableNonCoherent
>      from Oscar Mateo <oscar.mateo@intel.com>
>    - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
>      applies to B0 as well.
>    - WaPipeControlBefore3DStateSamplePattern WABB was being applied
>      to ICL incorrectly.
> v4:
>    - Wrap the commit message
>    - s/dev_priv/p to please checkpatch
> v5: Rebased on top of the WA refactoring
> v6: Rebased on top of further whitelist registers refactoring (Michel)
> v7: Added WaRsForcewakeAddDelayForAck
> v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h          |  9 +++++++
>   drivers/gpu/drm/i915/i915_gem_gtt.c      |  4 +--
>   drivers/gpu/drm/i915/i915_reg.h          |  1 +
>   drivers/gpu/drm/i915/intel_lrc.c         |  2 ++
>   drivers/gpu/drm/i915/intel_pm.c          |  4 ++-
>   drivers/gpu/drm/i915/intel_uncore.c      |  7 +++--
>   drivers/gpu/drm/i915/intel_workarounds.c | 46 ++++++++++++++++++++++++++++++++
>   7 files changed, 68 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 193176b..7a3b0b1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2466,6 +2466,15 @@ static inline unsigned int i915_sg_segment_size(void)
>   #define IS_CNL_REVID(p, since, until) \
>   	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>   
> +#define ICL_REVID_A0		0x0
> +#define ICL_REVID_A2		0x1
> +#define ICL_REVID_B0		0x3
> +#define ICL_REVID_B2		0x4
> +#define ICL_REVID_C0		0x5
> +
> +#define IS_ICL_REVID(p, since, until) \
> +	(IS_ICELAKE(p) && IS_REVID(p, since, until))
> +
>   /*
>    * The genX designation typically refers to the render engine, so render
>    * capability related checks should use IS_GEN, while display and other checks
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 21d72f6..221b873 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2140,12 +2140,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>   	 * called on driver load and after a GPU reset, so you can place
>   	 * workarounds here even if they get overwritten by GPU reset.
>   	 */
> -	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
> +	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
>   	if (IS_BROADWELL(dev_priv))
>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>   	else if (IS_CHERRYVIEW(dev_priv))
>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> -	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> +	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv) || IS_GEN11(dev_priv))
>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>   	else if (IS_GEN9_LP(dev_priv))
>   		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);

Sounds like:

if (IS_BROADWELL)
else if (IS_CHERRYVIEW)
else if (IS_GEN9_LP)
else if (IS_GEN >= 9) /* Here's the improvement */

Just a drive by, sorry. :)

Regards,

Tvrtko

> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 197c966..454009f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7238,6 +7238,7 @@ enum {
>   /* GEN8 chicken */
>   #define HDC_CHICKEN0				_MMIO(0x7300)
>   #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
> +#define ICL_HDC_MODE				_MMIO(0xE5F4)
>   #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE	(1<<15)
>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
>   #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 513aee6..d5fab47 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1661,6 +1661,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>   		return -EINVAL;
>   
>   	switch (INTEL_GEN(engine->i915)) {
> +	case 11:
> +		return 0;
>   	case 10:
>   		wa_bb_fn[0] = gen10_init_indirectctx_bb;
>   		wa_bb_fn[1] = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4126132..9c6e48c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9190,7 +9190,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>    */
>   void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>   {
> -	if (IS_CANNONLAKE(dev_priv))
> +	if (IS_ICELAKE(dev_priv))
> +		dev_priv->display.init_clock_gating = nop_init_clock_gating;
> +	else if (IS_CANNONLAKE(dev_priv))
>   		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>   	else if (IS_COFFEELAKE(dev_priv))
>   		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d6e20f0..448293e 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -139,7 +139,9 @@ enum ack_type {
>   	 * in the hope that the original ack will be delivered along with
>   	 * the fallback ack.
>   	 *
> -	 * This workaround is described in HSDES #1604254524
> +	 * This workaround is described in HSDES #1604254524 and it's known as:
> +	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
> +	 * although the name is a bit misleading.
>   	 */
>   
>   	pass = 1;
> @@ -1394,7 +1396,8 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>   	if (INTEL_GEN(dev_priv) >= 11) {
>   		int i;
>   
> -		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
> +		dev_priv->uncore.funcs.force_wake_get =
> +			fw_domains_get_with_fallback;
>   		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
>   		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
>   			       FORCEWAKE_RENDER_GEN9,
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ec9d340..9a793ac 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -441,6 +441,27 @@ static int cnl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>   	return 0;
>   }
>   
> +static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
> +{
> +	/* Wa_1604370585:icl (pre-prod)
> +	 * Formerly known as WaPushConstantDereferenceHoldDisable
> +	 */
> +	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> +		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
> +				  PUSH_CONSTANT_DEREF_DISABLE);
> +
> +	/* WaForceEnableNonCoherent:icl
> +	 * This is not the same workaround as in early Gen9 platforms, where
> +	 * lacking this could cause system hangs, but coherency performance
> +	 * overhead is high and only a few compute workloads really need it
> +	 * (the register is whitelisted in hardware now, so UMDs can opt in
> +	 * for coherency if they have a good reason).
> +	 */
> +	WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
> +
> +	return 0;
> +}
> +
>   int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>   {
>   	int err = 0;
> @@ -465,6 +486,8 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv)
>   		err = cfl_ctx_workarounds_init(dev_priv);
>   	else if (IS_CANNONLAKE(dev_priv))
>   		err = cnl_ctx_workarounds_init(dev_priv);
> +	else if (IS_ICELAKE(dev_priv))
> +		err = icl_ctx_workarounds_init(dev_priv);
>   	else
>   		MISSING_CASE(INTEL_GEN(dev_priv));
>   	if (err)
> @@ -663,6 +686,21 @@ static void cnl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>   		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
>   }
>   
> +static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> +{
> +	/* This is not an Wa. Enable for better image quality */
> +	I915_WRITE(_3D_CHICKEN3,
> +		   _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
> +
> +	/* WaInPlaceDecompressionHang:icl */
> +	I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA, (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
> +					     GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
> +
> +	/* WaPipelineFlushCoherentLines:icl */
> +	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> +				    GEN8_LQSC_FLUSH_COHERENT_LINES));
> +}
> +
>   void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>   {
>   	if (INTEL_GEN(dev_priv) < 8)
> @@ -683,6 +721,8 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>   		cfl_gt_workarounds_apply(dev_priv);
>   	else if (IS_CANNONLAKE(dev_priv))
>   		cnl_gt_workarounds_apply(dev_priv);
> +	else if (IS_ICELAKE(dev_priv))
> +		icl_gt_workarounds_apply(dev_priv);
>   	else
>   		MISSING_CASE(INTEL_GEN(dev_priv));
>   }
> @@ -761,6 +801,10 @@ static void cnl_whitelist_build(struct whitelist *w)
>   	whitelist_reg(w, GEN8_CS_CHICKEN1);
>   }
>   
> +static void icl_whitelist_build(struct whitelist *w)
> +{
> +}
> +
>   static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
>   					 struct whitelist *w)
>   {
> @@ -789,6 +833,8 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
>   		cfl_whitelist_build(w);
>   	else if (IS_CANNONLAKE(i915))
>   		cnl_whitelist_build(w);
> +	else if (IS_ICELAKE(i915))
> +		icl_whitelist_build(w);
>   	else
>   		MISSING_CASE(INTEL_GEN(i915));
>   
> 
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[PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Oscar Mateo]

Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on Gen11.

v2: Wrong operation to clear the bit (Praveen)
v3: Rebased on top of the WA refactoring
v4: Move to icl_init_clock_gating, since it's not a WA (Rodrigo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Praveen Paneri <praveen.paneri@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 3 +++
 drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 454009f..3b5d298 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8253,6 +8253,9 @@ enum {
 #define GEN8_GARBCNTL                   _MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
 
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
+#define   DFR_DISABLE			(1 << 9)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9c6e48c..4a63e38 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8664,6 +8664,13 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
 
+static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+	/* This is not an Wa. Enable to reduce Sampler power */
+	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
+		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
+}
+
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	if (!HAS_PCH_CNP(dev_priv))
@@ -9191,7 +9198,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_ICELAKE(dev_priv))
-		dev_priv->display.init_clock_gating = nop_init_clock_gating;
+		dev_priv->display.init_clock_gating = icl_init_clock_gating;
 	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
 	else if (IS_COFFEELAKE(dev_priv))
-- 
1.9.1

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Re: [PATCH 02/22] drm/i915/icl: Enable Sampler DFR

[Rodrigo Vivi]

On Wed, May 02, 2018 at 01:34:01PM -0700, Oscar Mateo wrote:
> Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
> power by dynamically changing its clock frequency in low-throughput
> conditions. This patches enables it by default on Gen11.
> 
> v2: Wrong operation to clear the bit (Praveen)
> v3: Rebased on top of the WA refactoring
> v4: Move to icl_init_clock_gating, since it's not a WA (Rodrigo)

thanks

> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Praveen Paneri <praveen.paneri@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 454009f..3b5d298 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8253,6 +8253,9 @@ enum {
>  #define GEN8_GARBCNTL                   _MMIO(0xB004)
>  #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
>  
> +#define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
> +#define   DFR_DISABLE			(1 << 9)
> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9c6e48c..4a63e38 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8664,6 +8664,13 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>  	I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>  }
>  
> +static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> +	/* This is not an Wa. Enable to reduce Sampler power */
> +	I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> +		   (I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE));
> +}
> +
>  static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
>  	if (!HAS_PCH_CNP(dev_priv))
> @@ -9191,7 +9198,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_ICELAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = nop_init_clock_gating;
> +		dev_priv->display.init_clock_gating = icl_init_clock_gating;
>  	else if (IS_CANNONLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>  	else if (IS_COFFEELAKE(dev_priv))
> -- 
> 1.9.1
> 
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[PATCH 03/22] drm/i915/icl: WaGAPZPriorityScheme

[Oscar Mateo]

The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.

v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
v4: Added HSDES reference number (Mika)

References: HSDES#1405543622
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3b5d298..0671066 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8250,8 +8250,9 @@ enum {
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
 #define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
 
-#define GEN8_GARBCNTL                   _MMIO(0xB004)
-#define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
+#define GEN8_GARBCNTL				_MMIO(0xB004)
+#define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
+#define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 9a793ac..68e6caa 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -699,6 +699,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	/* WaPipelineFlushCoherentLines:icl */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN8_LQSC_FLUSH_COHERENT_LINES));
+
+	/* Wa_1405543622:icl
+	 * Formerly known as WaGAPZPriorityScheme
+	 */
+	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
+				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Oscar Mateo]

Revert to an L3 non-hash model, for performance reasons.

v2:
  - Place the WA name above the actual change
  - Improve the register naming
v3:
  - Rebased
  - Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring
v5:
  - Added References (Mika)
  - Fixed wrong mask and value (Mika)
  - Do not apply together with another WA for the same
    register (not worth the hassle)

References: HSDES#1604223664
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  6 ++++++
 drivers/gpu/drm/i915/intel_workarounds.c | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0671066..62c4fd2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8253,6 +8253,12 @@ enum {
 #define GEN8_GARBCNTL				_MMIO(0xB004)
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
 #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
+#define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
+#define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
+
+#define GEN11_GLBLINVL				_MMIO(0xB404)
+#define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
+#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)
 
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 68e6caa..93591a0 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -705,6 +705,16 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	 */
 	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
 				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
+
+	/* Wa_1604223664:icl
+	 * Formerly known as WaL3BankAddressHashing
+	 */
+	I915_WRITE(GEN8_GARBCNTL,
+		   ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
+		    GEN11_HASH_CTRL_EXCL_BIT0));
+	I915_WRITE(GEN11_GLBLINVL,
+		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
+		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 04/22] drm/i915/icl: WaL3BankAddressHashing

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Revert to an L3 non-hash model, for performance reasons.
>
> v2:
>   - Place the WA name above the actual change
>   - Improve the register naming
> v3:
>   - Rebased
>   - Renamed to Wa_1604223664
> v4: Rebased on top of the WA refactoring
> v5:
>   - Added References (Mika)
>   - Fixed wrong mask and value (Mika)
>   - Do not apply together with another WA for the same
>     register (not worth the hassle)
>
> References: HSDES#1604223664
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h          |  6 ++++++
>  drivers/gpu/drm/i915/intel_workarounds.c | 10 ++++++++++
>  2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0671066..62c4fd2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8253,6 +8253,12 @@ enum {
>  #define GEN8_GARBCNTL				_MMIO(0xB004)
>  #define   GEN9_GAPS_TSV_CREDIT_DISABLE		(1 << 7)
>  #define   GEN11_ARBITRATION_PRIO_ORDER_MASK	(0x3f << 22)
> +#define   GEN11_HASH_CTRL_EXCL_MASK		(0x7f << 0)
> +#define   GEN11_HASH_CTRL_EXCL_BIT0		(1 << 0)
> +
> +#define GEN11_GLBLINVL				_MMIO(0xB404)
> +#define   GEN11_BANK_HASH_ADDR_EXCL_MASK	(0x7f << 5)
> +#define   GEN11_BANK_HASH_ADDR_EXCL_BIT0	(1 << 5)
>  
>  #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
>  #define   DFR_DISABLE			(1 << 9)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 68e6caa..93591a0 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -705,6 +705,16 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	 */
>  	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
>  				   GEN11_ARBITRATION_PRIO_ORDER_MASK));
> +
> +	/* Wa_1604223664:icl
> +	 * Formerly known as WaL3BankAddressHashing
> +	 */
> +	I915_WRITE(GEN8_GARBCNTL,
> +		   ((I915_READ(GEN8_GARBCNTL) & ~GEN11_HASH_CTRL_EXCL_MASK) |
> +		    GEN11_HASH_CTRL_EXCL_BIT0));
> +	I915_WRITE(GEN11_GLBLINVL,
> +		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
> +		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

[Oscar Mateo]

Adjust default GAM TLB partitioning for performance reasons.

v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
v4:
  - Added References (Mika)
  - Rebased

References: HSDES#220260670
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 62c4fd2..a132980 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8263,6 +8263,11 @@ enum {
 #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
 #define   DFR_DISABLE			(1 << 9)
 
+#define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
+#define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
+#define   GEN11_HASH_CTRL_BIT0			(1 << 0)
+#define   GEN11_HASH_CTRL_BIT4			(1 << 12)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 93591a0..2bb5dad 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -715,6 +715,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_GLBLINVL,
 		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
 		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
+
+	/* WaModifyGamTlbPartitioning:icl */
+	I915_WRITE(GEN11_GACB_PERF_CTRL,
+		   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
+		    GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 05/22] drm/i915/icl: WaModifyGamTlbPartitioning

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Adjust default GAM TLB partitioning for performance reasons.
>
> v2: Only touch the bits that we really need
> v3: Rebased on top of the WA refactoring
> v4:
>   - Added References (Mika)
>   - Rebased
>
> References: HSDES#220260670
s/220260670/220160670

> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
>  drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
>  2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 62c4fd2..a132980 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8263,6 +8263,11 @@ enum {
>  #define GEN10_DFR_RATIO_EN_AND_CHICKEN	_MMIO(0x9550)
>  #define   DFR_DISABLE			(1 << 9)
>  
> +#define GEN11_GACB_PERF_CTRL			_MMIO(0x4B80)
> +#define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)
> +#define   GEN11_HASH_CTRL_BIT0			(1 << 0)
> +#define   GEN11_HASH_CTRL_BIT4			(1 << 12)

Bspec only mentions that we should choose from group C, without
saying which hash to choose. And this is from group C.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 93591a0..2bb5dad 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -715,6 +715,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN11_GLBLINVL,
>  		   ((I915_READ(GEN11_GLBLINVL) & ~GEN11_BANK_HASH_ADDR_EXCL_MASK) |
>  		    GEN11_BANK_HASH_ADDR_EXCL_BIT0));
> +
> +	/* WaModifyGamTlbPartitioning:icl */
> +	I915_WRITE(GEN11_GACB_PERF_CTRL,
> +		   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
> +		    GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts

[Oscar Mateo]

Avoids an undefined LLC behavior.

BSpec: 9613

v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)

References: HSDES#1405733216
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a132980..845c7e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7232,8 +7232,9 @@ enum {
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
 
 #define GEN8_L3SQCREG4				_MMIO(0xb118)
-#define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
-#define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1<<21)
+#define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
+#define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
+#define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 2bb5dad..b0babe8 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -720,6 +720,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_GACB_PERF_CTRL,
 		   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
 		    GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
+
+	/* Wa_1405733216:icl
+	 * Formerly known as WaDisableCleanEvicts
+	 */
+	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+				    GEN11_LQSC_CLEAN_EVICT_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 06/22] drm/i915/icl: WaDisableCleanEvicts

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Avoids an undefined LLC behavior.
>
> BSpec: 9613
>
> v2: Renamed to Wa_1405733216
> v3: Spaces around '<<' and fix surrounding code
> v4: Rebased on top of the WA refactoring
> v5: Added References (Mika)
>
> References: HSDES#1405733216
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
>  drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
>  2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a132980..845c7e4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7232,8 +7232,9 @@ enum {
>  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
>  
>  #define GEN8_L3SQCREG4				_MMIO(0xb118)
> -#define  GEN8_LQSC_RO_PERF_DIS			(1<<27)
> -#define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1<<21)
> +#define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
> +#define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
> +#define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
>  
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				_MMIO(0x7300)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 2bb5dad..b0babe8 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -720,6 +720,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN11_GACB_PERF_CTRL,
>  		   ((I915_READ(GEN11_GACB_PERF_CTRL) & ~GEN11_HASH_CTRL_MASK) |
>  		    GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4));
> +
> +	/* Wa_1405733216:icl
> +	 * Formerly known as WaDisableCleanEvicts
> +	 */
> +	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> +				    GEN11_LQSC_CLEAN_EVICT_DISABLE));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Oscar Mateo]

This workarounds an issue with insufficient storage for the
CL2 and SF units.

v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)

References: HSDES#1405766107
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 4 ++++
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 845c7e4..e8ab663 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8269,6 +8269,10 @@ enum {
 #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
 #define   GEN11_HASH_CTRL_BIT4			(1 << 12)
 
+#define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC	(1 << 9)
+#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index b0babe8..312846e 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -726,6 +726,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	 */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN11_LQSC_CLEAN_EVICT_DISABLE));
+
+	/* Wa_1405766107:icl
+	 * Formerly known as WaCL2SFHalfMaxAlloc
+	 */
+	I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
+				       GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
+				       GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 07/22] drm/i915/icl: WaCL2SFHalfMaxAlloc

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> This workarounds an issue with insufficient storage for the
> CL2 and SF units.
>
> v2: Renamed to Wa_1405766107
> v3: Wrapped the commit message
> v4: Rebased on top of the WA refactoring
> v5: Added References (Mika)
>
> References: HSDES#1405766107
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 4 ++++
>  drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
>  2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 845c7e4..e8ab663 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8269,6 +8269,10 @@ enum {
>  #define   GEN11_HASH_CTRL_BIT0			(1 << 0)
>  #define   GEN11_HASH_CTRL_BIT4			(1 << 12)
>  
> +#define GEN11_LSN_UNSLCVC				_MMIO(0xB43C)
> +#define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC	(1 << 9)

s/MACALLOC/MAXALLOC

The bspec didn't know this reg (for icl) but
igt/gem_workarounds will surely tell if the write sticks.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> +#define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index b0babe8..312846e 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -726,6 +726,13 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	 */
>  	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>  				    GEN11_LQSC_CLEAN_EVICT_DISABLE));
> +
> +	/* Wa_1405766107:icl
> +	 * Formerly known as WaCL2SFHalfMaxAlloc
> +	 */
> +	I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
> +				       GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
> +				       GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[PATCH 08/22] drm/i915/icl: WaDisCtxReload

[Oscar Mateo]

Revert to the legacy implementation to avoid a system hang.

v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)

References: HSDES#220166154
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e8ab663..344509a4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8273,6 +8273,9 @@ enum {
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC	(1 << 9)
 #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
 
+#define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
+#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 312846e..64f2c9b9 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -733,6 +733,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
 				       GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
 				       GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
+
+	/* Wa_220166154:icl
+	 * Formerly known as WaDisCtxReload
+	 */
+	I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
+					    GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 08/22] drm/i915/icl: WaDisCtxReload

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Revert to the legacy implementation to avoid a system hang.
>
> v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
> v3: Renamed to Wa_220166154
> v4: Rebased on top of the WA refactoring
> v5: Added References (Mika)
>
> References: HSDES#220166154
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>

Yeah and me asking for references tag for these workarounds where
we have a hsdes entry as a wa name nowadays was very silly.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>  drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
>  2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e8ab663..344509a4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8273,6 +8273,9 @@ enum {
>  #define   GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC	(1 << 9)
>  #define   GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC	(1 << 7)
>  
> +#define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
> +#define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
> +
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
>  #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 312846e..64f2c9b9 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -733,6 +733,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN11_LSN_UNSLCVC, (I915_READ(GEN11_LSN_UNSLCVC) |
>  				       GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC |
>  				       GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MACALLOC));
> +
> +	/* Wa_220166154:icl
> +	 * Formerly known as WaDisCtxReload
> +	 */
> +	I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
> +					    GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[PATCH 09/22] drm/i915/icl: Wa_1405779004

[Oscar Mateo]

Disable MSC clock gating to prevent data corruption.

BSpec: 19257

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)

References: HSDES#1405779004
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 344509a4..b7e5ca0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3840,6 +3840,7 @@ enum {
 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
 #define  RCCUNIT_CLKGATE_DIS		(1 << 7)
+#define  MSCUNIT_CLKGATE_DIS		(1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
 #define  GWUNIT_CLKGATE_DIS		(1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 64f2c9b9..38e3776 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -739,6 +739,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	 */
 	I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
 					    GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
+
+	/* Wa_1405779004:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
+			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
+			    MSCUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 09/22] drm/i915/icl: Wa_1405779004

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Disable MSC clock gating to prevent data corruption.
>
> BSpec: 19257
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1405779004
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 344509a4..b7e5ca0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3840,6 +3840,7 @@ enum {
>  #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
>  #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
>  #define  RCCUNIT_CLKGATE_DIS		(1 << 7)
> +#define  MSCUNIT_CLKGATE_DIS		(1 << 10)
>  
>  #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
>  #define  GWUNIT_CLKGATE_DIS		(1 << 16)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 64f2c9b9..38e3776 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -739,6 +739,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	 */
>  	I915_WRITE(GAMW_ECO_DEV_RW_IA_REG, (I915_READ(GAMW_ECO_DEV_RW_IA_REG) |
>  					    GAMW_ECO_DEV_CTX_RELOAD_DISABLE));
> +
> +	/* Wa_1405779004:icl (pre-prod) */
> +	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> +		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
> +			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> +			    MSCUNIT_CLKGATE_DIS));

This is A0 only.

With that changed,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[PATCH 10/22] drm/i915/icl: Wa_1406680159

[Oscar Mateo]

Disable GWL clock gating to prevent two different issues that
might cause hangs.

Please notice that one of the issues is pre-production only.

v2: Rebased on top of the WA refactoring
v3: Wa_2201832410 officially merged with Wa_1406680159
v4: Added References (Mika)

References: HSDES#1406680159
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 38e3776..ffb0e30 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -745,6 +745,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
 			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
 			    MSCUNIT_CLKGATE_DIS));
+
+	/* Wa_1406680159:icl */
+	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
+		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
+		    GWUNIT_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 10/22] drm/i915/icl: Wa_1406680159

[Rodrigo Vivi]

On Wed, May 02, 2018 at 01:34:09PM -0700, Oscar Mateo wrote:
> Disable GWL clock gating to prevent two different issues that
> might cause hangs.
> 
> Please notice that one of the issues is pre-production only.
> 
> v2: Rebased on top of the WA refactoring
> v3: Wa_2201832410 officially merged with Wa_1406680159
> v4: Added References (Mika)
> 
> References: HSDES#1406680159

Probably worth to mention HSDES 1406681710
where WA is better described.

> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 38e3776..ffb0e30 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -745,6 +745,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
>  			   (I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
>  			    MSCUNIT_CLKGATE_DIS));
> +
> +	/* Wa_1406680159:icl */
> +	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
> +		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
> +		    GWUNIT_CLKGATE_DIS));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
> 
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[PATCH 11/22] drm/i915/icl: Wa_1604302699

[Oscar Mateo]

Disable I2M Write for performance reasons.

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)

References: HSDES#1604302699
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 4 +++-
 drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b7e5ca0..f6a38fd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7227,7 +7227,9 @@ enum {
 #define GEN7_L3CNTLREG3				_MMIO(0xB024)
 
 #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
-#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
+#define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
+#define  GEN7_WA_L3_CHICKEN_MODE		0x20000000
+#define  GEN11_I2M_WRITE_DISABLE		(1 << 28)
 
 #define GEN7_L3SQCREG4				_MMIO(0xb034)
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index ffb0e30..bba43fd 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -750,6 +750,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
 		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
 		    GWUNIT_CLKGATE_DIS));
+
+	/* Wa_1604302699:icl */
+	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
+		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
+		    GEN11_I2M_WRITE_DISABLE));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 11/22] drm/i915/icl: Wa_1604302699

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Disable I2M Write for performance reasons.
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1604302699
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 4 +++-
>  drivers/gpu/drm/i915/intel_workarounds.c | 5 +++++
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b7e5ca0..f6a38fd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7227,7 +7227,9 @@ enum {
>  #define GEN7_L3CNTLREG3				_MMIO(0xB024)
>  
>  #define GEN7_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB030)
> -#define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> +#define GEN10_L3_CHICKEN_MODE_REGISTER		_MMIO(0xB114)
> +#define  GEN7_WA_L3_CHICKEN_MODE		0x20000000

Seems that the GEN7 part jumped on the wrong side of the fence.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> +#define  GEN11_I2M_WRITE_DISABLE		(1 << 28)
>  
>  #define GEN7_L3SQCREG4				_MMIO(0xb034)
>  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index ffb0e30..bba43fd 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -750,6 +750,11 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	I915_WRITE(SUBSLICE_UNIT_LEVEL_CLKGATE,
>  		   (I915_READ(SUBSLICE_UNIT_LEVEL_CLKGATE) |
>  		    GWUNIT_CLKGATE_DIS));
> +
> +	/* Wa_1604302699:icl */
> +	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
> +		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
> +		    GEN11_I2M_WRITE_DISABLE));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[PATCH 12/22] drm/i915/icl: Wa_1406838659

[Oscar Mateo]

Disable CGPSF unit clock gating to prevent an issue.

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)

References: HSDES#1406838659
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 13 ++++++++-----
 drivers/gpu/drm/i915/intel_workarounds.c |  6 ++++++
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6a38fd..8caf42f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3838,15 +3838,18 @@ enum {
  * GEN10 clock gating regs
  */
 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
-#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
-#define  RCCUNIT_CLKGATE_DIS		(1 << 7)
-#define  MSCUNIT_CLKGATE_DIS		(1 << 10)
+#define   SARBUNIT_CLKGATE_DIS		(1 << 5)
+#define   RCCUNIT_CLKGATE_DIS		(1 << 7)
+#define   MSCUNIT_CLKGATE_DIS		(1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
-#define  GWUNIT_CLKGATE_DIS		(1 << 16)
+#define   GWUNIT_CLKGATE_DIS		(1 << 16)
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
-#define  VFUNIT_CLKGATE_DIS		(1 << 20)
+#define   VFUNIT_CLKGATE_DIS		(1 << 20)
+
+#define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
+#define   CGPSF_CLKGATE_DIS		(1 << 3)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index bba43fd..35f2de3 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -755,6 +755,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
 		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
 		    GEN11_I2M_WRITE_DISABLE));
+
+	/* Wa_1406838659:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
+		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+			    CGPSF_CLKGATE_DIS));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 12/22] drm/i915/icl: Wa_1406838659

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Disable CGPSF unit clock gating to prevent an issue.
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1406838659
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 13 ++++++++-----
>  drivers/gpu/drm/i915/intel_workarounds.c |  6 ++++++
>  2 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6a38fd..8caf42f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3838,15 +3838,18 @@ enum {
>   * GEN10 clock gating regs
>   */
>  #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
> -#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
> -#define  RCCUNIT_CLKGATE_DIS		(1 << 7)
> -#define  MSCUNIT_CLKGATE_DIS		(1 << 10)
> +#define   SARBUNIT_CLKGATE_DIS		(1 << 5)
> +#define   RCCUNIT_CLKGATE_DIS		(1 << 7)
> +#define   MSCUNIT_CLKGATE_DIS		(1 << 10)
>  
>  #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
> -#define  GWUNIT_CLKGATE_DIS		(1 << 16)
> +#define   GWUNIT_CLKGATE_DIS		(1 << 16)
>  
>  #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
> -#define  VFUNIT_CLKGATE_DIS		(1 << 20)
> +#define   VFUNIT_CLKGATE_DIS		(1 << 20)

Some unintentional whitespace movements?

> +
> +#define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
> +#define   CGPSF_CLKGATE_DIS		(1 << 3)
>  
>  /*
>   * Display engine regs
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index bba43fd..35f2de3 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -755,6 +755,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
>  		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
>  		    GEN11_I2M_WRITE_DISABLE));
> +
> +	/* Wa_1406838659:icl (pre-prod) */
> +	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))

It is inclusive and C0 is fixed so,
IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))

With that and whitespace on check,
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> +		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
> +			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
> +			    CGPSF_CLKGATE_DIS));
>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset

[Oscar Mateo]

Avoids a hang during soft reset.

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)

References: HSDES#1405476379
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
 drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8caf42f..8da119f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9895,6 +9895,11 @@ enum skl_power_gate {
 #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
 #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
 
+#define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
+#define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
+#define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
+#define   PMFLUSHDONE_LNEBLK		(1 << 22)
+
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
 #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 35f2de3..f89a5c2 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -761,6 +761,14 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
 		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
 			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
 			    CGPSF_CLKGATE_DIS));
+
+	/* WaForwardProgressSoftReset:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		I915_WRITE(GEN10_SCRATCH_LNCF2,
+			   (I915_READ(GEN10_SCRATCH_LNCF2) |
+			    PMFLUSHDONE_LNICRSDROP |
+			    PMFLUSH_GAPL3UNBLOCK |
+			    PMFLUSHDONE_LNEBLK));
 }
 
 void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
-- 
1.9.1

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Re: [PATCH 13/22] drm/i915/icl: WaForwardProgressSoftReset

[Mika Kuoppala]

Oscar Mateo <oscar.mateo@intel.com> writes:

> Avoids a hang during soft reset.
>
> v2: Rebased on top of the WA refactoring
> v3: Added References (Mika)
>
> References: HSDES#1405476379
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 5 +++++
>  drivers/gpu/drm/i915/intel_workarounds.c | 8 ++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8caf42f..8da119f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9895,6 +9895,11 @@ enum skl_power_gate {
>  #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
>  #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
>  
> +#define GEN10_SCRATCH_LNCF2		_MMIO(0xb0a0)
> +#define   PMFLUSHDONE_LNICRSDROP	(1 << 20)
> +#define   PMFLUSH_GAPL3UNBLOCK		(1 << 21)
> +#define   PMFLUSHDONE_LNEBLK		(1 << 22)
> +
>  /* gamt regs */
>  #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
>  #define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 35f2de3..f89a5c2 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -761,6 +761,14 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
>  		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
>  			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
>  			    CGPSF_CLKGATE_DIS));
> +
> +	/* WaForwardProgressSoftReset:icl (pre-prod) */
> +	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
> +		I915_WRITE(GEN10_SCRATCH_LNCF2,
> +			   (I915_READ(GEN10_SCRATCH_LNCF2) |
> +			    PMFLUSHDONE_LNICRSDROP |
> +			    PMFLUSH_GAPL3UNBLOCK |
> +			    PMFLUSHDONE_LNEBLK));

The references on this are someone contradicting.

I did found anything that would point it being fixed in C0
even tho wa database says that for B0.

Bspec says that you must set these unconditionally.
I would go with the bspec and unconditionally enable these
three bits.

-Mika


>  }
>  
>  void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> -- 
> 1.9.1
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[PATCH 14/22] drm/i915/icl: WaDisableImprovedTdlClkGating

[Oscar Mateo]

Revert to the legacy implementation.

v2: GEN7_ROW_CHICKEN2 is masked
v3:
  - Rebased
  - Renamed to Wa_2006611047
  - A0 and B0 only
v4:
  - Add spaces around '<<' (and fix the surrounding code as well)
  - Mark the WA as pre-prod
v5: Rebased on top of the WA refactoring
v6: Added References (Mika)

References: HSDES#2006611047
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 5 +++--
 drivers/gpu/drm/i915/intel_workarounds.c | 7 +++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8da119f..eb2eede 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8319,8 +8319,9 @@ enum {
 
 #define GEN7_ROW_CHICKEN2		_MMIO(0xe4f4)
 #define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)
-#define   DOP_CLOCK_GATING_DISABLE	(1<<0)
-#define   PUSH_CONSTANT_DEREF_DISABLE	(1<<8)
+#define   DOP_CLOCK_GATING_DISABLE	(1 << 0)
+#define   PUSH_CONSTANT_DEREF_DISABLE	(1 << 8)
+#define   GEN11_TDL_CLOCK_GATING_FIX_DISABLE	(1 << 1)
 
 #define HSW_ROW_CHICKEN3		_MMIO(0xe49c)
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index f89a5c2..7302759 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -459,6 +459,13 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	 */
 	WA_SET_BIT_MASKED(ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
 
+	/* Wa_2006611047:icl (pre-prod)
+	 * Formerly known as WaDisableImprovedTdlClkGating
+	 */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
+				  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 15/22] drm/i915/icl: WaEnableStateCacheRedirectToCS

[Oscar Mateo]

Redirects the state cache to the CS Command buffer section for
performance reasons.

v2: Rebased
v3: Rebased on top of the WA refactoring
v3: Added References (Mika)

References: HSDES#1604325460
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 1 +
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eb2eede..5e4ddc9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7208,6 +7208,7 @@ enum {
 #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
+#define   GEN11_STATE_CACHE_REDIRECT_TO_CS	(1 << 11)
 
 #define GEN7_L3SQCREG1				_MMIO(0xB010)
 #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 7302759..bff999c 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -466,6 +466,10 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 				  GEN11_TDL_CLOCK_GATING_FIX_DISABLE);
 
+	/* WaEnableStateCacheRedirectToCS:icl */
+	WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
+			  GEN11_STATE_CACHE_REDIRECT_TO_CS);
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 16/22] drm/i915/icl: Wa_2006665173

[Oscar Mateo]

Disable blend embellishment in RCC.

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)

References: HSDES#2006665173
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 18 +++++++++++-------
 drivers/gpu/drm/i915/intel_workarounds.c |  5 +++++
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e4ddc9..b3efcf0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7192,13 +7192,17 @@ enum {
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1		_MMIO(0x7010)
-# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1<<10) | (1<<26))
-# define GEN9_RHWO_OPTIMIZATION_DISABLE		(1<<14)
-#define COMMON_SLICE_CHICKEN2			_MMIO(0x7014)
-# define GEN9_PBE_COMPRESSED_HASH_SELECTION	(1<<13)
-# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
-# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
-# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE	(1<<0)
+  #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC	((1 << 10) | (1 << 26))
+  #define GEN9_RHWO_OPTIMIZATION_DISABLE	(1 << 14)
+
+#define COMMON_SLICE_CHICKEN2					_MMIO(0x7014)
+  #define GEN9_PBE_COMPRESSED_HASH_SELECTION			(1 << 13)
+  #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE	(1 << 12)
+  #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION		(1 << 8)
+  #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE			(1 << 0)
+
+#define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
+  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
 
 #define HIZ_CHICKEN					_MMIO(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X				(1<<15)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index bff999c..d2d89bf 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -470,6 +470,11 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	WA_SET_BIT_MASKED(GEN9_SLICE_COMMON_ECO_CHICKEN1,
 			  GEN11_STATE_CACHE_REDIRECT_TO_CS);
 
+	/* Wa_2006665173:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_B0))
+		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 17/22] drm/i915/icl: WaEnableFloatBlendOptimization

[Oscar Mateo]

Enables blend optimization for floating point RTs

v2: Rebased on top of the WA refactoring
v3: Added References (Mika)

References: HSDES#1406393558
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b3efcf0..fe44c99 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2663,6 +2663,9 @@ enum i915_power_well_id {
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1<<6)
 #define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1<<1)
 
+#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
+#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
+
 #define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)
 #define   GEN6_BLITTER_LOCK_SHIFT			16
 #define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index d2d89bf..c1c45ce 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -475,6 +475,9 @@ static int icl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
 				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
 
+	/* WaEnableFloatBlendOptimization:icl */
+	WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS, FLOAT_BLEND_OPTIMIZATION_ENABLE);
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 18/22] drm/i915/icl: WaSendPushConstantsFromMMIO

[Oscar Mateo]

Allows UMDs to set 'Disable Gather at Set Shader Common Slice'.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it...

v2: Rebased
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the WA whitelist reg refactoring (Michel)
v5: Added References (Mika)

References: HSDES#1405764967
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index c1c45ce..07e529b 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -892,6 +892,8 @@ static void cnl_whitelist_build(struct whitelist *w)
 
 static void icl_whitelist_build(struct whitelist *w)
 {
+	/* WaSendPushConstantsFromMMIO:icl */
+	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[PATCH 19/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2

[Oscar Mateo]

Required to dinamically set 'Small PL Lossless Fix Enable'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
v5: Added References (Mika)

References: HSDES#1804860039
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 07e529b..7cf5d89 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -894,6 +894,9 @@ static void icl_whitelist_build(struct whitelist *w)
 {
 	/* WaSendPushConstantsFromMMIO:icl */
 	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+	/* WaAllowUMDToModifyHalfSliceChicken2:icl */
+	whitelist_reg(w, HALF_SLICE_CHICKEN2);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[PATCH 20/22] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7

[Oscar Mateo]

Required to dinamically set 'Trilinear Filter Quality Mode'

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)
v5: Added References (Mika)

References: HSDES#1804860157
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 7cf5d89..2f37ead 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -897,6 +897,9 @@ static void icl_whitelist_build(struct whitelist *w)
 
 	/* WaAllowUMDToModifyHalfSliceChicken2:icl */
 	whitelist_reg(w, HALF_SLICE_CHICKEN2);
+
+	/* WaAllowUMDToModifyHalfSliceChicken7:icl */
+	whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[PATCH 21/22] drm/i915/icl: WaAllowUmdWriteTRTTRootTable

[Oscar Mateo]

Required for TR-TT (Tiled Resource Translation Table) support.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: For whatever reason, this ended up in KBL (??!!)
v3: Rebased on top of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)

Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 3 +++
 drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe44c99..a9866df 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8290,6 +8290,9 @@ enum {
 #define GAMW_ECO_DEV_RW_IA_REG			_MMIO(0x4080)
 #define   GAMW_ECO_DEV_CTX_RELOAD_DISABLE	(1 << 7)
 
+#define TR_VA_TTL3_PTR_DW0		_MMIO(0x4DE0)
+#define TR_VA_TTL3_PTR_DW1		_MMIO(0x4DE4)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 2f37ead..3c507d1 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -900,6 +900,10 @@ static void icl_whitelist_build(struct whitelist *w)
 
 	/* WaAllowUMDToModifyHalfSliceChicken7:icl */
 	whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+	/* WaAllowUmdWriteTRTTRootTable:icl */
+	whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
+	whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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[PATCH 22/22] drm/i915/icl: WaAllowUMDToModifySamplerMode

[Oscar Mateo]

Required for Bindless samplers.

Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.

v2: Rebased on top of the WA refactoring (Michel)
v3: Added References (Mika)

References: HSDES#1404695891
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          | 2 ++
 drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a9866df..d36cf61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8293,6 +8293,8 @@ enum {
 #define TR_VA_TTL3_PTR_DW0		_MMIO(0x4DE0)
 #define TR_VA_TTL3_PTR_DW1		_MMIO(0x4DE4)
 
+#define GEN10_SAMPLER_MODE		_MMIO(0xE18C)
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff<<14)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 3c507d1..bca46b5 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -904,6 +904,9 @@ static void icl_whitelist_build(struct whitelist *w)
 	/* WaAllowUmdWriteTRTTRootTable:icl */
 	whitelist_reg(w, TR_VA_TTL3_PTR_DW0);
 	whitelist_reg(w, TR_VA_TTL3_PTR_DW1);
+
+	/* WaAllowUMDToModifySamplerMode:icl */
+	whitelist_reg(w, GEN10_SAMPLER_MODE);
 }
 
 static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
-- 
1.9.1

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Re: [PATCH v2 00/22] Workarounds for Icelake

[Chris Wilson]

Quoting Oscar Mateo (2018-05-02 21:33:59)
> List of GT workarounds for Icelake that we have been carrying in internal.

(Is (checkpatch
     (((going to complain)
       (that this isn't))
      (lisp))))?
-Chris
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Re: [PATCH v2 00/22] Workarounds for Icelake

[Oscar Mateo Lozano]

On 5/2/2018 1:40 PM, Chris Wilson wrote:
> Quoting Oscar Mateo (2018-05-02 21:33:59)
>> List of GT workarounds for Icelake that we have been carrying in internal.
> (Is (checkpatch
>       (((going to complain)
>         (that this isn't))
>        (lisp))))?
> -Chris

Maybe. Or maybe checkpatch has given up completely on checking the 
parentheses in the WAs?
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✗ Fi.CI.CHECKPATCH: warning for Workarounds for Icelake (rev2)

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake (rev2)
URL   : https://patchwork.freedesktop.org/series/42055/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fb5717243f07 drm/i915/icl: Introduce initial Icelake Workarounds
-:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#50: FILE: drivers/gpu/drm/i915/i915_drv.h:2478:
+#define IS_ICL_REVID(p, since, until) \
+	(IS_ICELAKE(p) && IS_REVID(p, since, until))

total: 0 errors, 0 warnings, 1 checks, 155 lines checked
524aa53726c5 drm/i915/icl: Enable Sampler DFR
b83e1d29370d drm/i915/icl: WaGAPZPriorityScheme
5ccfff75b3b6 drm/i915/icl: WaL3BankAddressHashing
7e5a63f17cc4 drm/i915/icl: WaModifyGamTlbPartitioning
fba6d3b485a6 drm/i915/icl: WaDisableCleanEvicts
8df450e10606 drm/i915/icl: WaCL2SFHalfMaxAlloc
abc10f464133 drm/i915/icl: WaDisCtxReload
372bd9a2b18a drm/i915/icl: Wa_1405779004
dad22eb7f668 drm/i915/icl: Wa_1406680159
0795711c286f drm/i915/icl: Wa_1604302699
fc7b510deeb0 drm/i915/icl: Wa_1406838659
0b81764193f2 drm/i915/icl: WaForwardProgressSoftReset
7d0e57431841 drm/i915/icl: WaDisableImprovedTdlClkGating
3d6111048c11 drm/i915/icl: WaEnableStateCacheRedirectToCS
9fddbebf26dd drm/i915/icl: Wa_2006665173
c98c2c3b8139 drm/i915/icl: WaEnableFloatBlendOptimization
1d0fa8c6e2c0 drm/i915/icl: WaSendPushConstantsFromMMIO
6e49fc5ec7e1 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
be65dff8954c drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
b6fc6c9d86cf drm/i915/icl: WaAllowUmdWriteTRTTRootTable
e6c837fdc77d drm/i915/icl: WaAllowUMDToModifySamplerMode

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✗ Fi.CI.SPARSE: warning for Workarounds for Icelake (rev2)

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake (rev2)
URL   : https://patchwork.freedesktop.org/series/42055/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Introduce initial Icelake Workarounds
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3663:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3672:16: warning: expression using sizeof(void)

Commit: drm/i915/icl: Enable Sampler DFR
Okay!

Commit: drm/i915/icl: WaGAPZPriorityScheme
Okay!

Commit: drm/i915/icl: WaL3BankAddressHashing
Okay!

Commit: drm/i915/icl: WaModifyGamTlbPartitioning
Okay!

Commit: drm/i915/icl: WaDisableCleanEvicts
Okay!

Commit: drm/i915/icl: WaCL2SFHalfMaxAlloc
Okay!

Commit: drm/i915/icl: WaDisCtxReload
Okay!

Commit: drm/i915/icl: Wa_1405779004
Okay!

Commit: drm/i915/icl: Wa_1406680159
Okay!

Commit: drm/i915/icl: Wa_1604302699
Okay!

Commit: drm/i915/icl: Wa_1406838659
Okay!

Commit: drm/i915/icl: WaForwardProgressSoftReset
Okay!

Commit: drm/i915/icl: WaDisableImprovedTdlClkGating
Okay!

Commit: drm/i915/icl: WaEnableStateCacheRedirectToCS
Okay!

Commit: drm/i915/icl: Wa_2006665173
Okay!

Commit: drm/i915/icl: WaEnableFloatBlendOptimization
Okay!

Commit: drm/i915/icl: WaSendPushConstantsFromMMIO
Okay!

Commit: drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
Okay!

Commit: drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
Okay!

Commit: drm/i915/icl: WaAllowUmdWriteTRTTRootTable
Okay!

Commit: drm/i915/icl: WaAllowUMDToModifySamplerMode
Okay!

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✓ Fi.CI.BAT: success for Workarounds for Icelake (rev2)

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake (rev2)
URL   : https://patchwork.freedesktop.org/series/42055/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4124 -> Patchwork_8883 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_8883 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
      fi-cnl-psr:         PASS -> FAIL (fdo#103481)

    
    ==== Possible fixes ====

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         FAIL (fdo#102575) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    igt@prime_vgem@basic-fence-flip:
      fi-glk-j4005:       FAIL (fdo#104008) -> PASS

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008


== Participating hosts (39 -> 36) ==

  Additional (1): fi-bxt-dsi 
  Missing    (4): fi-ctg-p8600 fi-ilk-m540 fi-cnl-y3 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4124 -> Patchwork_8883

  CI_DRM_4124: f8d7a96b18809b25ffc00bb9fd4245a0e826057b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4456: 43761534c6482dc67b9c3d8eeecd425ef40b3c4c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8883: e6c837fdc77dc95dc5069050d22f973b060f8098 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4456: 30b992bdc047073e1fe99b1ac622f026618a8081 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

e6c837fdc77d drm/i915/icl: WaAllowUMDToModifySamplerMode
b6fc6c9d86cf drm/i915/icl: WaAllowUmdWriteTRTTRootTable
be65dff8954c drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
6e49fc5ec7e1 drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken2
1d0fa8c6e2c0 drm/i915/icl: WaSendPushConstantsFromMMIO
c98c2c3b8139 drm/i915/icl: WaEnableFloatBlendOptimization
9fddbebf26dd drm/i915/icl: Wa_2006665173
3d6111048c11 drm/i915/icl: WaEnableStateCacheRedirectToCS
7d0e57431841 drm/i915/icl: WaDisableImprovedTdlClkGating
0b81764193f2 drm/i915/icl: WaForwardProgressSoftReset
fc7b510deeb0 drm/i915/icl: Wa_1406838659
0795711c286f drm/i915/icl: Wa_1604302699
dad22eb7f668 drm/i915/icl: Wa_1406680159
372bd9a2b18a drm/i915/icl: Wa_1405779004
abc10f464133 drm/i915/icl: WaDisCtxReload
8df450e10606 drm/i915/icl: WaCL2SFHalfMaxAlloc
fba6d3b485a6 drm/i915/icl: WaDisableCleanEvicts
7e5a63f17cc4 drm/i915/icl: WaModifyGamTlbPartitioning
5ccfff75b3b6 drm/i915/icl: WaL3BankAddressHashing
b83e1d29370d drm/i915/icl: WaGAPZPriorityScheme
524aa53726c5 drm/i915/icl: Enable Sampler DFR
fb5717243f07 drm/i915/icl: Introduce initial Icelake Workarounds

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8883/issues.html
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✓ Fi.CI.IGT: success for Workarounds for Icelake (rev2)

[Patchwork]

== Series Details ==

Series: Workarounds for Icelake (rev2)
URL   : https://patchwork.freedesktop.org/series/42055/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4124_full -> Patchwork_8883_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8883_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8883_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42055/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8883_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-bsd1:
      shard-kbl:          PASS -> SKIP

    igt@pm_rc6_residency@rc6-accuracy:
      shard-kbl:          SKIP -> PASS +2
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_8883_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_cursor_crc@cursor-128x128-dpms:
      shard-apl:          PASS -> FAIL (fdo#103232, fdo#104645)

    igt@kms_flip@absolute-wf_vblank-interruptible:
      shard-glk:          PASS -> FAIL (fdo#106087)

    igt@kms_flip@dpms-vs-vblank-race-interruptible:
      shard-glk:          PASS -> FAIL (fdo#103060)

    igt@kms_flip@flip-vs-expired-vblank:
      shard-glk:          PASS -> FAIL (fdo#102887, fdo#105363)

    igt@kms_flip@wf_vblank-ts-check-interruptible:
      shard-glk:          PASS -> FAIL (fdo#100368)

    
    ==== Possible fixes ====

    igt@kms_cursor_crc@cursor-128x128-suspend:
      shard-apl:          FAIL (fdo#103375) -> PASS

    igt@kms_cursor_crc@cursor-64x64-dpms:
      shard-apl:          FAIL (fdo#103232, fdo#104645) -> PASS

    igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
      shard-hsw:          FAIL (fdo#104873) -> PASS

    igt@kms_flip@flip-vs-expired-vblank:
      shard-hsw:          FAIL (fdo#105707) -> PASS

    igt@kms_flip@plain-flip-ts-check-interruptible:
      shard-hsw:          FAIL (fdo#100368) -> PASS

    igt@kms_sysfs_edid_timing:
      shard-apl:          WARN (fdo#100047) -> PASS

    igt@kms_vblank@pipe-a-accuracy-idle:
      shard-hsw:          FAIL (fdo#102583) -> PASS

    

  === Piglit changes ===

    ==== Issues hit ====

    spec@arb_tessellation_shader@execution@variable-indexing@vs-output-array-float-index-wr-before-tcs:
      pig-glk-j4005:      NOTRUN -> FAIL (fdo#106148) +35

    spec@glsl-1.40-compat@execution@built-in-constants:
      pig-glk-j4005:      NOTRUN -> FAIL (fdo#106277)
      pig-hsw-4770r:      NOTRUN -> FAIL (fdo#106277)

    
  fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
  fdo#104645 https://bugs.freedesktop.org/show_bug.cgi?id=104645
  fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
  fdo#106148 https://bugs.freedesktop.org/show_bug.cgi?id=106148
  fdo#106277 https://bugs.freedesktop.org/show_bug.cgi?id=106277


== Participating hosts (6 -> 8) ==

  Additional (2): pig-glk-j4005 pig-hsw-4770r 


== Build changes ==

    * Linux: CI_DRM_4124 -> Patchwork_8883

  CI_DRM_4124: f8d7a96b18809b25ffc00bb9fd4245a0e826057b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4456: 43761534c6482dc67b9c3d8eeecd425ef40b3c4c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8883: e6c837fdc77dc95dc5069050d22f973b060f8098 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4456: 30b992bdc047073e1fe99b1ac622f026618a8081 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8883/shards.html
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