LS1043A : "synchronous abort" at boot due to PCI config read

LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Dear developers,

I currently have two functional workarounds for this issue but would like to know which one you would recommend, if any :-)
I'm using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous external abort" when booting because of a PCI config read 
during PCI scan.

I'm using a custom hardware (based on LS1043ARDB) having a PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI slot 
for legacy devices. This bridge only supports PCI-Compatible config accesses (offset 0x00-0xFF).
On this PCI slot I connect a PCI module made of a PCI-to-PCIe bridge plus PCIe devices behind.
The problem occurs when the kernel probes the PCIe devices : as they are PCIe devices, the kernel does a PCI config read access at 
offset 0x100 to check if "PCIe extended capability registers" are accessible (see drivers/pci/probe.c, function 
pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI bridge that is in the path reports an error to the CPU for this 
access, and it seems there's no way to disable that on this bridge.

The first workaround I found was to patch drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set to 0x9400 instead of 
0x9401 (for PCIE_ABSERR register) to disable error reporting. This only impacts an NXP part of the Linux kernel code, but I'm not 
sure this is a good idea (however it seems to be like that on Intel platforms where even MEM accesses to a no-device address return 
FF without any error).

I've also tried another workaround that works : patch drivers/pci/probe.c to use bus_flags to remember if a bus is behind a bridge 
without extended address capability, to avoid PCi config read accesses at offset 0x100 in
pci_cfg_space_size() / pci_cfg_space_size_ext(). But this patch impacts the generic PCI probe method of Linux.

Any Idea to properly handle that issue ?

Best regards

Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Ard Biesheuvel]

(add Bjorn and linux-pci)

On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
> Dear developers,
>
> I currently have two functional workarounds for this issue but would like to know which one you would recommend, if any :-)
> I'm using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous external abort" when booting because of a PCI config read
> during PCI scan.
>
> I'm using a custom hardware (based on LS1043ARDB) having a PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI slot
> for legacy devices. This bridge only supports PCI-Compatible config accesses (offset 0x00-0xFF).
> On this PCI slot I connect a PCI module made of a PCI-to-PCIe bridge plus PCIe devices behind.
> The problem occurs when the kernel probes the PCIe devices : as they are PCIe devices, the kernel does a PCI config read access at
> offset 0x100 to check if "PCIe extended capability registers" are accessible (see drivers/pci/probe.c, function
> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI bridge that is in the path reports an error to the CPU for this
> access, and it seems there's no way to disable that on this bridge.
>
> The first workaround I found was to patch drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set to 0x9400 instead of
> 0x9401 (for PCIE_ABSERR register) to disable error reporting. This only impacts an NXP part of the Linux kernel code, but I'm not
> sure this is a good idea (however it seems to be like that on Intel platforms where even MEM accesses to a no-device address return
> FF without any error).
>
> I've also tried another workaround that works : patch drivers/pci/probe.c to use bus_flags to remember if a bus is behind a bridge
> without extended address capability, to avoid PCi config read accesses at offset 0x100 in
> pci_cfg_space_size() / pci_cfg_space_size_ext(). But this patch impacts the generic PCI probe method of Linux.
>
> Any Idea to properly handle that issue ?
>

This seems like a rather unusual configuration, but I guess that if
the first bridge/switch advertises its inability to support extended
config space accesses, we should not be performing them on any of its
subordinate buses. How does the PEX8112 advertise this limitation?

That said, I wonder if it is reasonable in the first place to expect
that a PCIe device works as expected passing through a legacy PCI
layer like that.

LS1043A : "synchronous abort" at boot due to PCI config read

[Ard Biesheuvel]

(add Bjorn and linux-pci)

On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
> Dear developers,
>
> I currently have two functional workarounds for this issue but would like to know which one you would recommend, if any :-)
> I'm using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous external abort" when booting because of a PCI config read
> during PCI scan.
>
> I'm using a custom hardware (based on LS1043ARDB) having a PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI slot
> for legacy devices. This bridge only supports PCI-Compatible config accesses (offset 0x00-0xFF).
> On this PCI slot I connect a PCI module made of a PCI-to-PCIe bridge plus PCIe devices behind.
> The problem occurs when the kernel probes the PCIe devices : as they are PCIe devices, the kernel does a PCI config read access at
> offset 0x100 to check if "PCIe extended capability registers" are accessible (see drivers/pci/probe.c, function
> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI bridge that is in the path reports an error to the CPU for this
> access, and it seems there's no way to disable that on this bridge.
>
> The first workaround I found was to patch drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set to 0x9400 instead of
> 0x9401 (for PCIE_ABSERR register) to disable error reporting. This only impacts an NXP part of the Linux kernel code, but I'm not
> sure this is a good idea (however it seems to be like that on Intel platforms where even MEM accesses to a no-device address return
> FF without any error).
>
> I've also tried another workaround that works : patch drivers/pci/probe.c to use bus_flags to remember if a bus is behind a bridge
> without extended address capability, to avoid PCi config read accesses at offset 0x100 in
> pci_cfg_space_size() / pci_cfg_space_size_ext(). But this patch impacts the generic PCI probe method of Linux.
>
> Any Idea to properly handle that issue ?
>

This seems like a rather unusual configuration, but I guess that if
the first bridge/switch advertises its inability to support extended
config space accesses, we should not be performing them on any of its
subordinate buses. How does the PEX8112 advertise this limitation?

That said, I wonder if it is reasonable in the first place to expect
that a PCIe device works as expected passing through a legacy PCI
layer like that.

Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

[-- Attachment #1: Type: text/plain, Size: 3324 bytes --]

Le 27/04/2018 10:43, Ard Biesheuvel a écrit :
> (add Bjorn and linux-pci)
>
> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
>> Dear developers,
>>
>> I currently have two functional workarounds for this issue but would like to know which one you would recommend, if any :-)
>> I'm using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous external abort" when booting because of a PCI config read
>> during PCI scan.
>>
>> I'm using a custom hardware (based on LS1043ARDB) having a PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI slot
>> for legacy devices. This bridge only supports PCI-Compatible config accesses (offset 0x00-0xFF).
>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe bridge plus PCIe devices behind.
>> The problem occurs when the kernel probes the PCIe devices : as they are PCIe devices, the kernel does a PCI config read access at
>> offset 0x100 to check if "PCIe extended capability registers" are accessible (see drivers/pci/probe.c, function
>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI bridge that is in the path reports an error to the CPU for this
>> access, and it seems there's no way to disable that on this bridge.
>>
>> The first workaround I found was to patch drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set to 0x9400 instead of
>> 0x9401 (for PCIE_ABSERR register) to disable error reporting. This only impacts an NXP part of the Linux kernel code, but I'm not
>> sure this is a good idea (however it seems to be like that on Intel platforms where even MEM accesses to a no-device address return
>> FF without any error).
>>
>> I've also tried another workaround that works : patch drivers/pci/probe.c to use bus_flags to remember if a bus is behind a bridge
>> without extended address capability, to avoid PCi config read accesses at offset 0x100 in
>> pci_cfg_space_size() / pci_cfg_space_size_ext(). But this patch impacts the generic PCI probe method of Linux.
>>
>> Any Idea to properly handle that issue ?
>>
> This seems like a rather unusual configuration, but I guess that if
> the first bridge/switch advertises its inability to support extended
> config space accesses, we should not be performing them on any of its
> subordinate buses. How does the PEX8112 advertise this limitation?
>
> That said, I wonder if it is reasonable in the first place to expect
> that a PCIe device works as expected passing through a legacy PCI
> layer like that.
>
> .
The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but has no PCI_CAP_ID_PCIX capability.
As I understand the lack of PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no support for PCI config offset >=0x100).
Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this limitation would be advertised by the lack of PCI_X_STATUS_266MHZ 
and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at pci_cfg_space_size())

I'm currently using the attached patch (for kernel 4.1.35-rt41 from NXP Yocto BSP). It uses bus_flags to remember if a bus is behind 
a bridge without extended address capability to avoid PCi config accesses at offset >= 0x100. Thanks to this patch I now have a 
functional system with functional PCI/PCIe devices.

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: cfgspace.patch --]
[-- Type: text/x-patch; name=cfgspace.patch, Size: 1943 bytes --]

--- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
+++ include/linux/pci.h	2018-03-26 16:51:27.660000000 +0000
@@ -193,6 +193,7 @@
 enum pci_bus_flags {
 	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
 	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
+	PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
 };
 
 /* These values come from the PCI Express Spec */
--- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
+++ drivers/pci/probe.c	2018-03-26 16:54:30.830000000 +0000
@@ -827,6 +827,28 @@
 			child->primary = primary;
 			pci_bus_insert_busn_res(child, secondary, subordinate);
 			child->bridge_ctl = bctl;
+
+			{
+				int pos;
+				u32 status;
+				bool pci_compat_cfg_space = false;
+
+				if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)) {
+					/* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X capabilities */
+					pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+					if (pos) {
+						pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
+						if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
+							pci_compat_cfg_space = true;
+					} else {
+						pci_compat_cfg_space = true;
+					}
+					if (pci_compat_cfg_space) {
+						dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor, dev->device);
+						child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
+					}
+				}
+			}
 		}
 
 		cmax = pci_scan_child_bus(child);
@@ -1098,6 +1120,11 @@
 			goto fail;
 	}
 
+	if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
+		dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
+		return PCI_CFG_SPACE_SIZE;
+	}
+
 	return pci_cfg_space_size_ext(dev);
 
  fail:

[-- Attachment #3: Type: text/plain, Size: 176 bytes --]

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LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Le 27/04/2018 10:43, Ard Biesheuvel a ?crit :
> (add Bjorn and linux-pci)
>
> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
>> Dear developers,
>>
>> I currently have two functional workarounds for this issue but would like to know which one you would recommend, if any :-)
>> I'm using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous external abort" when booting because of a PCI config read
>> during PCI scan.
>>
>> I'm using a custom hardware (based on LS1043ARDB) having a PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI slot
>> for legacy devices. This bridge only supports PCI-Compatible config accesses (offset 0x00-0xFF).
>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe bridge plus PCIe devices behind.
>> The problem occurs when the kernel probes the PCIe devices : as they are PCIe devices, the kernel does a PCI config read access at
>> offset 0x100 to check if "PCIe extended capability registers" are accessible (see drivers/pci/probe.c, function
>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI bridge that is in the path reports an error to the CPU for this
>> access, and it seems there's no way to disable that on this bridge.
>>
>> The first workaround I found was to patch drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set to 0x9400 instead of
>> 0x9401 (for PCIE_ABSERR register) to disable error reporting. This only impacts an NXP part of the Linux kernel code, but I'm not
>> sure this is a good idea (however it seems to be like that on Intel platforms where even MEM accesses to a no-device address return
>> FF without any error).
>>
>> I've also tried another workaround that works : patch drivers/pci/probe.c to use bus_flags to remember if a bus is behind a bridge
>> without extended address capability, to avoid PCi config read accesses at offset 0x100 in
>> pci_cfg_space_size() / pci_cfg_space_size_ext(). But this patch impacts the generic PCI probe method of Linux.
>>
>> Any Idea to properly handle that issue ?
>>
> This seems like a rather unusual configuration, but I guess that if
> the first bridge/switch advertises its inability to support extended
> config space accesses, we should not be performing them on any of its
> subordinate buses. How does the PEX8112 advertise this limitation?
>
> That said, I wonder if it is reasonable in the first place to expect
> that a PCIe device works as expected passing through a legacy PCI
> layer like that.
>
> .
The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but has no PCI_CAP_ID_PCIX capability.
As I understand the lack of PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no support for PCI config offset >=0x100).
Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this limitation would be advertised by the lack of PCI_X_STATUS_266MHZ 
and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at pci_cfg_space_size())

I'm currently using the attached patch (for kernel 4.1.35-rt41 from NXP Yocto BSP). It uses bus_flags to remember if a bus is behind 
a bridge without extended address capability to avoid PCi config accesses at offset >= 0x100. Thanks to this patch I now have a 
functional system with functional PCI/PCIe devices.
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Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Bjorn Helgaas]

On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
> Le 27/04/2018 10:43, Ard Biesheuvel a écrit :
> > (add Bjorn and linux-pci)
> >
> > On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
> >> Dear developers,
> >>
> >> I currently have two functional workarounds for this issue but
> >> would like to know which one you would recommend, if any :-) I'm
> >> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
> >> external abort" when booting because of a PCI config read during
> >> PCI scan.
> >>
> >> I'm using a custom hardware (based on LS1043ARDB) having a
> >> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
> >> slot for legacy devices. This bridge only supports PCI-Compatible
> >> config accesses (offset 0x00-0xFF).

I would guess the PEX8112 itself has 4K of config space, but it only
forwards 256 bytes of config space to the conventional PCI secondary
bus.

> >> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
> >> bridge plus PCIe devices behind.
> >>
> >> The problem occurs when the kernel probes the PCIe devices : as
> >> they are PCIe devices, the kernel does a PCI config read access
> >> at offset 0x100 to check if "PCIe extended capability registers"
> >> are accessible (see drivers/pci/probe.c, function
> >> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
> >> bridge that is in the path reports an error to the CPU for this
> >> access, and it seems there's no way to disable that on this
> >> bridge.
> >>
> >> The first workaround I found was to patch
> >> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
> >> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
> >> error reporting. This only impacts an NXP part of the Linux
> >> kernel code, but I'm not sure this is a good idea (however it
> >> seems to be like that on Intel platforms where even MEM accesses
> >> to a no-device address return FF without any error).
> >>
> >> I've also tried another workaround that works : patch
> >> drivers/pci/probe.c to use bus_flags to remember if a bus is
> >> behind a bridge without extended address capability, to avoid PCi
> >> config read accesses at offset 0x100 in pci_cfg_space_size() /
> >> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
> >> probe method of Linux.
> >>
> >> Any Idea to properly handle that issue ?
> >>
> > This seems like a rather unusual configuration, but I guess that
> > if the first bridge/switch advertises its inability to support
> > extended config space accesses, we should not be performing them
> > on any of its subordinate buses. How does the PEX8112 advertise
> > this limitation?
> >
> > That said, I wonder if it is reasonable in the first place to
> > expect that a PCIe device works as expected passing through a
> > legacy PCI layer like that.
> >
> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
> support for PCI config offset >=0x100).

Sounds right to me.

> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
> pci_cfg_space_size())

Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
should be enough, but it shouldn't hurt to check for either
PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.

> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
> bridge without extended address capability to avoid PCi config
> accesses at offset >= 0x100. Thanks to this patch I now have a
> functional system with functional PCI/PCIe devices.

The patch seems like it's looking at the right things, but I don't
want to build it into pci_scan_bridge_extend() because that function
is much too complicated already.

I'd rather build it into pci_cfg_space_size() or
pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
that case, I think all 4K would be accessible on the PCI-X side.

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ac91b6fd0bcd..d8b091f0bcd1 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
  * pci_cfg_space_size - Get the configuration space size of the PCI device
  * @dev: PCI device
  *
- * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
+ * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express devices
  * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
  * access it.  Maybe we don't have a way to generate extended config space
  * accesses, or the device is behind a reverse Express bridge.  So we try
@@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
  */
 static int pci_cfg_space_size_ext(struct pci_dev *dev)
 {
+	struct pci_dev *bridge = pci_upstream_bridge(dev);
 	u32 status;
 	int pos = PCI_CFG_SPACE_SIZE;
 
+	if (bridge && pci_is_pcie(bridge) &&
+	    pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
+		return PCI_CFG_SPACE_SIZE;
+
 	if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
 		return PCI_CFG_SPACE_SIZE;
 	if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))

> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
> +++ include/linux/pci.h	2018-03-26 16:51:27.660000000 +0000
> @@ -193,6 +193,7 @@
>  enum pci_bus_flags {
>  	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>  	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
> +	PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>  };
>  
>  /* These values come from the PCI Express Spec */
> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
> +++ drivers/pci/probe.c	2018-03-26 16:54:30.830000000 +0000
> @@ -827,6 +827,28 @@
>  			child->primary = primary;
>  			pci_bus_insert_busn_res(child, secondary, subordinate);
>  			child->bridge_ctl = bctl;
> +
> +			{
> +				int pos;
> +				u32 status;
> +				bool pci_compat_cfg_space = false;
> +
> +				if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)) {
> +					/* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X capabilities */
> +					pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
> +					if (pos) {
> +						pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
> +						if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
> +							pci_compat_cfg_space = true;
> +					} else {
> +						pci_compat_cfg_space = true;
> +					}
> +					if (pci_compat_cfg_space) {
> +						dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor, dev->device);
> +						child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
> +					}
> +				}
> +			}
>  		}
>  
>  		cmax = pci_scan_child_bus(child);
> @@ -1098,6 +1120,11 @@
>  			goto fail;
>  	}
>  
> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
> +		dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
> +		return PCI_CFG_SPACE_SIZE;
> +	}
> +
>  	return pci_cfg_space_size_ext(dev);
>  
>   fail:

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LS1043A : "synchronous abort" at boot due to PCI config read

[Bjorn Helgaas]

On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
> Le 27/04/2018 10:43, Ard Biesheuvel a ?crit :
> > (add Bjorn and linux-pci)
> >
> > On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
> >> Dear developers,
> >>
> >> I currently have two functional workarounds for this issue but
> >> would like to know which one you would recommend, if any :-) I'm
> >> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
> >> external abort" when booting because of a PCI config read during
> >> PCI scan.
> >>
> >> I'm using a custom hardware (based on LS1043ARDB) having a
> >> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
> >> slot for legacy devices. This bridge only supports PCI-Compatible
> >> config accesses (offset 0x00-0xFF).

I would guess the PEX8112 itself has 4K of config space, but it only
forwards 256 bytes of config space to the conventional PCI secondary
bus.

> >> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
> >> bridge plus PCIe devices behind.
> >>
> >> The problem occurs when the kernel probes the PCIe devices : as
> >> they are PCIe devices, the kernel does a PCI config read access
> >> at offset 0x100 to check if "PCIe extended capability registers"
> >> are accessible (see drivers/pci/probe.c, function
> >> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
> >> bridge that is in the path reports an error to the CPU for this
> >> access, and it seems there's no way to disable that on this
> >> bridge.
> >>
> >> The first workaround I found was to patch
> >> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
> >> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
> >> error reporting. This only impacts an NXP part of the Linux
> >> kernel code, but I'm not sure this is a good idea (however it
> >> seems to be like that on Intel platforms where even MEM accesses
> >> to a no-device address return FF without any error).
> >>
> >> I've also tried another workaround that works : patch
> >> drivers/pci/probe.c to use bus_flags to remember if a bus is
> >> behind a bridge without extended address capability, to avoid PCi
> >> config read accesses at offset 0x100 in pci_cfg_space_size() /
> >> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
> >> probe method of Linux.
> >>
> >> Any Idea to properly handle that issue ?
> >>
> > This seems like a rather unusual configuration, but I guess that
> > if the first bridge/switch advertises its inability to support
> > extended config space accesses, we should not be performing them
> > on any of its subordinate buses. How does the PEX8112 advertise
> > this limitation?
> >
> > That said, I wonder if it is reasonable in the first place to
> > expect that a PCIe device works as expected passing through a
> > legacy PCI layer like that.
> >
> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
> support for PCI config offset >=0x100).

Sounds right to me.

> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
> pci_cfg_space_size())

Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
should be enough, but it shouldn't hurt to check for either
PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.

> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
> bridge without extended address capability to avoid PCi config
> accesses at offset >= 0x100. Thanks to this patch I now have a
> functional system with functional PCI/PCIe devices.

The patch seems like it's looking at the right things, but I don't
want to build it into pci_scan_bridge_extend() because that function
is much too complicated already.

I'd rather build it into pci_cfg_space_size() or
pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
that case, I think all 4K would be accessible on the PCI-X side.

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ac91b6fd0bcd..d8b091f0bcd1 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
  * pci_cfg_space_size - Get the configuration space size of the PCI device
  * @dev: PCI device
  *
- * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
+ * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express devices
  * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
  * access it.  Maybe we don't have a way to generate extended config space
  * accesses, or the device is behind a reverse Express bridge.  So we try
@@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
  */
 static int pci_cfg_space_size_ext(struct pci_dev *dev)
 {
+	struct pci_dev *bridge = pci_upstream_bridge(dev);
 	u32 status;
 	int pos = PCI_CFG_SPACE_SIZE;
 
+	if (bridge && pci_is_pcie(bridge) &&
+	    pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
+		return PCI_CFG_SPACE_SIZE;
+
 	if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
 		return PCI_CFG_SPACE_SIZE;
 	if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))

> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
> +++ include/linux/pci.h	2018-03-26 16:51:27.660000000 +0000
> @@ -193,6 +193,7 @@
>  enum pci_bus_flags {
>  	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>  	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
> +	PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>  };
>  
>  /* These values come from the PCI Express Spec */
> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
> +++ drivers/pci/probe.c	2018-03-26 16:54:30.830000000 +0000
> @@ -827,6 +827,28 @@
>  			child->primary = primary;
>  			pci_bus_insert_busn_res(child, secondary, subordinate);
>  			child->bridge_ctl = bctl;
> +
> +			{
> +				int pos;
> +				u32 status;
> +				bool pci_compat_cfg_space = false;
> +
> +				if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)) {
> +					/* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X capabilities */
> +					pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
> +					if (pos) {
> +						pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
> +						if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
> +							pci_compat_cfg_space = true;
> +					} else {
> +						pci_compat_cfg_space = true;
> +					}
> +					if (pci_compat_cfg_space) {
> +						dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor, dev->device);
> +						child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
> +					}
> +				}
> +			}
>  		}
>  
>  		cmax = pci_scan_child_bus(child);
> @@ -1098,6 +1120,11 @@
>  			goto fail;
>  	}
>  
> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
> +		dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
> +		return PCI_CFG_SPACE_SIZE;
> +	}
> +
>  	return pci_cfg_space_size_ext(dev);
>  
>   fail:

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Le 27/04/2018 18:56, Bjorn Helgaas a =E9crit :
> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
>> Le 27/04/2018 10:43, Ard Biesheuvel a =E9crit :
>>> (add Bjorn and linux-pci)
>>>
>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrot=
e:
>>>> Dear developers,
>>>>
>>>> I currently have two functional workarounds for this issue but
>>>> would like to know which one you would recommend, if any :-) I'm
>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
>>>> external abort" when booting because of a PCI config read during
>>>> PCI scan.
>>>>
>>>> I'm using a custom hardware (based on LS1043ARDB) having a
>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
>>>> slot for legacy devices. This bridge only supports PCI-Compatible
>>>> config accesses (offset 0x00-0xFF).
> I would guess the PEX8112 itself has 4K of config space, but it only
> forwards 256 bytes of config space to the conventional PCI secondary
> bus.
>
>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
>>>> bridge plus PCIe devices behind.
>>>>
>>>> The problem occurs when the kernel probes the PCIe devices : as
>>>> they are PCIe devices, the kernel does a PCI config read access
>>>> at offset 0x100 to check if "PCIe extended capability registers"
>>>> are accessible (see drivers/pci/probe.c, function
>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
>>>> bridge that is in the path reports an error to the CPU for this
>>>> access, and it seems there's no way to disable that on this
>>>> bridge.
>>>>
>>>> The first workaround I found was to patch
>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
>>>> error reporting. This only impacts an NXP part of the Linux
>>>> kernel code, but I'm not sure this is a good idea (however it
>>>> seems to be like that on Intel platforms where even MEM accesses
>>>> to a no-device address return FF without any error).
>>>>
>>>> I've also tried another workaround that works : patch
>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
>>>> behind a bridge without extended address capability, to avoid PCi
>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
>>>> probe method of Linux.
>>>>
>>>> Any Idea to properly handle that issue ?
>>>>
>>> This seems like a rather unusual configuration, but I guess that
>>> if the first bridge/switch advertises its inability to support
>>> extended config space accesses, we should not be performing them
>>> on any of its subordinate buses. How does the PEX8112 advertise
>>> this limitation?
>>>
>>> That said, I wonder if it is reasonable in the first place to
>>> expect that a PCIe device works as expected passing through a
>>> legacy PCI layer like that.
>>>
>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
>> support for PCI config offset >=3D0x100).
> Sounds right to me.
>
>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
>> pci_cfg_space_size())
> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
> should be enough, but it shouldn't hurt to check for either
> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
>
>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
>> bridge without extended address capability to avoid PCi config
>> accesses at offset >=3D 0x100. Thanks to this patch I now have a
>> functional system with functional PCI/PCIe devices.
> The patch seems like it's looking at the right things, but I don't
> want to build it into pci_scan_bridge_extend() because that function
> is much too complicated already.
>
> I'd rather build it into pci_cfg_space_size() or
> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
> that case, I think all 4K would be accessible on the PCI-X side.
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index ac91b6fd0bcd..d8b091f0bcd1 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *=
dev)
>    * pci_cfg_space_size - Get the configuration space size of the PCI dev=
ice
>    * @dev: PCI device
>    *
> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devic=
es
> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express =
devices
>    * have 4096 bytes.  Even if the device is capable, that doesn't mean w=
e can
>    * access it.  Maybe we don't have a way to generate extended config sp=
ace
>    * accesses, or the device is behind a reverse Express bridge.  So we t=
ry
> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev =
*dev)
>    */
>   static int pci_cfg_space_size_ext(struct pci_dev *dev)
>   {
> +	struct pci_dev *bridge =3D pci_upstream_bridge(dev);
>   	u32 status;
>   	int pos =3D PCI_CFG_SPACE_SIZE;
>   =

> +	if (bridge && pci_is_pcie(bridge) &&
> +	    pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE)
> +		return PCI_CFG_SPACE_SIZE;
> +
>   	if (pci_read_config_dword(dev, pos, &status) !=3D PCIBIOS_SUCCESSFUL)
>   		return PCI_CFG_SPACE_SIZE;
>   	if (status =3D=3D 0xffffffff || pci_ext_cfg_is_aliased(dev))
>
>> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
>> +++ include/linux/pci.h	2018-03-26 16:51:27.660000000 +0000
>> @@ -193,6 +193,7 @@
>>   enum pci_bus_flags {
>>   	PCI_BUS_FLAGS_NO_MSI   =3D (__force pci_bus_flags_t) 1,
>>   	PCI_BUS_FLAGS_NO_MMRBC =3D (__force pci_bus_flags_t) 2,
>> +	PCI_BUS_FLAGS_COMPAT_CFG_SPACE =3D (__force pci_bus_flags_t) 4,
>>   };
>>   =

>>   /* These values come from the PCI Express Spec */
>> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
>> +++ drivers/pci/probe.c	2018-03-26 16:54:30.830000000 +0000
>> @@ -827,6 +827,28 @@
>>   			child->primary =3D primary;
>>   			pci_bus_insert_busn_res(child, secondary, subordinate);
>>   			child->bridge_ctl =3D bctl;
>> +
>> +			{
>> +				int pos;
>> +				u32 status;
>> +				bool pci_compat_cfg_space =3D false;
>> +
>> +				if (!pci_is_pcie(dev) || (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_PC=
IE_BRIDGE) || (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE)) {
>> +					/* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse m=
ode, we have to check for PCI-X capabilities */
>> +					pos =3D pci_find_capability(dev, PCI_CAP_ID_PCIX);
>> +					if (pos) {
>> +						pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>> +						if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>> +							pci_compat_cfg_space =3D true;
>> +					} else {
>> +						pci_compat_cfg_space =3D true;
>> +					}
>> +					if (pci_compat_cfg_space) {
>> +						dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compati=
ble config space\n", dev->vendor, dev->device);
>> +						child->bus_flags |=3D PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>> +					}
>> +				}
>> +			}
>>   		}
>>   =

>>   		cmax =3D pci_scan_child_bus(child);
>> @@ -1098,6 +1120,11 @@
>>   			goto fail;
>>   	}
>>   =

>> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
>> +		dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due=
 to parent bus(es)\n", dev->vendor, dev->device);
>> +		return PCI_CFG_SPACE_SIZE;
>> +	}
>> +
>>   	return pci_cfg_space_size_ext(dev);
>>   =

>>    fail:
Bjorn,
If I'm right about your proposed patch to pci_cfg_space_size_ext(), *bridge=
 is pointing to the upper device of device *dev being =

checked. I understand the purpose, but I think this fails for my config tha=
t is :

LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector -> PCI=
-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe =

devices (one on each port)

because :
- when pci_cfg_space_size_ext() is run on the 4 PCIe devices, *bridge is th=
e PCIe switch which is not matching =

PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be checked for th=
e parent bus of the PCIe switch, and so on.
- when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge, *bridge =
is the PEX8112 that is also not matching =

PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads to a confi=
g access at offset 0x100 to the PCI-to-PCIe bridge, so a =

crash (because of the PEX8112)

I think setting a bit in bus_flags when creating a child bus is very effici=
ent because once set it is automatically inherited by all =

child buses and then the only thing that pci_cfg_space_size() has to do for=
 each device is to check for this bit. Also this =

PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property that is comp=
liant with the purpose of bus_flags.

I agree that pci_scan_bridge_extend() is already too complicated, so would =
you be okay to only add one line to it :
   pci_bus_set_compat_cfg_space(child);
and put all the code I suggested in this new function pci_bus_set_compat_cf=
g_space() ? (also supporting PCI-X Mode 2 devices)
Improvement : this function can return immediately if the child bus has alr=
eady inherited the flag from its parent.


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LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Le 27/04/2018 18:56, Bjorn Helgaas a ?crit :
> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
>> Le 27/04/2018 10:43, Ard Biesheuvel a ?crit :
>>> (add Bjorn and linux-pci)
>>>
>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
>>>> Dear developers,
>>>>
>>>> I currently have two functional workarounds for this issue but
>>>> would like to know which one you would recommend, if any :-) I'm
>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
>>>> external abort" when booting because of a PCI config read during
>>>> PCI scan.
>>>>
>>>> I'm using a custom hardware (based on LS1043ARDB) having a
>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
>>>> slot for legacy devices. This bridge only supports PCI-Compatible
>>>> config accesses (offset 0x00-0xFF).
> I would guess the PEX8112 itself has 4K of config space, but it only
> forwards 256 bytes of config space to the conventional PCI secondary
> bus.
>
>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
>>>> bridge plus PCIe devices behind.
>>>>
>>>> The problem occurs when the kernel probes the PCIe devices : as
>>>> they are PCIe devices, the kernel does a PCI config read access
>>>> at offset 0x100 to check if "PCIe extended capability registers"
>>>> are accessible (see drivers/pci/probe.c, function
>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
>>>> bridge that is in the path reports an error to the CPU for this
>>>> access, and it seems there's no way to disable that on this
>>>> bridge.
>>>>
>>>> The first workaround I found was to patch
>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
>>>> error reporting. This only impacts an NXP part of the Linux
>>>> kernel code, but I'm not sure this is a good idea (however it
>>>> seems to be like that on Intel platforms where even MEM accesses
>>>> to a no-device address return FF without any error).
>>>>
>>>> I've also tried another workaround that works : patch
>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
>>>> behind a bridge without extended address capability, to avoid PCi
>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
>>>> probe method of Linux.
>>>>
>>>> Any Idea to properly handle that issue ?
>>>>
>>> This seems like a rather unusual configuration, but I guess that
>>> if the first bridge/switch advertises its inability to support
>>> extended config space accesses, we should not be performing them
>>> on any of its subordinate buses. How does the PEX8112 advertise
>>> this limitation?
>>>
>>> That said, I wonder if it is reasonable in the first place to
>>> expect that a PCIe device works as expected passing through a
>>> legacy PCI layer like that.
>>>
>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
>> support for PCI config offset >=0x100).
> Sounds right to me.
>
>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
>> pci_cfg_space_size())
> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
> should be enough, but it shouldn't hurt to check for either
> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
>
>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
>> bridge without extended address capability to avoid PCi config
>> accesses at offset >= 0x100. Thanks to this patch I now have a
>> functional system with functional PCI/PCIe devices.
> The patch seems like it's looking at the right things, but I don't
> want to build it into pci_scan_bridge_extend() because that function
> is much too complicated already.
>
> I'd rather build it into pci_cfg_space_size() or
> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
> that case, I think all 4K would be accessible on the PCI-X side.
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index ac91b6fd0bcd..d8b091f0bcd1 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>    * pci_cfg_space_size - Get the configuration space size of the PCI device
>    * @dev: PCI device
>    *
> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express devices
>    * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
>    * access it.  Maybe we don't have a way to generate extended config space
>    * accesses, or the device is behind a reverse Express bridge.  So we try
> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>    */
>   static int pci_cfg_space_size_ext(struct pci_dev *dev)
>   {
> +	struct pci_dev *bridge = pci_upstream_bridge(dev);
>   	u32 status;
>   	int pos = PCI_CFG_SPACE_SIZE;
>   
> +	if (bridge && pci_is_pcie(bridge) &&
> +	    pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
> +		return PCI_CFG_SPACE_SIZE;
> +
>   	if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
>   		return PCI_CFG_SPACE_SIZE;
>   	if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
>
>> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
>> +++ include/linux/pci.h	2018-03-26 16:51:27.660000000 +0000
>> @@ -193,6 +193,7 @@
>>   enum pci_bus_flags {
>>   	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>   	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>> +	PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>>   };
>>   
>>   /* These values come from the PCI Express Spec */
>> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
>> +++ drivers/pci/probe.c	2018-03-26 16:54:30.830000000 +0000
>> @@ -827,6 +827,28 @@
>>   			child->primary = primary;
>>   			pci_bus_insert_busn_res(child, secondary, subordinate);
>>   			child->bridge_ctl = bctl;
>> +
>> +			{
>> +				int pos;
>> +				u32 status;
>> +				bool pci_compat_cfg_space = false;
>> +
>> +				if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)) {
>> +					/* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X capabilities */
>> +					pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
>> +					if (pos) {
>> +						pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>> +						if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>> +							pci_compat_cfg_space = true;
>> +					} else {
>> +						pci_compat_cfg_space = true;
>> +					}
>> +					if (pci_compat_cfg_space) {
>> +						dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor, dev->device);
>> +						child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>> +					}
>> +				}
>> +			}
>>   		}
>>   
>>   		cmax = pci_scan_child_bus(child);
>> @@ -1098,6 +1120,11 @@
>>   			goto fail;
>>   	}
>>   
>> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
>> +		dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
>> +		return PCI_CFG_SPACE_SIZE;
>> +	}
>> +
>>   	return pci_cfg_space_size_ext(dev);
>>   
>>    fail:
Bjorn,
If I'm right about your proposed patch to pci_cfg_space_size_ext(), *bridge is pointing to the upper device of device *dev being 
checked. I understand the purpose, but I think this fails for my config that is :

LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector -> PCI-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe 
devices (one on each port)

because :
- when pci_cfg_space_size_ext() is run on the 4 PCIe devices, *bridge is the PCIe switch which is not matching 
PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be checked for the parent bus of the PCIe switch, and so on.
- when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge, *bridge is the PEX8112 that is also not matching 
PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads to a config access at offset 0x100 to the PCI-to-PCIe bridge, so a 
crash (because of the PEX8112)

I think setting a bit in bus_flags when creating a child bus is very efficient because once set it is automatically inherited by all 
child buses and then the only thing that pci_cfg_space_size() has to do for each device is to check for this bit. Also this 
PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property that is compliant with the purpose of bus_flags.

I agree that pci_scan_bridge_extend() is already too complicated, so would you be okay to only add one line to it :
   pci_bus_set_compat_cfg_space(child);
and put all the code I suggested in this new function pci_bus_set_compat_cfg_space() ? (also supporting PCI-X Mode 2 devices)
Improvement : this function can return immediately if the child bus has already inherited the flag from its parent.

Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

[-- Attachment #1: Type: text/plain, Size: 10522 bytes --]

Le 30/04/2018 10:46, Gilles BULOZ a écrit :
> Le 27/04/2018 18:56, Bjorn Helgaas a écrit :
>> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
>>> Le 27/04/2018 10:43, Ard Biesheuvel a écrit :
>>>> (add Bjorn and linux-pci)
>>>>
>>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
>>>>> Dear developers,
>>>>>
>>>>> I currently have two functional workarounds for this issue but
>>>>> would like to know which one you would recommend, if any :-) I'm
>>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
>>>>> external abort" when booting because of a PCI config read during
>>>>> PCI scan.
>>>>>
>>>>> I'm using a custom hardware (based on LS1043ARDB) having a
>>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
>>>>> slot for legacy devices. This bridge only supports PCI-Compatible
>>>>> config accesses (offset 0x00-0xFF).
>> I would guess the PEX8112 itself has 4K of config space, but it only
>> forwards 256 bytes of config space to the conventional PCI secondary
>> bus.
>>
>>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
>>>>> bridge plus PCIe devices behind.
>>>>>
>>>>> The problem occurs when the kernel probes the PCIe devices : as
>>>>> they are PCIe devices, the kernel does a PCI config read access
>>>>> at offset 0x100 to check if "PCIe extended capability registers"
>>>>> are accessible (see drivers/pci/probe.c, function
>>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
>>>>> bridge that is in the path reports an error to the CPU for this
>>>>> access, and it seems there's no way to disable that on this
>>>>> bridge.
>>>>>
>>>>> The first workaround I found was to patch
>>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
>>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
>>>>> error reporting. This only impacts an NXP part of the Linux
>>>>> kernel code, but I'm not sure this is a good idea (however it
>>>>> seems to be like that on Intel platforms where even MEM accesses
>>>>> to a no-device address return FF without any error).
>>>>>
>>>>> I've also tried another workaround that works : patch
>>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
>>>>> behind a bridge without extended address capability, to avoid PCi
>>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
>>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
>>>>> probe method of Linux.
>>>>>
>>>>> Any Idea to properly handle that issue ?
>>>>>
>>>> This seems like a rather unusual configuration, but I guess that
>>>> if the first bridge/switch advertises its inability to support
>>>> extended config space accesses, we should not be performing them
>>>> on any of its subordinate buses. How does the PEX8112 advertise
>>>> this limitation?
>>>>
>>>> That said, I wonder if it is reasonable in the first place to
>>>> expect that a PCIe device works as expected passing through a
>>>> legacy PCI layer like that.
>>>>
>>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
>>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
>>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
>>> support for PCI config offset >=0x100).
>> Sounds right to me.
>>
>>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
>>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
>>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
>>> pci_cfg_space_size())
>> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
>> should be enough, but it shouldn't hurt to check for either
>> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
>>
>>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
>>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
>>> bridge without extended address capability to avoid PCi config
>>> accesses at offset >= 0x100. Thanks to this patch I now have a
>>> functional system with functional PCI/PCIe devices.
>> The patch seems like it's looking at the right things, but I don't
>> want to build it into pci_scan_bridge_extend() because that function
>> is much too complicated already.
>>
>> I'd rather build it into pci_cfg_space_size() or
>> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
>> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
>> that case, I think all 4K would be accessible on the PCI-X side.
>>
>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>> index ac91b6fd0bcd..d8b091f0bcd1 100644
>> --- a/drivers/pci/probe.c
>> +++ b/drivers/pci/probe.c
>> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>    * pci_cfg_space_size - Get the configuration space size of the PCI device
>>    * @dev: PCI device
>>    *
>> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
>> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express devices
>>    * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
>>    * access it.  Maybe we don't have a way to generate extended config space
>>    * accesses, or the device is behind a reverse Express bridge.  So we try
>> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>    */
>>   static int pci_cfg_space_size_ext(struct pci_dev *dev)
>>   {
>> +    struct pci_dev *bridge = pci_upstream_bridge(dev);
>>       u32 status;
>>       int pos = PCI_CFG_SPACE_SIZE;
>>   +    if (bridge && pci_is_pcie(bridge) &&
>> +        pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
>> +        return PCI_CFG_SPACE_SIZE;
>> +
>>       if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
>>           return PCI_CFG_SPACE_SIZE;
>>       if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
>>
>>> --- include/linux/pci.h.orig 2018-03-26 16:51:18.050000000 +0000
>>> +++ include/linux/pci.h    2018-03-26 16:51:27.660000000 +0000
>>> @@ -193,6 +193,7 @@
>>>   enum pci_bus_flags {
>>>       PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>>       PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>>>   };
>>>     /* These values come from the PCI Express Spec */
>>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
>>> +++ drivers/pci/probe.c    2018-03-26 16:54:30.830000000 +0000
>>> @@ -827,6 +827,28 @@
>>>               child->primary = primary;
>>>               pci_bus_insert_busn_res(child, secondary, subordinate);
>>>               child->bridge_ctl = bctl;
>>> +
>>> +            {
>>> +                int pos;
>>> +                u32 status;
>>> +                bool pci_compat_cfg_space = false;
>>> +
>>> +                if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) == 
>>> PCI_EXP_TYPE_PCI_BRIDGE)) {
>>> +                    /* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X 
>>> capabilities */
>>> +                    pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
>>> +                    if (pos) {
>>> +                        pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>>> +                        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>>> +                            pci_compat_cfg_space = true;
>>> +                    } else {
>>> +                        pci_compat_cfg_space = true;
>>> +                    }
>>> +                    if (pci_compat_cfg_space) {
>>> +                        dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor, 
>>> dev->device);
>>> +                        child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>>> +                    }
>>> +                }
>>> +            }
>>>           }
>>>             cmax = pci_scan_child_bus(child);
>>> @@ -1098,6 +1120,11 @@
>>>               goto fail;
>>>       }
>>>   +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
>>> +        dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
>>> +        return PCI_CFG_SPACE_SIZE;
>>> +    }
>>> +
>>>       return pci_cfg_space_size_ext(dev);
>>>      fail:
> Bjorn,
> If I'm right about your proposed patch to pci_cfg_space_size_ext(), *bridge is pointing to the upper device of device *dev being 
> checked. I understand the purpose, but I think this fails for my config that is :
>
> LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector -> PCI-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe 
> devices (one on each port)
>
> because :
> - when pci_cfg_space_size_ext() is run on the 4 PCIe devices, *bridge is the PCIe switch which is not matching 
> PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be checked for the parent bus of the PCIe switch, and so on.
> - when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge, *bridge is the PEX8112 that is also not matching 
> PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads to a config access at offset 0x100 to the PCI-to-PCIe bridge, so 
> a crash (because of the PEX8112)
>
> I think setting a bit in bus_flags when creating a child bus is very efficient because once set it is automatically inherited by 
> all child buses and then the only thing that pci_cfg_space_size() has to do for each device is to check for this bit. Also this 
> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property that is compliant with the purpose of bus_flags.
>
> I agree that pci_scan_bridge_extend() is already too complicated, so would you be okay to only add one line to it :
>   pci_bus_set_compat_cfg_space(child);
> and put all the code I suggested in this new function pci_bus_set_compat_cfg_space() ? (also supporting PCI-X Mode 2 devices)
> Improvement : this function can return immediately if the child bus has already inherited the flag from its parent.
>
I mean something like the attached patch I tested this morning...
Sorry, this is for old kernel 4.1.35 but just to clarify what I propose (also applies to 4.16.6 by changing value of 
PCI_BUS_FLAGS_COMPAT_CFG_SPACE in pci.h to 8).

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: cfgspace2_4.1.35.patch --]
[-- Type: text/x-patch; name=cfgspace2_4.1.35.patch, Size: 2201 bytes --]

--- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
+++ include/linux/pci.h	2018-04-30 09:50:57.660000000 +0000
@@ -193,6 +193,7 @@
 enum pci_bus_flags {
 	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
 	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
+	PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
 };
 
 /* These values come from the PCI Express Spec */
--- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
+++ drivers/pci/probe.c	2018-04-30 13:29:50.600000000 +0000
@@ -754,6 +754,35 @@
 					 PCI_EXP_RTCTL_CRSSVE);
 }
 
+static void pci_bus_check_compat_cfg_space(struct pci_bus *bus)
+{
+	struct pci_dev *dev = bus->self;
+	bool pci_compat_cfg_space = false;
+	int pos;
+	u32 status;
+
+	if (bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
+		return;
+
+	if (!pci_is_pcie(dev) || /* PCI/PCI bridge */
+	    (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
+	    (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/PCI bridge in reverse mode */
+		pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
+		if (pos) {
+			pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
+			if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
+				pci_compat_cfg_space = true;
+		} else {
+			pci_compat_cfg_space = true;
+		}
+		if (pci_compat_cfg_space) {
+			dev_info(&dev->dev, "bus %02x limited to PCI-Compatible config space\n",
+				 bus->number);
+			bus->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
+		}
+	}
+}
+
 /*
  * If it's a bridge, configure it and scan the bus behind it.
  * For CardBus bridges, we don't scan behind as the devices will
@@ -827,6 +856,7 @@
 			child->primary = primary;
 			pci_bus_insert_busn_res(child, secondary, subordinate);
 			child->bridge_ctl = bctl;
+			pci_bus_check_compat_cfg_space(child);
 		}
 
 		cmax = pci_scan_child_bus(child);
@@ -1084,6 +1114,9 @@
 	u32 status;
 	u16 class;
 
+	if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
+		return PCI_CFG_SPACE_SIZE;
+
 	class = dev->class >> 8;
 	if (class == PCI_CLASS_BRIDGE_HOST)
 		return pci_cfg_space_size_ext(dev);

[-- Attachment #3: Type: text/plain, Size: 176 bytes --]

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LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Le 30/04/2018 10:46, Gilles BULOZ a ?crit :
> Le 27/04/2018 18:56, Bjorn Helgaas a ?crit :
>> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
>>> Le 27/04/2018 10:43, Ard Biesheuvel a ?crit :
>>>> (add Bjorn and linux-pci)
>>>>
>>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
>>>>> Dear developers,
>>>>>
>>>>> I currently have two functional workarounds for this issue but
>>>>> would like to know which one you would recommend, if any :-) I'm
>>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
>>>>> external abort" when booting because of a PCI config read during
>>>>> PCI scan.
>>>>>
>>>>> I'm using a custom hardware (based on LS1043ARDB) having a
>>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
>>>>> slot for legacy devices. This bridge only supports PCI-Compatible
>>>>> config accesses (offset 0x00-0xFF).
>> I would guess the PEX8112 itself has 4K of config space, but it only
>> forwards 256 bytes of config space to the conventional PCI secondary
>> bus.
>>
>>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
>>>>> bridge plus PCIe devices behind.
>>>>>
>>>>> The problem occurs when the kernel probes the PCIe devices : as
>>>>> they are PCIe devices, the kernel does a PCI config read access
>>>>> at offset 0x100 to check if "PCIe extended capability registers"
>>>>> are accessible (see drivers/pci/probe.c, function
>>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
>>>>> bridge that is in the path reports an error to the CPU for this
>>>>> access, and it seems there's no way to disable that on this
>>>>> bridge.
>>>>>
>>>>> The first workaround I found was to patch
>>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
>>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
>>>>> error reporting. This only impacts an NXP part of the Linux
>>>>> kernel code, but I'm not sure this is a good idea (however it
>>>>> seems to be like that on Intel platforms where even MEM accesses
>>>>> to a no-device address return FF without any error).
>>>>>
>>>>> I've also tried another workaround that works : patch
>>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
>>>>> behind a bridge without extended address capability, to avoid PCi
>>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
>>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
>>>>> probe method of Linux.
>>>>>
>>>>> Any Idea to properly handle that issue ?
>>>>>
>>>> This seems like a rather unusual configuration, but I guess that
>>>> if the first bridge/switch advertises its inability to support
>>>> extended config space accesses, we should not be performing them
>>>> on any of its subordinate buses. How does the PEX8112 advertise
>>>> this limitation?
>>>>
>>>> That said, I wonder if it is reasonable in the first place to
>>>> expect that a PCIe device works as expected passing through a
>>>> legacy PCI layer like that.
>>>>
>>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
>>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
>>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
>>> support for PCI config offset >=0x100).
>> Sounds right to me.
>>
>>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
>>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
>>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
>>> pci_cfg_space_size())
>> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
>> should be enough, but it shouldn't hurt to check for either
>> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
>>
>>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
>>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
>>> bridge without extended address capability to avoid PCi config
>>> accesses at offset >= 0x100. Thanks to this patch I now have a
>>> functional system with functional PCI/PCIe devices.
>> The patch seems like it's looking at the right things, but I don't
>> want to build it into pci_scan_bridge_extend() because that function
>> is much too complicated already.
>>
>> I'd rather build it into pci_cfg_space_size() or
>> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
>> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
>> that case, I think all 4K would be accessible on the PCI-X side.
>>
>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>> index ac91b6fd0bcd..d8b091f0bcd1 100644
>> --- a/drivers/pci/probe.c
>> +++ b/drivers/pci/probe.c
>> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>    * pci_cfg_space_size - Get the configuration space size of the PCI device
>>    * @dev: PCI device
>>    *
>> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
>> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express devices
>>    * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
>>    * access it.  Maybe we don't have a way to generate extended config space
>>    * accesses, or the device is behind a reverse Express bridge.  So we try
>> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>    */
>>   static int pci_cfg_space_size_ext(struct pci_dev *dev)
>>   {
>> +    struct pci_dev *bridge = pci_upstream_bridge(dev);
>>       u32 status;
>>       int pos = PCI_CFG_SPACE_SIZE;
>>   +    if (bridge && pci_is_pcie(bridge) &&
>> +        pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
>> +        return PCI_CFG_SPACE_SIZE;
>> +
>>       if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
>>           return PCI_CFG_SPACE_SIZE;
>>       if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
>>
>>> --- include/linux/pci.h.orig 2018-03-26 16:51:18.050000000 +0000
>>> +++ include/linux/pci.h    2018-03-26 16:51:27.660000000 +0000
>>> @@ -193,6 +193,7 @@
>>>   enum pci_bus_flags {
>>>       PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>>       PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>>>   };
>>>     /* These values come from the PCI Express Spec */
>>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
>>> +++ drivers/pci/probe.c    2018-03-26 16:54:30.830000000 +0000
>>> @@ -827,6 +827,28 @@
>>>               child->primary = primary;
>>>               pci_bus_insert_busn_res(child, secondary, subordinate);
>>>               child->bridge_ctl = bctl;
>>> +
>>> +            {
>>> +                int pos;
>>> +                u32 status;
>>> +                bool pci_compat_cfg_space = false;
>>> +
>>> +                if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) == 
>>> PCI_EXP_TYPE_PCI_BRIDGE)) {
>>> +                    /* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X 
>>> capabilities */
>>> +                    pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
>>> +                    if (pos) {
>>> +                        pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>>> +                        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>>> +                            pci_compat_cfg_space = true;
>>> +                    } else {
>>> +                        pci_compat_cfg_space = true;
>>> +                    }
>>> +                    if (pci_compat_cfg_space) {
>>> +                        dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor, 
>>> dev->device);
>>> +                        child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>>> +                    }
>>> +                }
>>> +            }
>>>           }
>>>             cmax = pci_scan_child_bus(child);
>>> @@ -1098,6 +1120,11 @@
>>>               goto fail;
>>>       }
>>>   +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
>>> +        dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
>>> +        return PCI_CFG_SPACE_SIZE;
>>> +    }
>>> +
>>>       return pci_cfg_space_size_ext(dev);
>>>      fail:
> Bjorn,
> If I'm right about your proposed patch to pci_cfg_space_size_ext(), *bridge is pointing to the upper device of device *dev being 
> checked. I understand the purpose, but I think this fails for my config that is :
>
> LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector -> PCI-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe 
> devices (one on each port)
>
> because :
> - when pci_cfg_space_size_ext() is run on the 4 PCIe devices, *bridge is the PCIe switch which is not matching 
> PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be checked for the parent bus of the PCIe switch, and so on.
> - when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge, *bridge is the PEX8112 that is also not matching 
> PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads to a config access at offset 0x100 to the PCI-to-PCIe bridge, so 
> a crash (because of the PEX8112)
>
> I think setting a bit in bus_flags when creating a child bus is very efficient because once set it is automatically inherited by 
> all child buses and then the only thing that pci_cfg_space_size() has to do for each device is to check for this bit. Also this 
> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property that is compliant with the purpose of bus_flags.
>
> I agree that pci_scan_bridge_extend() is already too complicated, so would you be okay to only add one line to it :
>   pci_bus_set_compat_cfg_space(child);
> and put all the code I suggested in this new function pci_bus_set_compat_cfg_space() ? (also supporting PCI-X Mode 2 devices)
> Improvement : this function can return immediately if the child bus has already inherited the flag from its parent.
>
I mean something like the attached patch I tested this morning...
Sorry, this is for old kernel 4.1.35 but just to clarify what I propose (also applies to 4.16.6 by changing value of 
PCI_BUS_FLAGS_COMPAT_CFG_SPACE in pci.h to 8).
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Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Bjorn Helgaas]

On Mon, Apr 30, 2018 at 01:36:53PM +0000, Gilles Buloz wrote:
> Le 30/04/2018 10:46, Gilles BULOZ a =E9crit :
> > Le 27/04/2018 18:56, Bjorn Helgaas a =E9crit :
> >> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
> >>> Le 27/04/2018 10:43, Ard Biesheuvel a =E9crit :
> >>>> (add Bjorn and linux-pci)
> >>>>
> >>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> w=
rote:
> >>>>> Dear developers,
> >>>>>
> >>>>> I currently have two functional workarounds for this issue but
> >>>>> would like to know which one you would recommend, if any :-) I'm
> >>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
> >>>>> external abort" when booting because of a PCI config read during
> >>>>> PCI scan.
> >>>>>
> >>>>> I'm using a custom hardware (based on LS1043ARDB) having a
> >>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
> >>>>> slot for legacy devices. This bridge only supports PCI-Compatible
> >>>>> config accesses (offset 0x00-0xFF).
> >> I would guess the PEX8112 itself has 4K of config space, but it only
> >> forwards 256 bytes of config space to the conventional PCI secondary
> >> bus.
> >>
> >>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
> >>>>> bridge plus PCIe devices behind.
> >>>>>
> >>>>> The problem occurs when the kernel probes the PCIe devices : as
> >>>>> they are PCIe devices, the kernel does a PCI config read access
> >>>>> at offset 0x100 to check if "PCIe extended capability registers"
> >>>>> are accessible (see drivers/pci/probe.c, function
> >>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
> >>>>> bridge that is in the path reports an error to the CPU for this
> >>>>> access, and it seems there's no way to disable that on this
> >>>>> bridge.
> >>>>>
> >>>>> The first workaround I found was to patch
> >>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
> >>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
> >>>>> error reporting. This only impacts an NXP part of the Linux
> >>>>> kernel code, but I'm not sure this is a good idea (however it
> >>>>> seems to be like that on Intel platforms where even MEM accesses
> >>>>> to a no-device address return FF without any error).
> >>>>>
> >>>>> I've also tried another workaround that works : patch
> >>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
> >>>>> behind a bridge without extended address capability, to avoid PCi
> >>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
> >>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
> >>>>> probe method of Linux.
> >>>>>
> >>>>> Any Idea to properly handle that issue ?
> >>>>>
> >>>> This seems like a rather unusual configuration, but I guess that
> >>>> if the first bridge/switch advertises its inability to support
> >>>> extended config space accesses, we should not be performing them
> >>>> on any of its subordinate buses. How does the PEX8112 advertise
> >>>> this limitation?
> >>>>
> >>>> That said, I wonder if it is reasonable in the first place to
> >>>> expect that a PCIe device works as expected passing through a
> >>>> legacy PCI layer like that.
> >>>>
> >>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
> >>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
> >>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
> >>> support for PCI config offset >=3D0x100).
> >> Sounds right to me.
> >>
> >>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
> >>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
> >>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
> >>> pci_cfg_space_size())
> >> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266M=
HZ
> >> should be enough, but it shouldn't hurt to check for either
> >> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
> >>
> >>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
> >>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
> >>> bridge without extended address capability to avoid PCi config
> >>> accesses at offset >=3D 0x100. Thanks to this patch I now have a
> >>> functional system with functional PCI/PCIe devices.
> >> The patch seems like it's looking at the right things, but I don't
> >> want to build it into pci_scan_bridge_extend() because that function
> >> is much too complicated already.
> >>
> >> I'd rather build it into pci_cfg_space_size() or
> >> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
> >> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
> >> that case, I think all 4K would be accessible on the PCI-X side.
> >>
> >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> >> index ac91b6fd0bcd..d8b091f0bcd1 100644
> >> --- a/drivers/pci/probe.c
> >> +++ b/drivers/pci/probe.c
> >> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_de=
v *dev)
> >>    * pci_cfg_space_size - Get the configuration space size of the PCI =
device
> >>    * @dev: PCI device
> >>    *
> >> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express de=
vices
> >> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Expre=
ss devices
> >>    * have 4096 bytes.  Even if the device is capable, that doesn't mea=
n we can
> >>    * access it.  Maybe we don't have a way to generate extended config=
 space
> >>    * accesses, or the device is behind a reverse Express bridge.  So w=
e try
> >> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_d=
ev *dev)
> >>    */
> >>   static int pci_cfg_space_size_ext(struct pci_dev *dev)
> >>   {
> >> +    struct pci_dev *bridge =3D pci_upstream_bridge(dev);
> >>       u32 status;
> >>       int pos =3D PCI_CFG_SPACE_SIZE;
> >>   +    if (bridge && pci_is_pcie(bridge) &&
> >> +        pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE)
> >> +        return PCI_CFG_SPACE_SIZE;
> >> +
> >>       if (pci_read_config_dword(dev, pos, &status) !=3D PCIBIOS_SUCCES=
SFUL)
> >>           return PCI_CFG_SPACE_SIZE;
> >>       if (status =3D=3D 0xffffffff || pci_ext_cfg_is_aliased(dev))
> >>
> >>> --- include/linux/pci.h.orig 2018-03-26 16:51:18.050000000 +0000
> >>> +++ include/linux/pci.h    2018-03-26 16:51:27.660000000 +0000
> >>> @@ -193,6 +193,7 @@
> >>>   enum pci_bus_flags {
> >>>       PCI_BUS_FLAGS_NO_MSI   =3D (__force pci_bus_flags_t) 1,
> >>>       PCI_BUS_FLAGS_NO_MMRBC =3D (__force pci_bus_flags_t) 2,
> >>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE =3D (__force pci_bus_flags_t) 4,
> >>>   };
> >>>     /* These values come from the PCI Express Spec */
> >>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
> >>> +++ drivers/pci/probe.c    2018-03-26 16:54:30.830000000 +0000
> >>> @@ -827,6 +827,28 @@
> >>>               child->primary =3D primary;
> >>>               pci_bus_insert_busn_res(child, secondary, subordinate);
> >>>               child->bridge_ctl =3D bctl;
> >>> +
> >>> +            {
> >>> +                int pos;
> >>> +                u32 status;
> >>> +                bool pci_compat_cfg_space =3D false;
> >>> +
> >>> +                if (!pci_is_pcie(dev) || (pci_pcie_type(dev) =3D=3D =
PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) =3D=3D =

> >>> PCI_EXP_TYPE_PCI_BRIDGE)) {
> >>> +                    /* for PCI/PCI bridges, or PCIe/PCI bridge in fo=
rward or reverse mode, we have to check for PCI-X =

> >>> capabilities */
> >>> +                    pos =3D pci_find_capability(dev, PCI_CAP_ID_PCIX=
);
> >>> +                    if (pos) {
> >>> +                        pci_read_config_dword(dev, pos + PCI_X_STATU=
S, &status);
> >>> +                        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_=
STATUS_533MHZ)))
> >>> +                            pci_compat_cfg_space =3D true;
> >>> +                    } else {
> >>> +                        pci_compat_cfg_space =3D true;
> >>> +                    }
> >>> +                    if (pci_compat_cfg_space) {
> >>> +                        dev_info(&dev->dev, "[%04x:%04x] Child bus l=
imited to PCI-Compatible config space\n", dev->vendor, =

> >>> dev->device);
> >>> +                        child->bus_flags |=3D PCI_BUS_FLAGS_COMPAT_C=
FG_SPACE;
> >>> +                    }
> >>> +                }
> >>> +            }
> >>>           }
> >>>             cmax =3D pci_scan_child_bus(child);
> >>> @@ -1098,6 +1120,11 @@
> >>>               goto fail;
> >>>       }
> >>>   +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
> >>> +        dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space=
 only due to parent bus(es)\n", dev->vendor, dev->device);
> >>> +        return PCI_CFG_SPACE_SIZE;
> >>> +    }
> >>> +
> >>>       return pci_cfg_space_size_ext(dev);
> >>>      fail:
> > Bjorn,
> > If I'm right about your proposed patch to
> > pci_cfg_space_size_ext(), *bridge is pointing to the upper device
> > of device *dev being checked. I understand the purpose, but I
> > think this fails for my config that is :
> >
> > LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector ->=
 PCI-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe =

> > devices (one on each port)
> >
> > because :
> > - when pci_cfg_space_size_ext() is run on the 4 PCIe devices,
> > *bridge is the PCIe switch which is not matching
> > PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be
> > checked for the parent bus of the PCIe switch, and so on.
> > - when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge,
> > *bridge is the PEX8112 that is also not matching
> > PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads
> > to a config access at offset 0x100 to the PCI-to-PCIe bridge, so a
> > crash (because of the PEX8112)
> >
> > I think setting a bit in bus_flags when creating a child bus is
> > very efficient because once set it is automatically inherited by
> > all child buses and then the only thing that pci_cfg_space_size()
> > has to do for each device is to check for this bit. Also this
> > PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property
> > that is compliant with the purpose of bus_flags.

Yeah, it needs to be inherited somehow, and I don't like the idea of
traversing up the tree, so I prefer your idea.  Although I don't
actually see the inheritance in the patch below -- I thought there
would be something like this:

  dev =3D bus->self;
  parent_bus =3D dev->bus;
  if (parent_bus && parent_bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
    bus->bus_flags |=3D PCI_BUS_FLAGS_COMPAT_CFG_SPACE;

pci_scan_bridge_extend() calls pci_add_new_bus() from two places.  You
added a call to pci_bus_check_compat_cfg_space() at one of them, and
it's not obvious why we wouldn't need it at the other place, too.

Can you set this up in pci_alloc_child_bus()?  If you can put it
there, it would be clear that every time we allocate a secondary bus,
we figure out whether extended config space is accessible on that bus.

That doesn't cover the root bus case, where we currently assume the
host bridge can generate config accesses to all config space supported
by devices on the root bus.  But we don't have a problem there, so I
guess we don't need to worry about it now.

If you can put it in pci_alloc_child_bus(), could you make your new
function return a boolean, e.g., pci_bus_ext_cfg_accessible(), or
similar, and then use the result to set the
PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag?  Names like "*_check_*()" don't
tell the reader much about what's happening.

> > I agree that pci_scan_bridge_extend() is already too complicated,
> > so would you be okay to only add one line to it :
> >   pci_bus_set_compat_cfg_space(child);
> > and put all the code I suggested in this new function
> > pci_bus_set_compat_cfg_space() ? (also supporting PCI-X Mode 2
> > devices)
> >
> > Improvement : this function can return immediately if the child
> > bus has already inherited the flag from its parent.

> I mean something like the attached patch I tested this morning...
> Sorry, this is for old kernel 4.1.35 but just to clarify what I
> propose (also applies to 4.16.6 by changing value of
> PCI_BUS_FLAGS_COMPAT_CFG_SPACE in pci.h to 8).

> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
> +++ include/linux/pci.h	2018-04-30 09:50:57.660000000 +0000
> @@ -193,6 +193,7 @@
>  enum pci_bus_flags {
>  	PCI_BUS_FLAGS_NO_MSI   =3D (__force pci_bus_flags_t) 1,
>  	PCI_BUS_FLAGS_NO_MMRBC =3D (__force pci_bus_flags_t) 2,
> +	PCI_BUS_FLAGS_COMPAT_CFG_SPACE =3D (__force pci_bus_flags_t) 4,
>  };
>  =

>  /* These values come from the PCI Express Spec */
> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
> +++ drivers/pci/probe.c	2018-04-30 13:29:50.600000000 +0000
> @@ -754,6 +754,35 @@
>  					 PCI_EXP_RTCTL_CRSSVE);
>  }
>  =

> +static void pci_bus_check_compat_cfg_space(struct pci_bus *bus)
> +{
> +	struct pci_dev *dev =3D bus->self;
> +	bool pci_compat_cfg_space =3D false;
> +	int pos;
> +	u32 status;
> +
> +	if (bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
> +		return;
> +
> +	if (!pci_is_pcie(dev) || /* PCI/PCI bridge */
> +	    (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI=
 bridge in forward mode */
> +	    (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/PCI=
 bridge in reverse mode */
> +		pos =3D pci_find_capability(dev, PCI_CAP_ID_PCIX);
> +		if (pos) {
> +			pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
> +			if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
> +				pci_compat_cfg_space =3D true;
> +		} else {
> +			pci_compat_cfg_space =3D true;
> +		}
> +		if (pci_compat_cfg_space) {
> +			dev_info(&dev->dev, "bus %02x limited to PCI-Compatible config space\=
n",
> +				 bus->number);
> +			bus->bus_flags |=3D PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
> +		}
> +	}
> +}
> +
>  /*
>   * If it's a bridge, configure it and scan the bus behind it.
>   * For CardBus bridges, we don't scan behind as the devices will
> @@ -827,6 +856,7 @@
>  			child->primary =3D primary;
>  			pci_bus_insert_busn_res(child, secondary, subordinate);
>  			child->bridge_ctl =3D bctl;
> +			pci_bus_check_compat_cfg_space(child);
>  		}
>  =

>  		cmax =3D pci_scan_child_bus(child);
> @@ -1084,6 +1114,9 @@
>  	u32 status;
>  	u16 class;
>  =

> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
> +		return PCI_CFG_SPACE_SIZE;
> +
>  	class =3D dev->class >> 8;
>  	if (class =3D=3D PCI_CLASS_BRIDGE_HOST)
>  		return pci_cfg_space_size_ext(dev);

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LS1043A : "synchronous abort" at boot due to PCI config read

[Bjorn Helgaas]

On Mon, Apr 30, 2018 at 01:36:53PM +0000, Gilles Buloz wrote:
> Le 30/04/2018 10:46, Gilles BULOZ a ?crit :
> > Le 27/04/2018 18:56, Bjorn Helgaas a ?crit :
> >> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
> >>> Le 27/04/2018 10:43, Ard Biesheuvel a ?crit :
> >>>> (add Bjorn and linux-pci)
> >>>>
> >>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
> >>>>> Dear developers,
> >>>>>
> >>>>> I currently have two functional workarounds for this issue but
> >>>>> would like to know which one you would recommend, if any :-) I'm
> >>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
> >>>>> external abort" when booting because of a PCI config read during
> >>>>> PCI scan.
> >>>>>
> >>>>> I'm using a custom hardware (based on LS1043ARDB) having a
> >>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
> >>>>> slot for legacy devices. This bridge only supports PCI-Compatible
> >>>>> config accesses (offset 0x00-0xFF).
> >> I would guess the PEX8112 itself has 4K of config space, but it only
> >> forwards 256 bytes of config space to the conventional PCI secondary
> >> bus.
> >>
> >>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
> >>>>> bridge plus PCIe devices behind.
> >>>>>
> >>>>> The problem occurs when the kernel probes the PCIe devices : as
> >>>>> they are PCIe devices, the kernel does a PCI config read access
> >>>>> at offset 0x100 to check if "PCIe extended capability registers"
> >>>>> are accessible (see drivers/pci/probe.c, function
> >>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
> >>>>> bridge that is in the path reports an error to the CPU for this
> >>>>> access, and it seems there's no way to disable that on this
> >>>>> bridge.
> >>>>>
> >>>>> The first workaround I found was to patch
> >>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
> >>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
> >>>>> error reporting. This only impacts an NXP part of the Linux
> >>>>> kernel code, but I'm not sure this is a good idea (however it
> >>>>> seems to be like that on Intel platforms where even MEM accesses
> >>>>> to a no-device address return FF without any error).
> >>>>>
> >>>>> I've also tried another workaround that works : patch
> >>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
> >>>>> behind a bridge without extended address capability, to avoid PCi
> >>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
> >>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
> >>>>> probe method of Linux.
> >>>>>
> >>>>> Any Idea to properly handle that issue ?
> >>>>>
> >>>> This seems like a rather unusual configuration, but I guess that
> >>>> if the first bridge/switch advertises its inability to support
> >>>> extended config space accesses, we should not be performing them
> >>>> on any of its subordinate buses. How does the PEX8112 advertise
> >>>> this limitation?
> >>>>
> >>>> That said, I wonder if it is reasonable in the first place to
> >>>> expect that a PCIe device works as expected passing through a
> >>>> legacy PCI layer like that.
> >>>>
> >>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
> >>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
> >>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
> >>> support for PCI config offset >=0x100).
> >> Sounds right to me.
> >>
> >>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
> >>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
> >>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
> >>> pci_cfg_space_size())
> >> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
> >> should be enough, but it shouldn't hurt to check for either
> >> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
> >>
> >>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
> >>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
> >>> bridge without extended address capability to avoid PCi config
> >>> accesses at offset >= 0x100. Thanks to this patch I now have a
> >>> functional system with functional PCI/PCIe devices.
> >> The patch seems like it's looking at the right things, but I don't
> >> want to build it into pci_scan_bridge_extend() because that function
> >> is much too complicated already.
> >>
> >> I'd rather build it into pci_cfg_space_size() or
> >> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
> >> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
> >> that case, I think all 4K would be accessible on the PCI-X side.
> >>
> >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> >> index ac91b6fd0bcd..d8b091f0bcd1 100644
> >> --- a/drivers/pci/probe.c
> >> +++ b/drivers/pci/probe.c
> >> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
> >>    * pci_cfg_space_size - Get the configuration space size of the PCI device
> >>    * @dev: PCI device
> >>    *
> >> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
> >> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express devices
> >>    * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
> >>    * access it.  Maybe we don't have a way to generate extended config space
> >>    * accesses, or the device is behind a reverse Express bridge.  So we try
> >> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
> >>    */
> >>   static int pci_cfg_space_size_ext(struct pci_dev *dev)
> >>   {
> >> +    struct pci_dev *bridge = pci_upstream_bridge(dev);
> >>       u32 status;
> >>       int pos = PCI_CFG_SPACE_SIZE;
> >>   +    if (bridge && pci_is_pcie(bridge) &&
> >> +        pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
> >> +        return PCI_CFG_SPACE_SIZE;
> >> +
> >>       if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
> >>           return PCI_CFG_SPACE_SIZE;
> >>       if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
> >>
> >>> --- include/linux/pci.h.orig 2018-03-26 16:51:18.050000000 +0000
> >>> +++ include/linux/pci.h    2018-03-26 16:51:27.660000000 +0000
> >>> @@ -193,6 +193,7 @@
> >>>   enum pci_bus_flags {
> >>>       PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
> >>>       PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
> >>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
> >>>   };
> >>>     /* These values come from the PCI Express Spec */
> >>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
> >>> +++ drivers/pci/probe.c    2018-03-26 16:54:30.830000000 +0000
> >>> @@ -827,6 +827,28 @@
> >>>               child->primary = primary;
> >>>               pci_bus_insert_busn_res(child, secondary, subordinate);
> >>>               child->bridge_ctl = bctl;
> >>> +
> >>> +            {
> >>> +                int pos;
> >>> +                u32 status;
> >>> +                bool pci_compat_cfg_space = false;
> >>> +
> >>> +                if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) == 
> >>> PCI_EXP_TYPE_PCI_BRIDGE)) {
> >>> +                    /* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X 
> >>> capabilities */
> >>> +                    pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
> >>> +                    if (pos) {
> >>> +                        pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
> >>> +                        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
> >>> +                            pci_compat_cfg_space = true;
> >>> +                    } else {
> >>> +                        pci_compat_cfg_space = true;
> >>> +                    }
> >>> +                    if (pci_compat_cfg_space) {
> >>> +                        dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor, 
> >>> dev->device);
> >>> +                        child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
> >>> +                    }
> >>> +                }
> >>> +            }
> >>>           }
> >>>             cmax = pci_scan_child_bus(child);
> >>> @@ -1098,6 +1120,11 @@
> >>>               goto fail;
> >>>       }
> >>>   +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
> >>> +        dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
> >>> +        return PCI_CFG_SPACE_SIZE;
> >>> +    }
> >>> +
> >>>       return pci_cfg_space_size_ext(dev);
> >>>      fail:
> > Bjorn,
> > If I'm right about your proposed patch to
> > pci_cfg_space_size_ext(), *bridge is pointing to the upper device
> > of device *dev being checked. I understand the purpose, but I
> > think this fails for my config that is :
> >
> > LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector -> PCI-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe 
> > devices (one on each port)
> >
> > because :
> > - when pci_cfg_space_size_ext() is run on the 4 PCIe devices,
> > *bridge is the PCIe switch which is not matching
> > PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be
> > checked for the parent bus of the PCIe switch, and so on.
> > - when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge,
> > *bridge is the PEX8112 that is also not matching
> > PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads
> > to a config access at offset 0x100 to the PCI-to-PCIe bridge, so a
> > crash (because of the PEX8112)
> >
> > I think setting a bit in bus_flags when creating a child bus is
> > very efficient because once set it is automatically inherited by
> > all child buses and then the only thing that pci_cfg_space_size()
> > has to do for each device is to check for this bit. Also this
> > PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property
> > that is compliant with the purpose of bus_flags.

Yeah, it needs to be inherited somehow, and I don't like the idea of
traversing up the tree, so I prefer your idea.  Although I don't
actually see the inheritance in the patch below -- I thought there
would be something like this:

  dev = bus->self;
  parent_bus = dev->bus;
  if (parent_bus && parent_bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
    bus->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;

pci_scan_bridge_extend() calls pci_add_new_bus() from two places.  You
added a call to pci_bus_check_compat_cfg_space() at one of them, and
it's not obvious why we wouldn't need it at the other place, too.

Can you set this up in pci_alloc_child_bus()?  If you can put it
there, it would be clear that every time we allocate a secondary bus,
we figure out whether extended config space is accessible on that bus.

That doesn't cover the root bus case, where we currently assume the
host bridge can generate config accesses to all config space supported
by devices on the root bus.  But we don't have a problem there, so I
guess we don't need to worry about it now.

If you can put it in pci_alloc_child_bus(), could you make your new
function return a boolean, e.g., pci_bus_ext_cfg_accessible(), or
similar, and then use the result to set the
PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag?  Names like "*_check_*()" don't
tell the reader much about what's happening.

> > I agree that pci_scan_bridge_extend() is already too complicated,
> > so would you be okay to only add one line to it :
> >   pci_bus_set_compat_cfg_space(child);
> > and put all the code I suggested in this new function
> > pci_bus_set_compat_cfg_space() ? (also supporting PCI-X Mode 2
> > devices)
> >
> > Improvement : this function can return immediately if the child
> > bus has already inherited the flag from its parent.

> I mean something like the attached patch I tested this morning...
> Sorry, this is for old kernel 4.1.35 but just to clarify what I
> propose (also applies to 4.16.6 by changing value of
> PCI_BUS_FLAGS_COMPAT_CFG_SPACE in pci.h to 8).

> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
> +++ include/linux/pci.h	2018-04-30 09:50:57.660000000 +0000
> @@ -193,6 +193,7 @@
>  enum pci_bus_flags {
>  	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>  	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
> +	PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>  };
>  
>  /* These values come from the PCI Express Spec */
> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
> +++ drivers/pci/probe.c	2018-04-30 13:29:50.600000000 +0000
> @@ -754,6 +754,35 @@
>  					 PCI_EXP_RTCTL_CRSSVE);
>  }
>  
> +static void pci_bus_check_compat_cfg_space(struct pci_bus *bus)
> +{
> +	struct pci_dev *dev = bus->self;
> +	bool pci_compat_cfg_space = false;
> +	int pos;
> +	u32 status;
> +
> +	if (bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
> +		return;
> +
> +	if (!pci_is_pcie(dev) || /* PCI/PCI bridge */
> +	    (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
> +	    (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/PCI bridge in reverse mode */
> +		pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
> +		if (pos) {
> +			pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
> +			if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
> +				pci_compat_cfg_space = true;
> +		} else {
> +			pci_compat_cfg_space = true;
> +		}
> +		if (pci_compat_cfg_space) {
> +			dev_info(&dev->dev, "bus %02x limited to PCI-Compatible config space\n",
> +				 bus->number);
> +			bus->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
> +		}
> +	}
> +}
> +
>  /*
>   * If it's a bridge, configure it and scan the bus behind it.
>   * For CardBus bridges, we don't scan behind as the devices will
> @@ -827,6 +856,7 @@
>  			child->primary = primary;
>  			pci_bus_insert_busn_res(child, secondary, subordinate);
>  			child->bridge_ctl = bctl;
> +			pci_bus_check_compat_cfg_space(child);
>  		}
>  
>  		cmax = pci_scan_child_bus(child);
> @@ -1084,6 +1114,9 @@
>  	u32 status;
>  	u16 class;
>  
> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
> +		return PCI_CFG_SPACE_SIZE;
> +
>  	class = dev->class >> 8;
>  	if (class == PCI_CLASS_BRIDGE_HOST)
>  		return pci_cfg_space_size_ext(dev);

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Le 30/04/2018 19:04, Bjorn Helgaas a =E9crit :
> On Mon, Apr 30, 2018 at 01:36:53PM +0000, Gilles Buloz wrote:
>> Le 30/04/2018 10:46, Gilles BULOZ a =E9crit :
>>> Le 27/04/2018 18:56, Bjorn Helgaas a =E9crit :
>>>> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
>>>>> Le 27/04/2018 10:43, Ard Biesheuvel a =E9crit :
>>>>>> (add Bjorn and linux-pci)
>>>>>>
>>>>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> w=
rote:
>>>>>>> Dear developers,
>>>>>>>
>>>>>>> I currently have two functional workarounds for this issue but
>>>>>>> would like to know which one you would recommend, if any :-) I'm
>>>>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
>>>>>>> external abort" when booting because of a PCI config read during
>>>>>>> PCI scan.
>>>>>>>
>>>>>>> I'm using a custom hardware (based on LS1043ARDB) having a
>>>>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
>>>>>>> slot for legacy devices. This bridge only supports PCI-Compatible
>>>>>>> config accesses (offset 0x00-0xFF).
>>>> I would guess the PEX8112 itself has 4K of config space, but it only
>>>> forwards 256 bytes of config space to the conventional PCI secondary
>>>> bus.
>>>>
>>>>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
>>>>>>> bridge plus PCIe devices behind.
>>>>>>>
>>>>>>> The problem occurs when the kernel probes the PCIe devices : as
>>>>>>> they are PCIe devices, the kernel does a PCI config read access
>>>>>>> at offset 0x100 to check if "PCIe extended capability registers"
>>>>>>> are accessible (see drivers/pci/probe.c, function
>>>>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
>>>>>>> bridge that is in the path reports an error to the CPU for this
>>>>>>> access, and it seems there's no way to disable that on this
>>>>>>> bridge.
>>>>>>>
>>>>>>> The first workaround I found was to patch
>>>>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
>>>>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
>>>>>>> error reporting. This only impacts an NXP part of the Linux
>>>>>>> kernel code, but I'm not sure this is a good idea (however it
>>>>>>> seems to be like that on Intel platforms where even MEM accesses
>>>>>>> to a no-device address return FF without any error).
>>>>>>>
>>>>>>> I've also tried another workaround that works : patch
>>>>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
>>>>>>> behind a bridge without extended address capability, to avoid PCi
>>>>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
>>>>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
>>>>>>> probe method of Linux.
>>>>>>>
>>>>>>> Any Idea to properly handle that issue ?
>>>>>>>
>>>>>> This seems like a rather unusual configuration, but I guess that
>>>>>> if the first bridge/switch advertises its inability to support
>>>>>> extended config space accesses, we should not be performing them
>>>>>> on any of its subordinate buses. How does the PEX8112 advertise
>>>>>> this limitation?
>>>>>>
>>>>>> That said, I wonder if it is reasonable in the first place to
>>>>>> expect that a PCIe device works as expected passing through a
>>>>>> legacy PCI layer like that.
>>>>>>
>>>>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
>>>>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
>>>>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
>>>>> support for PCI config offset >=3D0x100).
>>>> Sounds right to me.
>>>>
>>>>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
>>>>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
>>>>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
>>>>> pci_cfg_space_size())
>>>> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266M=
HZ
>>>> should be enough, but it shouldn't hurt to check for either
>>>> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
>>>>
>>>>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
>>>>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
>>>>> bridge without extended address capability to avoid PCi config
>>>>> accesses at offset >=3D 0x100. Thanks to this patch I now have a
>>>>> functional system with functional PCI/PCIe devices.
>>>> The patch seems like it's looking at the right things, but I don't
>>>> want to build it into pci_scan_bridge_extend() because that function
>>>> is much too complicated already.
>>>>
>>>> I'd rather build it into pci_cfg_space_size() or
>>>> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
>>>> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
>>>> that case, I think all 4K would be accessible on the PCI-X side.
>>>>
>>>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>>>> index ac91b6fd0bcd..d8b091f0bcd1 100644
>>>> --- a/drivers/pci/probe.c
>>>> +++ b/drivers/pci/probe.c
>>>> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_de=
v *dev)
>>>>     * pci_cfg_space_size - Get the configuration space size of the PCI=
 device
>>>>     * @dev: PCI device
>>>>     *
>>>> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express de=
vices
>>>> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Expre=
ss devices
>>>>     * have 4096 bytes.  Even if the device is capable, that doesn't me=
an we can
>>>>     * access it.  Maybe we don't have a way to generate extended confi=
g space
>>>>     * accesses, or the device is behind a reverse Express bridge.  So =
we try
>>>> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_d=
ev *dev)
>>>>     */
>>>>    static int pci_cfg_space_size_ext(struct pci_dev *dev)
>>>>    {
>>>> +    struct pci_dev *bridge =3D pci_upstream_bridge(dev);
>>>>        u32 status;
>>>>        int pos =3D PCI_CFG_SPACE_SIZE;
>>>>    +    if (bridge && pci_is_pcie(bridge) &&
>>>> +        pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE)
>>>> +        return PCI_CFG_SPACE_SIZE;
>>>> +
>>>>        if (pci_read_config_dword(dev, pos, &status) !=3D PCIBIOS_SUCCE=
SSFUL)
>>>>            return PCI_CFG_SPACE_SIZE;
>>>>        if (status =3D=3D 0xffffffff || pci_ext_cfg_is_aliased(dev))
>>>>
>>>>> --- include/linux/pci.h.orig 2018-03-26 16:51:18.050000000 +0000
>>>>> +++ include/linux/pci.h    2018-03-26 16:51:27.660000000 +0000
>>>>> @@ -193,6 +193,7 @@
>>>>>    enum pci_bus_flags {
>>>>>        PCI_BUS_FLAGS_NO_MSI   =3D (__force pci_bus_flags_t) 1,
>>>>>        PCI_BUS_FLAGS_NO_MMRBC =3D (__force pci_bus_flags_t) 2,
>>>>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE =3D (__force pci_bus_flags_t) 4,
>>>>>    };
>>>>>      /* These values come from the PCI Express Spec */
>>>>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
>>>>> +++ drivers/pci/probe.c    2018-03-26 16:54:30.830000000 +0000
>>>>> @@ -827,6 +827,28 @@
>>>>>                child->primary =3D primary;
>>>>>                pci_bus_insert_busn_res(child, secondary, subordinate)=
;
>>>>>                child->bridge_ctl =3D bctl;
>>>>> +
>>>>> +            {
>>>>> +                int pos;
>>>>> +                u32 status;
>>>>> +                bool pci_compat_cfg_space =3D false;
>>>>> +
>>>>> +                if (!pci_is_pcie(dev) || (pci_pcie_type(dev) =3D=3D =
PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) =3D=3D
>>>>> PCI_EXP_TYPE_PCI_BRIDGE)) {
>>>>> +                    /* for PCI/PCI bridges, or PCIe/PCI bridge in fo=
rward or reverse mode, we have to check for PCI-X
>>>>> capabilities */
>>>>> +                    pos =3D pci_find_capability(dev, PCI_CAP_ID_PCIX=
);
>>>>> +                    if (pos) {
>>>>> +                        pci_read_config_dword(dev, pos + PCI_X_STATU=
S, &status);
>>>>> +                        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_=
STATUS_533MHZ)))
>>>>> +                            pci_compat_cfg_space =3D true;
>>>>> +                    } else {
>>>>> +                        pci_compat_cfg_space =3D true;
>>>>> +                    }
>>>>> +                    if (pci_compat_cfg_space) {
>>>>> +                        dev_info(&dev->dev, "[%04x:%04x] Child bus l=
imited to PCI-Compatible config space\n", dev->vendor,
>>>>> dev->device);
>>>>> +                        child->bus_flags |=3D PCI_BUS_FLAGS_COMPAT_C=
FG_SPACE;
>>>>> +                    }
>>>>> +                }
>>>>> +            }
>>>>>            }
>>>>>              cmax =3D pci_scan_child_bus(child);
>>>>> @@ -1098,6 +1120,11 @@
>>>>>                goto fail;
>>>>>        }
>>>>>    +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
>>>>> +        dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space=
 only due to parent bus(es)\n", dev->vendor, dev->device);
>>>>> +        return PCI_CFG_SPACE_SIZE;
>>>>> +    }
>>>>> +
>>>>>        return pci_cfg_space_size_ext(dev);
>>>>>       fail:
>>> Bjorn,
>>> If I'm right about your proposed patch to
>>> pci_cfg_space_size_ext(), *bridge is pointing to the upper device
>>> of device *dev being checked. I understand the purpose, but I
>>> think this fails for my config that is :
>>>
>>> LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector ->=
 PCI-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe
>>> devices (one on each port)
>>>
>>> because :
>>> - when pci_cfg_space_size_ext() is run on the 4 PCIe devices,
>>> *bridge is the PCIe switch which is not matching
>>> PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be
>>> checked for the parent bus of the PCIe switch, and so on.
>>> - when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge,
>>> *bridge is the PEX8112 that is also not matching
>>> PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads
>>> to a config access at offset 0x100 to the PCI-to-PCIe bridge, so a
>>> crash (because of the PEX8112)
>>>
>>> I think setting a bit in bus_flags when creating a child bus is
>>> very efficient because once set it is automatically inherited by
>>> all child buses and then the only thing that pci_cfg_space_size()
>>> has to do for each device is to check for this bit. Also this
>>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property
>>> that is compliant with the purpose of bus_flags.
> Yeah, it needs to be inherited somehow, and I don't like the idea of
> traversing up the tree, so I prefer your idea.  Although I don't
> actually see the inheritance in the patch below -- I thought there
> would be something like this:
>
>    dev =3D bus->self;
>    parent_bus =3D dev->bus;
>    if (parent_bus && parent_bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPA=
CE)
>      bus->bus_flags |=3D PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>
> pci_scan_bridge_extend() calls pci_add_new_bus() from two places.  You
> added a call to pci_bus_check_compat_cfg_space() at one of them, and
> it's not obvious why we wouldn't need it at the other place, too.
>
> Can you set this up in pci_alloc_child_bus()?  If you can put it
> there, it would be clear that every time we allocate a secondary bus,
> we figure out whether extended config space is accessible on that bus.
>
> That doesn't cover the root bus case, where we currently assume the
> host bridge can generate config accesses to all config space supported
> by devices on the root bus.  But we don't have a problem there, so I
> guess we don't need to worry about it now.
>
> If you can put it in pci_alloc_child_bus(), could you make your new
> function return a boolean, e.g., pci_bus_ext_cfg_accessible(), or
> similar, and then use the result to set the
> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag?  Names like "*_check_*()" don't
> tell the reader much about what's happening.
>
>>> I agree that pci_scan_bridge_extend() is already too complicated,
>>> so would you be okay to only add one line to it :
>>>    pci_bus_set_compat_cfg_space(child);
>>> and put all the code I suggested in this new function
>>> pci_bus_set_compat_cfg_space() ? (also supporting PCI-X Mode 2
>>> devices)
>>>
>>> Improvement : this function can return immediately if the child
>>> bus has already inherited the flag from its parent.
>> I mean something like the attached patch I tested this morning...
>> Sorry, this is for old kernel 4.1.35 but just to clarify what I
>> propose (also applies to 4.16.6 by changing value of
>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE in pci.h to 8).
>> --- include/linux/pci.h.orig=092018-03-26 16:51:18.050000000 +0000
>> +++ include/linux/pci.h=092018-04-30 09:50:57.660000000 +0000
>> @@ -193,6 +193,7 @@
>>   enum pci_bus_flags {
>>   =09PCI_BUS_FLAGS_NO_MSI   =3D (__force pci_bus_flags_t) 1,
>>   =09PCI_BUS_FLAGS_NO_MMRBC =3D (__force pci_bus_flags_t) 2,
>> +=09PCI_BUS_FLAGS_COMPAT_CFG_SPACE =3D (__force pci_bus_flags_t) 4,
>>   };
>>  =20
>>   /* These values come from the PCI Express Spec */
>> --- drivers/pci/probe.c.orig=092018-01-22 09:29:52.000000000 +0000
>> +++ drivers/pci/probe.c=092018-04-30 13:29:50.600000000 +0000
>> @@ -754,6 +754,35 @@
>>   =09=09=09=09=09 PCI_EXP_RTCTL_CRSSVE);
>>   }
>>  =20
>> +static void pci_bus_check_compat_cfg_space(struct pci_bus *bus)
>> +{
>> +=09struct pci_dev *dev =3D bus->self;
>> +=09bool pci_compat_cfg_space =3D false;
>> +=09int pos;
>> +=09u32 status;
>> +
>> +=09if (bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>> +=09=09return;
>> +
>> +=09if (!pci_is_pcie(dev) || /* PCI/PCI bridge */
>> +=09    (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/=
PCI bridge in forward mode */
>> +=09    (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/=
PCI bridge in reverse mode */
>> +=09=09pos =3D pci_find_capability(dev, PCI_CAP_ID_PCIX);
>> +=09=09if (pos) {
>> +=09=09=09pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>> +=09=09=09if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>> +=09=09=09=09pci_compat_cfg_space =3D true;
>> +=09=09} else {
>> +=09=09=09pci_compat_cfg_space =3D true;
>> +=09=09}
>> +=09=09if (pci_compat_cfg_space) {
>> +=09=09=09dev_info(&dev->dev, "bus %02x limited to PCI-Compatible config=
 space\n",
>> +=09=09=09=09 bus->number);
>> +=09=09=09bus->bus_flags |=3D PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>> +=09=09}
>> +=09}
>> +}
>> +
>>   /*
>>    * If it's a bridge, configure it and scan the bus behind it.
>>    * For CardBus bridges, we don't scan behind as the devices will
>> @@ -827,6 +856,7 @@
>>   =09=09=09child->primary =3D primary;
>>   =09=09=09pci_bus_insert_busn_res(child, secondary, subordinate);
>>   =09=09=09child->bridge_ctl =3D bctl;
>> +=09=09=09pci_bus_check_compat_cfg_space(child);
>>   =09=09}
>>  =20
>>   =09=09cmax =3D pci_scan_child_bus(child);
>> @@ -1084,6 +1114,9 @@
>>   =09u32 status;
>>   =09u16 class;
>>  =20
>> +=09if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>> +=09=09return PCI_CFG_SPACE_SIZE;
>> +
>>   =09class =3D dev->class >> 8;
>>   =09if (class =3D=3D PCI_CLASS_BRIDGE_HOST)
>>   =09=09return pci_cfg_space_size_ext(dev);
>
The inheritence is made by this line in pci_alloc_child_bus() :
     child->bus_flags =3D parent->bus_flags;
So once we detect a limitation on a bridge impacting a child bus and that w=
e set the flag in child->bus_flags, this flag is=20
automatically present in the child->bus_flags of all its children buses.

I agree with your remarks and will create a function named pci_bus_check_co=
mpat_cfg_space() that will be called from=20
pci_alloc_child_bus().
I'll test that on Wednesday 2th and will give you my feedback.

LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Le 30/04/2018 19:04, Bjorn Helgaas a ?crit :
> On Mon, Apr 30, 2018 at 01:36:53PM +0000, Gilles Buloz wrote:
>> Le 30/04/2018 10:46, Gilles BULOZ a ?crit :
>>> Le 27/04/2018 18:56, Bjorn Helgaas a ?crit :
>>>> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
>>>>> Le 27/04/2018 10:43, Ard Biesheuvel a ?crit :
>>>>>> (add Bjorn and linux-pci)
>>>>>>
>>>>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
>>>>>>> Dear developers,
>>>>>>>
>>>>>>> I currently have two functional workarounds for this issue but
>>>>>>> would like to know which one you would recommend, if any :-) I'm
>>>>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
>>>>>>> external abort" when booting because of a PCI config read during
>>>>>>> PCI scan.
>>>>>>>
>>>>>>> I'm using a custom hardware (based on LS1043ARDB) having a
>>>>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
>>>>>>> slot for legacy devices. This bridge only supports PCI-Compatible
>>>>>>> config accesses (offset 0x00-0xFF).
>>>> I would guess the PEX8112 itself has 4K of config space, but it only
>>>> forwards 256 bytes of config space to the conventional PCI secondary
>>>> bus.
>>>>
>>>>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
>>>>>>> bridge plus PCIe devices behind.
>>>>>>>
>>>>>>> The problem occurs when the kernel probes the PCIe devices : as
>>>>>>> they are PCIe devices, the kernel does a PCI config read access
>>>>>>> at offset 0x100 to check if "PCIe extended capability registers"
>>>>>>> are accessible (see drivers/pci/probe.c, function
>>>>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
>>>>>>> bridge that is in the path reports an error to the CPU for this
>>>>>>> access, and it seems there's no way to disable that on this
>>>>>>> bridge.
>>>>>>>
>>>>>>> The first workaround I found was to patch
>>>>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
>>>>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
>>>>>>> error reporting. This only impacts an NXP part of the Linux
>>>>>>> kernel code, but I'm not sure this is a good idea (however it
>>>>>>> seems to be like that on Intel platforms where even MEM accesses
>>>>>>> to a no-device address return FF without any error).
>>>>>>>
>>>>>>> I've also tried another workaround that works : patch
>>>>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
>>>>>>> behind a bridge without extended address capability, to avoid PCi
>>>>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
>>>>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
>>>>>>> probe method of Linux.
>>>>>>>
>>>>>>> Any Idea to properly handle that issue ?
>>>>>>>
>>>>>> This seems like a rather unusual configuration, but I guess that
>>>>>> if the first bridge/switch advertises its inability to support
>>>>>> extended config space accesses, we should not be performing them
>>>>>> on any of its subordinate buses. How does the PEX8112 advertise
>>>>>> this limitation?
>>>>>>
>>>>>> That said, I wonder if it is reasonable in the first place to
>>>>>> expect that a PCIe device works as expected passing through a
>>>>>> legacy PCI layer like that.
>>>>>>
>>>>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
>>>>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
>>>>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
>>>>> support for PCI config offset >=0x100).
>>>> Sounds right to me.
>>>>
>>>>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
>>>>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
>>>>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
>>>>> pci_cfg_space_size())
>>>> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
>>>> should be enough, but it shouldn't hurt to check for either
>>>> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
>>>>
>>>>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
>>>>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
>>>>> bridge without extended address capability to avoid PCi config
>>>>> accesses at offset >= 0x100. Thanks to this patch I now have a
>>>>> functional system with functional PCI/PCIe devices.
>>>> The patch seems like it's looking at the right things, but I don't
>>>> want to build it into pci_scan_bridge_extend() because that function
>>>> is much too complicated already.
>>>>
>>>> I'd rather build it into pci_cfg_space_size() or
>>>> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
>>>> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
>>>> that case, I think all 4K would be accessible on the PCI-X side.
>>>>
>>>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>>>> index ac91b6fd0bcd..d8b091f0bcd1 100644
>>>> --- a/drivers/pci/probe.c
>>>> +++ b/drivers/pci/probe.c
>>>> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>>>     * pci_cfg_space_size - Get the configuration space size of the PCI device
>>>>     * @dev: PCI device
>>>>     *
>>>> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
>>>> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express devices
>>>>     * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
>>>>     * access it.  Maybe we don't have a way to generate extended config space
>>>>     * accesses, or the device is behind a reverse Express bridge.  So we try
>>>> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>>>     */
>>>>    static int pci_cfg_space_size_ext(struct pci_dev *dev)
>>>>    {
>>>> +    struct pci_dev *bridge = pci_upstream_bridge(dev);
>>>>        u32 status;
>>>>        int pos = PCI_CFG_SPACE_SIZE;
>>>>    +    if (bridge && pci_is_pcie(bridge) &&
>>>> +        pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
>>>> +        return PCI_CFG_SPACE_SIZE;
>>>> +
>>>>        if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
>>>>            return PCI_CFG_SPACE_SIZE;
>>>>        if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
>>>>
>>>>> --- include/linux/pci.h.orig 2018-03-26 16:51:18.050000000 +0000
>>>>> +++ include/linux/pci.h    2018-03-26 16:51:27.660000000 +0000
>>>>> @@ -193,6 +193,7 @@
>>>>>    enum pci_bus_flags {
>>>>>        PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>>>>        PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>>>>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>>>>>    };
>>>>>      /* These values come from the PCI Express Spec */
>>>>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
>>>>> +++ drivers/pci/probe.c    2018-03-26 16:54:30.830000000 +0000
>>>>> @@ -827,6 +827,28 @@
>>>>>                child->primary = primary;
>>>>>                pci_bus_insert_busn_res(child, secondary, subordinate);
>>>>>                child->bridge_ctl = bctl;
>>>>> +
>>>>> +            {
>>>>> +                int pos;
>>>>> +                u32 status;
>>>>> +                bool pci_compat_cfg_space = false;
>>>>> +
>>>>> +                if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) ==
>>>>> PCI_EXP_TYPE_PCI_BRIDGE)) {
>>>>> +                    /* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X
>>>>> capabilities */
>>>>> +                    pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
>>>>> +                    if (pos) {
>>>>> +                        pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>>>>> +                        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>>>>> +                            pci_compat_cfg_space = true;
>>>>> +                    } else {
>>>>> +                        pci_compat_cfg_space = true;
>>>>> +                    }
>>>>> +                    if (pci_compat_cfg_space) {
>>>>> +                        dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor,
>>>>> dev->device);
>>>>> +                        child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>>>>> +                    }
>>>>> +                }
>>>>> +            }
>>>>>            }
>>>>>              cmax = pci_scan_child_bus(child);
>>>>> @@ -1098,6 +1120,11 @@
>>>>>                goto fail;
>>>>>        }
>>>>>    +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
>>>>> +        dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
>>>>> +        return PCI_CFG_SPACE_SIZE;
>>>>> +    }
>>>>> +
>>>>>        return pci_cfg_space_size_ext(dev);
>>>>>       fail:
>>> Bjorn,
>>> If I'm right about your proposed patch to
>>> pci_cfg_space_size_ext(), *bridge is pointing to the upper device
>>> of device *dev being checked. I understand the purpose, but I
>>> think this fails for my config that is :
>>>
>>> LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector -> PCI-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe
>>> devices (one on each port)
>>>
>>> because :
>>> - when pci_cfg_space_size_ext() is run on the 4 PCIe devices,
>>> *bridge is the PCIe switch which is not matching
>>> PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be
>>> checked for the parent bus of the PCIe switch, and so on.
>>> - when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge,
>>> *bridge is the PEX8112 that is also not matching
>>> PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads
>>> to a config access at offset 0x100 to the PCI-to-PCIe bridge, so a
>>> crash (because of the PEX8112)
>>>
>>> I think setting a bit in bus_flags when creating a child bus is
>>> very efficient because once set it is automatically inherited by
>>> all child buses and then the only thing that pci_cfg_space_size()
>>> has to do for each device is to check for this bit. Also this
>>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property
>>> that is compliant with the purpose of bus_flags.
> Yeah, it needs to be inherited somehow, and I don't like the idea of
> traversing up the tree, so I prefer your idea.  Although I don't
> actually see the inheritance in the patch below -- I thought there
> would be something like this:
>
>    dev = bus->self;
>    parent_bus = dev->bus;
>    if (parent_bus && parent_bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>      bus->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>
> pci_scan_bridge_extend() calls pci_add_new_bus() from two places.  You
> added a call to pci_bus_check_compat_cfg_space() at one of them, and
> it's not obvious why we wouldn't need it at the other place, too.
>
> Can you set this up in pci_alloc_child_bus()?  If you can put it
> there, it would be clear that every time we allocate a secondary bus,
> we figure out whether extended config space is accessible on that bus.
>
> That doesn't cover the root bus case, where we currently assume the
> host bridge can generate config accesses to all config space supported
> by devices on the root bus.  But we don't have a problem there, so I
> guess we don't need to worry about it now.
>
> If you can put it in pci_alloc_child_bus(), could you make your new
> function return a boolean, e.g., pci_bus_ext_cfg_accessible(), or
> similar, and then use the result to set the
> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag?  Names like "*_check_*()" don't
> tell the reader much about what's happening.
>
>>> I agree that pci_scan_bridge_extend() is already too complicated,
>>> so would you be okay to only add one line to it :
>>>    pci_bus_set_compat_cfg_space(child);
>>> and put all the code I suggested in this new function
>>> pci_bus_set_compat_cfg_space() ? (also supporting PCI-X Mode 2
>>> devices)
>>>
>>> Improvement : this function can return immediately if the child
>>> bus has already inherited the flag from its parent.
>> I mean something like the attached patch I tested this morning...
>> Sorry, this is for old kernel 4.1.35 but just to clarify what I
>> propose (also applies to 4.16.6 by changing value of
>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE in pci.h to 8).
>> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
>> +++ include/linux/pci.h	2018-04-30 09:50:57.660000000 +0000
>> @@ -193,6 +193,7 @@
>>   enum pci_bus_flags {
>>   	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>   	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>> +	PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>>   };
>>   
>>   /* These values come from the PCI Express Spec */
>> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
>> +++ drivers/pci/probe.c	2018-04-30 13:29:50.600000000 +0000
>> @@ -754,6 +754,35 @@
>>   					 PCI_EXP_RTCTL_CRSSVE);
>>   }
>>   
>> +static void pci_bus_check_compat_cfg_space(struct pci_bus *bus)
>> +{
>> +	struct pci_dev *dev = bus->self;
>> +	bool pci_compat_cfg_space = false;
>> +	int pos;
>> +	u32 status;
>> +
>> +	if (bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>> +		return;
>> +
>> +	if (!pci_is_pcie(dev) || /* PCI/PCI bridge */
>> +	    (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
>> +	    (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/PCI bridge in reverse mode */
>> +		pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
>> +		if (pos) {
>> +			pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>> +			if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>> +				pci_compat_cfg_space = true;
>> +		} else {
>> +			pci_compat_cfg_space = true;
>> +		}
>> +		if (pci_compat_cfg_space) {
>> +			dev_info(&dev->dev, "bus %02x limited to PCI-Compatible config space\n",
>> +				 bus->number);
>> +			bus->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>> +		}
>> +	}
>> +}
>> +
>>   /*
>>    * If it's a bridge, configure it and scan the bus behind it.
>>    * For CardBus bridges, we don't scan behind as the devices will
>> @@ -827,6 +856,7 @@
>>   			child->primary = primary;
>>   			pci_bus_insert_busn_res(child, secondary, subordinate);
>>   			child->bridge_ctl = bctl;
>> +			pci_bus_check_compat_cfg_space(child);
>>   		}
>>   
>>   		cmax = pci_scan_child_bus(child);
>> @@ -1084,6 +1114,9 @@
>>   	u32 status;
>>   	u16 class;
>>   
>> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>> +		return PCI_CFG_SPACE_SIZE;
>> +
>>   	class = dev->class >> 8;
>>   	if (class == PCI_CLASS_BRIDGE_HOST)
>>   		return pci_cfg_space_size_ext(dev);
>
The inheritence is made by this line in pci_alloc_child_bus() :
     child->bus_flags = parent->bus_flags;
So once we detect a limitation on a bridge impacting a child bus and that we set the flag in child->bus_flags, this flag is 
automatically present in the child->bus_flags of all its children buses.

I agree with your remarks and will create a function named pci_bus_check_compat_cfg_space() that will be called from 
pci_alloc_child_bus().
I'll test that on Wednesday 2th and will give you my feedback.

Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

[-- Attachment #1: Type: text/plain, Size: 16155 bytes --]

Le 30/04/2018 19:53, Gilles BULOZ a écrit :
> Le 30/04/2018 19:04, Bjorn Helgaas a écrit :
>> On Mon, Apr 30, 2018 at 01:36:53PM +0000, Gilles Buloz wrote:
>>> Le 30/04/2018 10:46, Gilles BULOZ a écrit :
>>>> Le 27/04/2018 18:56, Bjorn Helgaas a écrit :
>>>>> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
>>>>>> Le 27/04/2018 10:43, Ard Biesheuvel a écrit :
>>>>>>> (add Bjorn and linux-pci)
>>>>>>>
>>>>>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
>>>>>>>> Dear developers,
>>>>>>>>
>>>>>>>> I currently have two functional workarounds for this issue but
>>>>>>>> would like to know which one you would recommend, if any :-) I'm
>>>>>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
>>>>>>>> external abort" when booting because of a PCI config read during
>>>>>>>> PCI scan.
>>>>>>>>
>>>>>>>> I'm using a custom hardware (based on LS1043ARDB) having a
>>>>>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
>>>>>>>> slot for legacy devices. This bridge only supports PCI-Compatible
>>>>>>>> config accesses (offset 0x00-0xFF).
>>>>> I would guess the PEX8112 itself has 4K of config space, but it only
>>>>> forwards 256 bytes of config space to the conventional PCI secondary
>>>>> bus.
>>>>>
>>>>>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
>>>>>>>> bridge plus PCIe devices behind.
>>>>>>>>
>>>>>>>> The problem occurs when the kernel probes the PCIe devices : as
>>>>>>>> they are PCIe devices, the kernel does a PCI config read access
>>>>>>>> at offset 0x100 to check if "PCIe extended capability registers"
>>>>>>>> are accessible (see drivers/pci/probe.c, function
>>>>>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
>>>>>>>> bridge that is in the path reports an error to the CPU for this
>>>>>>>> access, and it seems there's no way to disable that on this
>>>>>>>> bridge.
>>>>>>>>
>>>>>>>> The first workaround I found was to patch
>>>>>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
>>>>>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
>>>>>>>> error reporting. This only impacts an NXP part of the Linux
>>>>>>>> kernel code, but I'm not sure this is a good idea (however it
>>>>>>>> seems to be like that on Intel platforms where even MEM accesses
>>>>>>>> to a no-device address return FF without any error).
>>>>>>>>
>>>>>>>> I've also tried another workaround that works : patch
>>>>>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
>>>>>>>> behind a bridge without extended address capability, to avoid PCi
>>>>>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
>>>>>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
>>>>>>>> probe method of Linux.
>>>>>>>>
>>>>>>>> Any Idea to properly handle that issue ?
>>>>>>>>
>>>>>>> This seems like a rather unusual configuration, but I guess that
>>>>>>> if the first bridge/switch advertises its inability to support
>>>>>>> extended config space accesses, we should not be performing them
>>>>>>> on any of its subordinate buses. How does the PEX8112 advertise
>>>>>>> this limitation?
>>>>>>>
>>>>>>> That said, I wonder if it is reasonable in the first place to
>>>>>>> expect that a PCIe device works as expected passing through a
>>>>>>> legacy PCI layer like that.
>>>>>>>
>>>>>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
>>>>>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
>>>>>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
>>>>>> support for PCI config offset >=0x100).
>>>>> Sounds right to me.
>>>>>
>>>>>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
>>>>>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
>>>>>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
>>>>>> pci_cfg_space_size())
>>>>> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
>>>>> should be enough, but it shouldn't hurt to check for either
>>>>> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
>>>>>
>>>>>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
>>>>>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
>>>>>> bridge without extended address capability to avoid PCi config
>>>>>> accesses at offset >= 0x100. Thanks to this patch I now have a
>>>>>> functional system with functional PCI/PCIe devices.
>>>>> The patch seems like it's looking at the right things, but I don't
>>>>> want to build it into pci_scan_bridge_extend() because that function
>>>>> is much too complicated already.
>>>>>
>>>>> I'd rather build it into pci_cfg_space_size() or
>>>>> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
>>>>> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
>>>>> that case, I think all 4K would be accessible on the PCI-X side.
>>>>>
>>>>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>>>>> index ac91b6fd0bcd..d8b091f0bcd1 100644
>>>>> --- a/drivers/pci/probe.c
>>>>> +++ b/drivers/pci/probe.c
>>>>> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>>>>     * pci_cfg_space_size - Get the configuration space size of the PCI device
>>>>>     * @dev: PCI device
>>>>>     *
>>>>> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
>>>>> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express devices
>>>>>     * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
>>>>>     * access it.  Maybe we don't have a way to generate extended config space
>>>>>     * accesses, or the device is behind a reverse Express bridge.  So we try
>>>>> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>>>>     */
>>>>>    static int pci_cfg_space_size_ext(struct pci_dev *dev)
>>>>>    {
>>>>> +    struct pci_dev *bridge = pci_upstream_bridge(dev);
>>>>>        u32 status;
>>>>>        int pos = PCI_CFG_SPACE_SIZE;
>>>>>    +    if (bridge && pci_is_pcie(bridge) &&
>>>>> +        pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
>>>>> +        return PCI_CFG_SPACE_SIZE;
>>>>> +
>>>>>        if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
>>>>>            return PCI_CFG_SPACE_SIZE;
>>>>>        if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
>>>>>
>>>>>> --- include/linux/pci.h.orig 2018-03-26 16:51:18.050000000 +0000
>>>>>> +++ include/linux/pci.h    2018-03-26 16:51:27.660000000 +0000
>>>>>> @@ -193,6 +193,7 @@
>>>>>>    enum pci_bus_flags {
>>>>>>        PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>>>>>        PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>>>>>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>>>>>>    };
>>>>>>      /* These values come from the PCI Express Spec */
>>>>>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
>>>>>> +++ drivers/pci/probe.c    2018-03-26 16:54:30.830000000 +0000
>>>>>> @@ -827,6 +827,28 @@
>>>>>>                child->primary = primary;
>>>>>>                pci_bus_insert_busn_res(child, secondary, subordinate);
>>>>>>                child->bridge_ctl = bctl;
>>>>>> +
>>>>>> +            {
>>>>>> +                int pos;
>>>>>> +                u32 status;
>>>>>> +                bool pci_compat_cfg_space = false;
>>>>>> +
>>>>>> +                if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) ==
>>>>>> PCI_EXP_TYPE_PCI_BRIDGE)) {
>>>>>> +                    /* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X
>>>>>> capabilities */
>>>>>> +                    pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
>>>>>> +                    if (pos) {
>>>>>> +                        pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>>>>>> +                        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>>>>>> +                            pci_compat_cfg_space = true;
>>>>>> +                    } else {
>>>>>> +                        pci_compat_cfg_space = true;
>>>>>> +                    }
>>>>>> +                    if (pci_compat_cfg_space) {
>>>>>> +                        dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor,
>>>>>> dev->device);
>>>>>> +                        child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>>>>>> +                    }
>>>>>> +                }
>>>>>> +            }
>>>>>>            }
>>>>>>              cmax = pci_scan_child_bus(child);
>>>>>> @@ -1098,6 +1120,11 @@
>>>>>>                goto fail;
>>>>>>        }
>>>>>>    +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
>>>>>> +        dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
>>>>>> +        return PCI_CFG_SPACE_SIZE;
>>>>>> +    }
>>>>>> +
>>>>>>        return pci_cfg_space_size_ext(dev);
>>>>>>       fail:
>>>> Bjorn,
>>>> If I'm right about your proposed patch to
>>>> pci_cfg_space_size_ext(), *bridge is pointing to the upper device
>>>> of device *dev being checked. I understand the purpose, but I
>>>> think this fails for my config that is :
>>>>
>>>> LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector -> PCI-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe
>>>> devices (one on each port)
>>>>
>>>> because :
>>>> - when pci_cfg_space_size_ext() is run on the 4 PCIe devices,
>>>> *bridge is the PCIe switch which is not matching
>>>> PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be
>>>> checked for the parent bus of the PCIe switch, and so on.
>>>> - when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge,
>>>> *bridge is the PEX8112 that is also not matching
>>>> PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads
>>>> to a config access at offset 0x100 to the PCI-to-PCIe bridge, so a
>>>> crash (because of the PEX8112)
>>>>
>>>> I think setting a bit in bus_flags when creating a child bus is
>>>> very efficient because once set it is automatically inherited by
>>>> all child buses and then the only thing that pci_cfg_space_size()
>>>> has to do for each device is to check for this bit. Also this
>>>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property
>>>> that is compliant with the purpose of bus_flags.
>> Yeah, it needs to be inherited somehow, and I don't like the idea of
>> traversing up the tree, so I prefer your idea.  Although I don't
>> actually see the inheritance in the patch below -- I thought there
>> would be something like this:
>>
>>    dev = bus->self;
>>    parent_bus = dev->bus;
>>    if (parent_bus && parent_bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>>      bus->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>>
>> pci_scan_bridge_extend() calls pci_add_new_bus() from two places.  You
>> added a call to pci_bus_check_compat_cfg_space() at one of them, and
>> it's not obvious why we wouldn't need it at the other place, too.
>>
>> Can you set this up in pci_alloc_child_bus()?  If you can put it
>> there, it would be clear that every time we allocate a secondary bus,
>> we figure out whether extended config space is accessible on that bus.
>>
>> That doesn't cover the root bus case, where we currently assume the
>> host bridge can generate config accesses to all config space supported
>> by devices on the root bus.  But we don't have a problem there, so I
>> guess we don't need to worry about it now.
>>
>> If you can put it in pci_alloc_child_bus(), could you make your new
>> function return a boolean, e.g., pci_bus_ext_cfg_accessible(), or
>> similar, and then use the result to set the
>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag?  Names like "*_check_*()" don't
>> tell the reader much about what's happening.
>>
>>>> I agree that pci_scan_bridge_extend() is already too complicated,
>>>> so would you be okay to only add one line to it :
>>>>    pci_bus_set_compat_cfg_space(child);
>>>> and put all the code I suggested in this new function
>>>> pci_bus_set_compat_cfg_space() ? (also supporting PCI-X Mode 2
>>>> devices)
>>>>
>>>> Improvement : this function can return immediately if the child
>>>> bus has already inherited the flag from its parent.
>>> I mean something like the attached patch I tested this morning...
>>> Sorry, this is for old kernel 4.1.35 but just to clarify what I
>>> propose (also applies to 4.16.6 by changing value of
>>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE in pci.h to 8).
>>> --- include/linux/pci.h.orig    2018-03-26 16:51:18.050000000 +0000
>>> +++ include/linux/pci.h    2018-04-30 09:50:57.660000000 +0000
>>> @@ -193,6 +193,7 @@
>>>   enum pci_bus_flags {
>>>       PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>>       PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>>>   };
>>>     /* These values come from the PCI Express Spec */
>>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
>>> +++ drivers/pci/probe.c    2018-04-30 13:29:50.600000000 +0000
>>> @@ -754,6 +754,35 @@
>>>                        PCI_EXP_RTCTL_CRSSVE);
>>>   }
>>>   +static void pci_bus_check_compat_cfg_space(struct pci_bus *bus)
>>> +{
>>> +    struct pci_dev *dev = bus->self;
>>> +    bool pci_compat_cfg_space = false;
>>> +    int pos;
>>> +    u32 status;
>>> +
>>> +    if (bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>>> +        return;
>>> +
>>> +    if (!pci_is_pcie(dev) || /* PCI/PCI bridge */
>>> +        (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
>>> +        (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)) { /* PCIe/PCI bridge in reverse mode */
>>> +        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
>>> +        if (pos) {
>>> +            pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>>> +            if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>>> +                pci_compat_cfg_space = true;
>>> +        } else {
>>> +            pci_compat_cfg_space = true;
>>> +        }
>>> +        if (pci_compat_cfg_space) {
>>> +            dev_info(&dev->dev, "bus %02x limited to PCI-Compatible config space\n",
>>> +                 bus->number);
>>> +            bus->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>>> +        }
>>> +    }
>>> +}
>>> +
>>>   /*
>>>    * If it's a bridge, configure it and scan the bus behind it.
>>>    * For CardBus bridges, we don't scan behind as the devices will
>>> @@ -827,6 +856,7 @@
>>>               child->primary = primary;
>>>               pci_bus_insert_busn_res(child, secondary, subordinate);
>>>               child->bridge_ctl = bctl;
>>> +            pci_bus_check_compat_cfg_space(child);
>>>           }
>>>             cmax = pci_scan_child_bus(child);
>>> @@ -1084,6 +1114,9 @@
>>>       u32 status;
>>>       u16 class;
>>>   +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>>> +        return PCI_CFG_SPACE_SIZE;
>>> +
>>>       class = dev->class >> 8;
>>>       if (class == PCI_CLASS_BRIDGE_HOST)
>>>           return pci_cfg_space_size_ext(dev);
>>
> The inheritence is made by this line in pci_alloc_child_bus() :
>     child->bus_flags = parent->bus_flags;
> So once we detect a limitation on a bridge impacting a child bus and that we set the flag in child->bus_flags, this flag is 
> automatically present in the child->bus_flags of all its children buses.
>
> I agree with your remarks and will create a function named pci_bus_check_compat_cfg_space() that will be called from 
> pci_alloc_child_bus().
> I'll test that on Wednesday 2th and will give you my feedback.
Hi Bjorn,
See attached patch (tested ok this morning)

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: cfgspace3_4.1.35.patch --]
[-- Type: text/x-patch; name=cfgspace3_4.1.35.patch, Size: 2246 bytes --]

--- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
+++ include/linux/pci.h	2018-04-30 18:29:14.140000000 +0000
@@ -193,6 +193,7 @@
 enum pci_bus_flags {
 	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
 	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
+	PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 4,
 };
 
 /* These values come from the PCI Express Spec */
--- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
+++ drivers/pci/probe.c	2018-05-02 13:44:35.530000000 +0000
@@ -664,6 +664,23 @@
 	}
 }
 
+static bool pci_bridge_child_bus_ext_cfg_accessible(struct pci_dev *bridge)
+{
+	int pos;
+	u32 status;
+
+	if (!pci_is_pcie(bridge) || /* PCI/PCI bridge */
+	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
+	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/PCI bridge in reverse mode */
+		pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
+		if (pos)
+			pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
+		return pos && (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ));
+	}
+
+	return true;
+}
+
 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 					   struct pci_dev *bridge, int busnr)
 {
@@ -725,6 +742,19 @@
 	/* Create legacy_io and legacy_mem files for this bus */
 	pci_create_legacy_files(child);
 
+	/*
+	 * if bus_flags inherited from parent bus do not already report lack of extended config
+	 * space support, check if supported by child bus by checking its parent bridge
+	 */
+	if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)) {
+		if (!pci_bridge_child_bus_ext_cfg_accessible(bridge)) {
+			child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
+			dev_info(&child->dev, "extended config space not accessible due to parent bridge\n");
+		}
+	} else {
+		dev_info(&child->dev, "extended config space not accessible due to parent bus\n");
+	}
+
 	return child;
 }
 
@@ -1084,6 +1114,9 @@
 	u32 status;
 	u16 class;
 
+	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
+		return PCI_CFG_SPACE_SIZE;
+
 	class = dev->class >> 8;
 	if (class == PCI_CLASS_BRIDGE_HOST)
 		return pci_cfg_space_size_ext(dev);

LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Le 30/04/2018 19:53, Gilles BULOZ a ?crit :
> Le 30/04/2018 19:04, Bjorn Helgaas a ?crit :
>> On Mon, Apr 30, 2018 at 01:36:53PM +0000, Gilles Buloz wrote:
>>> Le 30/04/2018 10:46, Gilles BULOZ a ?crit :
>>>> Le 27/04/2018 18:56, Bjorn Helgaas a ?crit :
>>>>> On Fri, Apr 27, 2018 at 12:29:32PM +0000, Gilles Buloz wrote:
>>>>>> Le 27/04/2018 10:43, Ard Biesheuvel a ?crit :
>>>>>>> (add Bjorn and linux-pci)
>>>>>>>
>>>>>>> On 13 April 2018 at 19:32, Gilles Buloz <Gilles.Buloz@kontron.com> wrote:
>>>>>>>> Dear developers,
>>>>>>>>
>>>>>>>> I currently have two functional workarounds for this issue but
>>>>>>>> would like to know which one you would recommend, if any :-) I'm
>>>>>>>> using a LS1043A CPU (NXP QorIQ Layerscape) and get a "synchronous
>>>>>>>> external abort" when booting because of a PCI config read during
>>>>>>>> PCI scan.
>>>>>>>>
>>>>>>>> I'm using a custom hardware (based on LS1043ARDB) having a
>>>>>>>> PEX8112 PCIe-to-PCI bridge connected to the LS1043A to have a PCI
>>>>>>>> slot for legacy devices. This bridge only supports PCI-Compatible
>>>>>>>> config accesses (offset 0x00-0xFF).
>>>>> I would guess the PEX8112 itself has 4K of config space, but it only
>>>>> forwards 256 bytes of config space to the conventional PCI secondary
>>>>> bus.
>>>>>
>>>>>>>> On this PCI slot I connect a PCI module made of a PCI-to-PCIe
>>>>>>>> bridge plus PCIe devices behind.
>>>>>>>>
>>>>>>>> The problem occurs when the kernel probes the PCIe devices : as
>>>>>>>> they are PCIe devices, the kernel does a PCI config read access
>>>>>>>> at offset 0x100 to check if "PCIe extended capability registers"
>>>>>>>> are accessible (see drivers/pci/probe.c, function
>>>>>>>> pci_cfg_space_size_ext()). Unfortunately the PEX8112 PCIe-to-PCI
>>>>>>>> bridge that is in the path reports an error to the CPU for this
>>>>>>>> access, and it seems there's no way to disable that on this
>>>>>>>> bridge.
>>>>>>>>
>>>>>>>> The first workaround I found was to patch
>>>>>>>> drivers/pci/host/pci-layerscape.c to have PCIE_ABSERR_SETTING set
>>>>>>>> to 0x9400 instead of 0x9401 (for PCIE_ABSERR register) to disable
>>>>>>>> error reporting. This only impacts an NXP part of the Linux
>>>>>>>> kernel code, but I'm not sure this is a good idea (however it
>>>>>>>> seems to be like that on Intel platforms where even MEM accesses
>>>>>>>> to a no-device address return FF without any error).
>>>>>>>>
>>>>>>>> I've also tried another workaround that works : patch
>>>>>>>> drivers/pci/probe.c to use bus_flags to remember if a bus is
>>>>>>>> behind a bridge without extended address capability, to avoid PCi
>>>>>>>> config read accesses at offset 0x100 in pci_cfg_space_size() /
>>>>>>>> pci_cfg_space_size_ext(). But this patch impacts the generic PCI
>>>>>>>> probe method of Linux.
>>>>>>>>
>>>>>>>> Any Idea to properly handle that issue ?
>>>>>>>>
>>>>>>> This seems like a rather unusual configuration, but I guess that
>>>>>>> if the first bridge/switch advertises its inability to support
>>>>>>> extended config space accesses, we should not be performing them
>>>>>>> on any of its subordinate buses. How does the PEX8112 advertise
>>>>>>> this limitation?
>>>>>>>
>>>>>>> That said, I wonder if it is reasonable in the first place to
>>>>>>> expect that a PCIe device works as expected passing through a
>>>>>>> legacy PCI layer like that.
>>>>>>>
>>>>>> The PEX8112 PCIe-to-PCI bridge has capability PCI_CAP_ID_EXP, but
>>>>>> has no PCI_CAP_ID_PCIX capability.  As I understand the lack of
>>>>>> PCI_CAP_ID_PCIX is advertising this limitation on the PCI side (no
>>>>>> support for PCI config offset >=0x100).
>>>>> Sounds right to me.
>>>>>
>>>>>> Also I guess in the case of a bridge having PCI_CAP_ID_PCIX, this
>>>>>> limitation would be advertised by the lack of PCI_X_STATUS_266MHZ
>>>>>> and PCI_X_STATUS_533MHZ (as done in drivers/pci/probe.c at
>>>>>> pci_cfg_space_size())
>>>>> Also sounds right.  Per the PCI-X spec, checking for PCI_X_STATUS_266MHZ
>>>>> should be enough, but it shouldn't hurt to check for either
>>>>> PCI_X_STATUS_266MHZ or PCI_X_STATUS_533MHZ.
>>>>>
>>>>>> I'm currently using the attached patch (for kernel 4.1.35-rt41 from
>>>>>> NXP Yocto BSP). It uses bus_flags to remember if a bus is behind a
>>>>>> bridge without extended address capability to avoid PCi config
>>>>>> accesses at offset >= 0x100. Thanks to this patch I now have a
>>>>>> functional system with functional PCI/PCIe devices.
>>>>> The patch seems like it's looking at the right things, but I don't
>>>>> want to build it into pci_scan_bridge_extend() because that function
>>>>> is much too complicated already.
>>>>>
>>>>> I'd rather build it into pci_cfg_space_size() or
>>>>> pci_cfg_space_size_ext() somehow.  Maybe something along these lines?
>>>>> This doesn't account for the case of a PCIe-to-PCI-X Mode 2 bridge; in
>>>>> that case, I think all 4K would be accessible on the PCI-X side.
>>>>>
>>>>> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
>>>>> index ac91b6fd0bcd..d8b091f0bcd1 100644
>>>>> --- a/drivers/pci/probe.c
>>>>> +++ b/drivers/pci/probe.c
>>>>> @@ -1367,7 +1367,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>>>>     * pci_cfg_space_size - Get the configuration space size of the PCI device
>>>>>     * @dev: PCI device
>>>>>     *
>>>>> - * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
>>>>> + * Regular PCI devices have 256 bytes, but PCI-X Mode 2 and PCI Express devices
>>>>>     * have 4096 bytes.  Even if the device is capable, that doesn't mean we can
>>>>>     * access it.  Maybe we don't have a way to generate extended config space
>>>>>     * accesses, or the device is behind a reverse Express bridge.  So we try
>>>>> @@ -1376,9 +1376,14 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
>>>>>     */
>>>>>    static int pci_cfg_space_size_ext(struct pci_dev *dev)
>>>>>    {
>>>>> +    struct pci_dev *bridge = pci_upstream_bridge(dev);
>>>>>        u32 status;
>>>>>        int pos = PCI_CFG_SPACE_SIZE;
>>>>>    +    if (bridge && pci_is_pcie(bridge) &&
>>>>> +        pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
>>>>> +        return PCI_CFG_SPACE_SIZE;
>>>>> +
>>>>>        if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
>>>>>            return PCI_CFG_SPACE_SIZE;
>>>>>        if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
>>>>>
>>>>>> --- include/linux/pci.h.orig 2018-03-26 16:51:18.050000000 +0000
>>>>>> +++ include/linux/pci.h    2018-03-26 16:51:27.660000000 +0000
>>>>>> @@ -193,6 +193,7 @@
>>>>>>    enum pci_bus_flags {
>>>>>>        PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>>>>>        PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>>>>>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>>>>>>    };
>>>>>>      /* These values come from the PCI Express Spec */
>>>>>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
>>>>>> +++ drivers/pci/probe.c    2018-03-26 16:54:30.830000000 +0000
>>>>>> @@ -827,6 +827,28 @@
>>>>>>                child->primary = primary;
>>>>>>                pci_bus_insert_busn_res(child, secondary, subordinate);
>>>>>>                child->bridge_ctl = bctl;
>>>>>> +
>>>>>> +            {
>>>>>> +                int pos;
>>>>>> +                u32 status;
>>>>>> +                bool pci_compat_cfg_space = false;
>>>>>> +
>>>>>> +                if (!pci_is_pcie(dev) || (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || (pci_pcie_type(dev) ==
>>>>>> PCI_EXP_TYPE_PCI_BRIDGE)) {
>>>>>> +                    /* for PCI/PCI bridges, or PCIe/PCI bridge in forward or reverse mode, we have to check for PCI-X
>>>>>> capabilities */
>>>>>> +                    pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
>>>>>> +                    if (pos) {
>>>>>> +                        pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>>>>>> +                        if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>>>>>> +                            pci_compat_cfg_space = true;
>>>>>> +                    } else {
>>>>>> +                        pci_compat_cfg_space = true;
>>>>>> +                    }
>>>>>> +                    if (pci_compat_cfg_space) {
>>>>>> +                        dev_info(&dev->dev, "[%04x:%04x] Child bus limited to PCI-Compatible config space\n", dev->vendor,
>>>>>> dev->device);
>>>>>> +                        child->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>>>>>> +                    }
>>>>>> +                }
>>>>>> +            }
>>>>>>            }
>>>>>>              cmax = pci_scan_child_bus(child);
>>>>>> @@ -1098,6 +1120,11 @@
>>>>>>                goto fail;
>>>>>>        }
>>>>>>    +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE) {
>>>>>> +        dev_info(&dev->dev, "[%04x:%04x] PCI-Compatible config space only due to parent bus(es)\n", dev->vendor, dev->device);
>>>>>> +        return PCI_CFG_SPACE_SIZE;
>>>>>> +    }
>>>>>> +
>>>>>>        return pci_cfg_space_size_ext(dev);
>>>>>>       fail:
>>>> Bjorn,
>>>> If I'm right about your proposed patch to
>>>> pci_cfg_space_size_ext(), *bridge is pointing to the upper device
>>>> of device *dev being checked. I understand the purpose, but I
>>>> think this fails for my config that is :
>>>>
>>>> LS1043 PCIe root -> PEX8112 PCIe-to-PCI bridge -> PMC slot connector -> PCI-to-PCIe bridge -> PCIe switch (4 ports) -> 4 PCIe
>>>> devices (one on each port)
>>>>
>>>> because :
>>>> - when pci_cfg_space_size_ext() is run on the 4 PCIe devices,
>>>> *bridge is the PCIe switch which is not matching
>>>> PCI_EXP_TYPE_PCI_BRIDGE. In this case *bridge should also be
>>>> checked for the parent bus of the PCIe switch, and so on.
>>>> - when pci_cfg_space_size_ext() is run for the PCI-to-PCIe bridge,
>>>> *bridge is the PEX8112 that is also not matching
>>>> PCI_EXP_TYPE_PCI_BRIDGE but PCI_EXP_TYPE_PCIE_BRIDGE. This leads
>>>> to a config access at offset 0x100 to the PCI-to-PCIe bridge, so a
>>>> crash (because of the PEX8112)
>>>>
>>>> I think setting a bit in bus_flags when creating a child bus is
>>>> very efficient because once set it is automatically inherited by
>>>> all child buses and then the only thing that pci_cfg_space_size()
>>>> has to do for each device is to check for this bit. Also this
>>>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag is actually a bus property
>>>> that is compliant with the purpose of bus_flags.
>> Yeah, it needs to be inherited somehow, and I don't like the idea of
>> traversing up the tree, so I prefer your idea.  Although I don't
>> actually see the inheritance in the patch below -- I thought there
>> would be something like this:
>>
>>    dev = bus->self;
>>    parent_bus = dev->bus;
>>    if (parent_bus && parent_bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>>      bus->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>>
>> pci_scan_bridge_extend() calls pci_add_new_bus() from two places.  You
>> added a call to pci_bus_check_compat_cfg_space() at one of them, and
>> it's not obvious why we wouldn't need it at the other place, too.
>>
>> Can you set this up in pci_alloc_child_bus()?  If you can put it
>> there, it would be clear that every time we allocate a secondary bus,
>> we figure out whether extended config space is accessible on that bus.
>>
>> That doesn't cover the root bus case, where we currently assume the
>> host bridge can generate config accesses to all config space supported
>> by devices on the root bus.  But we don't have a problem there, so I
>> guess we don't need to worry about it now.
>>
>> If you can put it in pci_alloc_child_bus(), could you make your new
>> function return a boolean, e.g., pci_bus_ext_cfg_accessible(), or
>> similar, and then use the result to set the
>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE flag?  Names like "*_check_*()" don't
>> tell the reader much about what's happening.
>>
>>>> I agree that pci_scan_bridge_extend() is already too complicated,
>>>> so would you be okay to only add one line to it :
>>>>    pci_bus_set_compat_cfg_space(child);
>>>> and put all the code I suggested in this new function
>>>> pci_bus_set_compat_cfg_space() ? (also supporting PCI-X Mode 2
>>>> devices)
>>>>
>>>> Improvement : this function can return immediately if the child
>>>> bus has already inherited the flag from its parent.
>>> I mean something like the attached patch I tested this morning...
>>> Sorry, this is for old kernel 4.1.35 but just to clarify what I
>>> propose (also applies to 4.16.6 by changing value of
>>> PCI_BUS_FLAGS_COMPAT_CFG_SPACE in pci.h to 8).
>>> --- include/linux/pci.h.orig    2018-03-26 16:51:18.050000000 +0000
>>> +++ include/linux/pci.h    2018-04-30 09:50:57.660000000 +0000
>>> @@ -193,6 +193,7 @@
>>>   enum pci_bus_flags {
>>>       PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>>       PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>>> +    PCI_BUS_FLAGS_COMPAT_CFG_SPACE = (__force pci_bus_flags_t) 4,
>>>   };
>>>     /* These values come from the PCI Express Spec */
>>> --- drivers/pci/probe.c.orig    2018-01-22 09:29:52.000000000 +0000
>>> +++ drivers/pci/probe.c    2018-04-30 13:29:50.600000000 +0000
>>> @@ -754,6 +754,35 @@
>>>                        PCI_EXP_RTCTL_CRSSVE);
>>>   }
>>>   +static void pci_bus_check_compat_cfg_space(struct pci_bus *bus)
>>> +{
>>> +    struct pci_dev *dev = bus->self;
>>> +    bool pci_compat_cfg_space = false;
>>> +    int pos;
>>> +    u32 status;
>>> +
>>> +    if (bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>>> +        return;
>>> +
>>> +    if (!pci_is_pcie(dev) || /* PCI/PCI bridge */
>>> +        (pci_pcie_type(dev) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
>>> +        (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)) { /* PCIe/PCI bridge in reverse mode */
>>> +        pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
>>> +        if (pos) {
>>> +            pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
>>> +            if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
>>> +                pci_compat_cfg_space = true;
>>> +        } else {
>>> +            pci_compat_cfg_space = true;
>>> +        }
>>> +        if (pci_compat_cfg_space) {
>>> +            dev_info(&dev->dev, "bus %02x limited to PCI-Compatible config space\n",
>>> +                 bus->number);
>>> +            bus->bus_flags |= PCI_BUS_FLAGS_COMPAT_CFG_SPACE;
>>> +        }
>>> +    }
>>> +}
>>> +
>>>   /*
>>>    * If it's a bridge, configure it and scan the bus behind it.
>>>    * For CardBus bridges, we don't scan behind as the devices will
>>> @@ -827,6 +856,7 @@
>>>               child->primary = primary;
>>>               pci_bus_insert_busn_res(child, secondary, subordinate);
>>>               child->bridge_ctl = bctl;
>>> +            pci_bus_check_compat_cfg_space(child);
>>>           }
>>>             cmax = pci_scan_child_bus(child);
>>> @@ -1084,6 +1114,9 @@
>>>       u32 status;
>>>       u16 class;
>>>   +    if (dev->bus->bus_flags & PCI_BUS_FLAGS_COMPAT_CFG_SPACE)
>>> +        return PCI_CFG_SPACE_SIZE;
>>> +
>>>       class = dev->class >> 8;
>>>       if (class == PCI_CLASS_BRIDGE_HOST)
>>>           return pci_cfg_space_size_ext(dev);
>>
> The inheritence is made by this line in pci_alloc_child_bus() :
>     child->bus_flags = parent->bus_flags;
> So once we detect a limitation on a bridge impacting a child bus and that we set the flag in child->bus_flags, this flag is 
> automatically present in the child->bus_flags of all its children buses.
>
> I agree with your remarks and will create a function named pci_bus_check_compat_cfg_space() that will be called from 
> pci_alloc_child_bus().
> I'll test that on Wednesday 2th and will give you my feedback.
Hi Bjorn,
See attached patch (tested ok this morning)
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Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Bjorn Helgaas]

On Wed, May 02, 2018 at 12:57:31PM +0000, Gilles Buloz wrote:
> Hi Bjorn,
> See attached patch (tested ok this morning)

This looks good.  Minor comments below.

I can fix minor things myself, but I do need a signed-off-by from you
before applying (see
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst)

Please add a changelog, too, and include the patch inline (as opposed
to as an attachment) if possible.

> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
> +++ include/linux/pci.h	2018-04-30 18:29:14.140000000 +0000
> @@ -193,6 +193,7 @@
>  enum pci_bus_flags {
>  	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>  	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
> +	PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 4,

Best if you can rebase this to v4.17-rc1.

>  };
>  
>  /* These values come from the PCI Express Spec */
> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
> +++ drivers/pci/probe.c	2018-05-02 13:44:35.530000000 +0000
> @@ -664,6 +664,23 @@
>  	}
>  }
>  
> +static bool pci_bridge_child_bus_ext_cfg_accessible(struct pci_dev *bridge)
> +{
> +	int pos;
> +	u32 status;
> +
> +	if (!pci_is_pcie(bridge) || /* PCI/PCI bridge */
> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/PCI bridge in reverse mode */
> +		pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
> +		if (pos)
> +			pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
> +		return pos && (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ));
> +	}

Please arrange this so everything fits in 80 columns.

If you can split it into several simpler "if" statements rather
than one with a complicated expression, that would also be good.

> +
> +	return true;
> +}
> +
>  static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>  					   struct pci_dev *bridge, int busnr)
>  {
> @@ -725,6 +742,19 @@
>  	/* Create legacy_io and legacy_mem files for this bus */
>  	pci_create_legacy_files(child);
>  
> +	/*
> +	 * if bus_flags inherited from parent bus do not already report lack of extended config
> +	 * space support, check if supported by child bus by checking its parent bridge
> +	 */

Wrap to fit in 80 columns.

> +	if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)) {

The double negative makes this a little bit hard to read.  Maybe it
could be improved by reversing the sense of something?

> +		if (!pci_bridge_child_bus_ext_cfg_accessible(bridge)) {
> +			child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
> +			dev_info(&child->dev, "extended config space not accessible due to parent bridge\n");

In v4.17-rc1, there's a pci_info() that should work here (instead of
dev_info()).

> +		}
> +	} else {
> +		dev_info(&child->dev, "extended config space not accessible due to parent bus\n");
> +	}
> +
>  	return child;
>  }
>  
> @@ -1084,6 +1114,9 @@
>  	u32 status;
>  	u16 class;
>  
> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> +		return PCI_CFG_SPACE_SIZE;
> +
>  	class = dev->class >> 8;
>  	if (class == PCI_CLASS_BRIDGE_HOST)
>  		return pci_cfg_space_size_ext(dev);


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LS1043A : "synchronous abort" at boot due to PCI config read

[Bjorn Helgaas]

On Wed, May 02, 2018 at 12:57:31PM +0000, Gilles Buloz wrote:
> Hi Bjorn,
> See attached patch (tested ok this morning)

This looks good.  Minor comments below.

I can fix minor things myself, but I do need a signed-off-by from you
before applying (see
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst)

Please add a changelog, too, and include the patch inline (as opposed
to as an attachment) if possible.

> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
> +++ include/linux/pci.h	2018-04-30 18:29:14.140000000 +0000
> @@ -193,6 +193,7 @@
>  enum pci_bus_flags {
>  	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>  	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
> +	PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 4,

Best if you can rebase this to v4.17-rc1.

>  };
>  
>  /* These values come from the PCI Express Spec */
> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
> +++ drivers/pci/probe.c	2018-05-02 13:44:35.530000000 +0000
> @@ -664,6 +664,23 @@
>  	}
>  }
>  
> +static bool pci_bridge_child_bus_ext_cfg_accessible(struct pci_dev *bridge)
> +{
> +	int pos;
> +	u32 status;
> +
> +	if (!pci_is_pcie(bridge) || /* PCI/PCI bridge */
> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/PCI bridge in reverse mode */
> +		pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
> +		if (pos)
> +			pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
> +		return pos && (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ));
> +	}

Please arrange this so everything fits in 80 columns.

If you can split it into several simpler "if" statements rather
than one with a complicated expression, that would also be good.

> +
> +	return true;
> +}
> +
>  static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>  					   struct pci_dev *bridge, int busnr)
>  {
> @@ -725,6 +742,19 @@
>  	/* Create legacy_io and legacy_mem files for this bus */
>  	pci_create_legacy_files(child);
>  
> +	/*
> +	 * if bus_flags inherited from parent bus do not already report lack of extended config
> +	 * space support, check if supported by child bus by checking its parent bridge
> +	 */

Wrap to fit in 80 columns.

> +	if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)) {

The double negative makes this a little bit hard to read.  Maybe it
could be improved by reversing the sense of something?

> +		if (!pci_bridge_child_bus_ext_cfg_accessible(bridge)) {
> +			child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
> +			dev_info(&child->dev, "extended config space not accessible due to parent bridge\n");

In v4.17-rc1, there's a pci_info() that should work here (instead of
dev_info()).

> +		}
> +	} else {
> +		dev_info(&child->dev, "extended config space not accessible due to parent bus\n");
> +	}
> +
>  	return child;
>  }
>  
> @@ -1084,6 +1114,9 @@
>  	u32 status;
>  	u16 class;
>  
> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> +		return PCI_CFG_SPACE_SIZE;
> +
>  	class = dev->class >> 8;
>  	if (class == PCI_CLASS_BRIDGE_HOST)
>  		return pci_cfg_space_size_ext(dev);

Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Le 02/05/2018 15:26, Bjorn Helgaas a =E9crit :
> On Wed, May 02, 2018 at 12:57:31PM +0000, Gilles Buloz wrote:
>> Hi Bjorn,
>> See attached patch (tested ok this morning)
> This looks good.  Minor comments below.
>
> I can fix minor things myself, but I do need a signed-off-by from you
> before applying (see
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Docu=
mentation/process/submitting-patches.rst)
>
> Please add a changelog, too, and include the patch inline (as opposed
> to as an attachment) if possible.
>
>> --- include/linux/pci.h.orig=092018-03-26 16:51:18.050000000 +0000
>> +++ include/linux/pci.h=092018-04-30 18:29:14.140000000 +0000
>> @@ -193,6 +193,7 @@
>>   enum pci_bus_flags {
>>   =09PCI_BUS_FLAGS_NO_MSI   =3D (__force pci_bus_flags_t) 1,
>>   =09PCI_BUS_FLAGS_NO_MMRBC =3D (__force pci_bus_flags_t) 2,
>> +=09PCI_BUS_FLAGS_NO_EXTCFG =3D (__force pci_bus_flags_t) 4,
> Best if you can rebase this to v4.17-rc1.
>
>>   };
>>  =20
>>   /* These values come from the PCI Express Spec */
>> --- drivers/pci/probe.c.orig=092018-01-22 09:29:52.000000000 +0000
>> +++ drivers/pci/probe.c=092018-05-02 13:44:35.530000000 +0000
>> @@ -664,6 +664,23 @@
>>   =09}
>>   }
>>  =20
>> +static bool pci_bridge_child_bus_ext_cfg_accessible(struct pci_dev *bri=
dge)
>> +{
>> +=09int pos;
>> +=09u32 status;
>> +
>> +=09if (!pci_is_pcie(bridge) || /* PCI/PCI bridge */
>> +=09    (pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_PCIE_BRIDGE) || /* PC=
Ie/PCI bridge in forward mode */
>> +=09    (pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PC=
Ie/PCI bridge in reverse mode */
>> +=09=09pos =3D pci_find_capability(bridge, PCI_CAP_ID_PCIX);
>> +=09=09if (pos)
>> +=09=09=09pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
>> +=09=09return pos && (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MH=
Z));
>> +=09}
> Please arrange this so everything fits in 80 columns.
>
> If you can split it into several simpler "if" statements rather
> than one with a complicated expression, that would also be good.
>
>> +
>> +=09return true;
>> +}
>> +
>>   static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>>   =09=09=09=09=09   struct pci_dev *bridge, int busnr)
>>   {
>> @@ -725,6 +742,19 @@
>>   =09/* Create legacy_io and legacy_mem files for this bus */
>>   =09pci_create_legacy_files(child);
>>  =20
>> +=09/*
>> +=09 * if bus_flags inherited from parent bus do not already report lack=
 of extended config
>> +=09 * space support, check if supported by child bus by checking its pa=
rent bridge
>> +=09 */
> Wrap to fit in 80 columns.
>
>> +=09if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)) {
> The double negative makes this a little bit hard to read.  Maybe it
> could be improved by reversing the sense of something?
>
>> +=09=09if (!pci_bridge_child_bus_ext_cfg_accessible(bridge)) {
>> +=09=09=09child->bus_flags |=3D PCI_BUS_FLAGS_NO_EXTCFG;
>> +=09=09=09dev_info(&child->dev, "extended config space not accessible du=
e to parent bridge\n");
> In v4.17-rc1, there's a pci_info() that should work here (instead of
> dev_info()).
>
>> +=09=09}
>> +=09} else {
>> +=09=09dev_info(&child->dev, "extended config space not accessible due t=
o parent bus\n");
>> +=09}
>> +
>>   =09return child;
>>   }
>>  =20
>> @@ -1084,6 +1114,9 @@
>>   =09u32 status;
>>   =09u16 class;
>>  =20
>> +=09if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
>> +=09=09return PCI_CFG_SPACE_SIZE;
>> +
>>   =09class =3D dev->class >> 8;
>>   =09if (class =3D=3D PCI_CLASS_BRIDGE_HOST)
>>   =09=09return pci_cfg_space_size_ext(dev);
> .
>
OK I'm going to learn about signing (sorry this is my first "official" patc=
h).
I'll download kernel v4.17-rc1 and write the patch for it; however I hope I=
'll be able to test it on my platform without the=20
freescale addons I have on 4.1.35, because I don't want to send an untested=
 patch.
For "if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG))", I don't=
 understand what you mean with "double negative", as I=20
only have one "!"

Do you think it's worth keeping the two dev_info() ? The code would be smal=
ler without; however this may help to have it for debug.=20
Maybe use _dbg instead of _info ?

LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Le 02/05/2018 15:26, Bjorn Helgaas a ?crit :
> On Wed, May 02, 2018 at 12:57:31PM +0000, Gilles Buloz wrote:
>> Hi Bjorn,
>> See attached patch (tested ok this morning)
> This looks good.  Minor comments below.
>
> I can fix minor things myself, but I do need a signed-off-by from you
> before applying (see
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst)
>
> Please add a changelog, too, and include the patch inline (as opposed
> to as an attachment) if possible.
>
>> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
>> +++ include/linux/pci.h	2018-04-30 18:29:14.140000000 +0000
>> @@ -193,6 +193,7 @@
>>   enum pci_bus_flags {
>>   	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
>>   	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
>> +	PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 4,
> Best if you can rebase this to v4.17-rc1.
>
>>   };
>>   
>>   /* These values come from the PCI Express Spec */
>> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
>> +++ drivers/pci/probe.c	2018-05-02 13:44:35.530000000 +0000
>> @@ -664,6 +664,23 @@
>>   	}
>>   }
>>   
>> +static bool pci_bridge_child_bus_ext_cfg_accessible(struct pci_dev *bridge)
>> +{
>> +	int pos;
>> +	u32 status;
>> +
>> +	if (!pci_is_pcie(bridge) || /* PCI/PCI bridge */
>> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
>> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/PCI bridge in reverse mode */
>> +		pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
>> +		if (pos)
>> +			pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
>> +		return pos && (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ));
>> +	}
> Please arrange this so everything fits in 80 columns.
>
> If you can split it into several simpler "if" statements rather
> than one with a complicated expression, that would also be good.
>
>> +
>> +	return true;
>> +}
>> +
>>   static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>>   					   struct pci_dev *bridge, int busnr)
>>   {
>> @@ -725,6 +742,19 @@
>>   	/* Create legacy_io and legacy_mem files for this bus */
>>   	pci_create_legacy_files(child);
>>   
>> +	/*
>> +	 * if bus_flags inherited from parent bus do not already report lack of extended config
>> +	 * space support, check if supported by child bus by checking its parent bridge
>> +	 */
> Wrap to fit in 80 columns.
>
>> +	if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)) {
> The double negative makes this a little bit hard to read.  Maybe it
> could be improved by reversing the sense of something?
>
>> +		if (!pci_bridge_child_bus_ext_cfg_accessible(bridge)) {
>> +			child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
>> +			dev_info(&child->dev, "extended config space not accessible due to parent bridge\n");
> In v4.17-rc1, there's a pci_info() that should work here (instead of
> dev_info()).
>
>> +		}
>> +	} else {
>> +		dev_info(&child->dev, "extended config space not accessible due to parent bus\n");
>> +	}
>> +
>>   	return child;
>>   }
>>   
>> @@ -1084,6 +1114,9 @@
>>   	u32 status;
>>   	u16 class;
>>   
>> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
>> +		return PCI_CFG_SPACE_SIZE;
>> +
>>   	class = dev->class >> 8;
>>   	if (class == PCI_CLASS_BRIDGE_HOST)
>>   		return pci_cfg_space_size_ext(dev);
> .
>
OK I'm going to learn about signing (sorry this is my first "official" patch).
I'll download kernel v4.17-rc1 and write the patch for it; however I hope I'll be able to test it on my platform without the 
freescale addons I have on 4.1.35, because I don't want to send an untested patch.
For "if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG))", I don't understand what you mean with "double negative", as I 
only have one "!"

Do you think it's worth keeping the two dev_info() ? The code would be smaller without; however this may help to have it for debug. 
Maybe use _dbg instead of _info ?

Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Bjorn Helgaas]

On Wed, May 02, 2018 at 01:48:27PM +0000, Gilles Buloz wrote:
> Le 02/05/2018 15:26, Bjorn Helgaas a =E9crit :
> > On Wed, May 02, 2018 at 12:57:31PM +0000, Gilles Buloz wrote:
> >> Hi Bjorn,
> >> See attached patch (tested ok this morning)
> > This looks good.  Minor comments below.
> >
> > I can fix minor things myself, but I do need a signed-off-by from you
> > before applying (see
> > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Do=
cumentation/process/submitting-patches.rst)
> >
> > Please add a changelog, too, and include the patch inline (as opposed
> > to as an attachment) if possible.
> >
> >> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
> >> +++ include/linux/pci.h	2018-04-30 18:29:14.140000000 +0000
> >> @@ -193,6 +193,7 @@
> >>   enum pci_bus_flags {
> >>   	PCI_BUS_FLAGS_NO_MSI   =3D (__force pci_bus_flags_t) 1,
> >>   	PCI_BUS_FLAGS_NO_MMRBC =3D (__force pci_bus_flags_t) 2,
> >> +	PCI_BUS_FLAGS_NO_EXTCFG =3D (__force pci_bus_flags_t) 4,
> > Best if you can rebase this to v4.17-rc1.
> >
> >>   };
> >>   =

> >>   /* These values come from the PCI Express Spec */
> >> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
> >> +++ drivers/pci/probe.c	2018-05-02 13:44:35.530000000 +0000
> >> @@ -664,6 +664,23 @@
> >>   	}
> >>   }
> >>   =

> >> +static bool pci_bridge_child_bus_ext_cfg_accessible(struct pci_dev *b=
ridge)
> >> +{
> >> +	int pos;
> >> +	u32 status;
> >> +
> >> +	if (!pci_is_pcie(bridge) || /* PCI/PCI bridge */
> >> +	    (pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_PCIE_BRIDGE) || /* PC=
Ie/PCI bridge in forward mode */
> >> +	    (pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PC=
Ie/PCI bridge in reverse mode */
> >> +		pos =3D pci_find_capability(bridge, PCI_CAP_ID_PCIX);
> >> +		if (pos)
> >> +			pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
> >> +		return pos && (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)=
);
> >> +	}
> > Please arrange this so everything fits in 80 columns.
> >
> > If you can split it into several simpler "if" statements rather
> > than one with a complicated expression, that would also be good.
> >
> >> +
> >> +	return true;
> >> +}
> >> +
> >>   static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
> >>   					   struct pci_dev *bridge, int busnr)
> >>   {
> >> @@ -725,6 +742,19 @@
> >>   	/* Create legacy_io and legacy_mem files for this bus */
> >>   	pci_create_legacy_files(child);
> >>   =

> >> +	/*
> >> +	 * if bus_flags inherited from parent bus do not already report lack=
 of extended config
> >> +	 * space support, check if supported by child bus by checking its pa=
rent bridge
> >> +	 */
> > Wrap to fit in 80 columns.
> >
> >> +	if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)) {
> > The double negative makes this a little bit hard to read.  Maybe it
> > could be improved by reversing the sense of something?
> >
> >> +		if (!pci_bridge_child_bus_ext_cfg_accessible(bridge)) {
> >> +			child->bus_flags |=3D PCI_BUS_FLAGS_NO_EXTCFG;
> >> +			dev_info(&child->dev, "extended config space not accessible due to=
 parent bridge\n");
> > In v4.17-rc1, there's a pci_info() that should work here (instead of
> > dev_info()).
> >
> >> +		}
> >> +	} else {
> >> +		dev_info(&child->dev, "extended config space not accessible due to =
parent bus\n");
> >> +	}
> >> +
> >>   	return child;
> >>   }
> >>   =

> >> @@ -1084,6 +1114,9 @@
> >>   	u32 status;
> >>   	u16 class;
> >>   =

> >> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> >> +		return PCI_CFG_SPACE_SIZE;
> >> +
> >>   	class =3D dev->class >> 8;
> >>   	if (class =3D=3D PCI_CLASS_BRIDGE_HOST)
> >>   		return pci_cfg_space_size_ext(dev);
> > .
> >
> OK I'm going to learn about signing (sorry this is my first
> "official" patch).

Great, welcome!  The signoff is no big deal -- it's just plain text
(no crypto signature or anything) and it's basically just an assertion
that you wrote it and have the right to contribute it.

> I'll download kernel v4.17-rc1 and write the patch for it; however I
> hope I'll be able to test it on my platform without the freescale
> addons I have on 4.1.35, because I don't want to send an untested
> patch.

Don't worry too much about the 4.1 vs 4.17 issue.  If you tested it
on 4.1.35 that should be fine.

> For "if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG))",
> I don't understand what you mean with "double negative", as I only
> have one "!"

The "!" and the "NO" part of "NO_EXTCFG" is what I meant.  E.g., maybe
the flag could be something like "COMPAT_CFG_ONLY" so there's no
negation in the test at all.

> Do you think it's worth keeping the two dev_info() ? The code would
> be smaller without; however this may help to have it for debug.
> Maybe use _dbg instead of _info ?

Probably one pci_info() is enough as a clue that extended config space =

isn't available below this point in the hierarchy.

I personally don't like the _dbg() version because it's so complicated
to figure out when the output is enabled.

Bjorn

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

LS1043A : "synchronous abort" at boot due to PCI config read

[Bjorn Helgaas]

On Wed, May 02, 2018 at 01:48:27PM +0000, Gilles Buloz wrote:
> Le 02/05/2018 15:26, Bjorn Helgaas a ?crit :
> > On Wed, May 02, 2018 at 12:57:31PM +0000, Gilles Buloz wrote:
> >> Hi Bjorn,
> >> See attached patch (tested ok this morning)
> > This looks good.  Minor comments below.
> >
> > I can fix minor things myself, but I do need a signed-off-by from you
> > before applying (see
> > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst)
> >
> > Please add a changelog, too, and include the patch inline (as opposed
> > to as an attachment) if possible.
> >
> >> --- include/linux/pci.h.orig	2018-03-26 16:51:18.050000000 +0000
> >> +++ include/linux/pci.h	2018-04-30 18:29:14.140000000 +0000
> >> @@ -193,6 +193,7 @@
> >>   enum pci_bus_flags {
> >>   	PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
> >>   	PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
> >> +	PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 4,
> > Best if you can rebase this to v4.17-rc1.
> >
> >>   };
> >>   
> >>   /* These values come from the PCI Express Spec */
> >> --- drivers/pci/probe.c.orig	2018-01-22 09:29:52.000000000 +0000
> >> +++ drivers/pci/probe.c	2018-05-02 13:44:35.530000000 +0000
> >> @@ -664,6 +664,23 @@
> >>   	}
> >>   }
> >>   
> >> +static bool pci_bridge_child_bus_ext_cfg_accessible(struct pci_dev *bridge)
> >> +{
> >> +	int pos;
> >> +	u32 status;
> >> +
> >> +	if (!pci_is_pcie(bridge) || /* PCI/PCI bridge */
> >> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCIE_BRIDGE) || /* PCIe/PCI bridge in forward mode */
> >> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)) {  /* PCIe/PCI bridge in reverse mode */
> >> +		pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
> >> +		if (pos)
> >> +			pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
> >> +		return pos && (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ));
> >> +	}
> > Please arrange this so everything fits in 80 columns.
> >
> > If you can split it into several simpler "if" statements rather
> > than one with a complicated expression, that would also be good.
> >
> >> +
> >> +	return true;
> >> +}
> >> +
> >>   static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
> >>   					   struct pci_dev *bridge, int busnr)
> >>   {
> >> @@ -725,6 +742,19 @@
> >>   	/* Create legacy_io and legacy_mem files for this bus */
> >>   	pci_create_legacy_files(child);
> >>   
> >> +	/*
> >> +	 * if bus_flags inherited from parent bus do not already report lack of extended config
> >> +	 * space support, check if supported by child bus by checking its parent bridge
> >> +	 */
> > Wrap to fit in 80 columns.
> >
> >> +	if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)) {
> > The double negative makes this a little bit hard to read.  Maybe it
> > could be improved by reversing the sense of something?
> >
> >> +		if (!pci_bridge_child_bus_ext_cfg_accessible(bridge)) {
> >> +			child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
> >> +			dev_info(&child->dev, "extended config space not accessible due to parent bridge\n");
> > In v4.17-rc1, there's a pci_info() that should work here (instead of
> > dev_info()).
> >
> >> +		}
> >> +	} else {
> >> +		dev_info(&child->dev, "extended config space not accessible due to parent bus\n");
> >> +	}
> >> +
> >>   	return child;
> >>   }
> >>   
> >> @@ -1084,6 +1114,9 @@
> >>   	u32 status;
> >>   	u16 class;
> >>   
> >> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> >> +		return PCI_CFG_SPACE_SIZE;
> >> +
> >>   	class = dev->class >> 8;
> >>   	if (class == PCI_CLASS_BRIDGE_HOST)
> >>   		return pci_cfg_space_size_ext(dev);
> > .
> >
> OK I'm going to learn about signing (sorry this is my first
> "official" patch).

Great, welcome!  The signoff is no big deal -- it's just plain text
(no crypto signature or anything) and it's basically just an assertion
that you wrote it and have the right to contribute it.

> I'll download kernel v4.17-rc1 and write the patch for it; however I
> hope I'll be able to test it on my platform without the freescale
> addons I have on 4.1.35, because I don't want to send an untested
> patch.

Don't worry too much about the 4.1 vs 4.17 issue.  If you tested it
on 4.1.35 that should be fine.

> For "if (bridge && !(child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG))",
> I don't understand what you mean with "double negative", as I only
> have one "!"

The "!" and the "NO" part of "NO_EXTCFG" is what I meant.  E.g., maybe
the flag could be something like "COMPAT_CFG_ONLY" so there's no
negation in the test at all.

> Do you think it's worth keeping the two dev_info() ? The code would
> be smaller without; however this may help to have it for debug.
> Maybe use _dbg instead of _info ?

Probably one pci_info() is enough as a clue that extended config space 
isn't available below this point in the hierarchy.

I personally don't like the _dbg() version because it's so complicated
to figure out when the output is enabled.

Bjorn

Re: LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR

Even if a device supports extended config access, no such access must be
done to this device If there's a bridge not supporting that in the path
to this device. Doing such access with UR reporting enabled on the root
bridge leads to an exception.

This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
the following bus topology :
  LS1043 PCIe root
    -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
      -> PMC slot connector (for legacy PMC modules)
With a PMC module topology as follows :
  PMC connector
    -> PCI-to-PCIe bridge
      -> PCIe switch (4 ports)
        -> 4 PCIe devices (one on each port)
In this case all devices behind the PEX8112 are supporting extended config
access but this is prohibited by the PEX8112. Without this patch, an
exception (synchronous abort) occurs in pci_cfg_space_size_ext().

This patch checks the parent bridge of each allocated child bus to know if
extended config access is supported on the child bus, and sets a flag in
child->bus_flags if not supported. This  flag is inherited by all children
buses of this child bus and then is checked to avoid this unsupported
accesses to every device on these buses.

Thanks

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Gilles BULOZ
Senior software engineer
Kontron France
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D


Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>

--- linux-4.17-rc1/include/linux/pci.h.orig=092018-04-16 01:24:20.000000000=
 +0000
+++ linux-4.17-rc1/include/linux/pci.h=092018-05-03 09:53:03.270000000 +000=
0
@@ -217,6 +217,7 @@ enum pci_bus_flags {
  =09PCI_BUS_FLAGS_NO_MSI=09=3D (__force pci_bus_flags_t) 1,
  =09PCI_BUS_FLAGS_NO_MMRBC=09=3D (__force pci_bus_flags_t) 2,
  =09PCI_BUS_FLAGS_NO_AERSID=09=3D (__force pci_bus_flags_t) 4,
+=09PCI_BUS_FLAGS_NO_EXTCFG=09=3D (__force pci_bus_flags_t) 8,
  };
 =20
  /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
--- linux-4.17-rc1/drivers/pci/probe.c.orig=092018-05-03 09:45:21.110000000=
 +0000
+++ linux-4.17-rc1/drivers/pci/probe.c=092018-05-03 09:46:50.550000000 +000=
0
@@ -882,6 +882,24 @@ free:
  =09return err;
  }
 =20
+static bool pci_bridge_child_bus_ext_cfg_accessible(struct pci_dev *bridge=
)
+{
+=09int pos;
+=09u32 status;
+
+=09if (pci_is_pcie(bridge) &&
+=09    (pci_pcie_type(bridge) !=3D PCI_EXP_TYPE_PCIE_BRIDGE) &&
+=09    (pci_pcie_type(bridge) !=3D PCI_EXP_TYPE_PCI_BRIDGE))
+=09=09return true;
+
+=09/* PCI/PCI, or PCIe/PCI (forward), or PCI/PCIe (reverse) bridge */
+=09pos =3D pci_find_capability(bridge, PCI_CAP_ID_PCIX);
+=09if (pos)
+=09=09pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
+
+=09return pos && (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ));
+}
+
  static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
  =09=09=09=09=09   struct pci_dev *bridge, int busnr)
  {
@@ -930,6 +948,20 @@ static struct pci_bus *pci_alloc_child_b
  =09}
  =09bridge->subordinate =3D child;
 =20
+=09/*
+=09 * if bus_flags inherited from parent bus do not already report lack of
+=09 * extended config space support, check if supported by child bus by
+=09 * checking its parent bridge
+=09 */
+=09if (child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) {
+=09=09pci_info(child, "extended config space not accessible due to parent =
bus\n");
+=09} else {
+=09=09if (!pci_bridge_child_bus_ext_cfg_accessible(bridge)) {
+=09=09=09child->bus_flags |=3D PCI_BUS_FLAGS_NO_EXTCFG;
+=09=09=09pci_info(child, "extended config space not accessible due to pare=
nt bridge\n");
+=09=09}
+=09}
+
  add_dev:
  =09pci_set_bus_msi_domain(child);
  =09ret =3D device_register(&child->dev);
@@ -1393,6 +1425,9 @@ int pci_cfg_space_size(struct pci_dev *d
  =09u32 status;
  =09u16 class;
 =20
+=09if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
+=09=09return PCI_CFG_SPACE_SIZE;
+
  =09class =3D dev->class >> 8;
  =09if (class =3D=3D PCI_CLASS_BRIDGE_HOST)
  =09=09return pci_cfg_space_size_ext(dev);

LS1043A : "synchronous abort" at boot due to PCI config read

[Gilles Buloz]

Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR

Even if a device supports extended config access, no such access must be
done to this device If there's a bridge not supporting that in the path
to this device. Doing such access with UR reporting enabled on the root
bridge leads to an exception.

This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
the following bus topology :
  LS1043 PCIe root
    -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
      -> PMC slot connector (for legacy PMC modules)
With a PMC module topology as follows :
  PMC connector
    -> PCI-to-PCIe bridge
      -> PCIe switch (4 ports)
        -> 4 PCIe devices (one on each port)
In this case all devices behind the PEX8112 are supporting extended config
access but this is prohibited by the PEX8112. Without this patch, an
exception (synchronous abort) occurs in pci_cfg_space_size_ext().

This patch checks the parent bridge of each allocated child bus to know if
extended config access is supported on the child bus, and sets a flag in
child->bus_flags if not supported. This  flag is inherited by all children
buses of this child bus and then is checked to avoid this unsupported
accesses to every device on these buses.

Thanks

=====================
Gilles BULOZ
Senior software engineer
Kontron France
=====================


Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>

--- linux-4.17-rc1/include/linux/pci.h.orig	2018-04-16 01:24:20.000000000 +0000
+++ linux-4.17-rc1/include/linux/pci.h	2018-05-03 09:53:03.270000000 +0000
@@ -217,6 +217,7 @@ enum pci_bus_flags {
  	PCI_BUS_FLAGS_NO_MSI	= (__force pci_bus_flags_t) 1,
  	PCI_BUS_FLAGS_NO_MMRBC	= (__force pci_bus_flags_t) 2,
  	PCI_BUS_FLAGS_NO_AERSID	= (__force pci_bus_flags_t) 4,
+	PCI_BUS_FLAGS_NO_EXTCFG	= (__force pci_bus_flags_t) 8,
  };
  
  /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
--- linux-4.17-rc1/drivers/pci/probe.c.orig	2018-05-03 09:45:21.110000000 +0000
+++ linux-4.17-rc1/drivers/pci/probe.c	2018-05-03 09:46:50.550000000 +0000
@@ -882,6 +882,24 @@ free:
  	return err;
  }
  
+static bool pci_bridge_child_bus_ext_cfg_accessible(struct pci_dev *bridge)
+{
+	int pos;
+	u32 status;
+
+	if (pci_is_pcie(bridge) &&
+	    (pci_pcie_type(bridge) != PCI_EXP_TYPE_PCIE_BRIDGE) &&
+	    (pci_pcie_type(bridge) != PCI_EXP_TYPE_PCI_BRIDGE))
+		return true;
+
+	/* PCI/PCI, or PCIe/PCI (forward), or PCI/PCIe (reverse) bridge */
+	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
+	if (pos)
+		pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
+
+	return pos && (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ));
+}
+
  static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
  					   struct pci_dev *bridge, int busnr)
  {
@@ -930,6 +948,20 @@ static struct pci_bus *pci_alloc_child_b
  	}
  	bridge->subordinate = child;
  
+	/*
+	 * if bus_flags inherited from parent bus do not already report lack of
+	 * extended config space support, check if supported by child bus by
+	 * checking its parent bridge
+	 */
+	if (child->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) {
+		pci_info(child, "extended config space not accessible due to parent bus\n");
+	} else {
+		if (!pci_bridge_child_bus_ext_cfg_accessible(bridge)) {
+			child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
+			pci_info(child, "extended config space not accessible due to parent bridge\n");
+		}
+	}
+
  add_dev:
  	pci_set_bus_msi_domain(child);
  	ret = device_register(&child->dev);
@@ -1393,6 +1425,9 @@ int pci_cfg_space_size(struct pci_dev *d
  	u32 status;
  	u16 class;
  
+	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
+		return PCI_CFG_SPACE_SIZE;
+
  	class = dev->class >> 8;
  	if (class == PCI_CLASS_BRIDGE_HOST)
  		return pci_cfg_space_size_ext(dev);

[PATCH] PCI: Check whether bridges allow access to extended config space

[Bjorn Helgaas]

[+cc LKML]

On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
> Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR
> 
> Even if a device supports extended config access, no such access must be
> done to this device If there's a bridge not supporting that in the path
> to this device. Doing such access with UR reporting enabled on the root
> bridge leads to an exception.
> 
> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
> the following bus topology :
>   LS1043 PCIe root
>     -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
>       -> PMC slot connector (for legacy PMC modules)
> With a PMC module topology as follows :
>   PMC connector
>     -> PCI-to-PCIe bridge
>       -> PCIe switch (4 ports)
>         -> 4 PCIe devices (one on each port)
> In this case all devices behind the PEX8112 are supporting extended config
> access but this is prohibited by the PEX8112. Without this patch, an
> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
> 
> This patch checks the parent bridge of each allocated child bus to know if
> extended config access is supported on the child bus, and sets a flag in
> child->bus_flags if not supported. This  flag is inherited by all children
> buses of this child bus and then is checked to avoid this unsupported
> accesses to every device on these buses.

Hi Gilles,

Thanks for the patch!  I reworked it a little bit to simplify the code
in pci_alloc_child_bus().  Can you test it and make sure I didn't
break anything?


commit cbaaa85b558a8f974e301fa0364d568efaf491ce
Author: Gilles Buloz <Gilles.Buloz@kontron.com>
Date:   Thu May 3 15:21:44 2018 -0500

    PCI: Check whether bridges allow access to extended config space
    
    Even if a device supports extended config space, i.e., it is a PCI-X Mode 2
    or a PCI Express device, the extended space may not be accessible if
    there's a conventional PCI bus in the path to it.
    
    We currently figure that out in pci_cfg_space_size() by reading the first
    dword of extended config space.  On most platforms that returns ~0 data if
    the space is inaccessible, but it may set error bits in PCI status
    registers, and on some platforms it causes exceptions that we currently
    don't recover from.
    
    For example, a PCIe-to-conventional PCI bridge treats config transactions
    with a non-zero Extended Register Address as an Unsupported Request on PCIe
    and a received Master-Abort on the destination bus (see PCI Express to
    PCI/PCI-X Bridge spec, r1.0, sec 4.1.3).
    
    A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with the
    following bus topology:
    
      LS1043 PCIe Root Port
        -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI side)
          -> PMC slot connector (for legacy PMC modules)
    
    With a PMC module topology as follows:
    
      PMC connector
        -> PCI-to-PCIe bridge
          -> PCIe switch (4 ports)
            -> 4 PCIe devices (one on each port)
    
    The PCIe devices on the PMC module support extended config space, but we
    can't reach it because the PEX8112 can't generate accesses to the extended
    space on its secondary bus.  Attempts to access it cause Unsupported
    Request errors, which result in synchronous aborts on this platform.
    
    To avoid these errors, check whether bridges are capable of generating
    extended config space addresses on their secondary interfaces.  If they
    can't, we restrict devices below the bridge to only the 256-byte
    PCI-compatible config space.
    
    Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>
    [bhelgaas: changelog, rework patch so bus_flags testing is all in
    pci_bridge_child_ext_cfg_accessible()]
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ac91b6fd0bcd..7b1b7b2e01e4 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
 	return err;
 }
 
+static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
+{
+	int pos;
+	u32 status;
+
+	/*
+	 * If extended config space isn't accessible on a bridge's primary
+	 * bus, we certainly can't access it on the secondary bus.
+	 */
+	if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
+		return false;
+
+	/*
+	 * PCIe Root Ports and switch ports are PCIe on both sides, so if
+	 * extended config space is accessible on the primary, it's also
+	 * accessible on the secondary.
+	 */
+	if (pci_is_pcie(bridge) &&
+	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
+	     pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
+	     pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
+		return true;
+
+	/*
+	 * For the other bridge types:
+	 *   - PCI-to-PCI bridges
+	 *   - PCIe-to-PCI/PCI-X forward bridges
+	 *   - PCI/PCI-X-to-PCIe reverse bridges
+	 * extended config space on the secondary side is only accessible
+	 * if the bridge supports PCI-X Mode 2.
+	 */
+	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
+	if (!pos)
+		return false;
+
+	pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
+	return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
+}
+
 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 					   struct pci_dev *bridge, int busnr)
 {
@@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 	pci_set_bus_of_node(child);
 	pci_set_bus_speed(child);
 
+	/*
+	 * Check whether extended config space is accessible on the child
+	 * bus.  Note that we currently assume it is always accessible on
+	 * the root bus.
+	 */
+	if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
+		child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
+		pci_info(child, "extended config space not accessible on secondary bus\n");
+	}
+
 	/* Set up default resource pointers and names */
 	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
 		child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
@@ -1393,6 +1442,9 @@ int pci_cfg_space_size(struct pci_dev *dev)
 	u32 status;
 	u16 class;
 
+	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
+		return PCI_CFG_SPACE_SIZE;
+
 	class = dev->class >> 8;
 	if (class == PCI_CLASS_BRIDGE_HOST)
 		return pci_cfg_space_size_ext(dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 230615620a4a..f7aa6d9f8999 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -217,6 +217,7 @@ enum pci_bus_flags {
 	PCI_BUS_FLAGS_NO_MSI	= (__force pci_bus_flags_t) 1,
 	PCI_BUS_FLAGS_NO_MMRBC	= (__force pci_bus_flags_t) 2,
 	PCI_BUS_FLAGS_NO_AERSID	= (__force pci_bus_flags_t) 4,
+	PCI_BUS_FLAGS_NO_EXTCFG	= (__force pci_bus_flags_t) 8,
 };
 
 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */

[PATCH] PCI: Check whether bridges allow access to extended config space

[Bjorn Helgaas]

[+cc LKML]

On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
> Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR
> 
> Even if a device supports extended config access, no such access must be
> done to this device If there's a bridge not supporting that in the path
> to this device. Doing such access with UR reporting enabled on the root
> bridge leads to an exception.
> 
> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
> the following bus topology :
>   LS1043 PCIe root
>     -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
>       -> PMC slot connector (for legacy PMC modules)
> With a PMC module topology as follows :
>   PMC connector
>     -> PCI-to-PCIe bridge
>       -> PCIe switch (4 ports)
>         -> 4 PCIe devices (one on each port)
> In this case all devices behind the PEX8112 are supporting extended config
> access but this is prohibited by the PEX8112. Without this patch, an
> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
> 
> This patch checks the parent bridge of each allocated child bus to know if
> extended config access is supported on the child bus, and sets a flag in
> child->bus_flags if not supported. This  flag is inherited by all children
> buses of this child bus and then is checked to avoid this unsupported
> accesses to every device on these buses.

Hi Gilles,

Thanks for the patch!  I reworked it a little bit to simplify the code
in pci_alloc_child_bus().  Can you test it and make sure I didn't
break anything?


commit cbaaa85b558a8f974e301fa0364d568efaf491ce
Author: Gilles Buloz <Gilles.Buloz@kontron.com>
Date:   Thu May 3 15:21:44 2018 -0500

    PCI: Check whether bridges allow access to extended config space
    
    Even if a device supports extended config space, i.e., it is a PCI-X Mode 2
    or a PCI Express device, the extended space may not be accessible if
    there's a conventional PCI bus in the path to it.
    
    We currently figure that out in pci_cfg_space_size() by reading the first
    dword of extended config space.  On most platforms that returns ~0 data if
    the space is inaccessible, but it may set error bits in PCI status
    registers, and on some platforms it causes exceptions that we currently
    don't recover from.
    
    For example, a PCIe-to-conventional PCI bridge treats config transactions
    with a non-zero Extended Register Address as an Unsupported Request on PCIe
    and a received Master-Abort on the destination bus (see PCI Express to
    PCI/PCI-X Bridge spec, r1.0, sec 4.1.3).
    
    A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with the
    following bus topology:
    
      LS1043 PCIe Root Port
        -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI side)
          -> PMC slot connector (for legacy PMC modules)
    
    With a PMC module topology as follows:
    
      PMC connector
        -> PCI-to-PCIe bridge
          -> PCIe switch (4 ports)
            -> 4 PCIe devices (one on each port)
    
    The PCIe devices on the PMC module support extended config space, but we
    can't reach it because the PEX8112 can't generate accesses to the extended
    space on its secondary bus.  Attempts to access it cause Unsupported
    Request errors, which result in synchronous aborts on this platform.
    
    To avoid these errors, check whether bridges are capable of generating
    extended config space addresses on their secondary interfaces.  If they
    can't, we restrict devices below the bridge to only the 256-byte
    PCI-compatible config space.
    
    Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>
    [bhelgaas: changelog, rework patch so bus_flags testing is all in
    pci_bridge_child_ext_cfg_accessible()]
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ac91b6fd0bcd..7b1b7b2e01e4 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
 	return err;
 }
 
+static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
+{
+	int pos;
+	u32 status;
+
+	/*
+	 * If extended config space isn't accessible on a bridge's primary
+	 * bus, we certainly can't access it on the secondary bus.
+	 */
+	if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
+		return false;
+
+	/*
+	 * PCIe Root Ports and switch ports are PCIe on both sides, so if
+	 * extended config space is accessible on the primary, it's also
+	 * accessible on the secondary.
+	 */
+	if (pci_is_pcie(bridge) &&
+	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
+	     pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
+	     pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
+		return true;
+
+	/*
+	 * For the other bridge types:
+	 *   - PCI-to-PCI bridges
+	 *   - PCIe-to-PCI/PCI-X forward bridges
+	 *   - PCI/PCI-X-to-PCIe reverse bridges
+	 * extended config space on the secondary side is only accessible
+	 * if the bridge supports PCI-X Mode 2.
+	 */
+	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
+	if (!pos)
+		return false;
+
+	pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
+	return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
+}
+
 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 					   struct pci_dev *bridge, int busnr)
 {
@@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 	pci_set_bus_of_node(child);
 	pci_set_bus_speed(child);
 
+	/*
+	 * Check whether extended config space is accessible on the child
+	 * bus.  Note that we currently assume it is always accessible on
+	 * the root bus.
+	 */
+	if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
+		child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
+		pci_info(child, "extended config space not accessible on secondary bus\n");
+	}
+
 	/* Set up default resource pointers and names */
 	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
 		child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
@@ -1393,6 +1442,9 @@ int pci_cfg_space_size(struct pci_dev *dev)
 	u32 status;
 	u16 class;
 
+	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
+		return PCI_CFG_SPACE_SIZE;
+
 	class = dev->class >> 8;
 	if (class == PCI_CLASS_BRIDGE_HOST)
 		return pci_cfg_space_size_ext(dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 230615620a4a..f7aa6d9f8999 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -217,6 +217,7 @@ enum pci_bus_flags {
 	PCI_BUS_FLAGS_NO_MSI	= (__force pci_bus_flags_t) 1,
 	PCI_BUS_FLAGS_NO_MMRBC	= (__force pci_bus_flags_t) 2,
 	PCI_BUS_FLAGS_NO_AERSID	= (__force pci_bus_flags_t) 4,
+	PCI_BUS_FLAGS_NO_EXTCFG	= (__force pci_bus_flags_t) 8,
 };
 
 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */

[PATCH] PCI: Check whether bridges allow access to extended config space

[Bjorn Helgaas]

[+cc LKML]

On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
> Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR
> 
> Even if a device supports extended config access, no such access must be
> done to this device If there's a bridge not supporting that in the path
> to this device. Doing such access with UR reporting enabled on the root
> bridge leads to an exception.
> 
> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
> the following bus topology :
>   LS1043 PCIe root
>     -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
>       -> PMC slot connector (for legacy PMC modules)
> With a PMC module topology as follows :
>   PMC connector
>     -> PCI-to-PCIe bridge
>       -> PCIe switch (4 ports)
>         -> 4 PCIe devices (one on each port)
> In this case all devices behind the PEX8112 are supporting extended config
> access but this is prohibited by the PEX8112. Without this patch, an
> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
> 
> This patch checks the parent bridge of each allocated child bus to know if
> extended config access is supported on the child bus, and sets a flag in
> child->bus_flags if not supported. This  flag is inherited by all children
> buses of this child bus and then is checked to avoid this unsupported
> accesses to every device on these buses.

Hi Gilles,

Thanks for the patch!  I reworked it a little bit to simplify the code
in pci_alloc_child_bus().  Can you test it and make sure I didn't
break anything?


commit cbaaa85b558a8f974e301fa0364d568efaf491ce
Author: Gilles Buloz <Gilles.Buloz@kontron.com>
Date:   Thu May 3 15:21:44 2018 -0500

    PCI: Check whether bridges allow access to extended config space
    
    Even if a device supports extended config space, i.e., it is a PCI-X Mode 2
    or a PCI Express device, the extended space may not be accessible if
    there's a conventional PCI bus in the path to it.
    
    We currently figure that out in pci_cfg_space_size() by reading the first
    dword of extended config space.  On most platforms that returns ~0 data if
    the space is inaccessible, but it may set error bits in PCI status
    registers, and on some platforms it causes exceptions that we currently
    don't recover from.
    
    For example, a PCIe-to-conventional PCI bridge treats config transactions
    with a non-zero Extended Register Address as an Unsupported Request on PCIe
    and a received Master-Abort on the destination bus (see PCI Express to
    PCI/PCI-X Bridge spec, r1.0, sec 4.1.3).
    
    A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with the
    following bus topology:
    
      LS1043 PCIe Root Port
        -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI side)
          -> PMC slot connector (for legacy PMC modules)
    
    With a PMC module topology as follows:
    
      PMC connector
        -> PCI-to-PCIe bridge
          -> PCIe switch (4 ports)
            -> 4 PCIe devices (one on each port)
    
    The PCIe devices on the PMC module support extended config space, but we
    can't reach it because the PEX8112 can't generate accesses to the extended
    space on its secondary bus.  Attempts to access it cause Unsupported
    Request errors, which result in synchronous aborts on this platform.
    
    To avoid these errors, check whether bridges are capable of generating
    extended config space addresses on their secondary interfaces.  If they
    can't, we restrict devices below the bridge to only the 256-byte
    PCI-compatible config space.
    
    Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>
    [bhelgaas: changelog, rework patch so bus_flags testing is all in
    pci_bridge_child_ext_cfg_accessible()]
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ac91b6fd0bcd..7b1b7b2e01e4 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
 	return err;
 }
 
+static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
+{
+	int pos;
+	u32 status;
+
+	/*
+	 * If extended config space isn't accessible on a bridge's primary
+	 * bus, we certainly can't access it on the secondary bus.
+	 */
+	if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
+		return false;
+
+	/*
+	 * PCIe Root Ports and switch ports are PCIe on both sides, so if
+	 * extended config space is accessible on the primary, it's also
+	 * accessible on the secondary.
+	 */
+	if (pci_is_pcie(bridge) &&
+	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
+	     pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
+	     pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
+		return true;
+
+	/*
+	 * For the other bridge types:
+	 *   - PCI-to-PCI bridges
+	 *   - PCIe-to-PCI/PCI-X forward bridges
+	 *   - PCI/PCI-X-to-PCIe reverse bridges
+	 * extended config space on the secondary side is only accessible
+	 * if the bridge supports PCI-X Mode 2.
+	 */
+	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
+	if (!pos)
+		return false;
+
+	pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
+	return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
+}
+
 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 					   struct pci_dev *bridge, int busnr)
 {
@@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
 	pci_set_bus_of_node(child);
 	pci_set_bus_speed(child);
 
+	/*
+	 * Check whether extended config space is accessible on the child
+	 * bus.  Note that we currently assume it is always accessible on
+	 * the root bus.
+	 */
+	if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
+		child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
+		pci_info(child, "extended config space not accessible on secondary bus\n");
+	}
+
 	/* Set up default resource pointers and names */
 	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
 		child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
@@ -1393,6 +1442,9 @@ int pci_cfg_space_size(struct pci_dev *dev)
 	u32 status;
 	u16 class;
 
+	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
+		return PCI_CFG_SPACE_SIZE;
+
 	class = dev->class >> 8;
 	if (class == PCI_CLASS_BRIDGE_HOST)
 		return pci_cfg_space_size_ext(dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 230615620a4a..f7aa6d9f8999 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -217,6 +217,7 @@ enum pci_bus_flags {
 	PCI_BUS_FLAGS_NO_MSI	= (__force pci_bus_flags_t) 1,
 	PCI_BUS_FLAGS_NO_MMRBC	= (__force pci_bus_flags_t) 2,
 	PCI_BUS_FLAGS_NO_AERSID	= (__force pci_bus_flags_t) 4,
+	PCI_BUS_FLAGS_NO_EXTCFG	= (__force pci_bus_flags_t) 8,
 };
 
 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH] PCI: Check whether bridges allow access to extended config space

[Gilles Buloz]

Le 04/05/2018 00:31, Bjorn Helgaas a écrit :
> [+cc LKML]
>
> On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
>> Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR
>>
>> Even if a device supports extended config access, no such access must be
>> done to this device If there's a bridge not supporting that in the path
>> to this device. Doing such access with UR reporting enabled on the root
>> bridge leads to an exception.
>>
>> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
>> the following bus topology :
>>    LS1043 PCIe root
>>      -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
>>        -> PMC slot connector (for legacy PMC modules)
>> With a PMC module topology as follows :
>>    PMC connector
>>      -> PCI-to-PCIe bridge
>>        -> PCIe switch (4 ports)
>>          -> 4 PCIe devices (one on each port)
>> In this case all devices behind the PEX8112 are supporting extended config
>> access but this is prohibited by the PEX8112. Without this patch, an
>> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
>>
>> This patch checks the parent bridge of each allocated child bus to know if
>> extended config access is supported on the child bus, and sets a flag in
>> child->bus_flags if not supported. This  flag is inherited by all children
>> buses of this child bus and then is checked to avoid this unsupported
>> accesses to every device on these buses.
> Hi Gilles,
>
> Thanks for the patch!  I reworked it a little bit to simplify the code
> in pci_alloc_child_bus().  Can you test it and make sure I didn't
> break anything?
>
Hi Bjorn,

Your rework works as expected. Tested on LS1043A platform with kernel 4.17-rc1, and with some backport on kernel 4.1.35

Suggestion : maybe change the pci_info() string to have :
     pci_bus 0000:xx: extended config space not accessible
instead of
     pci_bus 0000:xx: extended config space not accessible on secondary bus
as xx is already the number of the secondary bus

Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=off to have the PMC devices behind the
PCI-to-PCIe bridge of the PMC safely detected/configured. But this is not caused by the patch.
Without pcie_aspm=off I saw this at one boot :
    "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this bridge, but devices
    correctly detected/configured
but at most boots I get :
    no ASPM message but "pci 0000:04:02.0: bridge configuration invalid ([bus ff-ff]), reconfiguring "
    instead, and some devices are missing. Also lspci show "rev ff" for some devices.
I don't see this problem on 4.1.35 with the same backported patch.

Gilles
> commit cbaaa85b558a8f974e301fa0364d568efaf491ce
> Author: Gilles Buloz <Gilles.Buloz@kontron.com>
> Date:   Thu May 3 15:21:44 2018 -0500
>
>      PCI: Check whether bridges allow access to extended config space
>      
>      Even if a device supports extended config space, i.e., it is a PCI-X Mode 2
>      or a PCI Express device, the extended space may not be accessible if
>      there's a conventional PCI bus in the path to it.
>      
>      We currently figure that out in pci_cfg_space_size() by reading the first
>      dword of extended config space.  On most platforms that returns ~0 data if
>      the space is inaccessible, but it may set error bits in PCI status
>      registers, and on some platforms it causes exceptions that we currently
>      don't recover from.
>      
>      For example, a PCIe-to-conventional PCI bridge treats config transactions
>      with a non-zero Extended Register Address as an Unsupported Request on PCIe
>      and a received Master-Abort on the destination bus (see PCI Express to
>      PCI/PCI-X Bridge spec, r1.0, sec 4.1.3).
>      
>      A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with the
>      following bus topology:
>      
>        LS1043 PCIe Root Port
>          -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI side)
>            -> PMC slot connector (for legacy PMC modules)
>      
>      With a PMC module topology as follows:
>      
>        PMC connector
>          -> PCI-to-PCIe bridge
>            -> PCIe switch (4 ports)
>              -> 4 PCIe devices (one on each port)
>      
>      The PCIe devices on the PMC module support extended config space, but we
>      can't reach it because the PEX8112 can't generate accesses to the extended
>      space on its secondary bus.  Attempts to access it cause Unsupported
>      Request errors, which result in synchronous aborts on this platform.
>      
>      To avoid these errors, check whether bridges are capable of generating
>      extended config space addresses on their secondary interfaces.  If they
>      can't, we restrict devices below the bridge to only the 256-byte
>      PCI-compatible config space.
>      
>      Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>
>      [bhelgaas: changelog, rework patch so bus_flags testing is all in
>      pci_bridge_child_ext_cfg_accessible()]
>      Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index ac91b6fd0bcd..7b1b7b2e01e4 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
>   	return err;
>   }
>   
> +static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
> +{
> +	int pos;
> +	u32 status;
> +
> +	/*
> +	 * If extended config space isn't accessible on a bridge's primary
> +	 * bus, we certainly can't access it on the secondary bus.
> +	 */
> +	if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> +		return false;
> +
> +	/*
> +	 * PCIe Root Ports and switch ports are PCIe on both sides, so if
> +	 * extended config space is accessible on the primary, it's also
> +	 * accessible on the secondary.
> +	 */
> +	if (pci_is_pcie(bridge) &&
> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
> +	     pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
> +	     pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
> +		return true;
> +
> +	/*
> +	 * For the other bridge types:
> +	 *   - PCI-to-PCI bridges
> +	 *   - PCIe-to-PCI/PCI-X forward bridges
> +	 *   - PCI/PCI-X-to-PCIe reverse bridges
> +	 * extended config space on the secondary side is only accessible
> +	 * if the bridge supports PCI-X Mode 2.
> +	 */
> +	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
> +	if (!pos)
> +		return false;
> +
> +	pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
> +	return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
> +}
> +
>   static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>   					   struct pci_dev *bridge, int busnr)
>   {
> @@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>   	pci_set_bus_of_node(child);
>   	pci_set_bus_speed(child);
>   
> +	/*
> +	 * Check whether extended config space is accessible on the child
> +	 * bus.  Note that we currently assume it is always accessible on
> +	 * the root bus.
> +	 */
> +	if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
> +		child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
> +		pci_info(child, "extended config space not accessible on secondary bus\n");
> +	}
> +
>   	/* Set up default resource pointers and names */
>   	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
>   		child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
> @@ -1393,6 +1442,9 @@ int pci_cfg_space_size(struct pci_dev *dev)
>   	u32 status;
>   	u16 class;
>   
> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> +		return PCI_CFG_SPACE_SIZE;
> +
>   	class = dev->class >> 8;
>   	if (class == PCI_CLASS_BRIDGE_HOST)
>   		return pci_cfg_space_size_ext(dev);
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 230615620a4a..f7aa6d9f8999 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -217,6 +217,7 @@ enum pci_bus_flags {
>   	PCI_BUS_FLAGS_NO_MSI	= (__force pci_bus_flags_t) 1,
>   	PCI_BUS_FLAGS_NO_MMRBC	= (__force pci_bus_flags_t) 2,
>   	PCI_BUS_FLAGS_NO_AERSID	= (__force pci_bus_flags_t) 4,
> +	PCI_BUS_FLAGS_NO_EXTCFG	= (__force pci_bus_flags_t) 8,
>   };
>   
>   /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
>
> .
>

[PATCH] PCI: Check whether bridges allow access to extended config space

[Gilles Buloz]

Le 04/05/2018 00:31, Bjorn Helgaas a ?crit :
> [+cc LKML]
>
> On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
>> Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR
>>
>> Even if a device supports extended config access, no such access must be
>> done to this device If there's a bridge not supporting that in the path
>> to this device. Doing such access with UR reporting enabled on the root
>> bridge leads to an exception.
>>
>> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
>> the following bus topology :
>>    LS1043 PCIe root
>>      -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
>>        -> PMC slot connector (for legacy PMC modules)
>> With a PMC module topology as follows :
>>    PMC connector
>>      -> PCI-to-PCIe bridge
>>        -> PCIe switch (4 ports)
>>          -> 4 PCIe devices (one on each port)
>> In this case all devices behind the PEX8112 are supporting extended config
>> access but this is prohibited by the PEX8112. Without this patch, an
>> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
>>
>> This patch checks the parent bridge of each allocated child bus to know if
>> extended config access is supported on the child bus, and sets a flag in
>> child->bus_flags if not supported. This  flag is inherited by all children
>> buses of this child bus and then is checked to avoid this unsupported
>> accesses to every device on these buses.
> Hi Gilles,
>
> Thanks for the patch!  I reworked it a little bit to simplify the code
> in pci_alloc_child_bus().  Can you test it and make sure I didn't
> break anything?
>
Hi Bjorn,

Your rework works as expected. Tested on LS1043A platform with kernel 4.17-rc1, and with some backport on kernel 4.1.35

Suggestion : maybe change the pci_info() string to have :
     pci_bus 0000:xx: extended config space not accessible
instead of
     pci_bus 0000:xx: extended config space not accessible on secondary bus
as xx is already the number of the secondary bus

Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=off to have the PMC devices behind the
PCI-to-PCIe bridge of the PMC safely detected/configured. But this is not caused by the patch.
Without pcie_aspm=off I saw this at one boot :
    "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this bridge, but devices
    correctly detected/configured
but at most boots I get :
    no ASPM message but "pci 0000:04:02.0: bridge configuration invalid ([bus ff-ff]), reconfiguring "
    instead, and some devices are missing. Also lspci show "rev ff" for some devices.
I don't see this problem on 4.1.35 with the same backported patch.

Gilles
> commit cbaaa85b558a8f974e301fa0364d568efaf491ce
> Author: Gilles Buloz <Gilles.Buloz@kontron.com>
> Date:   Thu May 3 15:21:44 2018 -0500
>
>      PCI: Check whether bridges allow access to extended config space
>      
>      Even if a device supports extended config space, i.e., it is a PCI-X Mode 2
>      or a PCI Express device, the extended space may not be accessible if
>      there's a conventional PCI bus in the path to it.
>      
>      We currently figure that out in pci_cfg_space_size() by reading the first
>      dword of extended config space.  On most platforms that returns ~0 data if
>      the space is inaccessible, but it may set error bits in PCI status
>      registers, and on some platforms it causes exceptions that we currently
>      don't recover from.
>      
>      For example, a PCIe-to-conventional PCI bridge treats config transactions
>      with a non-zero Extended Register Address as an Unsupported Request on PCIe
>      and a received Master-Abort on the destination bus (see PCI Express to
>      PCI/PCI-X Bridge spec, r1.0, sec 4.1.3).
>      
>      A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with the
>      following bus topology:
>      
>        LS1043 PCIe Root Port
>          -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI side)
>            -> PMC slot connector (for legacy PMC modules)
>      
>      With a PMC module topology as follows:
>      
>        PMC connector
>          -> PCI-to-PCIe bridge
>            -> PCIe switch (4 ports)
>              -> 4 PCIe devices (one on each port)
>      
>      The PCIe devices on the PMC module support extended config space, but we
>      can't reach it because the PEX8112 can't generate accesses to the extended
>      space on its secondary bus.  Attempts to access it cause Unsupported
>      Request errors, which result in synchronous aborts on this platform.
>      
>      To avoid these errors, check whether bridges are capable of generating
>      extended config space addresses on their secondary interfaces.  If they
>      can't, we restrict devices below the bridge to only the 256-byte
>      PCI-compatible config space.
>      
>      Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>
>      [bhelgaas: changelog, rework patch so bus_flags testing is all in
>      pci_bridge_child_ext_cfg_accessible()]
>      Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index ac91b6fd0bcd..7b1b7b2e01e4 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
>   	return err;
>   }
>   
> +static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
> +{
> +	int pos;
> +	u32 status;
> +
> +	/*
> +	 * If extended config space isn't accessible on a bridge's primary
> +	 * bus, we certainly can't access it on the secondary bus.
> +	 */
> +	if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> +		return false;
> +
> +	/*
> +	 * PCIe Root Ports and switch ports are PCIe on both sides, so if
> +	 * extended config space is accessible on the primary, it's also
> +	 * accessible on the secondary.
> +	 */
> +	if (pci_is_pcie(bridge) &&
> +	    (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
> +	     pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
> +	     pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
> +		return true;
> +
> +	/*
> +	 * For the other bridge types:
> +	 *   - PCI-to-PCI bridges
> +	 *   - PCIe-to-PCI/PCI-X forward bridges
> +	 *   - PCI/PCI-X-to-PCIe reverse bridges
> +	 * extended config space on the secondary side is only accessible
> +	 * if the bridge supports PCI-X Mode 2.
> +	 */
> +	pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
> +	if (!pos)
> +		return false;
> +
> +	pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
> +	return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
> +}
> +
>   static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>   					   struct pci_dev *bridge, int busnr)
>   {
> @@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>   	pci_set_bus_of_node(child);
>   	pci_set_bus_speed(child);
>   
> +	/*
> +	 * Check whether extended config space is accessible on the child
> +	 * bus.  Note that we currently assume it is always accessible on
> +	 * the root bus.
> +	 */
> +	if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
> +		child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
> +		pci_info(child, "extended config space not accessible on secondary bus\n");
> +	}
> +
>   	/* Set up default resource pointers and names */
>   	for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
>   		child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
> @@ -1393,6 +1442,9 @@ int pci_cfg_space_size(struct pci_dev *dev)
>   	u32 status;
>   	u16 class;
>   
> +	if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> +		return PCI_CFG_SPACE_SIZE;
> +
>   	class = dev->class >> 8;
>   	if (class == PCI_CLASS_BRIDGE_HOST)
>   		return pci_cfg_space_size_ext(dev);
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 230615620a4a..f7aa6d9f8999 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -217,6 +217,7 @@ enum pci_bus_flags {
>   	PCI_BUS_FLAGS_NO_MSI	= (__force pci_bus_flags_t) 1,
>   	PCI_BUS_FLAGS_NO_MMRBC	= (__force pci_bus_flags_t) 2,
>   	PCI_BUS_FLAGS_NO_AERSID	= (__force pci_bus_flags_t) 4,
> +	PCI_BUS_FLAGS_NO_EXTCFG	= (__force pci_bus_flags_t) 8,
>   };
>   
>   /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
>
> .
>

Re: [PATCH] PCI: Check whether bridges allow access to extended config space

[Gilles Buloz]

Le 04/05/2018 00:31, Bjorn Helgaas a =E9crit :
> [+cc LKML]
>
> On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
>> Subject:    [PATCH] For exception at PCI probe due to bridge reporting U=
R
>>
>> Even if a device supports extended config access, no such access must be
>> done to this device If there's a bridge not supporting that in the path
>> to this device. Doing such access with UR reporting enabled on the root
>> bridge leads to an exception.
>>
>> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
>> the following bus topology :
>>    LS1043 PCIe root
>>      -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
>>        -> PMC slot connector (for legacy PMC modules)
>> With a PMC module topology as follows :
>>    PMC connector
>>      -> PCI-to-PCIe bridge
>>        -> PCIe switch (4 ports)
>>          -> 4 PCIe devices (one on each port)
>> In this case all devices behind the PEX8112 are supporting extended conf=
ig
>> access but this is prohibited by the PEX8112. Without this patch, an
>> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
>>
>> This patch checks the parent bridge of each allocated child bus to know =
if
>> extended config access is supported on the child bus, and sets a flag in
>> child->bus_flags if not supported. This  flag is inherited by all childr=
en
>> buses of this child bus and then is checked to avoid this unsupported
>> accesses to every device on these buses.
> Hi Gilles,
>
> Thanks for the patch!  I reworked it a little bit to simplify the code
> in pci_alloc_child_bus().  Can you test it and make sure I didn't
> break anything?
>
Hi Bjorn,

Your rework works as expected. Tested on LS1043A platform with kernel 4.17-=
rc1, and with some backport on kernel 4.1.35

Suggestion : maybe change the pci_info() string to have :
     pci_bus 0000:xx: extended config space not accessible
instead of
     pci_bus 0000:xx: extended config space not accessible on secondary bus
as xx is already the number of the secondary bus

Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=3Doff to have th=
e PMC devices behind the
PCI-to-PCIe bridge of the PMC safely detected/configured. But this is not c=
aused by the patch.
Without pcie_aspm=3Doff I saw this at one boot :
    "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this bri=
dge, but devices
    correctly detected/configured
but at most boots I get :
    no ASPM message but "pci 0000:04:02.0: bridge configuration invalid ([b=
us ff-ff]), reconfiguring "
    instead, and some devices are missing. Also lspci show "rev ff" for som=
e devices.
I don't see this problem on 4.1.35 with the same backported patch.

Gilles
> commit cbaaa85b558a8f974e301fa0364d568efaf491ce
> Author: Gilles Buloz <Gilles.Buloz@kontron.com>
> Date:   Thu May 3 15:21:44 2018 -0500
>
>      PCI: Check whether bridges allow access to extended config space
>     =20
>      Even if a device supports extended config space, i.e., it is a PCI-X=
 Mode 2
>      or a PCI Express device, the extended space may not be accessible if
>      there's a conventional PCI bus in the path to it.
>     =20
>      We currently figure that out in pci_cfg_space_size() by reading the =
first
>      dword of extended config space.  On most platforms that returns ~0 d=
ata if
>      the space is inaccessible, but it may set error bits in PCI status
>      registers, and on some platforms it causes exceptions that we curren=
tly
>      don't recover from.
>     =20
>      For example, a PCIe-to-conventional PCI bridge treats config transac=
tions
>      with a non-zero Extended Register Address as an Unsupported Request =
on PCIe
>      and a received Master-Abort on the destination bus (see PCI Express =
to
>      PCI/PCI-X Bridge spec, r1.0, sec 4.1.3).
>     =20
>      A sample case is a LS1043A CPU (NXP QorIQ Layerscape) platform with =
the
>      following bus topology:
>     =20
>        LS1043 PCIe Root Port
>          -> PEX8112 PCIe-to-PCI bridge (doesn't support ext cfg on PCI si=
de)
>            -> PMC slot connector (for legacy PMC modules)
>     =20
>      With a PMC module topology as follows:
>     =20
>        PMC connector
>          -> PCI-to-PCIe bridge
>            -> PCIe switch (4 ports)
>              -> 4 PCIe devices (one on each port)
>     =20
>      The PCIe devices on the PMC module support extended config space, bu=
t we
>      can't reach it because the PEX8112 can't generate accesses to the ex=
tended
>      space on its secondary bus.  Attempts to access it cause Unsupported
>      Request errors, which result in synchronous aborts on this platform.
>     =20
>      To avoid these errors, check whether bridges are capable of generati=
ng
>      extended config space addresses on their secondary interfaces.  If t=
hey
>      can't, we restrict devices below the bridge to only the 256-byte
>      PCI-compatible config space.
>     =20
>      Signed-off-by: Gilles Buloz <gilles.buloz@kontron.com>
>      [bhelgaas: changelog, rework patch so bus_flags testing is all in
>      pci_bridge_child_ext_cfg_accessible()]
>      Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index ac91b6fd0bcd..7b1b7b2e01e4 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -882,6 +882,45 @@ static int pci_register_host_bridge(struct pci_host_=
bridge *bridge)
>   =09return err;
>   }
>  =20
> +static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
> +{
> +=09int pos;
> +=09u32 status;
> +
> +=09/*
> +=09 * If extended config space isn't accessible on a bridge's primary
> +=09 * bus, we certainly can't access it on the secondary bus.
> +=09 */
> +=09if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> +=09=09return false;
> +
> +=09/*
> +=09 * PCIe Root Ports and switch ports are PCIe on both sides, so if
> +=09 * extended config space is accessible on the primary, it's also
> +=09 * accessible on the secondary.
> +=09 */
> +=09if (pci_is_pcie(bridge) &&
> +=09    (pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_ROOT_PORT ||
> +=09     pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_UPSTREAM ||
> +=09     pci_pcie_type(bridge) =3D=3D PCI_EXP_TYPE_DOWNSTREAM))
> +=09=09return true;
> +
> +=09/*
> +=09 * For the other bridge types:
> +=09 *   - PCI-to-PCI bridges
> +=09 *   - PCIe-to-PCI/PCI-X forward bridges
> +=09 *   - PCI/PCI-X-to-PCIe reverse bridges
> +=09 * extended config space on the secondary side is only accessible
> +=09 * if the bridge supports PCI-X Mode 2.
> +=09 */
> +=09pos =3D pci_find_capability(bridge, PCI_CAP_ID_PCIX);
> +=09if (!pos)
> +=09=09return false;
> +
> +=09pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
> +=09return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
> +}
> +
>   static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>   =09=09=09=09=09   struct pci_dev *bridge, int busnr)
>   {
> @@ -923,6 +962,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pc=
i_bus *parent,
>   =09pci_set_bus_of_node(child);
>   =09pci_set_bus_speed(child);
>  =20
> +=09/*
> +=09 * Check whether extended config space is accessible on the child
> +=09 * bus.  Note that we currently assume it is always accessible on
> +=09 * the root bus.
> +=09 */
> +=09if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
> +=09=09child->bus_flags |=3D PCI_BUS_FLAGS_NO_EXTCFG;
> +=09=09pci_info(child, "extended config space not accessible on secondary=
 bus\n");
> +=09}
> +
>   =09/* Set up default resource pointers and names */
>   =09for (i =3D 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
>   =09=09child->resource[i] =3D &bridge->resource[PCI_BRIDGE_RESOURCES+i];
> @@ -1393,6 +1442,9 @@ int pci_cfg_space_size(struct pci_dev *dev)
>   =09u32 status;
>   =09u16 class;
>  =20
> +=09if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
> +=09=09return PCI_CFG_SPACE_SIZE;
> +
>   =09class =3D dev->class >> 8;
>   =09if (class =3D=3D PCI_CLASS_BRIDGE_HOST)
>   =09=09return pci_cfg_space_size_ext(dev);
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 230615620a4a..f7aa6d9f8999 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -217,6 +217,7 @@ enum pci_bus_flags {
>   =09PCI_BUS_FLAGS_NO_MSI=09=3D (__force pci_bus_flags_t) 1,
>   =09PCI_BUS_FLAGS_NO_MMRBC=09=3D (__force pci_bus_flags_t) 2,
>   =09PCI_BUS_FLAGS_NO_AERSID=09=3D (__force pci_bus_flags_t) 4,
> +=09PCI_BUS_FLAGS_NO_EXTCFG=09=3D (__force pci_bus_flags_t) 8,
>   };
>  =20
>   /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
>
> .
>

(no subject)

[Bjorn Helgaas]

Bcc: 
Subject: Re: [PATCH] PCI: Check whether bridges allow access to extended
 config space
Reply-To: 
In-Reply-To: <5AEC8002.5000309@kontron.com>

[+cc Fred, Sinan]

On Fri, May 04, 2018 at 03:45:07PM +0000, Gilles Buloz wrote:
> Le 04/05/2018 00:31, Bjorn Helgaas a écrit :
> > [+cc LKML]
> >
> > On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
> >> Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR
> >>
> >> Even if a device supports extended config access, no such access must be
> >> done to this device If there's a bridge not supporting that in the path
> >> to this device. Doing such access with UR reporting enabled on the root
> >> bridge leads to an exception.
> >>
> >> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
> >> the following bus topology :
> >>    LS1043 PCIe root
> >>      -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
> >>        -> PMC slot connector (for legacy PMC modules)
> >> With a PMC module topology as follows :
> >>    PMC connector
> >>      -> PCI-to-PCIe bridge
> >>        -> PCIe switch (4 ports)
> >>          -> 4 PCIe devices (one on each port)
> >> In this case all devices behind the PEX8112 are supporting extended config
> >> access but this is prohibited by the PEX8112. Without this patch, an
> >> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
> >>
> >> This patch checks the parent bridge of each allocated child bus to know if
> >> extended config access is supported on the child bus, and sets a flag in
> >> child->bus_flags if not supported. This  flag is inherited by all children
> >> buses of this child bus and then is checked to avoid this unsupported
> >> accesses to every device on these buses.
> > Hi Gilles,
> >
> > Thanks for the patch!  I reworked it a little bit to simplify the code
> > in pci_alloc_child_bus().  Can you test it and make sure I didn't
> > break anything?
> >
> Hi Bjorn,
> 
> Your rework works as expected. Tested on LS1043A platform with kernel 4.17-rc1, and with some backport on kernel 4.1.35
> 
> Suggestion : maybe change the pci_info() string to have :
>      pci_bus 0000:xx: extended config space not accessible
> instead of
>      pci_bus 0000:xx: extended config space not accessible on secondary bus
> as xx is already the number of the secondary bus

Oops, when I wrote that I was thinking it would be printed for the
bridge device (not the bus).  I changed it as you suggest.

Interesting, I didn't think about the fact that pci_info() would work
on a struct pci_bus * as well as on a struct pci_dev *, since it's a
macro and they both have a "dev" member.

> Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=off to
> have the PMC devices behind the PCI-to-PCIe bridge of the PMC safely
> detected/configured. But this is not caused by the patch.

> Without pcie_aspm=off I saw this at one boot :
>     "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this bridge, but devices
>     correctly detected/configured
> but at most boots I get :
>     no ASPM message but "pci 0000:04:02.0: bridge configuration invalid ([bus ff-ff]), reconfiguring "
>     instead, and some devices are missing. Also lspci show "rev ff" for some devices.
> I don't see this problem on 4.1.35 with the same backported patch.

This is interesting, especially since you have this unusual topology
of a path to the device that is PCIe, then conventional PCI, then PCIe
again.  We *should* be able to use ASPM on the PCIe links, but it's
definitely not a well-tested scenario.

Can you tell if something is actually broken?  Sinan's recent change,
04875177dbe0 ("PCI/ASPM: Don't warn if already in common clock mode"),
which appeared in v4.17-rc1, turns off the message in some cases.

The "bridge configuration invalid" message just means the firmware
didn't configure the bridge.  We *should* still set it up correctly,
but please report a bug if we don't.

lspci showing "ff" for some devices might be a symptom of the devices
being powered off.  In that case config reads normally return ~0 data
(though on your platform maybe it would cause exceptions).  I've seen
this in other situations and wondered if it would be worth adding a
hint to lspci so it could say "device may be powered off".

Anyway, if you are seeing something broken (more than just the
messages), please start a new thread about each one.  If you do, could
you please:

  - open a report at https://bugzilla.kernel.org/, in the Drivers/PCI
    component (open a separate bug for each issue you see)

  - use kernel version 4.17-rc1 and mark it as a regression if
    appropriate

  - attach (don't paste inline) the complete dmesg log and "lspci -vv"
    output (as root) to the bug

  - post a note to linux-pci@vger.kernel.org, cc Fred, Sinan, and me,
    and include the link to the bugzilla

Bjorn

Re: [PATCH] PCI: Check whether bridges allow access to extended config space

[Bjorn Helgaas]

On Fri, May 04, 2018 at 03:06:00PM -0500, Bjorn Helgaas wrote:
> On Fri, May 04, 2018 at 03:45:07PM +0000, Gilles Buloz wrote:
> > Le 04/05/2018 00:31, Bjorn Helgaas a écrit :
> > > [+cc LKML]
> > >
> > > On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
> > >> Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR
> > >>
> > >> Even if a device supports extended config access, no such access must be
> > >> done to this device If there's a bridge not supporting that in the path
> > >> to this device. Doing such access with UR reporting enabled on the root
> > >> bridge leads to an exception.
> > >>
> > >> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
> > >> the following bus topology :
> > >>    LS1043 PCIe root
> > >>      -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
> > >>        -> PMC slot connector (for legacy PMC modules)
> > >> With a PMC module topology as follows :
> > >>    PMC connector
> > >>      -> PCI-to-PCIe bridge
> > >>        -> PCIe switch (4 ports)
> > >>          -> 4 PCIe devices (one on each port)
> > >> In this case all devices behind the PEX8112 are supporting extended config
> > >> access but this is prohibited by the PEX8112. Without this patch, an
> > >> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
> > >>
> > >> This patch checks the parent bridge of each allocated child bus to know if
> > >> extended config access is supported on the child bus, and sets a flag in
> > >> child->bus_flags if not supported. This  flag is inherited by all children
> > >> buses of this child bus and then is checked to avoid this unsupported
> > >> accesses to every device on these buses.
> > > Hi Gilles,
> > >
> > > Thanks for the patch!  I reworked it a little bit to simplify the code
> > > in pci_alloc_child_bus().  Can you test it and make sure I didn't
> > > break anything?
> > >
> > Hi Bjorn,
> > 
> > Your rework works as expected. Tested on LS1043A platform with kernel
> > 4.17-rc1, and with some backport on kernel 4.1.35

Thanks for testing it!  I applied it to pci/enumeration for v4.18.

I think the ASPM issue below is unrelated.  But I would like to figure out
what's going on there, too, if you have any more information.

> > Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=off to
> > have the PMC devices behind the PCI-to-PCIe bridge of the PMC safely
> > detected/configured. But this is not caused by the patch.
> 
> > Without pcie_aspm=off I saw this at one boot :
> >     "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this bridge, but devices
> >     correctly detected/configured
> > but at most boots I get :
> >     no ASPM message but "pci 0000:04:02.0: bridge configuration invalid ([bus ff-ff]), reconfiguring "
> >     instead, and some devices are missing. Also lspci show "rev ff" for some devices.
> > I don't see this problem on 4.1.35 with the same backported patch.
> 
> This is interesting, especially since you have this unusual topology
> of a path to the device that is PCIe, then conventional PCI, then PCIe
> again.  We *should* be able to use ASPM on the PCIe links, but it's
> definitely not a well-tested scenario.
> 
> Can you tell if something is actually broken?  Sinan's recent change,
> 04875177dbe0 ("PCI/ASPM: Don't warn if already in common clock mode"),
> which appeared in v4.17-rc1, turns off the message in some cases.
> 
> The "bridge configuration invalid" message just means the firmware
> didn't configure the bridge.  We *should* still set it up correctly,
> but please report a bug if we don't.
> 
> lspci showing "ff" for some devices might be a symptom of the devices
> being powered off.  In that case config reads normally return ~0 data
> (though on your platform maybe it would cause exceptions).  I've seen
> this in other situations and wondered if it would be worth adding a
> hint to lspci so it could say "device may be powered off".
> 
> Anyway, if you are seeing something broken (more than just the
> messages), please start a new thread about each one.  If you do, could
> you please:
> 
>   - open a report at https://bugzilla.kernel.org/, in the Drivers/PCI
>     component (open a separate bug for each issue you see)
> 
>   - use kernel version 4.17-rc1 and mark it as a regression if
>     appropriate
> 
>   - attach (don't paste inline) the complete dmesg log and "lspci -vv"
>     output (as root) to the bug
> 
>   - post a note to linux-pci@vger.kernel.org, cc Fred, Sinan, and me,
>     and include the link to the bugzilla
> 
> Bjorn

[PATCH] PCI: Check whether bridges allow access to extended config space

[Bjorn Helgaas]

On Fri, May 04, 2018 at 03:06:00PM -0500, Bjorn Helgaas wrote:
> On Fri, May 04, 2018 at 03:45:07PM +0000, Gilles Buloz wrote:
> > Le 04/05/2018 00:31, Bjorn Helgaas a ?crit :
> > > [+cc LKML]
> > >
> > > On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
> > >> Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR
> > >>
> > >> Even if a device supports extended config access, no such access must be
> > >> done to this device If there's a bridge not supporting that in the path
> > >> to this device. Doing such access with UR reporting enabled on the root
> > >> bridge leads to an exception.
> > >>
> > >> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
> > >> the following bus topology :
> > >>    LS1043 PCIe root
> > >>      -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
> > >>        -> PMC slot connector (for legacy PMC modules)
> > >> With a PMC module topology as follows :
> > >>    PMC connector
> > >>      -> PCI-to-PCIe bridge
> > >>        -> PCIe switch (4 ports)
> > >>          -> 4 PCIe devices (one on each port)
> > >> In this case all devices behind the PEX8112 are supporting extended config
> > >> access but this is prohibited by the PEX8112. Without this patch, an
> > >> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
> > >>
> > >> This patch checks the parent bridge of each allocated child bus to know if
> > >> extended config access is supported on the child bus, and sets a flag in
> > >> child->bus_flags if not supported. This  flag is inherited by all children
> > >> buses of this child bus and then is checked to avoid this unsupported
> > >> accesses to every device on these buses.
> > > Hi Gilles,
> > >
> > > Thanks for the patch!  I reworked it a little bit to simplify the code
> > > in pci_alloc_child_bus().  Can you test it and make sure I didn't
> > > break anything?
> > >
> > Hi Bjorn,
> > 
> > Your rework works as expected. Tested on LS1043A platform with kernel
> > 4.17-rc1, and with some backport on kernel 4.1.35

Thanks for testing it!  I applied it to pci/enumeration for v4.18.

I think the ASPM issue below is unrelated.  But I would like to figure out
what's going on there, too, if you have any more information.

> > Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=off to
> > have the PMC devices behind the PCI-to-PCIe bridge of the PMC safely
> > detected/configured. But this is not caused by the patch.
> 
> > Without pcie_aspm=off I saw this at one boot :
> >     "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this bridge, but devices
> >     correctly detected/configured
> > but at most boots I get :
> >     no ASPM message but "pci 0000:04:02.0: bridge configuration invalid ([bus ff-ff]), reconfiguring "
> >     instead, and some devices are missing. Also lspci show "rev ff" for some devices.
> > I don't see this problem on 4.1.35 with the same backported patch.
> 
> This is interesting, especially since you have this unusual topology
> of a path to the device that is PCIe, then conventional PCI, then PCIe
> again.  We *should* be able to use ASPM on the PCIe links, but it's
> definitely not a well-tested scenario.
> 
> Can you tell if something is actually broken?  Sinan's recent change,
> 04875177dbe0 ("PCI/ASPM: Don't warn if already in common clock mode"),
> which appeared in v4.17-rc1, turns off the message in some cases.
> 
> The "bridge configuration invalid" message just means the firmware
> didn't configure the bridge.  We *should* still set it up correctly,
> but please report a bug if we don't.
> 
> lspci showing "ff" for some devices might be a symptom of the devices
> being powered off.  In that case config reads normally return ~0 data
> (though on your platform maybe it would cause exceptions).  I've seen
> this in other situations and wondered if it would be worth adding a
> hint to lspci so it could say "device may be powered off".
> 
> Anyway, if you are seeing something broken (more than just the
> messages), please start a new thread about each one.  If you do, could
> you please:
> 
>   - open a report at https://bugzilla.kernel.org/, in the Drivers/PCI
>     component (open a separate bug for each issue you see)
> 
>   - use kernel version 4.17-rc1 and mark it as a regression if
>     appropriate
> 
>   - attach (don't paste inline) the complete dmesg log and "lspci -vv"
>     output (as root) to the bug
> 
>   - post a note to linux-pci at vger.kernel.org, cc Fred, Sinan, and me,
>     and include the link to the bugzilla
> 
> Bjorn

Re: [PATCH] PCI: Check whether bridges allow access to extended config space

[Bjorn Helgaas]

On Fri, May 04, 2018 at 03:06:00PM -0500, Bjorn Helgaas wrote:
> On Fri, May 04, 2018 at 03:45:07PM +0000, Gilles Buloz wrote:
> > Le 04/05/2018 00:31, Bjorn Helgaas a =E9crit :
> > > [+cc LKML]
> > >
> > > On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
> > >> Subject:    [PATCH] For exception at PCI probe due to bridge reporti=
ng UR
> > >>
> > >> Even if a device supports extended config access, no such access mus=
t be
> > >> done to this device If there's a bridge not supporting that in the p=
ath
> > >> to this device. Doing such access with UR reporting enabled on the r=
oot
> > >> bridge leads to an exception.
> > >>
> > >> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform wi=
th
> > >> the following bus topology :
> > >>    LS1043 PCIe root
> > >>      -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI si=
de)
> > >>        -> PMC slot connector (for legacy PMC modules)
> > >> With a PMC module topology as follows :
> > >>    PMC connector
> > >>      -> PCI-to-PCIe bridge
> > >>        -> PCIe switch (4 ports)
> > >>          -> 4 PCIe devices (one on each port)
> > >> In this case all devices behind the PEX8112 are supporting extended =
config
> > >> access but this is prohibited by the PEX8112. Without this patch, an
> > >> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
> > >>
> > >> This patch checks the parent bridge of each allocated child bus to k=
now if
> > >> extended config access is supported on the child bus, and sets a fla=
g in
> > >> child->bus_flags if not supported. This  flag is inherited by all ch=
ildren
> > >> buses of this child bus and then is checked to avoid this unsupported
> > >> accesses to every device on these buses.
> > > Hi Gilles,
> > >
> > > Thanks for the patch!  I reworked it a little bit to simplify the code
> > > in pci_alloc_child_bus().  Can you test it and make sure I didn't
> > > break anything?
> > >
> > Hi Bjorn,
> > =

> > Your rework works as expected. Tested on LS1043A platform with kernel
> > 4.17-rc1, and with some backport on kernel 4.1.35

Thanks for testing it!  I applied it to pci/enumeration for v4.18.

I think the ASPM issue below is unrelated.  But I would like to figure out
what's going on there, too, if you have any more information.

> > Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=3Doff to
> > have the PMC devices behind the PCI-to-PCIe bridge of the PMC safely
> > detected/configured. But this is not caused by the patch.
> =

> > Without pcie_aspm=3Doff I saw this at one boot :
> >     "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this=
 bridge, but devices
> >     correctly detected/configured
> > but at most boots I get :
> >     no ASPM message but "pci 0000:04:02.0: bridge configuration invalid=
 ([bus ff-ff]), reconfiguring "
> >     instead, and some devices are missing. Also lspci show "rev ff" for=
 some devices.
> > I don't see this problem on 4.1.35 with the same backported patch.
> =

> This is interesting, especially since you have this unusual topology
> of a path to the device that is PCIe, then conventional PCI, then PCIe
> again.  We *should* be able to use ASPM on the PCIe links, but it's
> definitely not a well-tested scenario.
> =

> Can you tell if something is actually broken?  Sinan's recent change,
> 04875177dbe0 ("PCI/ASPM: Don't warn if already in common clock mode"),
> which appeared in v4.17-rc1, turns off the message in some cases.
> =

> The "bridge configuration invalid" message just means the firmware
> didn't configure the bridge.  We *should* still set it up correctly,
> but please report a bug if we don't.
> =

> lspci showing "ff" for some devices might be a symptom of the devices
> being powered off.  In that case config reads normally return ~0 data
> (though on your platform maybe it would cause exceptions).  I've seen
> this in other situations and wondered if it would be worth adding a
> hint to lspci so it could say "device may be powered off".
> =

> Anyway, if you are seeing something broken (more than just the
> messages), please start a new thread about each one.  If you do, could
> you please:
> =

>   - open a report at https://bugzilla.kernel.org/, in the Drivers/PCI
>     component (open a separate bug for each issue you see)
> =

>   - use kernel version 4.17-rc1 and mark it as a regression if
>     appropriate
> =

>   - attach (don't paste inline) the complete dmesg log and "lspci -vv"
>     output (as root) to the bug
> =

>   - post a note to linux-pci@vger.kernel.org, cc Fred, Sinan, and me,
>     and include the link to the bugzilla
> =

> Bjorn

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH] PCI: Check whether bridges allow access to extended config space

[Gilles Buloz]

[-- Attachment #1: Type: text/plain, Size: 5958 bytes --]

Le 07/05/2018 23:56, Bjorn Helgaas a écrit :
> On Fri, May 04, 2018 at 03:06:00PM -0500, Bjorn Helgaas wrote:
>> On Fri, May 04, 2018 at 03:45:07PM +0000, Gilles Buloz wrote:
>>> Le 04/05/2018 00:31, Bjorn Helgaas a écrit :
>>>> [+cc LKML]
>>>>
>>>> On Thu, May 03, 2018 at 12:40:27PM +0000, Gilles Buloz wrote:
>>>>> Subject:    [PATCH] For exception at PCI probe due to bridge reporting UR
>>>>>
>>>>> Even if a device supports extended config access, no such access must be
>>>>> done to this device If there's a bridge not supporting that in the path
>>>>> to this device. Doing such access with UR reporting enabled on the root
>>>>> bridge leads to an exception.
>>>>>
>>>>> This is the case on a LS1043A CPU (NXP QorIQ Layerscape) platform with
>>>>> the following bus topology :
>>>>>     LS1043 PCIe root
>>>>>       -> PEX8112 PCIe-to-PCI bridge (not supporting ext cfg on PCI side)
>>>>>         -> PMC slot connector (for legacy PMC modules)
>>>>> With a PMC module topology as follows :
>>>>>     PMC connector
>>>>>       -> PCI-to-PCIe bridge
>>>>>         -> PCIe switch (4 ports)
>>>>>           -> 4 PCIe devices (one on each port)
>>>>> In this case all devices behind the PEX8112 are supporting extended config
>>>>> access but this is prohibited by the PEX8112. Without this patch, an
>>>>> exception (synchronous abort) occurs in pci_cfg_space_size_ext().
>>>>>
>>>>> This patch checks the parent bridge of each allocated child bus to know if
>>>>> extended config access is supported on the child bus, and sets a flag in
>>>>> child->bus_flags if not supported. This  flag is inherited by all children
>>>>> buses of this child bus and then is checked to avoid this unsupported
>>>>> accesses to every device on these buses.
>>>> Hi Gilles,
>>>>
>>>> Thanks for the patch!  I reworked it a little bit to simplify the code
>>>> in pci_alloc_child_bus().  Can you test it and make sure I didn't
>>>> break anything?
>>>>
>>> Hi Bjorn,
>>>
>>> Your rework works as expected. Tested on LS1043A platform with kernel
>>> 4.17-rc1, and with some backport on kernel 4.1.35
> Thanks for testing it!  I applied it to pci/enumeration for v4.18.
>
> I think the ASPM issue below is unrelated.  But I would like to figure out
> what's going on there, too, if you have any more information.
Hi Bjorn,

Here are full dmesg + lspci -vv + ... for the following cases :
- 4.17-rc1_probe_failed_without_pcieaspmoff.txt : I get a broken PCI config at most boots, without pcie_aspm=off
- 4.17-rc1_probe_ok_without_pcieaspmoff.txt : I get a correct PCI config at some boots, even without pcie_aspm=off
- 4.17-rc1_probe_always_ok_with_pcieaspmoff.txt : I get a correct PCI config at all boots when using pcie_aspm=off
- 4.1.35_probe_always_ok_without_pcieaspmoff.txt : I get a correct PCI config at all boots when using kernel 4.1.35-rt41 (from NXP 
Yocto BSP), even without pcie_aspm=off

I noticed these strange things :
- with 4.17-rc1, without pcie_aspm=off, the kernel is hanging during ~1 second :
   - before line "ASPM: Could not configure common clock" when PCI config is OK
   - or before line "bridge configuration invalid ([bus ff-ff]), reconfiguring" when PCI config is NOT OK
     (the FFs in "[bus ff-ff]" seems side effects of read returning ~0 because device is off)
- no such hang when pcie_aspm=off is used
- applying reverse patch for "PCI/ASPM: Don't warn if already in common clock mode"
   (commit 04875177dbe034055f23960981ecf6fb8ea1d638) does not give more message

>>> Info : with kernel 4.17-rc1, it turns out I need pcie_aspm=off to
>>> have the PMC devices behind the PCI-to-PCIe bridge of the PMC safely
>>> detected/configured. But this is not caused by the patch.
>>> Without pcie_aspm=off I saw this at one boot :
>>>      "pci 0000:02:0e.0: ASPM: Could not configure common clock" for this bridge, but devices
>>>      correctly detected/configured
>>> but at most boots I get :
>>>      no ASPM message but "pci 0000:04:02.0: bridge configuration invalid ([bus ff-ff]), reconfiguring "
>>>      instead, and some devices are missing. Also lspci show "rev ff" for some devices.
>>> I don't see this problem on 4.1.35 with the same backported patch.
>> This is interesting, especially since you have this unusual topology
>> of a path to the device that is PCIe, then conventional PCI, then PCIe
>> again.  We *should* be able to use ASPM on the PCIe links, but it's
>> definitely not a well-tested scenario.
>>
>> Can you tell if something is actually broken?  Sinan's recent change,
>> 04875177dbe0 ("PCI/ASPM: Don't warn if already in common clock mode"),
>> which appeared in v4.17-rc1, turns off the message in some cases.
>>
>> The "bridge configuration invalid" message just means the firmware
>> didn't configure the bridge.  We *should* still set it up correctly,
>> but please report a bug if we don't.
>>
>> lspci showing "ff" for some devices might be a symptom of the devices
>> being powered off.  In that case config reads normally return ~0 data
>> (though on your platform maybe it would cause exceptions).  I've seen
>> this in other situations and wondered if it would be worth adding a
>> hint to lspci so it could say "device may be powered off".
>>
>> Anyway, if you are seeing something broken (more than just the
>> messages), please start a new thread about each one.  If you do, could
>> you please:
>>
>>    - open a report at https://bugzilla.kernel.org/, in the Drivers/PCI
>>      component (open a separate bug for each issue you see)
>>
>>    - use kernel version 4.17-rc1 and mark it as a regression if
>>      appropriate
>>
>>    - attach (don't paste inline) the complete dmesg log and "lspci -vv"
>>      output (as root) to the bug
>>
>>    - post a note to linux-pci@vger.kernel.org, cc Fred, Sinan, and me,
>>      and include the link to the bugzilla
>>
>> Bjorn
> .
>


[-- Attachment #2: 4.1.35_probe_always_ok_without_pcieaspmoff.txt --]
[-- Type: text/plain, Size: 43211 bytes --]

[    0.000000] Booting Linux on physical CPU 0x0 
[    0.000000] Initializing cgroup subsys cpu 
[    0.000000] Linux version 4.1.35-rt41 (build@debian) (gcc version 4.9.3 20150311 (prerelease) (Linaro GCC 4.9-2015.03) ) #2 SMP Mon Jan 22 08:02:50 EST 2018 
[    0.000000] CPU: AArch64 Processor [410fd034] revision 4 
[    0.000000] Detected VIPT I-cache on CPU0 
[    0.000000] alternatives: enabling workaround for ARM erratum 845719 
[    0.000000] earlycon: Early serial console at MMIO 0x21c0500 (options '') 
[    0.000000] bootconsole [uart0] enabled 
[    0.000000] efi: Getting EFI parameters from FDT: 
[    0.000000] efi: UEFI not found. 
[    0.000000] Reserved memory: initialized node bman-fbpr, compatible id fsl,bman-fbpr 
[    0.000000] Reserved memory: initialized node qman-fqd, compatible id fsl,qman-fqd 
[    0.000000] Reserved memory: initialized node qman-pfdr, compatible id fsl,qman-pfdr 
[    0.000000] cma: Reserved 128 MiB at 0x00000000f7c00000 
[    0.000000] /cpus/cpu@2: missing enable-method property 
[    0.000000] /cpus/cpu@3: missing enable-method property 
[    0.000000] WARNING: x1-x3 nonzero in violation of boot protocol: 
[    0.000000]  x1: 0000000000000000 
[    0.000000]  x2: 0000000000000000 
[    0.000000]  x3: 0000000080080000 
[    0.000000] This indicates a broken bootloader or old kernel 
[    0.000000] PERCPU: Embedded 18 pages/cpu @ffff80087fd92000 s34880 r8192 d30656 u73728 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 1031688 
[    0.000000] Kernel command line: console=ttyS0,115200 root=/dev/mmcblk0p1 rw rootwait mtdparts=1550000.quadspi:2m(uboot),256k(boot-env),-(User_Data) earlycon=uart8250,mmio,0x
21c0500 cma=128M cpld_i2c.smb_tmo=0 
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) 
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) 
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) 
[    0.000000] software IO TLB [mem 0xf3c00000-0xf7c00000] (64MB) mapped at [ffff800073c00000-ffff800077bfffff] 
[    0.000000] Memory: 3852804K/4192256K available (7798K kernel code, 583K rwdata, 3128K rodata, 480K init, 755K bss, 208380K reserved, 131072K cma-reserved) 
[    0.000000] Virtual kernel memory layout: 
[    0.000000]     vmalloc : 0xffff000000000000 - 0xffff7bffbfff0000   (126974 GB) 
[    0.000000]     vmemmap : 0xffff7bffc0000000 - 0xffff7fffc0000000   (  4096 GB maximum) 
[    0.000000]               0xffff7bffc0000000 - 0xffff7bffe1ff8000   (   543 MB actual) 
[    0.000000]     fixed   : 0xffff7ffffabfd000 - 0xffff7ffffac00000   (    12 KB) 
[    0.000000]     PCI I/O : 0xffff7ffffae00000 - 0xffff7ffffbe00000   (    16 MB) 
[    0.000000]     modules : 0xffff7ffffc000000 - 0xffff800000000000   (    64 MB) 
[    0.000000]     memory  : 0xffff800000000000 - 0xffff80087fe00000   ( 34814 MB) 
[    0.000000]       .init : 0xffff800000b2e000 - 0xffff800000ba6000   (   480 KB) 
[    0.000000]       .text : 0xffff800000080000 - 0xffff800000b2d954   ( 10935 KB) 
[    0.000000]       .data : 0xffff800000bb8000 - 0xffff800000c49e00   (   584 KB) 
[    0.000000] Hierarchical RCU implementation. 
[    0.000000]  Additional per-CPU info printed with stalls. 
[    0.000000]  RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2. 
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 
[    0.000000] NR_IRQS:64 nr_irqs:64 0 
[    0.000000] Architected cp15 timer(s) running at 25.00MHz (phys). 
[    0.000000] clocksource arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x5c40939b5, max_idle_ns: 440795202646 ns 
[    0.000003] sched_clock: 56 bits at 25MHz, resolution 40ns, wraps every 4398046511100ns 
[    0.008383] Console: colour dummy device 80x25 
[    0.012855] Calibrating delay loop (skipped), value calculated using timer frequency.. 50.00 BogoMIPS (lpj=250000) 
[    0.023265] pid_max: default: 32768 minimum: 301 
[    0.027970] Security Framework initialized 
[    0.032123] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes) 
[    0.038857] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes) 
[    0.046497] Initializing cgroup subsys memory 
[    0.050889] Initializing cgroup subsys hugetlb 
[    0.055507] hw perfevents: enabled with arm/armv8-pmuv3 PMU driver, 7 counters available 
[    0.063663] EFI services will not be available. 
[    0.069070] CPU1: Booted secondary processor 
[    0.069075] Detected VIPT I-cache on CPU1 
[    0.069134] Brought up 2 CPUs 
[    0.080421] SMP: Total of 2 processors activated. 
[    0.085142] CPU: All CPU(s) started at EL2 
[    0.089267] alternatives: patching kernel code 
[    0.094043] devtmpfs: initialized 
[    0.101588] DMI not present or invalid. 
[    0.105575] clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns 
[    0.119580] pinctrl core: initialized pinctrl subsystem 
[    0.125806] NET: Registered protocol family 16 
[    0.175458] cpuidle: using governor ladder 
[    0.215464] cpuidle: using governor menu 
[    0.219454] fsl-mc bus type registered 
[    0.223255] MC object device driver fsl_mc_dprc registered 
[    0.228794] MC object device driver fsl_mc_allocator registered 
[    0.234774] Bman ver:0a02,02,01 
[    0.242273] qman-fqd addr 0x00000008ff000000 size 0x800000 
[    0.247782] qman-pfdr addr 0x00000008fc000000 size 0x2000000 
[    0.253473] Qman ver:0a01,03,02,00 
[    0.257078] vdso: 2 pages (1 code @ ffff800000bbd000, 1 data @ ffff800000bbc000) 
[    0.264543] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. 
[    0.271917] DMA: preallocated 256 KiB pool for atomic allocations 
[    0.278174] Serial: AMBA PL011 UART driver 
[    0.283357] Machine: VM6103 Board 
[    0.286681] SoC family: QorIQ LS1043A 
[    0.290366] SoC ID: svr:0x87920a10, Revision: 1.0 
[    0.332206] RCPM: layerscape_rcpm_init: The RCPM driver initialized. 
[    0.339362] vgaarb: loaded 
[    0.342247] SCSI subsystem initialized 
[    0.346318] usbcore: registered new interface driver usbfs 
[    0.351874] usbcore: registered new interface driver hub 
[    0.357239] usbcore: registered new device driver usb 
[    0.362933] i2c i2c-0: IMX I2C adapter registered 
[    0.367679] i2c i2c-0: can't use DMA 
[    0.371390] pps_core: LinuxPPS API ver. 1 registered 
[    0.376380] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> 
[    0.385576] PTP clock support registered 
[    0.389703] bman-fbpr addr 0x00000008fe000000 size 0x1000000 
[    0.395410] Bman err interrupt handler present 
[    0.400365] Bman portal initialised, cpu 0 
[    0.404557] Bman portal initialised, cpu 1 
[    0.408667] Bman portals initialised 
[    0.413135] Qman err interrupt handler present 
[    0.418052] QMan: Allocated lookup table at ffff000000205000, entry count 131073 
[    0.425958] Qman portal initialised, cpu 0 
[    0.430142] Qman portal initialised, cpu 1 
[    0.434252] Qman portals initialised 
[    0.437971] Bman: BPID allocator includes range 32:32 
[    0.443095] Qman: FQID allocator includes range 256:256 
[    0.448348] Qman: FQID allocator includes range 32768:32768 
[    0.454003] Qman: CGRID allocator includes range 0:256 
[    0.459311] Qman: pool channel allocator includes range 1025:15 
[    0.465334] No USDPAA memory, no 'fsl,usdpaa-mem' in device-tree 
[    0.471418] fsl-ifc 1530000.ifc: Freescale Integrated Flash Controller 
[    0.477985] fsl-ifc 1530000.ifc: IFC version 1.4, 8 banks 
[    0.484098] Switched to clocksource arch_sys_counter 
[    0.494547] NET: Registered protocol family 2 
[    0.499302] TCP established hash table entries: 32768 (order: 6, 262144 bytes) 
[    0.506874] TCP bind hash table entries: 32768 (order: 7, 524288 bytes) 
[    0.514095] TCP: Hash tables configured (established 32768 bind 32768) 
[    0.520702] UDP hash table entries: 2048 (order: 4, 65536 bytes) 
[    0.526829] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes) 
[    0.533488] NET: Registered protocol family 1 
[    0.538039] RPC: Registered named UNIX socket transport module. 
[    0.543985] RPC: Registered udp transport module. 
[    0.548719] RPC: Registered tcp transport module. 
[    0.553441] RPC: Registered tcp NFSv4.1 backchannel transport module. 
[    0.560280] hw perfevents: Failed to find logical CPU for cpu 
[    0.566386] kvm [1]: interrupt-controller@1404000 IRQ9 
[    0.571745] kvm [1]: timer IRQ3 
[    0.574908] kvm [1]: Hyp mode initialized successfully 
[    0.581661] futex hash table entries: 512 (order: 3, 32768 bytes) 
[    0.587853] audit: initializing netlink subsys (disabled) 
[    0.593294] audit: type=2000 audit(0.540:1): initialized 
[    0.599010] HugeTLB registered 2 MB page size, pre-allocated 0 pages 
[    0.605786] VFS: Disk quotas dquot_6.6.0 
[    0.609755] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) 
[    0.617151] NFS: Registering the id_resolver key type 
[    0.622241] Key type id_resolver registered 
[    0.626447] Key type id_legacy registered 
[    0.630590] fuse init (API version 7.23) 
[    0.634831] 9p: Installing v9fs 9p2000 file system support 
[    0.641086] io scheduler noop registered 
[    0.645060] io scheduler cfq registered (default) 
[    0.649973] ls-scfg-msi soc:msi-controller: ibs_shift:3 msir_irqs:32 msir_base:0x4 
[    0.657898] Find msi-controller /soc/msi-controller 
[    0.664517] PCI host bridge /soc/pcie@3400000 ranges: 
[    0.669601]    IO 0x4000010000..0x400001ffff -> 0x00000000 
[    0.675123]   MEM 0x4040000000..0x407fffffff -> 0x40000000 
[    0.680749] layerscape-pcie 3400000.pcie: PCI host bridge to bus 0000:00 
[    0.687495] pci_bus 0000:00: root bus resource [bus 00-ff] 
[    0.693006] pci_bus 0000:00: root bus resource [io  0x0000-0xffff] 
[    0.699224] pci_bus 0000:00: root bus resource [mem 0x4040000000-0x407fffffff] (bus address [0x40000000-0x7fffffff]) 
[    0.710694] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force' 
[    0.720917] pci_bus 0000:02: extended config space not accessible on secondary bus 
[    0.730067] pci_bus 0000:03: extended config space not accessible on secondary bus 
[    0.738153] pci 0000:03:00.0: of_irq_parse_pci() failed with rc=-19 
[    0.744858] pci_bus 0000:04: extended config space not accessible on secondary bus 
[    0.752983] pci 0000:04:02.0: of_irq_parse_pci() failed with rc=-19 
[    0.759863] pci 0000:04:03.0: of_irq_parse_pci() failed with rc=-19 
[    0.766746] pci 0000:04:04.0: of_irq_parse_pci() failed with rc=-19 
[    0.773627] pci 0000:04:05.0: of_irq_parse_pci() failed with rc=-19 
[    0.780369] pci_bus 0000:05: extended config space not accessible on secondary bus 
[    0.789109] pci_bus 0000:06: extended config space not accessible on secondary bus 
[    0.797851] pci_bus 0000:07: extended config space not accessible on secondary bus 
[    0.806592] pci_bus 0000:08: extended config space not accessible on secondary bus 
[    0.815692] pci 0000:00:00.0: BAR 8: assigned [mem 0x4040000000-0x404bffffff] 
[    0.822866] pci 0000:00:00.0: BAR 9: assigned [mem 0x404c000000-0x404c0fffff 64bit pref] 
[    0.831007] pci 0000:00:00.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    0.837138] pci 0000:00:00.0: BAR 6: assigned [mem 0x404c100000-0x404c1007ff pref] 
[    0.844757] pci 0000:01:00.0: BAR 8: assigned [mem 0x4040000000-0x404bffffff] 
[    0.851928] pci 0000:01:00.0: BAR 0: assigned [mem 0x404c000000-0x404c00ffff 64bit pref] 
[    0.860106] pci 0000:01:00.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    0.866240] pci 0000:02:09.0: BAR 1: assigned [mem 0x4040000000-0x4047ffffff] 
[    0.873424] pci 0000:02:09.0: BAR 0: assigned [mem 0x4048000000-0x40480fffff] 
[    0.880613] pci 0000:02:0e.0: BAR 8: assigned [mem 0x4048100000-0x40484fffff] 
[    0.887791] pci 0000:02:0e.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    0.893915] pci 0000:03:00.0: BAR 8: assigned [mem 0x4048100000-0x40484fffff] 
[    0.901093] pci 0000:03:00.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    0.907225] pci 0000:04:02.0: BAR 8: assigned [mem 0x4048100000-0x40481fffff] 
[    0.914403] pci 0000:04:03.0: BAR 8: assigned [mem 0x4048200000-0x40482fffff] 
[    0.921574] pci 0000:04:04.0: BAR 8: assigned [mem 0x4048300000-0x40483fffff] 
[    0.928752] pci 0000:04:05.0: BAR 8: assigned [mem 0x4048400000-0x40484fffff] 
[    0.935929] pci 0000:04:02.0: BAR 7: assigned [io  0x1000-0x1fff] 
[    0.942051] pci 0000:04:03.0: BAR 7: assigned [io  0x2000-0x2fff] 
[    0.948180] pci 0000:04:04.0: BAR 7: assigned [io  0x3000-0x3fff] 
[    0.954309] pci 0000:04:05.0: BAR 7: assigned [io  0x4000-0x4fff] 
[    0.960434] pci 0000:05:00.0: BAR 0: assigned [mem 0x4048100000-0x404811ffff] 
[    0.967628] pci 0000:05:00.0: BAR 3: assigned [mem 0x4048120000-0x4048123fff] 
[    0.974821] pci 0000:05:00.0: BAR 2: assigned [io  0x1000-0x101f] 
[    0.980958] pci 0000:04:02.0: PCI bridge to [bus 05] 
[    0.985958] pci 0000:04:02.0:   bridge window [io  0x1000-0x1fff] 
[    0.992099] pci 0000:04:02.0:   bridge window [mem 0x4048100000-0x40481fffff] 
[    0.999318] pci 0000:06:00.0: BAR 0: assigned [mem 0x4048200000-0x404821ffff] 
[    1.006512] pci 0000:06:00.0: BAR 3: assigned [mem 0x4048220000-0x4048223fff] 
[    1.013699] pci 0000:06:00.0: BAR 2: assigned [io  0x2000-0x201f] 
[    1.019843] pci 0000:04:03.0: PCI bridge to [bus 06] 
[    1.024842] pci 0000:04:03.0:   bridge window [io  0x2000-0x2fff] 
[    1.030982] pci 0000:04:03.0:   bridge window [mem 0x4048200000-0x40482fffff] 
[    1.038199] pci 0000:07:00.0: BAR 0: assigned [mem 0x4048300000-0x404831ffff] 
[    1.045396] pci 0000:07:00.0: BAR 3: assigned [mem 0x4048320000-0x4048323fff] 
[    1.052582] pci 0000:07:00.0: BAR 2: assigned [io  0x3000-0x301f] 
[    1.058726] pci 0000:04:04.0: PCI bridge to [bus 07] 
[    1.063719] pci 0000:04:04.0:   bridge window [io  0x3000-0x3fff] 
[    1.069866] pci 0000:04:04.0:   bridge window [mem 0x4048300000-0x40483fffff] 
[    1.077083] pci 0000:08:00.0: BAR 0: assigned [mem 0x4048400000-0x404841ffff] 
[    1.084277] pci 0000:08:00.0: BAR 3: assigned [mem 0x4048420000-0x4048423fff] 
[    1.091463] pci 0000:08:00.0: BAR 2: assigned [io  0x4000-0x401f] 
[    1.097606] pci 0000:04:05.0: PCI bridge to [bus 08] 
[    1.102599] pci 0000:04:05.0:   bridge window [io  0x4000-0x4fff] 
[    1.108746] pci 0000:04:05.0:   bridge window [mem 0x4048400000-0x40484fffff] 
[    1.115960] pci 0000:03:00.0: PCI bridge to [bus 04-08] 
[    1.121214] pci 0000:03:00.0:   bridge window [io  0x1000-0x4fff] 
[    1.127364] pci 0000:03:00.0:   bridge window [mem 0x4048100000-0x40484fffff] 
[    1.134578] pci 0000:02:0e.0: PCI bridge to [bus 03-08] 
[    1.139832] pci 0000:02:0e.0:   bridge window [io  0x1000-0x4fff] 
[    1.145978] pci 0000:02:0e.0:   bridge window [mem 0x4048100000-0x40484fffff] 
[    1.153181] pci 0000:01:00.0: PCI bridge to [bus 02-08] 
[    1.158441] pci 0000:01:00.0:   bridge window [io  0x1000-0x4fff] 
[    1.164586] pci 0000:01:00.0:   bridge window [mem 0x4040000000-0x404bffffff] 
[    1.171788] pci 0000:00:00.0: PCI bridge to [bus 01-08] 
[    1.177042] pci 0000:00:00.0:   bridge window [io  0x1000-0x4fff] 
[    1.183166] pci 0000:00:00.0:   bridge window [mem 0x4040000000-0x404bffffff] 
[    1.190343] pci 0000:00:00.0:   bridge window [mem 0x404c000000-0x404c0fffff 64bit pref] 
[    1.198742] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt 
[    1.205746] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt 
[    1.212304] pci 0000:02:09.0: Signaling PME through PCIe PME interrupt 
[    1.218868] pci 0000:02:0e.0: Signaling PME through PCIe PME interrupt 
[    1.225431] pci 0000:03:00.0: Signaling PME through PCIe PME interrupt 
[    1.231988] pci 0000:04:02.0: Signaling PME through PCIe PME interrupt 
[    1.238552] pci 0000:05:00.0: Signaling PME through PCIe PME interrupt 
[    1.245115] pci 0000:04:03.0: Signaling PME through PCIe PME interrupt 
[    1.251672] pci 0000:06:00.0: Signaling PME through PCIe PME interrupt 
[    1.258239] pci 0000:04:04.0: Signaling PME through PCIe PME interrupt 
[    1.264802] pci 0000:07:00.0: Signaling PME through PCIe PME interrupt 
[    1.271360] pci 0000:04:05.0: Signaling PME through PCIe PME interrupt 
[    1.277923] pci 0000:08:00.0: Signaling PME through PCIe PME interrupt 
[    1.285861] PCI host bridge /soc/pcie@3500000 ranges: 
[    1.290943]    IO 0x4800010000..0x480001ffff -> 0x00000000 
[    1.296465]   MEM 0x4840000000..0x487fffffff -> 0x40000000 
[    1.302084] layerscape-pcie 3500000.pcie: PCI host bridge to bus 0001:00 
[    1.308827] pci_bus 0001:00: root bus resource [bus 00-ff] 
[    1.314347] pci_bus 0001:00: root bus resource [io  0x10000-0x1ffff] (bus address [0x0000-0xffff]) 
[    1.323353] pci_bus 0001:00: root bus resource [mem 0x4840000000-0x487fffffff] (bus address [0x40000000-0x7fffffff]) 
[    1.334162] pci 0001:00:00.0: bridge configuration invalid ([bus 0a-0a]), reconfiguring 
[    1.342295] pci 0001:00:00.0: BAR 6: assigned [mem 0x4840000000-0x48400007ff pref] 
[    1.349911] pci 0001:00:00.0: PCI bridge to [bus 01] 
[    1.355009] pcieport 0001:00:00.0: Signaling PME through PCIe PME interrupt 
[    1.362298] PCI host bridge /soc/pcie@3600000 ranges: 
[    1.367388]    IO 0x5000010000..0x500001ffff -> 0x00000000 
[    1.372900]   MEM 0x5040000000..0x507fffffff -> 0x40000000 
[    1.378517] layerscape-pcie 3600000.pcie: PCI host bridge to bus 0002:00 
[    1.385263] pci_bus 0002:00: root bus resource [bus 00-ff] 
[    1.390775] pci_bus 0002:00: root bus resource [io  0x20000-0x2ffff] (bus address [0x0000-0xffff]) 
[    1.399789] pci_bus 0002:00: root bus resource [mem 0x5040000000-0x507fffffff] (bus address [0x40000000-0x7fffffff]) 
[    1.410592] pci 0002:00:00.0: bridge configuration invalid ([bus 0c-0c]), reconfiguring 
[    1.418730] pci 0002:00:00.0: BAR 6: assigned [mem 0x5040000000-0x50400007ff pref] 
[    1.426345] pci 0002:00:00.0: PCI bridge to [bus 01] 
[    1.431439] pcieport 0002:00:00.0: Signaling PME through PCIe PME interrupt 
[    1.439359] Freescale LS2 console driver 
[    1.443386] fsl-ls2-console: device fsl_mc_console registered 
[    1.449265] fsl-ls2-console: device fsl_aiop_console registered 
[    1.457800] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled 
[    1.465235] msm_serial: driver initialized 
[    1.469735] console [ttyS0] disabled 
[    1.473344] 21c0500.serial: ttyS0 at MMIO 0x21c0500 (irq = 18, base_baud = 25000000) is a 16550A 
[    1.482194] console [ttyS0] enabled 
[    1.482194] console [ttyS0] enabled 
[    1.489177] bootconsole [uart0] disabled 
[    1.489177] bootconsole [uart0] disabled 
[    1.497372] 21c0600.serial: ttyS1 at MMIO 0x21c0600 (irq = 18, base_baud = 25000000) is a 16550A 
[    1.506432] 21d0500.serial: ttyS2 at MMIO 0x21d0500 (irq = 19, base_baud = 25000000) is a 16550A 
[    1.515524] 21d0600.serial: ttyS3 at MMIO 0x21d0600 (irq = 19, base_baud = 25000000) is a 16550A 
[    1.525393] Unable to detect cache hierarcy from DT for CPU 0 
[    1.535667] brd: module loaded 
[    1.541248] loop: module loaded 
[    1.544619] at24 0-0052: 256 byte 24c02 EEPROM, writable, 1 bytes/write 
[    1.552090] ahci-qoriq 3200000.sata: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl platform mode 
[    1.561059] ahci-qoriq 3200000.sata: flags: 64bit ncq sntf pm clo only pmp fbs pio slum part ccc sds apst  
[    1.571259] scsi host0: ahci-qoriq 
[    1.574827] ata1: SATA max UDMA/133 mmio [mem 0x03200000-0x0320ffff] port 0x100 irq 30 
[    1.583819] fsl-quadspi 1550000.quadspi: Micron EVCR Quad bit not clear 
[    1.590436] fsl-quadspi 1550000.quadspi: Micron quad-read not enabled 
[    1.596879] fsl-quadspi 1550000.quadspi: quad mode not supported 
[    1.602878] fsl-quadspi 1550000.quadspi: Freescale QuadSPI probe failed 
[    1.609508] fsl-quadspi: probe of 1550000.quadspi failed with error -22 
[    1.617053] libphy: Fixed MDIO Bus: probed 
[    1.621252] tun: Universal TUN/TAP device driver, 1.6 
[    1.626303] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> 
[    1.632923] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.638578] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.643622] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.648670] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.653709] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.658755] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.663792] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.668836] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.673878] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.690903] Freescale FM module, FMD API version 21.1.0 
[    1.699761] Freescale FM Ports module 
[    1.703420] fsl_mac: fsl_mac: FSL FMan MAC API based driver 
[    1.709152] fsl_mac 1ae4000.ethernet: FMan MEMAC 
[    1.713768] fsl_mac 1ae4000.ethernet: FMan MAC address: 00:00:de:52:cb:d0 
[    1.720633] fsl_mac 1ae6000.ethernet: FMan MEMAC 
[    1.725253] fsl_mac 1ae6000.ethernet: FMan MAC address: 00:00:de:52:cb:d1 
[    1.732150] fsl_dpa: FSL DPAA Ethernet driver 
[    1.741901] fsl_dpa: fsl_dpa: Probed interface eth0 
[    1.752741] fsl_dpa: fsl_dpa: Probed interface eth1 
[    1.757739] fsl_advanced: FSL DPAA Advanced drivers: 
[    1.762698] fsl_proxy: FSL DPAA Proxy initialization driver 
[    1.768491] fsl_dpa_shared: FSL DPAA Shared Ethernet driver 
[    1.774182] fsl_dpa_macless: FSL DPAA MACless Ethernet driver 
[    1.780032] fsl_oh: FSL FMan Offline Parsing port driver 
[    1.785493] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI 
[    1.792531] e1000: Copyright (c) 1999-2006 Intel Corporation. 
[    1.798342] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k 
[    1.804175] e1000e: Copyright(c) 1999 - 2014 Intel Corporation. 
[    1.810406] e1000e 0000:05:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    1.934110] ata1: SATA link down (SStatus 0 SControl 300) 
[    1.942393] e1000e 0000:05:00.0 eth2: registered PHC clock 
[    1.947883] e1000e 0000:05:00.0 eth2: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:03 
[    1.955798] e1000e 0000:05:00.0 eth2: Intel(R) PRO/1000 Network Connection 
[    1.962755] e1000e 0000:05:00.0 eth2: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    1.969751] e1000e 0000:06:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    2.102215] e1000e 0000:06:00.0 eth3: registered PHC clock 
[    2.107705] e1000e 0000:06:00.0 eth3: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:02 
[    2.115621] e1000e 0000:06:00.0 eth3: Intel(R) PRO/1000 Network Connection 
[    2.122577] e1000e 0000:06:00.0 eth3: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    2.129549] e1000e 0000:07:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    2.262182] e1000e 0000:07:00.0 eth4: registered PHC clock 
[    2.267672] e1000e 0000:07:00.0 eth4: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:01 
[    2.275588] e1000e 0000:07:00.0 eth4: Intel(R) PRO/1000 Network Connection 
[    2.282543] e1000e 0000:07:00.0 eth4: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    2.289514] e1000e 0000:08:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    2.422190] e1000e 0000:08:00.0 eth5: registered PHC clock 
[    2.427680] e1000e 0000:08:00.0 eth5: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:00 
[    2.435595] e1000e 0000:08:00.0 eth5: Intel(R) PRO/1000 Network Connection 
[    2.442552] e1000e 0000:08:00.0 eth5: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    2.449300] sky2: driver version 1.30 
[    2.453877] VFIO - User Level meta-driver version: 0.3 
[    2.459243] vfio_fsl_mc_driver_init: Driver registration fails as no fsl_mc_bus found 
[    3.668517] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver 
[    3.675047] ehci-pci: EHCI PCI platform driver 
[    3.679523] ehci-platform: EHCI generic platform driver 
[    3.684925] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver 
[    3.691105] ohci-pci: OHCI PCI platform driver 
[    3.695588] ohci-platform: OHCI generic platform driver 
[    3.701215] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller 
[    3.706710] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1 
[    3.714622] xhci-hcd xhci-hcd.0.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x00010010 
[    3.723340] xhci-hcd xhci-hcd.0.auto: irq 27, io mem 0x02f00000 
[    3.729701] hub 1-0:1.0: USB hub found 
[    3.733461] hub 1-0:1.0: 1 port detected 
[    3.737579] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller 
[    3.743062] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2 
[    3.750765] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. 
[    3.759238] hub 2-0:1.0: USB hub found 
[    3.762995] hub 2-0:1.0: 1 port detected 
[    3.767122] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller 
[    3.772610] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 3 
[    3.780516] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x00010010 
[    3.789237] xhci-hcd xhci-hcd.1.auto: irq 28, io mem 0x03000000 
[    3.795527] hub 3-0:1.0: USB hub found 
[    3.799285] hub 3-0:1.0: 1 port detected 
[    3.803369] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller 
[    3.808861] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 4 
[    3.816558] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM. 
[    3.825005] hub 4-0:1.0: USB hub found 
[    3.828763] hub 4-0:1.0: 1 port detected 
[    3.832882] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller 
[    3.838380] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 5 
[    3.846324] xhci-hcd xhci-hcd.2.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x00010010 
[    3.855042] xhci-hcd xhci-hcd.2.auto: irq 29, io mem 0x03100000 
[    3.861325] hub 5-0:1.0: USB hub found 
[    3.865138] hub 5-0:1.0: 1 port detected 
[    3.869225] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller 
[    3.874717] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 6 
[    3.882414] usb usb6: We don't know the algorithms for LPM for this host, disabling LPM. 
[    3.890865] hub 6-0:1.0: USB hub found 
[    3.894667] hub 6-0:1.0: 1 port detected 
[    3.898902] usbcore: registered new interface driver usb-storage 
[    3.905111] mousedev: PS/2 mouse device common for all mice 
[    3.910984] rtc-pcf8563 0-0051: chip found, driver version 0.4.3 
[    3.923061] rtc-pcf8563 0-0051: rtc core: registered rtc-pcf8563 as rtc0 
[    3.929789] i2c /dev entries driver 
[    3.935971] ina2xx 0-0040: power monitor ina220 (Rshunt = 1000 uOhm) 
[    3.942392] 0-004c supply vcc not found, using dummy regulator 
[    3.949908] qoriq_cpufreq: Freescale QorIQ CPU frequency scaling driver 
[    3.956599] sdhci: Secure Digital Host Controller Interface driver 
[    3.962769] sdhci: Copyright(c) Pierre Ossman 
[    3.967156] sdhci-pltfm: SDHCI platform and OF driver helper 
[    3.974014] sdhci-esdhc 1560000.esdhc: No vmmc regulator found 
[    3.979850] sdhci-esdhc 1560000.esdhc: No vqmmc regulator found 
[    4.024109] mmc0: SDHCI controller on 1560000.esdhc [1560000.esdhc] using ADMA 64-bit 
[    4.037363] platform caam_qi: Linux CAAM Queue I/F driver initialised 
[    4.043807] caam 1700000.crypto: Instantiated RNG4 SH1 
[    4.048963] caam 1700000.crypto: device ID = 0x0a12060000000000 (Era 8) 
[    4.057581] caam 1700000.crypto: job rings = 4, qi = 1 
[    4.073508] caam algorithms registered in /proc/crypto 
[    4.079720] platform caam_qi: algorithms registered in /proc/crypto 
[    4.087130] caam_jr 1710000.jr: registering rng-caam 
[    4.092265] caam 1700000.crypto: fsl,sec-v5.4 algorithms registered in /proc/crypto 
[    4.099975] MC object device driver fsl_dpaa2_caam registered 
[    4.110208] usbcore: registered new interface driver usbhid 
[    4.115781] usbhid: USB HID core driver 
[    4.119729] fsl-mc bus not found, restool driver registration failed 
[    4.126117] MC object device driver fsl_dpio_drv registered 
[    4.132614] Freescale USDPAA process driver 
[    4.136800] fsl-usdpaa: no region found 
[    4.140630] Freescale USDPAA process IRQ driver 
[    4.145409] MC object device driver fsl_dpaa2_eth registered 
[    4.151082] MC object device driver dpaa2_mac registered 
[    4.156420] MC object device driver dpaa2_ethsw registered 
[    4.161917] MC object device driver dpaa2_evb registered 
[    4.167251] MC object device driver fsl_dce_api registered 
[    4.172749] MC object device driver dpaa2_rtc registered 
[    4.178214] Initializing XFRM netlink socket 
[    4.182550] NET: Registered protocol family 10 
[    4.187715] sit: IPv6 over IPv4 tunneling driver 
[    4.192691] NET: Registered protocol family 17 
[    4.197152] NET: Registered protocol family 15 
[    4.201618] 8021q: 802.1Q VLAN Support v1.8 
[    4.204115] usb 5-1: new full-speed USB device number 2 using xhci-hcd 
[    4.212379] 9pnet: Installing 9P2000 support 
[    4.216697] Key type dns_resolver registered 
[    4.221507] registered taskstats version 1 
[    4.226562] fsl_generic: FSL DPAA Generic Ethernet driver 
[    4.233451] rtc-pcf8563 0-0051: setting system clock to 2018-05-09 09:47:20 UTC (1525859240) 
[    4.242057] fdt: not creating '/sys/firmware/fdt': CRC check failed 
[    4.248891] mmc0: MAN_BKOPS_EN bit is not set 
[    4.253367] Waiting for root device /dev/mmcblk0p1... 
[    4.277745] mmc0: new high speed MMC card at address 0001 
[    4.283355] mmcblk0: mmc0:0001 R1J58L 55.1 GiB  
[    4.287948] mmcblk0boot0: mmc0:0001 R1J58L partition 1 16.0 MiB 
[    4.293918] mmcblk0boot1: mmc0:0001 R1J58L partition 2 16.0 MiB 
[    4.299901] mmcblk0rpmb: mmc0:0001 R1J58L partition 3 128 KiB 
[    4.306338]  mmcblk0: p1 
[    4.345257] usb 5-1: ep 0x81 - rounding interval to 1024 microframes, ep desc says 2000 microframes 
[    4.430707] hid-generic 0003:064F:2AF9.0001: device has no listeners, quitting 
[    4.474497] EXT3-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240) 
[    4.484003] EXT2-fs (mmcblk0p1): error: couldn't mount because of unsupported optional features (240) 
[    4.501944] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode. Opts: (null) 
[    4.510052] VFS: Mounted root (ext4 filesystem) on device 179:1. 
[    4.516975] devtmpfs: mounted 
[    4.520131] Freeing unused kernel memory: 480K (ffff800000b2e000 - ffff800000ba6000) 
[    4.527894] Freeing alternatives memory: 48K (ffff800000ba6000 - ffff800000bb2000) 
[    4.751104] random: systemd urandom read with 7 bits of entropy available 
[    4.759242] systemd[1]: systemd 215 running in system mode. (+PAM +AUDIT +SELINUX +IMA +SYSVINIT +LIBCRYPTSETUP +GCRYPT +ACL +XZ -SECCOMP -APPARMOR) 
[    4.772663] systemd[1]: Detected architecture 'arm64'. 
 
Welcome to 
   Debian GNU/Linux 8 (jessie)
   ! 
 
[    4.814819] systemd[1]: Set hostname to <debian>. 
[    4.991012] systemd[1]: Cannot add dependency job for unit dbus.socket, ignoring: Unit dbus.socket failed to load: No such file or directory. 
[    5.003808] systemd[1]: Cannot add dependency job for unit display-manager.service, ignoring: Unit display-manager.service failed to load: No such file or directory. 
[    5.019425] systemd[1]: Starting Forward Password Requests to Wall Directory Watch. 
[    5.027258] systemd[1]: Started Forward Password Requests to Wall Directory Watch. 
[    5.034889] systemd[1]: Expecting device dev-ttyS0.device... 
         Expecting device dev-ttyS0.device... 
[    5.064172] systemd[1]: Starting Remote File Systems (Pre). 
[
      OK  
   ] Reached target Remote File Systems (Pre). 
[    5.084163] systemd[1]: Reached target Remote File Systems (Pre). 
[    5.090301] systemd[1]: Starting Dispatch Password Requests to Console Directory Watch. 
[    5.098420] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. 
[    5.106380] systemd[1]: Starting Paths. 
[
      OK  
   ] Reached target Paths. 
[    5.124151] systemd[1]: Reached target Paths. 
[    5.128563] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point. 
[    5.137992] systemd[1]: Starting Encrypted Volumes. 
[
      OK  
   ] Reached target Encrypted Volumes. 
[    5.164147] systemd[1]: Reached target Encrypted Volumes. 
[    5.169563] systemd[1]: Starting Swap. 
[
      OK  
   ] Reached target Swap. 
[    5.194154] systemd[1]: Reached target Swap. 
[    5.198445] systemd[1]: Starting Root Slice. 
[
      OK  
   ] Created slice Root Slice. 
[    5.224153] systemd[1]: Created slice Root Slice. 
[    5.228876] systemd[1]: Starting User and Session Slice. 
[
      OK  
   ] Created slice User and Session Slice. 
[    5.254154] systemd[1]: Created slice User and Session Slice. 
[    5.259919] systemd[1]: Starting Delayed Shutdown Socket. 
[
      OK  
   ] Listening on Delayed Shutdown Socket. 
[    5.284153] systemd[1]: Listening on Delayed Shutdown Socket. 
[    5.289919] systemd[1]: Starting /dev/initctl Compatibility Named Pipe. 
[
      OK  
   ] Listening on /dev/initctl Compatibility Named Pipe. 
[    5.314154] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe. 
[    5.321134] systemd[1]: Starting Journal Socket (/dev/log). 
[
      OK  
   ] Listening on Journal Socket (/dev/log). 
[    5.344153] systemd[1]: Listening on Journal Socket (/dev/log). 
[    5.350101] systemd[1]: Starting udev Control Socket. 
[
      OK  
   ] Listening on udev Control Socket. 
[    5.374153] systemd[1]: Listening on udev Control Socket. 
[    5.379578] systemd[1]: Starting udev Kernel Socket. 
[
      OK  
   ] Listening on udev Kernel Socket. 
[    5.404153] systemd[1]: Listening on udev Kernel Socket. 
[    5.409491] systemd[1]: Starting Journal Socket. 
[
      OK  
   ] Listening on Journal Socket. 
[    5.434153] systemd[1]: Listening on Journal Socket. 
[    5.439151] systemd[1]: Starting Sockets. 
[
      OK  
   ] Reached target Sockets. 
[    5.464153] systemd[1]: Reached target Sockets. 
[    5.468707] systemd[1]: Starting System Slice. 
[
      OK  
   ] Created slice System Slice. 
[    5.494154] systemd[1]: Created slice System Slice. 
[    5.499056] systemd[1]: Starting system-getty.slice. 
[
      OK  
   ] Created slice system-getty.slice. 
[    5.524155] systemd[1]: Created slice system-getty.slice. 
[    5.529571] systemd[1]: Starting system-serial\x2dgetty.slice. 
[
      OK  
   ] Created slice system-serial\x2dgetty.slice. 
[    5.554154] systemd[1]: Created slice system-serial\x2dgetty.slice. 
[    5.567813] systemd[1]: Starting Load Kernel Modules... 
         Starting Load Kernel Modules... 
[    5.595066] systemd[1]: Mounting POSIX Message Queue File System... 
         Mounting POSIX Message Queue File System... 
[    5.625686] systemd[1]: Starting Create list of required static device nodes for the current kernel... 
         Starting Create list of required static device nodes...rrent kernel... 
[    5.650912] cpld cpld: CPLD Version 0x0 on CPUA : sysctrl - GEOID 3 
[    5.659591] systemd[1]: Mounting Huge Pages File System... 
         Mounting Huge Pages File System... 
[    5.670147] cpld-wdt: CPLD WDT driver initialized, reset mode, timeout 30 sec (nowayout=0, lock=0). Disabled. 
[    5.687647] systemd[1]: Started Set Up Additional Binary Formats. 
[    5.694226] systemd[1]: Mounting Debug File System... 
         Mounting Debug File System... 
[    5.715090] systemd[1]: Starting udev Coldplug all Devices... 
         Starting udev Coldplug all Devices... 
[    5.735198] systemd[1]: Starting Remount Root and Kernel File Systems... 
         Starting Remount Root and Kernel File Systems... 
[    5.765269] systemd[1]: Starting Journal Service... 
         Starting Journal Service... 
[
      OK  
   ] Started Journal Service. 
[    5.804197] systemd[1]: Started Journal Service. 
[
      OK  
   ] Reached target Slices. 
[
      OK  
   ] Mounted Debug File System. 
[
      OK  
   ] Mounted Huge Pages File System. 
[
      OK  
   ] Mounted POSIX Message Queue File System. 
[
      OK  
   ] Started Load Kernel Modules. 
[
      OK  
   ] Started Create list of required static device nodes ...current kernel. 
[
      OK  
   ] Started Remount Root and Kernel File Systems. 
[
      OK  
   ] Started udev Coldplug all Devices. 
         Starting Load/Save Random Seed... 
         Starting Create Static Device Nodes in /dev... 
         Starting Apply Kernel Variables... 
         Mounting FUSE Control File System... 
[
      OK  
   ] Started Load/Save Random Seed. 
[
      OK  
   ] Started Create Static Device Nodes in /dev. 
[
      OK  
   ] Started Apply Kernel Variables. 
[
      OK  
   ] Mounted FUSE Control File System. 
         Starting udev Kernel Device Manager... 
[
      OK  
   ] Reached target Local File Systems (Pre). 
[    6.243357] systemd-udevd[2201]: starting version 215 
         Mounting /var/tmp... 
         Mounting /tmp... 
[
      OK  
   ] Mounted /var/tmp. 
[
      OK  
   ] Mounted /tmp. 
[
      OK  
   ] Started udev Kernel Device Manager. 
[    6.348411] cpld-i2c: Local EEPROMs on high speed clock 
[    6.353641] cpld-i2c: id 22 
[    6.356450] cpld-i2c: multimaster off 
[    6.360150] cpld-i2c: using IRQ82 
[    6.363455] cpld-i2c: SMB Timeout management : no 
         Starting Copy rules generated while the root was ro... 
         Starting LSB: Tune IDE hard disk[    6.417806] lm73 22-0048: sensor 'lm73' 
s... 
[    6.432365] lm73 22-0049: sensor 'lm73' 
[    6.439492] lm73 22-004a: sensor 'lm73' 
[
      OK  
   ] Reached target Local File Systems. 
[    6.455869] cpld-i2c: id 23 
[    6.458675] cpld-i2c: using IRQ82 
[    6.461981] cpld-i2c: SMB Timeout management : no 
[
      OK  
   ] Reached target Remote File Systems. 
[    6.481591] cpld-i2c: id 24 
[    6.484415] cpld-i2c: using IRQ82 
[    6.487725] cpld-i2c: SMB Timeout management : no 
         Starting Trigger Flushing of Journal to Persistent Storage... 
[    6.504157] cpld-leds: CPLD LEDs driver probe done 
[    6.512938] cpld-gpio: CPLD GPIO driver : 5 GPIOs 
[    6.519035] cpld-gpio: CPLD GPIO driver probe done 
         Starting Create Volatile Files and Directories... 
         Starting LSB: Raise network interfaces.... 
[
      OK  
   ] Started Copy rules generated while the root was ro. 
[
      OK  
   ] Found device /dev/ttyS0. 
[
      OK  
   ] Started LSB: Tune IDE hard disks. 
[
      OK  
   ] Started Create Volatile Files and Directories. 
[    6.660911] systemd-journald[1717]: Received request to flush runtime journal from PID 1 
[
      OK  
   ] Started Trigger Flushing of Journal to Persistent Storage. 
[
      OK  
   ] Created slice system-ifup.slice. 
         Starting Update UTMP about System Boot/Shutdown... 
[    6.785902] ALMA INFO: VME Timeout register has a 8us per bit granularity (can have a timeout until 2.048ms) 
[    6.795746] ALMA INFO: Driver is currently using alma register accesses for holding/releasing the VME bus 
[    6.805331] ALMA INFO: almavme.c: V1.160 
[    6.809247] ALMA INFO: 2ESST Mode enabled 
[    6.813258] ALMA INFO: pcivme_list  ALLOC 0xffff800073308000 
[    6.818923] ALMA INFO: pciio_list  ALLOC 0xffff8008779be000 
[    6.825491] ALMA INFO:  PCI to VME Bridge (Rev 46): Registers area at 0xffff000000f00000 
[
      OK  
   ] Started Update UTMP about System Boot/Shutdown. 
[
      OK  
   ] Started LSB: Raise network interfaces.. 
         Starting ifup for eth0... 
[
      OK  
   ] Started ifup for eth0. 
[
      OK  
   ] Reached target Network. 
[
      OK  
   ] Reached target Network is Online. 
[
      OK  
   ] Reached target System Initialization. 
[
      OK  
   ] Reached target Timers. 
[
      OK  
   ] Reached target Basic System. 
         Starting Internet superserver... 
[
      OK  
   ] Started Internet superserver. 
         Starting Self Monitoring and Reporting Technology (SMART) Daemon... 
[
      OK  
   ] Started Self Monitoring and Reporting Technology (SMART) Daemon. 
         Starting OpenBSD Secure Shell server... 
         Starting Kontron KVX BSP Service... 
         Starting Kontron RTC2 Service... 
         Starting Initialize hardware monitoring sensors... 
         Starting /etc/rc.local Compatibility... 
         Starting getty on tty2-tty6 if dbus and logind are not available... 
         Starting LSB: disk temperature monitoring daemon... 
         Starting Permit User Sessions... 
[
      OK  
   ] Started /etc/rc.local Compatibility. 
[
      OK  
   ] Started LSB: disk temperature monitoring daemon. 
[
      OK  
   ] Started Permit User Sessions. 
[
      OK  
   ] Started Initialize hardware monitoring sensors. 
[
      OK  
   ] Started Kontron RTC2 Service. 
         Starting Getty on tty4... 
[
      OK  
   ] Started Getty on tty4. 
         Starting Getty on tty3... 
[
      OK  
   ] Started Getty on tty3. 
         Starting Getty on tty2... 
[
      OK  
   ] Started Getty on tty2. 
         Starting Getty on tty1... 
[
      OK  
   ] Started Getty on tty1. 
         Starting Serial Getty on ttyS0... 
[
      OK  
   ] Started Serial Getty on ttyS0. 
[
      OK  
   ] Started OpenBSD Secure Shell server. 
[
      OK  
   ] Started Kontron KVX BSP Service. 
         Starting Getty on tty6... 
[
      OK  
   ] Started Getty on tty6. 
         Starting Getty on tty5... 
[
      OK  
   ] Started Getty on tty5. 
[
      OK  
   ] Started getty on tty2-tty6 if dbus and logind are not available. 
[
      OK  
   ] Reached target Login Prompts. 
[
      OK  
   ] Reached target Multi-User System. 
[
      OK  
   ] Reached target Graphical Interface. 
         Starting Update UTMP about System Runlevel Changes... 
[
      OK  
   ] Started Update UTMP about System Runlevel Changes. 
  
Debian GNU/Linux 8 debian ttyS0 
 
debian login: root  
Password:  
Last login: Wed May  9 09:45:51 UTC 2018 on ttyS0 
Linux debian 4.1.35-rt41 #2 SMP Mon Jan 22 08:02:50 EST 2018 aarch64 
 
The programs included with the Debian GNU/Linux system are free software; 
the exact distribution terms for each program are described in the 
individual files in /usr/share/doc/*/copyright. 
 
Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent 
permitted by applicable law. 
root@debian:~# ls -ltr /boot 

[-- Attachment #3: 4.17-rc1_probe_always_ok_with_pcieaspmoff.txt --]
[-- Type: text/plain, Size: 70092 bytes --]

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] 
[    0.000000] Linux version 4.17.0-rc1 (root@debian) (gcc version 4.9.2 (Debian/Linaro 4.9.2-10)) #3 SMP Fri May 4 10:03:38 UTC 2018 
[    0.000000] Machine model: VM6103 Board 
[    0.000000] earlycon: uart8250 at MMIO 0x00000000021c0500 (options '') 
[    0.000000] bootconsole [uart8250] enabled 
[    0.000000] efi: Getting EFI parameters from FDT: 
[    0.000000] efi: UEFI not found. 
[    0.000000] cma: Reserved 128 MiB at 0x00000000f7c00000 
[    0.000000] /cpus/cpu@2: missing enable-method property 
[    0.000000] /cpus/cpu@3: missing enable-method property 
[    0.000000] WARNING: x1-x3 nonzero in violation of boot protocol: 
[    0.000000]  x1: 0000000000000000 
[    0.000000]  x2: 0000000000000000 
[    0.000000]  x3: 0000000080080000 
[    0.000000] This indicates a broken bootloader or old kernel 
[    0.000000] random: fast init done 
[    0.000000] percpu: Embedded 23 pages/cpu @        (ptrval) s55808 r8192 d30208 u94208 
[    0.000000] Detected VIPT I-cache on CPU0 
[    0.000000] CPU features: detected: Kernel page table isolation (KPTI) 
[    0.000000] CPU features: enabling workaround for ARM erratum 845719 
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1031688 
[    0.000000] Kernel command line: console=ttyS0,115200 root=/dev/mmcblk0p1 rw rootwait mtdparts=1550000.quadspi:2m(uboot),256k(boot-env),-(User_Data) earlycon=uart8250,mmio,0x21c05
00 cma=128M cpld_i2c.smb_tmo=0 pcie_aspm=off 
[    0.000000] PCIe ASPM is disabled 
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) 
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) 
[    0.000000] software IO TLB [mem 0xf3c00000-0xf7c00000] (64MB) mapped at [        (ptrval)-        (ptrval)] 
[    0.000000] Memory: 3853464K/4192256K available (7612K kernel code, 782K rwdata, 2904K rodata, 704K init, 232K bss, 207720K reserved, 131072K cma-reserved) 
[    0.000000] Hierarchical RCU implementation. 
[    0.000000]  RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2. 
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 
[    0.000000] GIC: Using split EOI/Deactivate mode 
[    0.000000] arch_timer: Enabling global workaround for Freescale erratum a005858 
[    0.000000] GIC: PPI14 is secure or misconfigured 
[    0.000000] arch_timer: WARNING: Invalid trigger for IRQ3, assuming level low 
[    0.000000] arch_timer: WARNING: Please fix your firmware 
[    0.000000] arch_timer: CPU0: Trapping CNTVCT access 
[    0.000000] arch_timer: cp15 timer(s) running at 25.00MHz (phys). 
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x5c40939b5, max_idle_ns: 440795202646 ns 
[    0.000003] sched_clock: 56 bits at 25MHz, resolution 40ns, wraps every 4398046511100ns 
[    0.008495] Console: colour dummy device 80x25 
[    0.012978] Calibrating delay loop (skipped), value calculated using timer frequency.. 50.00 BogoMIPS (lpj=100000) 
[    0.023388] pid_max: default: 32768 minimum: 301 
[    0.028102] Security Framework initialized 
[    0.032271] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes) 
[    0.039021] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes) 
[    0.046950] ASID allocator initialised with 32768 entries 
[    0.052433] Hierarchical SRCU implementation. 
[    0.057819] EFI services will not be available. 
[    0.062456] smp: Bringing up secondary CPUs ... 
[    0.067263] Detected VIPT I-cache on CPU1 
[    0.067291] arch_timer: CPU1: Trapping CNTVCT access 
[    0.067298] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] 
[    0.067362] smp: Brought up 1 node, 2 CPUs 
[    0.087062] SMP: Total of 2 processors activated. 
[    0.091791] CPU features: detected: 32-bit EL0 Support 
[    0.100054] CPU: All CPU(s) started at EL2 
[    0.104183] alternatives: patching kernel code 
[    0.109630] devtmpfs: initialized 
[    0.119561] Built 1 zonelists, mobility grouping on.  Total pages: 996134 
[    0.127411] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns 
[    0.137221] futex hash table entries: 512 (order: 4, 65536 bytes) 
[    0.143481] pinctrl core: initialized pinctrl subsystem 
[    0.149560] DMI not present or invalid. 
[    0.153590] NET: Registered protocol family 16 
[    0.158367] audit: initializing netlink subsys (disabled) 
[    0.164375] audit: type=2000 audit(0.112:1): state=initialized audit_enabled=0 res=1 
[    0.172193] cpuidle: using governor ladder 
[    0.176327] cpuidle: using governor menu 
[    0.180450] vdso: 2 pages (1 code @ 00000000ebe4f826, 1 data @ 000000000bede717) 
[    0.187895] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. 
[    0.195275] DMA: preallocated 256 KiB pool for atomic allocations 
[    0.201582] Serial: AMBA PL011 UART driver 
[    0.205971] irq: type mismatch, failed to map hwirq-30 for interrupt-controller@1400000! 
[    0.214920] Machine: VM6103 Board 
[    0.218253] SoC family: QorIQ LS1043A 
[    0.221927] SoC ID: svr:0x87920a10, Revision: 1.0 
[    0.252151] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages 
[    0.259200] cryptd: max_cpu_qlen set to 1000 
[    0.264806] vgaarb: loaded 
[    0.267671] SCSI subsystem initialized 
[    0.271772] usbcore: registered new interface driver usbfs 
[    0.277325] usbcore: registered new interface driver hub 
[    0.282694] usbcore: registered new device driver usb 
[    0.288055] imx-i2c 2180000.i2c: can't get pinctrl, bus recovery not supported 
[    0.295645] i2c i2c-0: IMX I2C adapter registered 
[    0.300385] i2c i2c-0: can't use DMA, using PIO instead. 
[    0.305871] pps_core: LinuxPPS API ver. 1 registered 
[    0.310863] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> 
[    0.320059] PTP clock support registered 
[    0.324122] fsl-ifc 1530000.ifc: Freescale Integrated Flash Controller 
[    0.330702] fsl-ifc 1530000.ifc: IFC version 1.4, 8 banks 
[    0.336898] clocksource: Switched to clocksource arch_sys_counter 
[    0.343125] VFS: Disk quotas dquot_6.6.0 
[    0.347126] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) 
[    0.361423] NET: Registered protocol family 2 
[    0.366149] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes) 
[    0.374076] TCP established hash table entries: 32768 (order: 6, 262144 bytes) 
[    0.381642] TCP bind hash table entries: 32768 (order: 7, 524288 bytes) 
[    0.388862] TCP: Hash tables configured (established 32768 bind 32768) 
[    0.395491] UDP hash table entries: 2048 (order: 4, 65536 bytes) 
[    0.401618] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes) 
[    0.408248] NET: Registered protocol family 1 
[    0.412859] RPC: Registered named UNIX socket transport module. 
[    0.418815] RPC: Registered udp transport module. 
[    0.423543] RPC: Registered tcp transport module. 
[    0.428271] RPC: Registered tcp NFSv4.1 backchannel transport module. 
[    0.435232] hw perfevents: failed to find logical CPU for cpu 
[    0.441045] hw perfevents: failed to find logical CPU for cpu 
[    0.446909] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available 
[    0.455166] kvm [1]: 8-bit VMID 
[    0.458833] kvm [1]: vgic interrupt IRQ1 
[    0.462783] kvm [1]: Invalid trigger for IRQ4, assuming level low 
[    0.468944] GIC: PPI11 is secure or misconfigured 
[    0.473749] kvm [1]: Hyp mode initialized successfully 
[    0.481808] workingset: timestamp_bits=46 max_order=20 bucket_order=0 
[    0.488913] NFS: Registering the id_resolver key type 
[    0.494006] Key type id_resolver registered 
[    0.498212] Key type id_legacy registered 
[    0.502339] fuse init (API version 7.26) 
[    0.506478] 9p: Installing v9fs 9p2000 file system support 
[    0.514472] io scheduler noop registered 
[    0.518446] io scheduler cfq registered (default) 
[    0.523183] io scheduler mq-deadline registered 
[    0.527738] io scheduler kyber registered 
[    0.534227] PCI: OF: host bridge /soc/pcie@3400000 ranges: 
[    0.539773] PCI: OF:    IO 0x4000010000..0x400001ffff -> 0x00000000 
[    0.546081] PCI: OF:   MEM 0x4040000000..0x407fffffff -> 0x40000000 
[    0.552496] layerscape-pcie 3400000.pcie: PCI host bridge to bus 0000:00 
[    0.559241] pci_bus 0000:00: root bus resource [bus 00-ff] 
[    0.564758] pci_bus 0000:00: root bus resource [io  0x0000-0xffff] 
[    0.570974] pci_bus 0000:00: root bus resource [mem 0x4040000000-0x407fffffff] (bus address [0x40000000-0x7fffffff]) 
[    0.586181] pci_bus 0000:02: extended config space not accessible on secondary bus 
[    0.595648] pci 0000:02:0e.0: enabling Extended Tags 
[    0.602334] pci_bus 0000:03: extended config space not accessible on secondary bus 
[    0.610291] pci 0000:03:00.0: enabling Extended Tags 
[    0.617519] pci_bus 0000:04: extended config space not accessible on secondary bus 
[    0.625606] pci 0000:04:02.0: enabling Extended Tags 
[    0.631395] pci 0000:04:03.0: enabling Extended Tags 
[    0.637187] pci 0000:04:04.0: enabling Extended Tags 
[    0.642972] pci 0000:04:05.0: enabling Extended Tags 
[    0.650184] pci_bus 0000:05: extended config space not accessible on secondary bus 
[    0.660830] pci_bus 0000:06: extended config space not accessible on secondary bus 
[    0.671482] pci_bus 0000:07: extended config space not accessible on secondary bus 
[    0.682140] pci_bus 0000:08: extended config space not accessible on secondary bus 
[    0.693177] pci 0000:00:00.0: BAR 8: assigned [mem 0x4040000000-0x404bffffff] 
[    0.700358] pci 0000:00:00.0: BAR 9: assigned [mem 0x404c000000-0x404c0fffff 64bit pref] 
[    0.708496] pci 0000:00:00.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    0.714625] pci 0000:00:00.0: BAR 6: assigned [mem 0x404c100000-0x404c1007ff pref] 
[    0.722241] pci 0000:01:00.0: BAR 8: assigned [mem 0x4040000000-0x404bffffff] 
[    0.729419] pci 0000:01:00.0: BAR 0: assigned [mem 0x404c000000-0x404c00ffff 64bit pref] 
[    0.737598] pci 0000:01:00.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    0.743729] pci 0000:02:09.0: BAR 1: assigned [mem 0x4040000000-0x4047ffffff] 
[    0.750919] pci 0000:02:09.0: BAR 0: assigned [mem 0x4048000000-0x40480fffff] 
[    0.758108] pci 0000:02:0e.0: BAR 8: assigned [mem 0x4048100000-0x40484fffff] 
[    0.765285] pci 0000:02:0e.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    0.771415] pci 0000:03:00.0: BAR 8: assigned [mem 0x4048100000-0x40484fffff] 
[    0.778591] pci 0000:03:00.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    0.784723] pci 0000:04:02.0: BAR 8: assigned [mem 0x4048100000-0x40481fffff] 
[    0.791900] pci 0000:04:03.0: BAR 8: assigned [mem 0x4048200000-0x40482fffff] 
[    0.799077] pci 0000:04:04.0: BAR 8: assigned [mem 0x4048300000-0x40483fffff] 
[    0.806253] pci 0000:04:05.0: BAR 8: assigned [mem 0x4048400000-0x40484fffff] 
[    0.813429] pci 0000:04:02.0: BAR 7: assigned [io  0x1000-0x1fff] 
[    0.819557] pci 0000:04:03.0: BAR 7: assigned [io  0x2000-0x2fff] 
[    0.825685] pci 0000:04:04.0: BAR 7: assigned [io  0x3000-0x3fff] 
[    0.831812] pci 0000:04:05.0: BAR 7: assigned [io  0x4000-0x4fff] 
[    0.837943] pci 0000:05:00.0: BAR 0: assigned [mem 0x4048100000-0x404811ffff] 
[    0.845136] pci 0000:05:00.0: BAR 3: assigned [mem 0x4048120000-0x4048123fff] 
[    0.852328] pci 0000:05:00.0: BAR 2: assigned [io  0x1000-0x101f] 
[    0.858473] pci 0000:04:02.0: PCI bridge to [bus 05] 
[    0.863471] pci 0000:04:02.0:   bridge window [io  0x1000-0x1fff] 
[    0.869619] pci 0000:04:02.0:   bridge window [mem 0x4048100000-0x40481fffff] 
[    0.876838] pci 0000:06:00.0: BAR 0: assigned [mem 0x4048200000-0x404821ffff] 
[    0.884032] pci 0000:06:00.0: BAR 3: assigned [mem 0x4048220000-0x4048223fff] 
[    0.891224] pci 0000:06:00.0: BAR 2: assigned [io  0x2000-0x201f] 
[    0.897368] pci 0000:04:03.0: PCI bridge to [bus 06] 
[    0.902366] pci 0000:04:03.0:   bridge window [io  0x2000-0x2fff] 
[    0.908514] pci 0000:04:03.0:   bridge window [mem 0x4048200000-0x40482fffff] 
[    0.915733] pci 0000:07:00.0: BAR 0: assigned [mem 0x4048300000-0x404831ffff] 
[    0.922926] pci 0000:07:00.0: BAR 3: assigned [mem 0x4048320000-0x4048323fff] 
[    0.930118] pci 0000:07:00.0: BAR 2: assigned [io  0x3000-0x301f] 
[    0.936262] pci 0000:04:04.0: PCI bridge to [bus 07] 
[    0.941260] pci 0000:04:04.0:   bridge window [io  0x3000-0x3fff] 
[    0.947407] pci 0000:04:04.0:   bridge window [mem 0x4048300000-0x40483fffff] 
[    0.954626] pci 0000:08:00.0: BAR 0: assigned [mem 0x4048400000-0x404841ffff] 
[    0.961819] pci 0000:08:00.0: BAR 3: assigned [mem 0x4048420000-0x4048423fff] 
[    0.969011] pci 0000:08:00.0: BAR 2: assigned [io  0x4000-0x401f] 
[    0.975155] pci 0000:04:05.0: PCI bridge to [bus 08] 
[    0.980153] pci 0000:04:05.0:   bridge window [io  0x4000-0x4fff] 
[    0.986301] pci 0000:04:05.0:   bridge window [mem 0x4048400000-0x40484fffff] 
[    0.993517] pci 0000:03:00.0: PCI bridge to [bus 04-08] 
[    0.998777] pci 0000:03:00.0:   bridge window [io  0x1000-0x4fff] 
[    1.004925] pci 0000:03:00.0:   bridge window [mem 0x4048100000-0x40484fffff] 
[    1.012141] pci 0000:02:0e.0: PCI bridge to [bus 03-08] 
[    1.017400] pci 0000:02:0e.0:   bridge window [io  0x1000-0x4fff] 
[    1.023546] pci 0000:02:0e.0:   bridge window [mem 0x4048100000-0x40484fffff] 
[    1.030758] pci 0000:01:00.0: PCI bridge to [bus 02-08] 
[    1.036017] pci 0000:01:00.0:   bridge window [io  0x1000-0x4fff] 
[    1.042162] pci 0000:01:00.0:   bridge window [mem 0x4040000000-0x404bffffff] 
[    1.049373] pci 0000:00:00.0: PCI bridge to [bus 01-ff] 
[    1.054627] pci 0000:00:00.0:   bridge window [io  0x1000-0x4fff] 
[    1.060755] pci 0000:00:00.0:   bridge window [mem 0x4040000000-0x404bffffff] 
[    1.067931] pci 0000:00:00.0:   bridge window [mem 0x404c000000-0x404c0fffff 64bit pref] 
[    1.076240] pcieport 0000:00:00.0: Signaling PME with IRQ 57 
[    1.082032] pcieport 0000:00:00.0: AER enabled with IRQ 57 
[    1.089143] PCI: OF: host bridge /soc/pcie@3500000 ranges: 
[    1.094672] PCI: OF:    IO 0x4800010000..0x480001ffff -> 0x00000000 
[    1.100978] PCI: OF:   MEM 0x4840000000..0x487fffffff -> 0x40000000 
[    1.107379] layerscape-pcie 3500000.pcie: PCI host bridge to bus 0001:00 
[    1.114122] pci_bus 0001:00: root bus resource [bus 00-ff] 
[    1.119640] pci_bus 0001:00: root bus resource [io  0x10000-0x1ffff] (bus address [0x0000-0xffff]) 
[    1.128651] pci_bus 0001:00: root bus resource [mem 0x4840000000-0x487fffffff] (bus address [0x40000000-0x7fffffff]) 
[    1.142959] pci 0001:00:00.0: BAR 6: assigned [mem 0x4840000000-0x48400007ff pref] 
[    1.150575] pci 0001:00:00.0: PCI bridge to [bus 01-ff] 
[    1.155959] pcieport 0001:00:00.0: Signaling PME with IRQ 59 
[    1.161726] pcieport 0001:00:00.0: AER enabled with IRQ 59 
[    1.167385] PCI: OF: host bridge /soc/pcie@3600000 ranges: 
[    1.172911] PCI: OF:    IO 0x5000010000..0x500001ffff -> 0x00000000 
[    1.179217] PCI: OF:   MEM 0x5040000000..0x507fffffff -> 0x40000000 
[    1.185616] layerscape-pcie 3600000.pcie: PCI host bridge to bus 0002:00 
[    1.192358] pci_bus 0002:00: root bus resource [bus 00-ff] 
[    1.197876] pci_bus 0002:00: root bus resource [io  0x20000-0x2ffff] (bus address [0x0000-0xffff]) 
[    1.206890] pci_bus 0002:00: root bus resource [mem 0x5040000000-0x507fffffff] (bus address [0x40000000-0x7fffffff]) 
[    1.221184] pci 0002:00:00.0: BAR 6: assigned [mem 0x5040000000-0x50400007ff pref] 
[    1.228799] pci 0002:00:00.0: PCI bridge to [bus 01-ff] 
[    1.234184] pcieport 0002:00:00.0: Signaling PME with IRQ 60 
[    1.239951] pcieport 0002:00:00.0: AER enabled with IRQ 60 
[    1.250361] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled 
[    1.258138] console [ttyS0] disabled 
[    1.261760] 21c0500.serial: ttyS0 at MMIO 0x21c0500 (irq = 18, base_baud = 25000000) is a 16550A 
[    1.270609] console [ttyS0] enabled 
[    1.270609] console [ttyS0] enabled 
[    1.277593] bootconsole [uart8250] disabled 
[    1.277593] bootconsole [uart8250] disabled 
[    1.286289] 21c0600.serial: ttyS1 at MMIO 0x21c0600 (irq = 18, base_baud = 25000000) is a 16550A 
[    1.295379] 21d0500.serial: ttyS2 at MMIO 0x21d0500 (irq = 19, base_baud = 25000000) is a 16550A 
[    1.304459] 21d0600.serial: ttyS3 at MMIO 0x21d0600 (irq = 19, base_baud = 25000000) is a 16550A 
[    1.313779] msm_serial: driver initialized 
[    1.319020] cacheinfo: Unable to detect cache hierarchy for CPU 0 
[    1.329578] brd: module loaded 
[    1.336786] loop: module loaded 
[    1.340118] WARNING: CPU: 0 PID: 1 at mm/slab_common.c:996 kmalloc_slab+0x60/0x68 
[    1.347590] Modules linked in: 
[    1.350641] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.17.0-rc1 #3 
[    1.356897] Hardware name: VM6103 Board (DT) 
[    1.361159] pstate: 20000005 (nzCv daif -PAN -UAO) 
[    1.365941] pc : kmalloc_slab+0x60/0x68 
[    1.369772] lr : __kmalloc_track_caller+0x18/0x10c 
[    1.374552] sp : ffff00000801ba10 
[    1.377857] x29: ffff00000801ba10 x28: 0000000000000000  
[    1.383161] x27: 0000000000000001 x26: 00000000088814a8  
[    1.388466] x25: 0000000000000001 x24: ffff800876e97020  
[    1.393770] x23: ffff00000887ff20 x22: 0000000000000000  
[    1.399073] x21: 00000000014080c0 x20: ffff800876e97020  
[    1.404378] x19: ffff8008770e0c00 x18: 0000000000000000  
[    1.409682] x17: 0000000000000001 x16: 0000000000000011  
[    1.414985] x15: 0000000000000cb0 x14: 0000000000000000  
[    1.420289] x13: 0000000000000000 x12: 0000000000000000  
[    1.425593] x11: 0000000000000013 x10: 0101010101010101  
[    1.430897] x9 : 0000000000000000 x8 : ffff800877112f00  
[    1.436200] x7 : 0000000000000000 x6 : 000000000000003f  
[    1.441504] x5 : 0000000000000040 x4 : 00000000014080c0  
[    1.446808] x3 : 00000000008881b0 x2 : 0000000000000000  
[    1.452111] x1 : 00000000014080c0 x0 : 00000000008881b0  
[    1.457415] Call trace: 
[    1.459856]  kmalloc_slab+0x60/0x68 
[    1.463338]  devm_kmalloc+0x28/0x70 
[    1.466820]  at24_probe+0x140/0x58c 
[    1.470302]  i2c_device_probe+0x14c/0x25c 
[    1.474305]  driver_probe_device+0x224/0x308 
[    1.478567]  __driver_attach+0xa4/0xa8 
[    1.482308]  bus_for_each_dev+0x50/0x98 
[    1.486135]  driver_attach+0x20/0x28 
[    1.489702]  bus_add_driver+0x1c0/0x224 
[    1.493530]  driver_register+0x60/0xf4 
[    1.497270]  i2c_register_driver+0x44/0x84 
[    1.501359]  at24_init+0x54/0x5c 
[    1.504580]  do_one_initcall+0x44/0x130 
[    1.508409]  kernel_init_freeable+0x13c/0x1e0 
[    1.512758]  kernel_init+0x10/0xfc 
[    1.516151]  ret_from_fork+0x10/0x18 
[    1.519719] ---[ end trace fd9a52c41828a6f2 ]--- 
[    1.524355] at24: probe of 0-0052 failed with error -12 
[    1.531145] ahci-qoriq 3200000.sata: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl platform mode 
[    1.540117] ahci-qoriq 3200000.sata: flags: 64bit ncq sntf pm clo only pmp fbs pio slum part ccc sds apst  
[    1.550271] scsi host0: ahci-qoriq 
[    1.553812] ata1: SATA max UDMA/133 mmio [mem 0x03200000-0x0320ffff] port 0x100 irq 30 
[    1.562822] fsl-quadspi 1550000.quadspi: n25q128a11 (16384 Kbytes) 
[    1.569016] 3 cmdlinepart partitions found on MTD device 1550000.quadspi 
[    1.575730] Creating 3 MTD partitions on "1550000.quadspi": 
[    1.581304] 0x000000000000-0x000000200000 : "uboot" 
[    1.586653] 0x000000200000-0x000000240000 : "boot-env" 
[    1.592232] 0x000000240000-0x000001000000 : "User_Data" 
[    1.598755] libphy: Fixed MDIO Bus: probed 
[    1.603090] tun: Universal TUN/TAP device driver, 1.6 
[    1.608717] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.614431] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.619506] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.624578] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.629649] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.634723] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.639791] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.644864] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.649936] libphy: Freescale XGMAC MDIO Bus: probed 
[    1.655017] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI 
[    1.662062] e1000: Copyright (c) 1999-2006 Intel Corporation. 
[    1.667859] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k 
[    1.673688] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. 
[    1.679994] e1000e 0000:05:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    1.689357] e1000e 0000:05:00.0 0000:05:00.0 (uninitialized): Failed to initialize MSI-X interrupts.  Falling back to MSI interrupts. 
[    1.701387] e1000e 0000:05:00.0 0000:05:00.0 (uninitialized): Failed to initialize MSI interrupts.  Falling back to legacy interrupts. 
[    1.774975] e1000e 0000:05:00.0 0000:05:00.0 (uninitialized): registered PHC clock 
[    1.844918] e1000e 0000:05:00.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:03 
[    1.852837] e1000e 0000:05:00.0 eth0: Intel(R) PRO/1000 Network Connection 
[    1.859802] e1000e 0000:05:00.0 eth0: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    1.866886] e1000e 0000:06:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    1.876244] e1000e 0000:06:00.0 0000:06:00.0 (uninitialized): Failed to initialize MSI-X interrupts.  Falling back to MSI interrupts. 
[    1.880268] ata1: SATA link down (SStatus 0 SControl 300) 
[    1.888276] e1000e 0000:06:00.0 0000:06:00.0 (uninitialized): Failed to initialize MSI interrupts.  Falling back to legacy interrupts. 
[    1.967002] e1000e 0000:06:00.0 0000:06:00.0 (uninitialized): registered PHC clock 
[    2.040867] e1000e 0000:06:00.0 eth1: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:02 
[    2.048787] e1000e 0000:06:00.0 eth1: Intel(R) PRO/1000 Network Connection 
[    2.055751] e1000e 0000:06:00.0 eth1: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    2.062798] e1000e 0000:07:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    2.072153] e1000e 0000:07:00.0 0000:07:00.0 (uninitialized): Failed to initialize MSI-X interrupts.  Falling back to MSI interrupts. 
[    2.084182] e1000e 0000:07:00.0 0000:07:00.0 (uninitialized): Failed to initialize MSI interrupts.  Falling back to legacy interrupts. 
[    2.158967] e1000e 0000:07:00.0 0000:07:00.0 (uninitialized): registered PHC clock 
[    2.228860] e1000e 0000:07:00.0 eth2: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:01 
[    2.236779] e1000e 0000:07:00.0 eth2: Intel(R) PRO/1000 Network Connection 
[    2.243743] e1000e 0000:07:00.0 eth2: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    2.250811] e1000e 0000:08:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    2.260166] e1000e 0000:08:00.0 0000:08:00.0 (uninitialized): Failed to initialize MSI-X interrupts.  Falling back to MSI interrupts. 
[    2.272195] e1000e 0000:08:00.0 0000:08:00.0 (uninitialized): Failed to initialize MSI interrupts.  Falling back to legacy interrupts. 
[    2.346975] e1000e 0000:08:00.0 0000:08:00.0 (uninitialized): registered PHC clock 
[    2.416858] e1000e 0000:08:00.0 eth3: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:00 
[    2.424777] e1000e 0000:08:00.0 eth3: Intel(R) PRO/1000 Network Connection 
[    2.431740] e1000e 0000:08:00.0 eth3: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    2.438490] sky2: driver version 1.30 
[    2.442961] VFIO - User Level meta-driver version: 0.3 
[    2.449803] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver 
[    2.456332] ehci-pci: EHCI PCI platform driver 
[    2.460807] ehci-platform: EHCI generic platform driver 
[    2.466237] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver 
[    2.472421] ohci-pci: OHCI PCI platform driver 
[    2.476904] ohci-platform: OHCI generic platform driver 
[    2.482800] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller 
[    2.488297] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1 
[    2.496206] xhci-hcd xhci-hcd.0.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x02010010 
[    2.504934] xhci-hcd xhci-hcd.0.auto: irq 27, io mem 0x02f00000 
[    2.511342] hub 1-0:1.0: USB hub found 
[    2.515115] hub 1-0:1.0: 1 port detected 
[    2.519262] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller 
[    2.524757] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2 
[    2.532419] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0  SuperSpeed 
[    2.539074] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. 
[    2.547519] hub 2-0:1.0: USB hub found 
[    2.551287] hub 2-0:1.0: 1 port detected 
[    2.555486] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller 
[    2.560981] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 3 
[    2.568872] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x02010010 
[    2.577597] xhci-hcd xhci-hcd.1.auto: irq 28, io mem 0x03000000 
[    2.583942] hub 3-0:1.0: USB hub found 
[    2.587711] hub 3-0:1.0: 1 port detected 
[    2.591834] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller 
[    2.597327] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 4 
[    2.604989] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0  SuperSpeed 
[    2.611640] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM. 
[    2.620069] hub 4-0:1.0: USB hub found 
[    2.623883] hub 4-0:1.0: 1 port detected 
[    2.628076] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller 
[    2.633571] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 5 
[    2.641463] xhci-hcd xhci-hcd.2.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x02010010 
[    2.650180] xhci-hcd xhci-hcd.2.auto: irq 29, io mem 0x03100000 
[    2.656532] hub 5-0:1.0: USB hub found 
[    2.660348] hub 5-0:1.0: 1 port detected 
[    2.664475] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller 
[    2.669972] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 6 
[    2.677633] xhci-hcd xhci-hcd.2.auto: Host supports USB 3.0  SuperSpeed 
[    2.684294] usb usb6: We don't know the algorithms for LPM for this host, disabling LPM. 
[    2.692725] hub 6-0:1.0: USB hub found 
[    2.696528] hub 6-0:1.0: 1 port detected 
[    2.700803] usbcore: registered new interface driver usb-storage 
[    2.706974] mousedev: PS/2 mouse device common for all mice 
[    2.719507] rtc-pcf8563 0-0051: rtc core: registered rtc-pcf8563 as rtc0 
[    2.727335] i2c /dev entries driver 
[    2.733713] ina2xx 0-0040: power monitor ina220 (Rshunt = 1000 uOhm) 
[    2.740195] lm90 0-004c: 0-004c supply vcc not found, using dummy regulator 
[    2.749218] qoriq_cpufreq: Freescale QorIQ CPU frequency scaling driver 
[    2.756124] sdhci: Secure Digital Host Controller Interface driver 
[    2.762303] sdhci: Copyright(c) Pierre Ossman 
[    2.766677] sdhci-pltfm: SDHCI platform and OF driver helper 
[    2.796906] mmc0: SDHCI controller on 1560000.esdhc [1560000.esdhc] using ADMA 64-bit 
[    2.806397] caam 1700000.crypto: Instantiated RNG4 SH1 
[    2.811541] caam 1700000.crypto: device ID = 0x0a12060000000000 (Era 8) 
[    2.818155] caam 1700000.crypto: job rings = 4, qi = 1, dpaa2 = no 
[    2.829468] caam algorithms registered in /proc/crypto 
[    2.835903] caam_jr 1710000.jr: registering rng-caam 
[    2.840975] caam 1700000.crypto: caam pkc algorithms registered in /proc/crypto 
[    2.848687] usbcore: registered new interface driver usbhid 
[    2.854260] usbhid: USB HID core driver 
[    2.858657] Initializing XFRM netlink socket 
[    2.863016] NET: Registered protocol family 10 
[    2.868146] Segment Routing with IPv6 
[    2.871851] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver 
[    2.878120] NET: Registered protocol family 17 
[    2.882572] NET: Registered protocol family 15 
[    2.887045] 8021q: 802.1Q VLAN Support v1.8 
[    2.891254] 9pnet: Installing 9P2000 support 
[    2.895560] Key type dns_resolver registered 
[    2.900330] registered taskstats version 1 
[    2.907002] rtc-pcf8563 0-0051: setting system clock to 2018-05-09 10:43:06 UTC (1525862586) 
[    2.916481] Waiting for root device /dev/mmcblk0p1... 
[    2.983590] mmc0: new high speed MMC card at address 0001 
[    2.989536] mmcblk0: mmc0:0001 R1J58L 55.1 GiB  
[    2.994516] mmcblk0boot0: mmc0:0001 R1J58L partition 1 16.0 MiB 
[    3.000873] mmcblk0boot1: mmc0:0001 R1J58L partition 2 16.0 MiB 
[    3.006874] mmcblk0rpmb: mmc0:0001 R1J58L partition 3 128 KiB, chardev (243:0) 
[    3.008911] usb 5-1: new full-speed USB device number 2 using xhci-hcd 
[    3.021178]  mmcblk0: p1 
[    3.043733] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode. Opts: (null) 
[    3.051846] VFS: Mounted root (ext4 filesystem) on device 179:1. 
[    3.058746] devtmpfs: mounted 
[    3.061949] Freeing unused kernel memory: 704K 
[    3.174246] alloc_contig_range: [f7c84, f7c85) PFNs busy 
[    3.179617] alloc_contig_range: [f7c85, f7c86) PFNs busy 
[    3.184987] alloc_contig_range: [f7c86, f7c87) PFNs busy 
[    3.190326] alloc_contig_range: [f7c87, f7c88) PFNs busy 
[    3.195810] alloc_contig_range: [f7c84, f7c85) PFNs busy 
[    3.201178] alloc_contig_range: [f7c85, f7c86) PFNs busy 
[    3.206544] alloc_contig_range: [f7c86, f7c87) PFNs busy 
[    3.211911] alloc_contig_range: [f7c87, f7c88) PFNs busy 
[    3.217279] alloc_contig_range: [f7c89, f7c8a) PFNs busy 
[    3.222646] alloc_contig_range: [f7c8a, f7c8b) PFNs busy 
[    3.304600] systemd[1]: systemd 215 running in system mode. (+PAM +AUDIT +SELINUX +IMA +SYSVINIT +LIBCRYPTSETUP +GCRYPT +ACL +XZ -SECCOMP -APPARMOR) 
[    3.318034] systemd[1]: Detected architecture 'arm64'. 
 
Welcome to 
   Debian GNU/Linux 8 (jessie)
   ! 
 
[    3.357636] systemd[1]: Set hostname to <debian>. 
[    3.447949] hid-generic 0003:064F:2AF9.0001: device has no listeners, quitting 
[    3.536854] systemd[1]: Cannot add dependency job for unit dbus.socket, ignoring: Unit dbus.socket failed to load: No such file or directory. 
[    3.549647] systemd[1]: Cannot add dependency job for unit display-manager.service, ignoring: Unit display-manager.service failed to load: No such file or directory. 
[    3.565306] systemd[1]: Starting Forward Password Requests to Wall Directory Watch. 
[    3.573158] systemd[1]: Started Forward Password Requests to Wall Directory Watch. 
[    3.580765] systemd[1]: Expecting device dev-ttyS0.device... 
         Expecting device dev-ttyS0.device... 
[    3.600961] systemd[1]: Starting Remote File Systems (Pre). 
[
      OK  
   ] Reached target Remote File Systems (Pre). 
[    3.620939] systemd[1]: Reached target Remote File Systems (Pre). 
[
      OK  
   ] Reached target Paths. 
[
      OK  
   ] Reached target Encrypted Volumes. 
[
      OK  
   ] Reached target Swap. 
[
      OK  
   ] Created slice Root Slice. 
[
      OK  
   ] Created slice User and Session Slice. 
[
      OK  
   ] Listening on Delayed Shutdown Socket. 
[
      OK  
   ] Listening on /dev/initctl Compatibility Named Pipe. 
[
      OK  
   ] Listening on Journal Socket (/dev/log). 
[
      OK  
   ] Listening on udev Control Socket. 
[
      OK  
   ] Listening on udev Kernel Socket. 
[
      OK  
   ] Listening on Journal Socket. 
[
      OK  
   ] Reached target Sockets. 
[
      OK  
   ] Created slice System Slice. 
[
      OK  
   ] Created slice system-getty.slice. 
[
      OK  
   ] Created slice system-serial\x2dgetty.slice. 
         Starting Load Kernel Modules... 
         Mounting POSIX Message Queue File System... 
         Starting Create Static Device Nodes in /dev... 
         Mounting Huge Pages File System... 
         Mounting Debug File System... 
         Starting udev Coldplug all Devices... 
         Starting Remount Root and Kernel File Systems... 
         Starting Journal Service... 
[
      OK  
   ] Started Journal Service. 
[
      OK  
   ] Reached target Slices. 
[
      OK  
   ] Mounted Debug File System. 
[
      OK  
   ] Mounted Huge Pages File System. 
[
      OK  
   ] Mounted POSIX Message Queue File System. 
[
      OK  
   ] Started Load Kernel Modules. 
[
      OK  
   ] Started Create Static Device Nodes in /dev. 
[
      OK  
   ] Started Remount Root and Kernel File Systems. 
         Starting Load/Save Random Seed... 
         Starting udev Kernel Device Manager... 
[
      OK  
   ] Reached target Local File Systems (Pre). 
         Mounting /var/tm[    4.195012] systemd-udevd[2012]: starting version 215 
p... 
         Mounting /tmp... 
         Starting Apply Kernel Variables... 
         Mounting FUSE Control File System... 
[
      OK  
   ] Mounted /tmp. 
[
      OK  
   ] Mounted /var/tmp. 
[
      OK  
   ] Mounted FUSE Control File System. 
[
      OK  
   ] Started udev Kernel Device Manager. 
[
      OK  
   ] Started udev Coldplug all Devices. 
[
      OK  
   ] Started Load/Save Random Seed. 
[
      OK  
   ] Started Apply Kernel Variables. 
         Starting Copy rules generated while the root was ro... 
         Starting LSB: Tune IDE hard disks... 
[
      OK  
   ] Reached target Local File Systems. 
[
      OK  
   ] Reached target Remote File Systems. 
         Starting Trigger Flushing of Journal to Persistent Storage... 
         Starting Create Volatile Files and Directories... 
         Starting LSB: Raise network interfaces.... 
[
      OK  
   ] Started Copy rules generated while the root was ro. 
[
      OK  
   ] Found device /dev/ttyS0. 
[    4.571107] systemd-journald[1329]: Received request to flush runtime journal from PID 1 
[
      OK  
   ] Started Create Volatile Files and Directories. 
[
      OK  
   ] Started Trigger Flushing of Journal to Persistent Storage. 
         Starting Update UTMP about System Boot/Shutdown... 
[
      OK  
   ] Started LSB: Tune IDE hard disks. 
[
      OK  
   ] Started Update UTMP about System Boot/Shutdown. 
[    4.702368] e1000e 0000:05:00.0 rename2: renamed from eth0 
[    4.719298] systemd-udevd[2022]: renamed network interface eth0 to rename2 
[    4.719431] e1000e 0000:06:00.0 rename3: renamed from eth1 
[    4.745749] e1000e 0000:07:00.0 eth4: renamed from eth2 
[    4.752631] systemd-udevd[2029]: renamed network interface eth1 to rename3 
[    4.765361] systemd-udevd[2023]: renamed network interface eth2 to eth4 
[    4.766961] e1000e 0000:08:00.0 eth5: renamed from eth3 
[    4.785850] systemd-udevd[2026]: renamed network interface eth3 to eth5 
[    4.787921] e1000e 0000:05:00.0 eth2: renamed from rename2 
[    4.807095] systemd-udevd[2022]: renamed network interface eth0 to eth2 
[    4.811056] e1000e 0000:06:00.0 eth3: renamed from rename3 
[    4.830639] systemd-udevd[2029]: renamed network interface eth1 to eth3 
[
      OK  
   ] Started LSB: Raise network interfaces.. 
[
      OK  
   ] Reached target Network. 
[
      OK  
   ] Reached target Network is Online. 
[
      OK  
   ] Reached target System Initialization. 
[
      OK  
   ] Reached target Timers. 
[
      OK  
   ] Reached target Basic System. 
         Starting Internet superserver... 
[
      OK  
   ] Started Internet superserver. 
         Starting Self Monitoring and Reporting Technology (SMART) Daemon... 
[
      OK  
   ] Started Self Monitoring and Reporting Technology (SMART) Daemon. 
         Starting OpenBSD Secure Shell server... 
         Starting Kontron KVX BSP Service... 
         Starting Kontron RTC2 Service... 
         Starting Initialize hardware monitoring sensors... 
         Starting /etc/rc.local Compatibility... 
         Starting getty on tty2-tty6 if dbus and logind are not available... 
         Starting LSB: disk temperature monitoring daemon... 
         Starting Permit User Sessions... 
[
      OK  
   ] Started /etc/rc.local Compatibility. 
[
      OK  
   ] Started LSB: disk temperature monitoring daemon. 
[
      OK  
   ] Started Permit User Sessions. 
[
      OK  
   ] Started Kontron RTC2 Service. 
[
      OK  
   ] Started Initialize hardware monitoring sensors. 
         Starting Getty on tty4... 
[
      OK  
   ] Started Getty on tty4. 
         Starting Getty on tty3... 
[
      OK  
   ] Started Getty on tty3. 
         Starting Getty on tty2... 
[
      OK  
   ] Started Getty on tty2. 
         Starting Getty on tty1... 
[
      OK  
   ] Started Getty on tty1. 
         Starting Serial Getty on ttyS0... 
[
      OK  
   ] Started Serial Getty on ttyS0. 
[
      OK  
   ] Started OpenBSD Secure Shell server. 
[
      OK  
   ] Started Kontron KVX BSP Service. 
[
      OK  
   ] Started getty on tty2-tty6 if dbus and logind are not available. 
         Starting Getty on tty6... 
[
      OK  
   ] Started Getty on tty6. 
         Starting Getty on tty5... 
[
      OK  
   ] Started Getty on tty5. 
[
      OK  
   ] Reached target Login Prompts. 
[
      OK  
   ] Reached target Multi-User System. 
[
      OK  
   ] Reached target Graphical Interface. 
         Starting Update UTMP about System Runlevel Changes... 
[
      OK  
   ] Started Update UTMP about System Runlevel Changes. 
  
Debian GNU/Linux 8 debian ttyS0 
 
debian login: root  
Password:  
Last login: Wed May  9 10:27:36 UTC 2018 on ttyS0 
Linux debian 4.17.0-rc1 #3 SMP Fri May 4 10:03:38 UTC 2018 aarch64 
 
The programs included with the Debian GNU/Linux system are free software; 
the exact distribution terms for each program are described in the 
individual files in /usr/share/doc/*/copyright. 
 
Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent 
permitted by applicable law. 
root@debian:~#  
root@debian:~#  
root@debian:~# lspci -vv 
0000:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0 
 I/O behind bridge: 00001000-00004fff 
 Memory behind bridge: 40000000-4bffffff 
 Prefetchable memory behind bridge: 000000004c000000-000000004c0fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
 Expansion ROM at 404c100000 [disabled] [size=2K] 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 3 
  Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag- RBE+ 
  DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited 
   ClockPM- Surprise- LLActRep+ BwNot+ 
  LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
  RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- 
  RootCap: CRSVisible- 
  RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
  DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd- 
  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- 
  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- 
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
    Compliance De-emphasis: -6dB 
  LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- 
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- 
 Capabilities: [100 v2] Advanced Error Reporting 
  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- 
  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- 
  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ 
  AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- 
 Capabilities: [148 v1] #19 
 Kernel driver in use: pcieport 
 
0000:01:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Region 0: Memory at 404c000000 (64-bit, prefetchable) [size=64K] 
 Bus: primary=01, secondary=02, subordinate=08, sec-latency=0 
 I/O behind bridge: 00001000-00004fff 
 Memory behind bridge: 40000000-4bffffff 
 Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 2 
  Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [60] Express (v1) PCI-Express to PCI/PCI-X Bridge, MSI 00 
  DevCap: MaxPayload 128 bytes, PhantFunc 0 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <16us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [100 v1] Power Budgeting <?> 
 
0000:02:09.0 Bridge: Kontron Device 9035 (rev 46) 
 Subsystem: Kontron Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 128 
 Interrupt: pin A routed to IRQ 0 
 Region 0: Memory at 4048000000 (32-bit, non-prefetchable) [size=1M] 
 Region 1: Memory at 4040000000 (32-bit, non-prefetchable) [size=128M] 
 Capabilities: [78] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 
0000:02:0e.0 PCI bridge: Pericom Semiconductor PCI Express to PCI-XPI7C9X130 PCI-X Bridge (rev 04) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 128, Cache Line Size: 32 bytes 
 Bus: primary=02, secondary=03, subordinate=08, sec-latency=0 
 I/O behind bridge: 00001000-00004fff 
 Memory behind bridge: 48100000-484fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [80] PCI-X bridge device 
  Secondary Status: 64bit- 133MHz- SCD- USC- SCO- SRD- Freq=conv 
  Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- 
  Upstream: Capacity=16 CommitmentLimit=16 
  Downstream: Capacity=16 CommitmentLimit=16 
 Capabilities: [90] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [a8] Subsystem: Device 0000:0000 
 Capabilities: [b0] Express (v1) PCI/PCI-X to PCI-Express Bridge, MSI 00 
  DevCap: MaxPayload 512 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend+ 
  LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <512ns, L1 <1us 
   ClockPM- Surprise- LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [f0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 
0000:03:00.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=03, secondary=04, subordinate=08, sec-latency=0 
 I/O behind bridge: 00001000-00004fff 
 Memory behind bridge: 48100000-484fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Upstream Port, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 0.000W 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Kernel driver in use: pcieport 
 
0000:04:02.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=04, secondary=05, subordinate=05, sec-latency=0 
 I/O behind bridge: 00001000-00001fff 
 Memory behind bridge: 48100000-481fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Downstream Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us 
   ClockPM- Surprise+ LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Kernel driver in use: pcieport 
 
0000:04:03.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=04, secondary=06, subordinate=06, sec-latency=0 
 I/O behind bridge: 00002000-00002fff 
 Memory behind bridge: 48200000-482fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Downstream Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us 
   ClockPM- Surprise+ LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Kernel driver in use: pcieport 
 
0000:04:04.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=04, secondary=07, subordinate=07, sec-latency=0 
 I/O behind bridge: 00003000-00003fff 
 Memory behind bridge: 48300000-483fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Downstream Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us 
   ClockPM- Surprise+ LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Kernel driver in use: pcieport 
 
0000:04:05.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=04, secondary=08, subordinate=08, sec-latency=0 
 I/O behind bridge: 00004000-00004fff 
 Memory behind bridge: 48400000-484fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Downstream Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us 
   ClockPM- Surprise+ LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Kernel driver in use: pcieport 
 
0000:05:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
 Subsystem: Intel Corporation Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 64 bytes 
 Interrupt: pin A routed to IRQ 57 
 Region 0: Memory at 4048100000 (32-bit, non-prefetchable) [size=128K] 
 Region 2: I/O ports at 1000 [disabled] [size=32] 
 Region 3: Memory at 4048120000 (32-bit, non-prefetchable) [size=16K] 
 Capabilities: [c8] Power Management version 2 
  Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [e0] Express (v1) Endpoint, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L0s <128ns, L1 <64us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [a0] MSI-X: Enable- Count=5 Masked- 
  Vector table: BAR=3 offset=00000000 
  PBA: BAR=3 offset=00002000 
 Kernel driver in use: e1000e 
 
0000:06:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
 Subsystem: Intel Corporation Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 64 bytes 
 Interrupt: pin A routed to IRQ 61 
 Region 0: Memory at 4048200000 (32-bit, non-prefetchable) [size=128K] 
 Region 2: I/O ports at 2000 [disabled] [size=32] 
 Region 3: Memory at 4048220000 (32-bit, non-prefetchable) [size=16K] 
 Capabilities: [c8] Power Management version 2 
  Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [e0] Express (v1) Endpoint, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L0s <128ns, L1 <64us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [a0] MSI-X: Enable- Count=5 Masked- 
  Vector table: BAR=3 offset=00000000 
  PBA: BAR=3 offset=00002000 
 Kernel driver in use: e1000e 
 
0000:07:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
 Subsystem: Intel Corporation Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 64 bytes 
 Interrupt: pin A routed to IRQ 58 
 Region 0: Memory at 4048300000 (32-bit, non-prefetchable) [size=128K] 
 Region 2: I/O ports at 3000 [disabled] [size=32] 
 Region 3: Memory at 4048320000 (32-bit, non-prefetchable) [size=16K] 
 Capabilities: [c8] Power Management version 2 
  Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [e0] Express (v1) Endpoint, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L0s <128ns, L1 <64us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [a0] MSI-X: Enable- Count=5 Masked- 
  Vector table: BAR=3 offset=00000000 
  PBA: BAR=3 offset=00002000 
 Kernel driver in use: e1000e 
 
0000:08:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
 Subsystem: Intel Corporation Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 64 bytes 
 Interrupt: pin A routed to IRQ 62 
 Region 0: Memory at 4048400000 (32-bit, non-prefetchable) [size=128K] 
 Region 2: I/O ports at 4000 [disabled] [size=32] 
 Region 3: Memory at 4048420000 (32-bit, non-prefetchable) [size=16K] 
 Capabilities: [c8] Power Management version 2 
  Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [e0] Express (v1) Endpoint, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L0s <128ns, L1 <64us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [a0] MSI-X: Enable- Count=5 Masked- 
  Vector table: BAR=3 offset=00000000 
  PBA: BAR=3 offset=00002000 
 Kernel driver in use: e1000e 
 
0001:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 Expansion ROM at 4840000000 [disabled] [size=2K] 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 3 
  Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag- RBE+ 
  DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited 
   ClockPM- Surprise- LLActRep+ BwNot+ 
  LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
  RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- 
  RootCap: CRSVisible- 
  RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
  DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd- 
  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- 
  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- 
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
    Compliance De-emphasis: -6dB 
  LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- 
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- 
 Capabilities: [100 v2] Advanced Error Reporting 
  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- 
  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- 
  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ 
  AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- 
 Capabilities: [148 v1] #19 
 Kernel driver in use: pcieport 
 
0002:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 Expansion ROM at 5040000000 [disabled] [size=2K] 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 3 
  Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag- RBE+ 
  DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited 
   ClockPM- Surprise- LLActRep+ BwNot+ 
  LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
  RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- 
  RootCap: CRSVisible- 
  RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
  DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd- 
  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- 
  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- 
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
    Compliance De-emphasis: -6dB 
  LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- 
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- 
 Capabilities: [100 v2] Advanced Error Reporting 
  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- 
  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- 
  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ 
  AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- 
 Capabilities: [148 v1] #19 
 Kernel driver in use: pcieport 
 
root@debian:~#  
root@debian:~#  
root@debian:~# lspci 
0000:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) 
0000:01:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) 
0000:02:09.0 Bridge: Kontron Device 9035 (rev 46) 
0000:02:0e.0 PCI bridge: Pericom Semiconductor PCI Express to PCI-XPI7C9X130 PCI-X Bridge (rev 04) 
0000:03:00.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:04:02.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:04:03.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:04:04.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:04:05.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:05:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
0000:06:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
0000:07:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
0000:08:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
0001:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) 
0002:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) 
root@debian:~#  
root@debian:~# lspci -t 
-+-[0002:00]---00.0-[01-ff]-- 
 +-[0001:00]---00.0-[01-ff]-- 
 \-[0000:00]---00.0-[01-ff]----00.0-[02-08]--+-09.0 
                                             \-0e.0-[03-08]----00.0-[04-08]--+-02.0-[05]----00.0 
                                                                             +-03.0-[06]----00.0 
                                                                             +-04.0-[07]----00.0 
                                                                             \-05.0-[08]----00.0 
root@debian:~# 

[-- Attachment #4: 4.17-rc1_probe_failed_without_pcieaspmoff.txt --]
[-- Type: text/plain, Size: 46121 bytes --]

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] 
[    0.000000] Linux version 4.17.0-rc1 (root@debian) (gcc version 4.9.2 (Debian/Linaro 4.9.2-10)) #3 SMP Fri May 4 10:03:38 UTC 2018 
[    0.000000] Machine model: VM6103 Board 
[    0.000000] earlycon: uart8250 at MMIO 0x00000000021c0500 (options '') 
[    0.000000] bootconsole [uart8250] enabled 
[    0.000000] efi: Getting EFI parameters from FDT: 
[    0.000000] efi: UEFI not found. 
[    0.000000] cma: Reserved 128 MiB at 0x00000000f7c00000 
[    0.000000] /cpus/cpu@2: missing enable-method property 
[    0.000000] /cpus/cpu@3: missing enable-method property 
[    0.000000] WARNING: x1-x3 nonzero in violation of boot protocol: 
[    0.000000]  x1: 0000000000000000 
[    0.000000]  x2: 0000000000000000 
[    0.000000]  x3: 0000000080080000 
[    0.000000] This indicates a broken bootloader or old kernel 
[    0.000000] random: fast init done 
[    0.000000] percpu: Embedded 23 pages/cpu @        (ptrval) s55808 r8192 d30208 u94208 
[    0.000000] Detected VIPT I-cache on CPU0 
[    0.000000] CPU features: detected: Kernel page table isolation (KPTI) 
[    0.000000] CPU features: enabling workaround for ARM erratum 845719 
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1031688 
[    0.000000] Kernel command line: console=ttyS0,115200 root=/dev/mmcblk0p1 rw rootwait mtdparts=1550000.quadspi:2m(uboot),256k(boot-env),-(User_Data) earlycon=uart8250,mmio,0x21
c0500 cma=128M cpld_i2c.smb_tmo=0 
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) 
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) 
[    0.000000] software IO TLB [mem 0xf3c00000-0xf7c00000] (64MB) mapped at [        (ptrval)-        (ptrval)] 
[    0.000000] Memory: 3853464K/4192256K available (7612K kernel code, 782K rwdata, 2904K rodata, 704K init, 232K bss, 207720K reserved, 131072K cma-reserved) 
[    0.000000] Hierarchical RCU implementation. 
[    0.000000]  RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2. 
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 
[    0.000000] GIC: Using split EOI/Deactivate mode 
[    0.000000] arch_timer: Enabling global workaround for Freescale erratum a005858 
[    0.000000] GIC: PPI14 is secure or misconfigured 
[    0.000000] arch_timer: WARNING: Invalid trigger for IRQ3, assuming level low 
[    0.000000] arch_timer: WARNING: Please fix your firmware 
[    0.000000] arch_timer: CPU0: Trapping CNTVCT access 
[    0.000000] arch_timer: cp15 timer(s) running at 25.00MHz (phys). 
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x5c40939b5, max_idle_ns: 440795202646 ns 
[    0.000003] sched_clock: 56 bits at 25MHz, resolution 40ns, wraps every 4398046511100ns 
[    0.008454] Console: colour dummy device 80x25 
[    0.012937] Calibrating delay loop (skipped), value calculated using timer frequency.. 50.00 BogoMIPS (lpj=100000) 
[    0.023346] pid_max: default: 32768 minimum: 301 
[    0.028061] Security Framework initialized 
[    0.032231] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes) 
[    0.038981] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes) 
[    0.046909] ASID allocator initialised with 32768 entries 
[    0.052391] Hierarchical SRCU implementation. 
[    0.057668] EFI services will not be available. 
[    0.062305] smp: Bringing up secondary CPUs ... 
[    0.067113] Detected VIPT I-cache on CPU1 
[    0.067140] arch_timer: CPU1: Trapping CNTVCT access 
[    0.067146] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] 
[    0.067211] smp: Brought up 1 node, 2 CPUs 
[    0.086911] SMP: Total of 2 processors activated. 
[    0.091641] CPU features: detected: 32-bit EL0 Support 
[    0.099900] CPU: All CPU(s) started at EL2 
[    0.104028] alternatives: patching kernel code 
[    0.109476] devtmpfs: initialized 
[    0.119391] Built 1 zonelists, mobility grouping on.  Total pages: 996134 
[    0.127224] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns 
[    0.137035] futex hash table entries: 512 (order: 4, 65536 bytes) 
[    0.143296] pinctrl core: initialized pinctrl subsystem 
[    0.149340] DMI not present or invalid. 
[    0.153371] NET: Registered protocol family 16 
[    0.158132] audit: initializing netlink subsys (disabled) 
[    0.164134] audit: type=2000 audit(0.112:1): state=initialized audit_enabled=0 res=1 
[    0.171953] cpuidle: using governor ladder 
[    0.176087] cpuidle: using governor menu 
[    0.180193] vdso: 2 pages (1 code @ 00000000af003dee, 1 data @ 00000000b686e24f) 
[    0.187638] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. 
[    0.195015] DMA: preallocated 256 KiB pool for atomic allocations 
[    0.201322] Serial: AMBA PL011 UART driver 
[    0.205697] irq: type mismatch, failed to map hwirq-30 for interrupt-controller@1400000! 
[    0.214627] Machine: VM6103 Board 
[    0.217960] SoC family: QorIQ LS1043A 
[    0.221633] SoC ID: svr:0x87920a10, Revision: 1.0 
[    0.251602] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages 
[    0.259257] cryptd: max_cpu_qlen set to 1000 
[    0.264267] vgaarb: loaded 
[    0.267122] SCSI subsystem initialized 
[    0.271149] usbcore: registered new interface driver usbfs 
[    0.276704] usbcore: registered new interface driver hub 
[    0.282074] usbcore: registered new device driver usb 
[    0.287426] imx-i2c 2180000.i2c: can't get pinctrl, bus recovery not supported 
[    0.295018] i2c i2c-0: IMX I2C adapter registered 
[    0.299758] i2c i2c-0: can't use DMA, using PIO instead. 
[    0.305235] pps_core: LinuxPPS API ver. 1 registered 
[    0.310227] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> 
[    0.319424] PTP clock support registered 
[    0.323488] fsl-ifc 1530000.ifc: Freescale Integrated Flash Controller 
[    0.330069] fsl-ifc 1530000.ifc: IFC version 1.4, 8 banks 
[    0.336251] clocksource: Switched to clocksource arch_sys_counter 
[    0.342479] VFS: Disk quotas dquot_6.6.0 
[    0.346480] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) 
[    0.360644] NET: Registered protocol family 2 
[    0.365368] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes) 
[    0.373294] TCP established hash table entries: 32768 (order: 6, 262144 bytes) 
[    0.380859] TCP bind hash table entries: 32768 (order: 7, 524288 bytes) 
[    0.388081] TCP: Hash tables configured (established 32768 bind 32768) 
[    0.394713] UDP hash table entries: 2048 (order: 4, 65536 bytes) 
[    0.400839] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes) 
[    0.407471] NET: Registered protocol family 1 
[    0.412073] RPC: Registered named UNIX socket transport module. 
[    0.418042] RPC: Registered udp transport module. 
[    0.422771] RPC: Registered tcp transport module. 
[    0.427499] RPC: Registered tcp NFSv4.1 backchannel transport module. 
[    0.434463] hw perfevents: failed to find logical CPU for cpu 
[    0.440269] hw perfevents: failed to find logical CPU for cpu 
[    0.446134] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available 
[    0.454350] kvm [1]: 8-bit VMID 
[    0.458017] kvm [1]: vgic interrupt IRQ1 
[    0.461966] kvm [1]: Invalid trigger for IRQ4, assuming level low 
[    0.468094] GIC: PPI11 is secure or misconfigured 
[    0.472891] kvm [1]: Hyp mode initialized successfully 
[    0.480993] workingset: timestamp_bits=46 max_order=20 bucket_order=0 
[    0.488067] NFS: Registering the id_resolver key type 
[    0.493164] Key type id_resolver registered 
[    0.497370] Key type id_legacy registered 
[    0.501498] fuse init (API version 7.26) 
[    0.505611] 9p: Installing v9fs 9p2000 file system support 
[    0.513627] io scheduler noop registered 
[    0.517599] io scheduler cfq registered (default) 
[    0.522329] io scheduler mq-deadline registered 
[    0.526885] io scheduler kyber registered 
[    0.533182] PCI: OF: host bridge /soc/pcie@3400000 ranges: 
[    0.538728] PCI: OF:    IO 0x4000010000..0x400001ffff -> 0x00000000 
[    0.545035] PCI: OF:   MEM 0x4040000000..0x407fffffff -> 0x40000000 
[    0.551454] layerscape-pcie 3400000.pcie: PCI host bridge to bus 0000:00 
[    0.558199] pci_bus 0000:00: root bus resource [bus 00-ff] 
[    0.563715] pci_bus 0000:00: root bus resource [io  0x0000-0xffff] 
[    0.569932] pci_bus 0000:00: root bus resource [mem 0x4040000000-0x407fffffff] (bus address [0x40000000-0x7fffffff]) 
[    0.583016] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force' 
[    0.594753] pci_bus 0000:02: extended config space not accessible on secondary bus 
[    0.604122] pci 0000:02:0e.0: enabling Extended Tags 
[    0.610671] pci_bus 0000:03: extended config space not accessible on secondary bus 
[    0.618629] pci 0000:03:00.0: enabling Extended Tags 
[    0.657988] pci_bus 0000:04: extended config space not accessible on secondary bus 
[    1.533082] pci 0000:04:02.0: bridge configuration invalid ([bus ff-ff]), reconfiguring 
[    1.692286] pci 0000:00:00.0: BAR 8: assigned [mem 0x4040000000-0x404bffffff] 
[    1.699471] pci 0000:00:00.0: BAR 9: assigned [mem 0x404c000000-0x404c0fffff 64bit pref] 
[    1.707612] pci 0000:00:00.0: BAR 6: assigned [mem 0x404c100000-0x404c1007ff pref] 
[    1.715231] pci 0000:01:00.0: BAR 8: assigned [mem 0x4040000000-0x404bffffff] 
[    1.722410] pci 0000:01:00.0: BAR 0: assigned [mem 0x404c000000-0x404c00ffff 64bit pref] 
[    1.730595] pci 0000:02:09.0: BAR 1: assigned [mem 0x4040000000-0x4047ffffff] 
[    1.737787] pci 0000:02:09.0: BAR 0: assigned [mem 0x4048000000-0x40480fffff] 
[    1.744979] pci 0000:03:00.0: PCI bridge to [bus 04-08] 
[    1.840825] pci 0000:02:0e.0: PCI bridge to [bus 03-08] 
[    1.846136] pci 0000:01:00.0: PCI bridge to [bus 02-08] 
[    1.851411] pci 0000:01:00.0:   bridge window [mem 0x4040000000-0x404bffffff] 
[    1.858624] pci 0000:00:00.0: PCI bridge to [bus 01-ff] 
[    1.863880] pci 0000:00:00.0:   bridge window [mem 0x4040000000-0x404bffffff] 
[    1.871059] pci 0000:00:00.0:   bridge window [mem 0x404c000000-0x404c0fffff 64bit pref] 
[    1.879362] pcieport 0000:00:00.0: Signaling PME with IRQ 57 
[    1.885172] pcieport 0000:00:00.0: AER enabled with IRQ 57 
[    1.978328] pcieport 0000:03:00.0: Refused to change power state, currently in D3 
[    2.479030] pcieport 0000:04:02.0: buffer not found in pci_save_pcie_state 
[    2.486094] PCI: OF: host bridge /soc/pcie@3500000 ranges: 
[    2.491621] PCI: OF:    IO 0x4800010000..0x480001ffff -> 0x00000000 
[    2.497928] PCI: OF:   MEM 0x4840000000..0x487fffffff -> 0x40000000 
[    2.504338] layerscape-pcie 3500000.pcie: PCI host bridge to bus 0001:00 
[    2.511082] pci_bus 0001:00: root bus resource [bus 00-ff] 
[    2.516600] pci_bus 0001:00: root bus resource [io  0x10000-0x1ffff] (bus address [0x0000-0xffff]) 
[    2.525612] pci_bus 0001:00: root bus resource [mem 0x4840000000-0x487fffffff] (bus address [0x40000000-0x7fffffff]) 
[    2.539461] pci 0001:00:00.0: BAR 6: assigned [mem 0x4840000000-0x48400007ff pref] 
[    2.547078] pci 0001:00:00.0: PCI bridge to [bus 01-ff] 
[    2.552463] pcieport 0001:00:00.0: Signaling PME with IRQ 59 
[    2.558235] pcieport 0001:00:00.0: AER enabled with IRQ 59 
[    2.563890] PCI: OF: host bridge /soc/pcie@3600000 ranges: 
[    2.569417] PCI: OF:    IO 0x5000010000..0x500001ffff -> 0x00000000 
[    2.575723] PCI: OF:   MEM 0x5040000000..0x507fffffff -> 0x40000000 
[    2.582124] layerscape-pcie 3600000.pcie: PCI host bridge to bus 0002:00 
[    2.588867] pci_bus 0002:00: root bus resource [bus 00-ff] 
[    2.594385] pci_bus 0002:00: root bus resource [io  0x20000-0x2ffff] (bus address [0x0000-0xffff]) 
[    2.603398] pci_bus 0002:00: root bus resource [mem 0x5040000000-0x507fffffff] (bus address [0x40000000-0x7fffffff]) 
[    2.617245] pci 0002:00:00.0: BAR 6: assigned [mem 0x5040000000-0x50400007ff pref] 
[    2.624861] pci 0002:00:00.0: PCI bridge to [bus 01-ff] 
[    2.630247] pcieport 0002:00:00.0: Signaling PME with IRQ 60 
[    2.636015] pcieport 0002:00:00.0: AER enabled with IRQ 60 
[    2.646025] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled 
[    2.653741] console [ttyS0] disabled 
[    2.657364] 21c0500.serial: ttyS0 at MMIO 0x21c0500 (irq = 18, base_baud = 25000000) is a 16550A 
[    2.666215] console [ttyS0] enabled 
[    2.666215] console [ttyS0] enabled 
[    2.673197] bootconsole [uart8250] disabled 
[    2.673197] bootconsole [uart8250] disabled 
[    2.681889] 21c0600.serial: ttyS1 at MMIO 0x21c0600 (irq = 18, base_baud = 25000000) is a 16550A 
[    2.690972] 21d0500.serial: ttyS2 at MMIO 0x21d0500 (irq = 19, base_baud = 25000000) is a 16550A 
[    2.700050] 21d0600.serial: ttyS3 at MMIO 0x21d0600 (irq = 19, base_baud = 25000000) is a 16550A 
[    2.709332] msm_serial: driver initialized 
[    2.714538] cacheinfo: Unable to detect cache hierarchy for CPU 0 
[    2.725111] brd: module loaded 
[    2.732395] loop: module loaded 
[    2.735706] WARNING: CPU: 1 PID: 1 at mm/slab_common.c:996 kmalloc_slab+0x60/0x68 
[    2.743178] Modules linked in: 
[    2.746230] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.17.0-rc1 #3 
[    2.752486] Hardware name: VM6103 Board (DT) 
[    2.756748] pstate: 20000005 (nzCv daif -PAN -UAO) 
[    2.761531] pc : kmalloc_slab+0x60/0x68 
[    2.765362] lr : __kmalloc_track_caller+0x18/0x10c 
[    2.770142] sp : ffff00000801ba10 
[    2.773446] x29: ffff00000801ba10 x28: 0000000000000000  
[    2.778751] x27: 0000000000000001 x26: 00000000088814a8  
[    2.784055] x25: 0000000000000001 x24: ffff800876e8e020  
[    2.789358] x23: ffff00000887ff20 x22: 0000000000000000  
[    2.794663] x21: 00000000014080c0 x20: ffff800876e8e020  
[    2.799967] x19: ffff80087702fc00 x18: 0000000000000007  
[    2.805270] x17: 000000000000000e x16: 0000000000000001  
[    2.810574] x15: 0000000000000019 x14: 0000000000000000  
[    2.815878] x13: 0000000000000000 x12: 0000000000000000  
[    2.821182] x11: 0000000000000013 x10: 0101010101010101  
[    2.826486] x9 : 0000000000000000 x8 : ffff80087704ea80  
[    2.831790] x7 : 0000000000000000 x6 : 000000000000003f  
[    2.837093] x5 : 0000000000000040 x4 : 00000000014080c0  
[    2.842397] x3 : 00000000008881b0 x2 : 0000000000000000  
[    2.847701] x1 : 00000000014080c0 x0 : 00000000008881b0  
[    2.853005] Call trace: 
[    2.855445]  kmalloc_slab+0x60/0x68 
[    2.858927]  devm_kmalloc+0x28/0x70 
[    2.862409]  at24_probe+0x140/0x58c 
[    2.865891]  i2c_device_probe+0x14c/0x25c 
[    2.869894]  driver_probe_device+0x224/0x308 
[    2.874156]  __driver_attach+0xa4/0xa8 
[    2.877898]  bus_for_each_dev+0x50/0x98 
[    2.881725]  driver_attach+0x20/0x28 
[    2.885292]  bus_add_driver+0x1c0/0x224 
[    2.889119]  driver_register+0x60/0xf4 
[    2.892859]  i2c_register_driver+0x44/0x84 
[    2.896949]  at24_init+0x54/0x5c 
[    2.900169]  do_one_initcall+0x44/0x130 
[    2.903998]  kernel_init_freeable+0x13c/0x1e0 
[    2.908349]  kernel_init+0x10/0xfc 
[    2.911741]  ret_from_fork+0x10/0x18 
[    2.915310] ---[ end trace 2f2df19ce09a6f60 ]--- 
[    2.919952] at24: probe of 0-0052 failed with error -12 
[    2.926618] ahci-qoriq 3200000.sata: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl platform mode 
[    2.935588] ahci-qoriq 3200000.sata: flags: 64bit ncq sntf pm clo only pmp fbs pio slum part ccc sds apst  
[    2.945746] scsi host0: ahci-qoriq 
[    2.949290] ata1: SATA max UDMA/133 mmio [mem 0x03200000-0x0320ffff] port 0x100 irq 30 
[    2.958228] fsl-quadspi 1550000.quadspi: n25q128a11 (16384 Kbytes) 
[    2.964418] 3 cmdlinepart partitions found on MTD device 1550000.quadspi 
[    2.971116] Creating 3 MTD partitions on "1550000.quadspi": 
[    2.976694] 0x000000000000-0x000000200000 : "uboot" 
[    2.982044] 0x000000200000-0x000000240000 : "boot-env" 
[    2.987615] 0x000000240000-0x000001000000 : "User_Data" 
[    2.994113] libphy: Fixed MDIO Bus: probed 
[    2.998442] tun: Universal TUN/TAP device driver, 1.6 
[    3.004032] libphy: Freescale XGMAC MDIO Bus: probed 
[    3.009750] libphy: Freescale XGMAC MDIO Bus: probed 
[    3.014827] libphy: Freescale XGMAC MDIO Bus: probed 
[    3.019898] libphy: Freescale XGMAC MDIO Bus: probed 
[    3.024972] libphy: Freescale XGMAC MDIO Bus: probed 
[    3.030047] libphy: Freescale XGMAC MDIO Bus: probed 
[    3.035120] libphy: Freescale XGMAC MDIO Bus: probed 
[    3.040190] libphy: Freescale XGMAC MDIO Bus: probed 
[    3.045264] libphy: Freescale XGMAC MDIO Bus: probed 
[    3.050339] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI 
[    3.057384] e1000: Copyright (c) 1999-2006 Intel Corporation. 
[    3.063170] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k 
[    3.069000] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. 
[    3.074954] sky2: driver version 1.30 
[    3.079322] VFIO - User Level meta-driver version: 0.3 
[    3.086073] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver 
[    3.092605] ehci-pci: EHCI PCI platform driver 
[    3.097081] ehci-platform: EHCI generic platform driver 
[    3.102491] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver 
[    3.108678] ohci-pci: OHCI PCI platform driver 
[    3.113150] ohci-platform: OHCI generic platform driver 
[    3.118976] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller 
[    3.124473] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1 
[    3.132394] xhci-hcd xhci-hcd.0.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x02010010 
[    3.141121] xhci-hcd xhci-hcd.0.auto: irq 27, io mem 0x02f00000 
[    3.147532] hub 1-0:1.0: USB hub found 
[    3.151305] hub 1-0:1.0: 1 port detected 
[    3.155452] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller 
[    3.160947] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2 
[    3.168607] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0  SuperSpeed 
[    3.175261] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. 
[    3.183707] hub 2-0:1.0: USB hub found 
[    3.187477] hub 2-0:1.0: 1 port detected 
[    3.191681] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller 
[    3.197177] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 3 
[    3.205072] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x02010010 
[    3.213797] xhci-hcd xhci-hcd.1.auto: irq 28, io mem 0x03000000 
[    3.220146] hub 3-0:1.0: USB hub found 
[    3.223917] hub 3-0:1.0: 1 port detected 
[    3.228034] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller 
[    3.233528] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 4 
[    3.241193] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0  SuperSpeed 
[    3.247846] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM. 
[    3.256291] hub 4-0:1.0: USB hub found 
[    3.260091] hub 4-0:1.0: 1 port detected 
[    3.264289] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller 
[    3.269783] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 5 
[    3.270480] ata1: SATA link down (SStatus 0 SControl 300) 
[    3.277671] xhci-hcd xhci-hcd.2.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x02010010 
[    3.291550] xhci-hcd xhci-hcd.2.auto: irq 29, io mem 0x03100000 
[    3.297952] hub 5-0:1.0: USB hub found 
[    3.301722] hub 5-0:1.0: 1 port detected 
[    3.305840] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller 
[    3.311335] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 6 
[    3.318995] xhci-hcd xhci-hcd.2.auto: Host supports USB 3.0  SuperSpeed 
[    3.325649] usb usb6: We don't know the algorithms for LPM for this host, disabling LPM. 
[    3.334121] hub 6-0:1.0: USB hub found 
[    3.337888] hub 6-0:1.0: 1 port detected 
[    3.342161] usbcore: registered new interface driver usb-storage 
[    3.348343] mousedev: PS/2 mouse device common for all mice 
[    3.360965] rtc-pcf8563 0-0051: rtc core: registered rtc-pcf8563 as rtc0 
[    3.368745] i2c /dev entries driver 
[    3.375039] ina2xx 0-0040: power monitor ina220 (Rshunt = 1000 uOhm) 
[    3.381509] lm90 0-004c: 0-004c supply vcc not found, using dummy regulator 
[    3.390515] qoriq_cpufreq: Freescale QorIQ CPU frequency scaling driver 
[    3.397413] sdhci: Secure Digital Host Controller Interface driver 
[    3.403591] sdhci: Copyright(c) Pierre Ossman 
[    3.407964] sdhci-pltfm: SDHCI platform and OF driver helper 
[    3.436261] mmc0: SDHCI controller on 1560000.esdhc [1560000.esdhc] using ADMA 64-bit 
[    3.445699] caam 1700000.crypto: Instantiated RNG4 SH1 
[    3.450841] caam 1700000.crypto: device ID = 0x0a12060000000000 (Era 8) 
[    3.457456] caam 1700000.crypto: job rings = 4, qi = 1, dpaa2 = no 
[    3.468738] caam algorithms registered in /proc/crypto 
[    3.475219] caam_jr 1710000.jr: registering rng-caam 
[    3.480462] caam 1700000.crypto: caam pkc algorithms registered in /proc/crypto 
[    3.488197] usbcore: registered new interface driver usbhid 
[    3.493770] usbhid: USB HID core driver 
[    3.498172] Initializing XFRM netlink socket 
[    3.502532] NET: Registered protocol family 10 
[    3.507411] Segment Routing with IPv6 
[    3.511128] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver 
[    3.517408] NET: Registered protocol family 17 
[    3.521860] NET: Registered protocol family 15 
[    3.526331] 8021q: 802.1Q VLAN Support v1.8 
[    3.530538] 9pnet: Installing 9P2000 support 
[    3.534845] Key type dns_resolver registered 
[    3.539671] registered taskstats version 1 
[    3.546368] rtc-pcf8563 0-0051: setting system clock to 2018-05-09 09:58:51 UTC (1525859931) 
[    3.555839] Waiting for root device /dev/mmcblk0p1... 
[    3.621926] mmc0: new high speed MMC card at address 0001 
[    3.627873] mmcblk0: mmc0:0001 R1J58L 55.1 GiB  
[    3.632857] mmcblk0boot0: mmc0:0001 R1J58L partition 1 16.0 MiB 
[    3.639218] mmcblk0boot1: mmc0:0001 R1J58L partition 2 16.0 MiB 
[    3.645219] mmcblk0rpmb: mmc0:0001 R1J58L partition 3 128 KiB, chardev (243:0) 
[    3.648275] usb 5-1: new full-speed USB device number 2 using xhci-hcd 
[    3.659703]  mmcblk0: p1 
[    3.689111] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode. Opts: (null) 
[    3.697220] VFS: Mounted root (ext4 filesystem) on device 179:1. 
[    3.704120] devtmpfs: mounted 
[    3.707326] Freeing unused kernel memory: 704K 
[    3.805566] alloc_contig_range: [f7c84, f7c85) PFNs busy 
[    3.810935] alloc_contig_range: [f7c85, f7c86) PFNs busy 
[    3.816321] alloc_contig_range: [f7c86, f7c87) PFNs busy 
[    3.822316] alloc_contig_range: [f7c87, f7c88) PFNs busy 
[    3.827760] alloc_contig_range: [f7c84, f7c85) PFNs busy 
[    3.833145] alloc_contig_range: [f7c85, f7c86) PFNs busy 
[    3.838482] alloc_contig_range: [f7c86, f7c87) PFNs busy 
[    3.843974] alloc_contig_range: [f7c87, f7c88) PFNs busy 
[    3.849327] alloc_contig_range: [f7c89, f7c8a) PFNs busy 
[    3.854759] alloc_contig_range: [f7c8a, f7c8b) PFNs busy 
[    3.953848] systemd[1]: systemd 215 running in system mode. (+PAM +AUDIT +SELINUX +IMA +SYSVINIT +LIBCRYPTSETUP +GCRYPT +ACL +XZ -SECCOMP -APPARMOR) 
[    3.967297] systemd[1]: Detected architecture 'arm64'. 
 
Welcome to 
   Debian GNU/Linux 8 (jessie)
   ! 
 
[    4.008950] systemd[1]: Set hostname to <debian>. 
[    4.089527] hid-generic 0003:064F:2AF9.0001: device has no listeners, quitting 
[    4.181619] systemd[1]: Cannot add dependency job for unit dbus.socket, ignoring: Unit dbus.socket failed to load: No such file or directory. 
[    4.194413] systemd[1]: Cannot add dependency job for unit display-manager.service, ignoring: Unit display-manager.service failed to load: No such file or directory. 
[    4.210052] systemd[1]: Starting Forward Password Requests to Wall Directory Watch. 
[    4.217894] systemd[1]: Started Forward Password Requests to Wall Directory Watch. 
[    4.225502] systemd[1]: Expecting device dev-ttyS0.device... 
         Expecting device dev-ttyS0.device... 
[    4.244329] systemd[1]: Starting Remote File Systems (Pre). 
[
      OK  
   ] Reached target Remote File Systems (Pre). 
[    4.264296] systemd[1]: Reached target Remote File Systems (Pre). 
[
      OK  
   ] Reached target Paths. 
[
      OK  
   ] Reached target Encrypted Volumes. 
[
      OK  
   ] Reached target Swap. 
[
      OK  
   ] Created slice Root Slice. 
[
      OK  
   ] Created slice User and Session Slice. 
[
      OK  
   ] Listening on Delayed Shutdown Socket. 
[
      OK  
   ] Listening on /dev/initctl Compatibility Named Pipe. 
[
      OK  
   ] Listening on Journal Socket (/dev/log). 
[
      OK  
   ] Listening on udev Control Socket. 
[
      OK  
   ] Listening on udev Kernel Socket. 
[
      OK  
   ] Listening on Journal Socket. 
[
      OK  
   ] Reached target Sockets. 
[
      OK  
   ] Created slice System Slice. 
[
      OK  
   ] Created slice system-getty.slice. 
[
      OK  
   ] Created slice system-serial\x2dgetty.slice. 
         Starting Load Kernel Modules... 
         Mounting POSIX Message Queue File System... 
         Starting Create Static Device Nodes in /dev... 
         Mounting Huge Pages File System... 
         Mounting Debug File System... 
         Starting udev Coldplug all Devices... 
         Starting Remount Root and Kernel File Systems... 
         Starting Journal Service... 
[
      OK  
   ] Started Journal Service. 
[
      OK  
   ] Reached target Slices. 
[
      OK  
   ] Mounted Debug File System. 
[
      OK  
   ] Mounted Huge Pages File System. 
[
      OK  
   ] Mounted POSIX Message Queue File System. 
[
      OK  
   ] Started Load Kernel Modules. 
[
      OK  
   ] Started Create Static Device Nodes in /dev. 
[
      OK  
   ] Started Remount Root and Kernel File Systems. 
         Starting Load/Save Random Seed... 
         Starting udev Kernel Device Manager... 
[
      OK  
   ] Reached target Local File Systems (Pre). 
         [    4.841702] systemd-udevd[1958]: starting version 215 
Mounting /var/tmp... 
         Mounting /tmp... 
         Starting Apply Kernel Variables... 
         Mounting FUSE Control File System... 
[
      OK  
   ] Mounted /tmp. 
[
      OK  
   ] Mounted /var/tmp. 
[
      OK  
   ] Mounted FUSE Control File System. 
[
      OK  
   ] Started udev Kernel Device Manager. 
[
      OK  
   ] Started udev Coldplug all Devices. 
[
      OK  
   ] Started Load/Save Random Seed. 
[
      OK  
   ] Started Apply Kernel Variables. 
[
      OK  
   ] Found device /dev/ttyS0. 
         Starting Copy rules generated while the root was ro... 
         Starting LSB: Tune IDE hard disks... 
[
      OK  
   ] Reached target Local File Systems. 
[
      OK  
   ] Reached target Remote File Systems. 
         Starting Trigger Flushing of Journal to Persistent Storage... 
         Starting Create Volatile Files and Directories... 
         Starting LSB: Raise network interfaces.... 
[
      OK  
   ] Started Copy rules generated while the root was ro. 
[
      OK  
   ] Started Create Volatile Files and Directories. 
[    5.248194] systemd-journald[1312]: Received request to flush runtime journal from PID 1 
         Starting Update UTMP about System Boot/Shutdown... 
[
      OK  
   ] Started Trigger Flushing of Journal to Persistent Storage. 
[
      OK  
   ] Started LSB: Tune IDE hard disks. 
[
      OK  
   ] Started Update UTMP about System Boot/Shutdown. 
[
      OK  
   ] Started LSB: Raise network interfaces.. 
[
      OK  
   ] Reached target Network. 
[
      OK  
   ] Reached target Network is Online. 
[
      OK  
   ] Reached target System Initialization. 
[
      OK  
   ] Reached target Timers. 
[
      OK  
   ] Reached target Basic System. 
         Starting Internet superserver... 
[
      OK  
   ] Started Internet superserver. 
         Starting Self Monitoring and Reporting Technology (SMART) Daemon... 
[
      OK  
   ] Started Self Monitoring and Reporting Technology (SMART) Daemon. 
         Starting OpenBSD Secure Shell server... 
         Starting Kontron KVX BSP Service... 
         Starting Kontron RTC2 Service... 
         Starting Initialize hardware monitoring sensors... 
         Starting /etc/rc.local Compatibility... 
         Starting getty on tty2-tty6 if dbus and logind are not available... 
         Starting LSB: disk temperature monitoring daemon... 
         Starting Permit User Sessions... 
[
      OK  
   ] Started /etc/rc.local Compatibility. 
[
      OK  
   ] Started LSB: disk temperature monitoring daemon. 
[
      OK  
   ] Started Permit User Sessions. 
[
      OK  
   ] Started getty on tty2-tty6 if dbus and logind are not available. 
[
      OK  
   ] Started Kontron RTC2 Service. 
[
      OK  
   ] Started Initialize hardware monitoring sensors. 
[
      OK  
   ] Started Kontron KVX BSP Service. 
         Starting Getty on tty6... 
[
      OK  
   ] Started Getty on tty6. 
         Starting Getty on tty5... 
[
      OK  
   ] Started Getty on tty5. 
         Starting Getty on tty4... 
[
      OK  
   ] Started Getty on tty4. 
         Starting Getty on tty3... 
[
      OK  
   ] Started Getty on tty3. 
         Starting Getty on tty2... 
[
      OK  
   ] Started Getty on tty2. 
         Starting Getty on tty1... 
[
      OK  
   ] Started Getty on tty1. 
         Starting Serial Getty on ttyS0... 
[
      OK  
   ] Started Serial Getty on ttyS0. 
[
      OK  
   ] Reached target Login Prompts. 
[
      OK  
   ] Started OpenBSD Secure Shell server. 
[
      OK  
   ] Reached target Multi-User System. 
[
      OK  
   ] Reached target Graphical Interface. 
         Starting Update UTMP about System Runlevel Changes... 
[
      OK  
   ] Started Update UTMP about System Runlevel Changes. 
  
Debian GNU/Linux 8 debian ttyS0 
 
debian login: root  
Password:  
Last login: Wed May  9 09:53:15 UTC 2018 on ttyS0 
Linux debian 4.17.0-rc1 #3 SMP Fri May 4 10:03:38 UTC 2018 aarch64 
 
The programs included with the Debian GNU/Linux system are free software; 
the exact distribution terms for each program are described in the 
individual files in /usr/share/doc/*/copyright. 
 
Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent 
permitted by applicable law. 
root@debian:~#  
root@debian:~#  
root@debian:~# lspci -vv 
0000:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0 
 Memory behind bridge: 40000000-4bffffff 
 Prefetchable memory behind bridge: 000000004c000000-000000004c0fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
 Expansion ROM at 404c100000 [disabled] [size=2K] 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 3 
  Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag- RBE+ 
  DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited 
   ClockPM- Surprise- LLActRep+ BwNot+ 
  LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
  RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- 
  RootCap: CRSVisible- 
  RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
  DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd- 
  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- 
  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- 
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
    Compliance De-emphasis: -6dB 
  LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- 
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- 
 Capabilities: [100 v2] Advanced Error Reporting 
  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- 
  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- 
  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ 
  AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- 
 Capabilities: [148 v1] #19 
 Kernel driver in use: pcieport 
 
0000:01:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Region 0: Memory at 404c000000 (64-bit, prefetchable) [size=64K] 
 Bus: primary=01, secondary=02, subordinate=08, sec-latency=0 
 Memory behind bridge: 40000000-4bffffff 
 Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 2 
  Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [60] Express (v1) PCI-Express to PCI/PCI-X Bridge, MSI 00 
  DevCap: MaxPayload 128 bytes, PhantFunc 0 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <16us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [100 v1] Power Budgeting <?> 
 
0000:02:09.0 Bridge: Kontron Device 9035 (rev 46) 
 Subsystem: Kontron Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 128 
 Interrupt: pin A routed to IRQ 0 
 Region 0: Memory at 4048000000 (32-bit, non-prefetchable) [size=1M] 
 Region 1: Memory at 4040000000 (32-bit, non-prefetchable) [size=128M] 
 Capabilities: [78] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 
0000:02:0e.0 PCI bridge: Pericom Semiconductor PCI Express to PCI-XPI7C9X130 PCI-X Bridge (rev 04) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 128, Cache Line Size: 32 bytes 
 Bus: primary=02, secondary=03, subordinate=08, sec-latency=0 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [80] PCI-X bridge device 
  Secondary Status: 64bit- 133MHz- SCD- USC- SCO- SRD- Freq=conv 
  Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- 
  Upstream: Capacity=16 CommitmentLimit=16 
  Downstream: Capacity=16 CommitmentLimit=16 
 Capabilities: [90] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [a8] Subsystem: Device 0000:0000 
 Capabilities: [b0] Express (v1) PCI/PCI-X to PCI-Express Bridge, MSI 00 
  DevCap: MaxPayload 512 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend+ 
  LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <512ns, L1 <1us 
   ClockPM- Surprise- LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk+ 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train+ SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [f0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 
0000:03:00.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev ff) (prog-if ff) 
 !!! Unknown header type 7f 
 Kernel driver in use: pcieport 
 
0000:04:02.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev ff) (prog-if ff) 
 !!! Unknown header type 7f 
 Kernel driver in use: pcieport 
 
0001:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 Expansion ROM at 4840000000 [disabled] [size=2K] 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 3 
  Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag- RBE+ 
  DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited 
   ClockPM- Surprise- LLActRep+ BwNot+ 
  LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
  RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- 
  RootCap: CRSVisible- 
  RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
  DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd- 
  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- 
  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- 
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
    Compliance De-emphasis: -6dB 
  LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- 
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- 
 Capabilities: [100 v2] Advanced Error Reporting 
  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- 
  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- 
  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ 
  AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- 
 Capabilities: [148 v1] #19 
 Kernel driver in use: pcieport 
 
0002:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 Expansion ROM at 5040000000 [disabled] [size=2K] 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 3 
  Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag- RBE+ 
  DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited 
   ClockPM- Surprise- LLActRep+ BwNot+ 
  LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
  RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- 
  RootCap: CRSVisible- 
  RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
  DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd- 
  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- 
  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- 
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
    Compliance De-emphasis: -6dB 
  LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- 
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- 
 Capabilities: [100 v2] Advanced Error Reporting 
  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- 
  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- 
  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ 
  AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- 
 Capabilities: [148 v1] #19 
 Kernel driver in use: pcieport 
 
root@debian:~#  
root@debian:~# lspci 
0000:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) 
0000:01:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) 
0000:02:09.0 Bridge: Kontron Device 9035 (rev 46) 
0000:02:0e.0 PCI bridge: Pericom Semiconductor PCI Express to PCI-XPI7C9X130 PCI-X Bridge (rev 04) 
0000:03:00.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev ff) 
0000:04:02.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev ff) 
0001:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) 
0002:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) 
root@debian:~#  
root@debian:~# lspci -t 
-+-[0002:00]---00.0-[01-ff]-- 
 +-[0001:00]---00.0-[01-ff]-- 
 \-[0000:00]---00.0-[01-ff]----00.0-[02-08]--+-09.0 
                                             \-0e.0-[03-08]--+-[0000:04]---02.0 
                                                             \-[0000:03]---00.0 
root@debian:~# 

[-- Attachment #5: 4.17-rc1_probe_ok_without_pcieaspmoff.txt --]
[-- Type: text/plain, Size: 70260 bytes --]

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] 
[    0.000000] Linux version 4.17.0-rc1 (root@debian) (gcc version 4.9.2 (Debian/Linaro 4.9.2-10)) #3 SMP Fri May 4 10:03:38 UTC 2018 
[    0.000000] Machine model: VM6103 Board 
[    0.000000] earlycon: uart8250 at MMIO 0x00000000021c0500 (options '') 
[    0.000000] bootconsole [uart8250] enabled 
[    0.000000] efi: Getting EFI parameters from FDT: 
[    0.000000] efi: UEFI not found. 
[    0.000000] cma: Reserved 128 MiB at 0x00000000f7c00000 
[    0.000000] /cpus/cpu@2: missing enable-method property 
[    0.000000] /cpus/cpu@3: missing enable-method property 
[    0.000000] WARNING: x1-x3 nonzero in violation of boot protocol: 
[    0.000000]  x1: 0000000000000000 
[    0.000000]  x2: 0000000000000000 
[    0.000000]  x3: 0000000080080000 
[    0.000000] This indicates a broken bootloader or old kernel 
[    0.000000] random: fast init done 
[    0.000000] percpu: Embedded 23 pages/cpu @        (ptrval) s55808 r8192 d30208 u94208 
[    0.000000] Detected VIPT I-cache on CPU0 
[    0.000000] CPU features: detected: Kernel page table isolation (KPTI) 
[    0.000000] CPU features: enabling workaround for ARM erratum 845719 
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1031688 
[    0.000000] Kernel command line: console=ttyS0,115200 root=/dev/mmcblk0p1 rw rootwait mtdparts=1550000.quadspi:2m(uboot),256k(boot-env),-(User_Data) earlycon=uart8250,mmio,0x21c0
500 cma=128M cpld_i2c.smb_tmo=0 
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) 
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) 
[    0.000000] software IO TLB [mem 0xf3c00000-0xf7c00000] (64MB) mapped at [        (ptrval)-        (ptrval)] 
[    0.000000] Memory: 3853464K/4192256K available (7612K kernel code, 782K rwdata, 2904K rodata, 704K init, 232K bss, 207720K reserved, 131072K cma-reserved) 
[    0.000000] Hierarchical RCU implementation. 
[    0.000000]  RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2. 
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 
[    0.000000] GIC: Using split EOI/Deactivate mode 
[    0.000000] arch_timer: Enabling global workaround for Freescale erratum a005858 
[    0.000000] GIC: PPI14 is secure or misconfigured 
[    0.000000] arch_timer: WARNING: Invalid trigger for IRQ3, assuming level low 
[    0.000000] arch_timer: WARNING: Please fix your firmware 
[    0.000000] arch_timer: CPU0: Trapping CNTVCT access 
[    0.000000] arch_timer: cp15 timer(s) running at 25.00MHz (phys). 
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x5c40939b5, max_idle_ns: 440795202646 ns 
[    0.000003] sched_clock: 56 bits at 25MHz, resolution 40ns, wraps every 4398046511100ns 
[    0.008453] Console: colour dummy device 80x25 
[    0.012936] Calibrating delay loop (skipped), value calculated using timer frequency.. 50.00 BogoMIPS (lpj=100000) 
[    0.023345] pid_max: default: 32768 minimum: 301 
[    0.028059] Security Framework initialized 
[    0.032228] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes) 
[    0.038979] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes) 
[    0.046911] ASID allocator initialised with 32768 entries 
[    0.052394] Hierarchical SRCU implementation. 
[    0.057672] EFI services will not be available. 
[    0.062308] smp: Bringing up secondary CPUs ... 
[    0.067111] Detected VIPT I-cache on CPU1 
[    0.067139] arch_timer: CPU1: Trapping CNTVCT access 
[    0.067145] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] 
[    0.067210] smp: Brought up 1 node, 2 CPUs 
[    0.086910] SMP: Total of 2 processors activated. 
[    0.091639] CPU features: detected: 32-bit EL0 Support 
[    0.099902] CPU: All CPU(s) started at EL2 
[    0.104031] alternatives: patching kernel code 
[    0.109476] devtmpfs: initialized 
[    0.119383] Built 1 zonelists, mobility grouping on.  Total pages: 996134 
[    0.127214] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns 
[    0.137025] futex hash table entries: 512 (order: 4, 65536 bytes) 
[    0.143284] pinctrl core: initialized pinctrl subsystem 
[    0.149325] DMI not present or invalid. 
[    0.153354] NET: Registered protocol family 16 
[    0.158115] audit: initializing netlink subsys (disabled) 
[    0.164115] audit: type=2000 audit(0.112:1): state=initialized audit_enabled=0 res=1 
[    0.171934] cpuidle: using governor ladder 
[    0.176068] cpuidle: using governor menu 
[    0.180172] vdso: 2 pages (1 code @ 00000000185e8872, 1 data @ 00000000ba7f08d1) 
[    0.187617] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. 
[    0.194994] DMA: preallocated 256 KiB pool for atomic allocations 
[    0.201302] Serial: AMBA PL011 UART driver 
[    0.205676] irq: type mismatch, failed to map hwirq-30 for interrupt-controller@1400000! 
[    0.214608] Machine: VM6103 Board 
[    0.217941] SoC family: QorIQ LS1043A 
[    0.221614] SoC ID: svr:0x87920a10, Revision: 1.0 
[    0.251583] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages 
[    0.258628] cryptd: max_cpu_qlen set to 1000 
[    0.264129] vgaarb: loaded 
[    0.267080] SCSI subsystem initialized 
[    0.271111] usbcore: registered new interface driver usbfs 
[    0.276661] usbcore: registered new interface driver hub 
[    0.282031] usbcore: registered new device driver usb 
[    0.287384] imx-i2c 2180000.i2c: can't get pinctrl, bus recovery not supported 
[    0.294973] i2c i2c-0: IMX I2C adapter registered 
[    0.299713] i2c i2c-0: can't use DMA, using PIO instead. 
[    0.305196] pps_core: LinuxPPS API ver. 1 registered 
[    0.310188] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> 
[    0.319385] PTP clock support registered 
[    0.323448] fsl-ifc 1530000.ifc: Freescale Integrated Flash Controller 
[    0.330028] fsl-ifc 1530000.ifc: IFC version 1.4, 8 banks 
[    0.336213] clocksource: Switched to clocksource arch_sys_counter 
[    0.342444] VFS: Disk quotas dquot_6.6.0 
[    0.346445] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) 
[    0.360666] NET: Registered protocol family 2 
[    0.365396] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes) 
[    0.373322] TCP established hash table entries: 32768 (order: 6, 262144 bytes) 
[    0.380888] TCP bind hash table entries: 32768 (order: 7, 524288 bytes) 
[    0.388109] TCP: Hash tables configured (established 32768 bind 32768) 
[    0.394739] UDP hash table entries: 2048 (order: 4, 65536 bytes) 
[    0.400865] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes) 
[    0.407495] NET: Registered protocol family 1 
[    0.412099] RPC: Registered named UNIX socket transport module. 
[    0.418069] RPC: Registered udp transport module. 
[    0.422799] RPC: Registered tcp transport module. 
[    0.427526] RPC: Registered tcp NFSv4.1 backchannel transport module. 
[    0.434516] hw perfevents: failed to find logical CPU for cpu 
[    0.440317] hw perfevents: failed to find logical CPU for cpu 
[    0.446186] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available 
[    0.454404] kvm [1]: 8-bit VMID 
[    0.458071] kvm [1]: vgic interrupt IRQ1 
[    0.462019] kvm [1]: Invalid trigger for IRQ4, assuming level low 
[    0.468147] GIC: PPI11 is secure or misconfigured 
[    0.472944] kvm [1]: Hyp mode initialized successfully 
[    0.481009] workingset: timestamp_bits=46 max_order=20 bucket_order=0 
[    0.488078] NFS: Registering the id_resolver key type 
[    0.493177] Key type id_resolver registered 
[    0.497382] Key type id_legacy registered 
[    0.501505] fuse init (API version 7.26) 
[    0.505615] 9p: Installing v9fs 9p2000 file system support 
[    0.513618] io scheduler noop registered 
[    0.517590] io scheduler cfq registered (default) 
[    0.522322] io scheduler mq-deadline registered 
[    0.526875] io scheduler kyber registered 
[    0.533168] PCI: OF: host bridge /soc/pcie@3400000 ranges: 
[    0.538714] PCI: OF:    IO 0x4000010000..0x400001ffff -> 0x00000000 
[    0.545022] PCI: OF:   MEM 0x4040000000..0x407fffffff -> 0x40000000 
[    0.551439] layerscape-pcie 3400000.pcie: PCI host bridge to bus 0000:00 
[    0.558185] pci_bus 0000:00: root bus resource [bus 00-ff] 
[    0.563701] pci_bus 0000:00: root bus resource [io  0x0000-0xffff] 
[    0.569917] pci_bus 0000:00: root bus resource [mem 0x4040000000-0x407fffffff] (bus address [0x40000000-0x7fffffff]) 
[    0.582999] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force' 
[    0.594738] pci_bus 0000:02: extended config space not accessible on secondary bus 
[    0.604103] pci 0000:02:0e.0: enabling Extended Tags 
[    0.610652] pci_bus 0000:03: extended config space not accessible on secondary bus 
[    0.618608] pci 0000:03:00.0: enabling Extended Tags 
[    1.628225] pci 0000:02:0e.0: ASPM: Could not configure common clock 
[    1.636299] pci_bus 0000:04: extended config space not accessible on secondary bus 
[    1.644389] pci 0000:04:02.0: enabling Extended Tags 
[    1.650174] pci 0000:04:03.0: enabling Extended Tags 
[    1.655968] pci 0000:04:04.0: enabling Extended Tags 
[    1.661768] pci 0000:04:05.0: enabling Extended Tags 
[    1.668828] pci_bus 0000:05: extended config space not accessible on secondary bus 
[    1.679395] pci_bus 0000:06: extended config space not accessible on secondary bus 
[    1.689972] pci_bus 0000:07: extended config space not accessible on secondary bus 
[    1.700545] pci_bus 0000:08: extended config space not accessible on secondary bus 
[    1.711496] pci 0000:00:00.0: BAR 8: assigned [mem 0x4040000000-0x404bffffff] 
[    1.718681] pci 0000:00:00.0: BAR 9: assigned [mem 0x404c000000-0x404c0fffff 64bit pref] 
[    1.726821] pci 0000:00:00.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    1.732952] pci 0000:00:00.0: BAR 6: assigned [mem 0x404c100000-0x404c1007ff pref] 
[    1.740572] pci 0000:01:00.0: BAR 8: assigned [mem 0x4040000000-0x404bffffff] 
[    1.747752] pci 0000:01:00.0: BAR 0: assigned [mem 0x404c000000-0x404c00ffff 64bit pref] 
[    1.755934] pci 0000:01:00.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    1.762070] pci 0000:02:09.0: BAR 1: assigned [mem 0x4040000000-0x4047ffffff] 
[    1.769262] pci 0000:02:09.0: BAR 0: assigned [mem 0x4048000000-0x40480fffff] 
[    1.776454] pci 0000:02:0e.0: BAR 8: assigned [mem 0x4048100000-0x40484fffff] 
[    1.783632] pci 0000:02:0e.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    1.789763] pci 0000:03:00.0: BAR 8: assigned [mem 0x4048100000-0x40484fffff] 
[    1.796942] pci 0000:03:00.0: BAR 7: assigned [io  0x1000-0x4fff] 
[    1.803075] pci 0000:04:02.0: BAR 8: assigned [mem 0x4048100000-0x40481fffff] 
[    1.810254] pci 0000:04:03.0: BAR 8: assigned [mem 0x4048200000-0x40482fffff] 
[    1.817433] pci 0000:04:04.0: BAR 8: assigned [mem 0x4048300000-0x40483fffff] 
[    1.824611] pci 0000:04:05.0: BAR 8: assigned [mem 0x4048400000-0x40484fffff] 
[    1.831789] pci 0000:04:02.0: BAR 7: assigned [io  0x1000-0x1fff] 
[    1.837919] pci 0000:04:03.0: BAR 7: assigned [io  0x2000-0x2fff] 
[    1.844049] pci 0000:04:04.0: BAR 7: assigned [io  0x3000-0x3fff] 
[    1.850178] pci 0000:04:05.0: BAR 7: assigned [io  0x4000-0x4fff] 
[    1.856311] pci 0000:05:00.0: BAR 0: assigned [mem 0x4048100000-0x404811ffff] 
[    1.863506] pci 0000:05:00.0: BAR 3: assigned [mem 0x4048120000-0x4048123fff] 
[    1.870701] pci 0000:05:00.0: BAR 2: assigned [io  0x1000-0x101f] 
[    1.876847] pci 0000:04:02.0: PCI bridge to [bus 05] 
[    1.881848] pci 0000:04:02.0:   bridge window [io  0x1000-0x1fff] 
[    1.887998] pci 0000:04:02.0:   bridge window [mem 0x4048100000-0x40481fffff] 
[    1.895222] pci 0000:06:00.0: BAR 0: assigned [mem 0x4048200000-0x404821ffff] 
[    1.902418] pci 0000:06:00.0: BAR 3: assigned [mem 0x4048220000-0x4048223fff] 
[    1.909613] pci 0000:06:00.0: BAR 2: assigned [io  0x2000-0x201f] 
[    1.915759] pci 0000:04:03.0: PCI bridge to [bus 06] 
[    1.920759] pci 0000:04:03.0:   bridge window [io  0x2000-0x2fff] 
[    1.926910] pci 0000:04:03.0:   bridge window [mem 0x4048200000-0x40482fffff] 
[    1.934130] pci 0000:07:00.0: BAR 0: assigned [mem 0x4048300000-0x404831ffff] 
[    1.941325] pci 0000:07:00.0: BAR 3: assigned [mem 0x4048320000-0x4048323fff] 
[    1.948520] pci 0000:07:00.0: BAR 2: assigned [io  0x3000-0x301f] 
[    1.954666] pci 0000:04:04.0: PCI bridge to [bus 07] 
[    1.959667] pci 0000:04:04.0:   bridge window [io  0x3000-0x3fff] 
[    1.965816] pci 0000:04:04.0:   bridge window [mem 0x4048300000-0x40483fffff] 
[    1.973037] pci 0000:08:00.0: BAR 0: assigned [mem 0x4048400000-0x404841ffff] 
[    1.980232] pci 0000:08:00.0: BAR 3: assigned [mem 0x4048420000-0x4048423fff] 
[    1.987427] pci 0000:08:00.0: BAR 2: assigned [io  0x4000-0x401f] 
[    1.993573] pci 0000:04:05.0: PCI bridge to [bus 08] 
[    1.998573] pci 0000:04:05.0:   bridge window [io  0x4000-0x4fff] 
[    2.004722] pci 0000:04:05.0:   bridge window [mem 0x4048400000-0x40484fffff] 
[    2.011940] pci 0000:03:00.0: PCI bridge to [bus 04-08] 
[    2.017202] pci 0000:03:00.0:   bridge window [io  0x1000-0x4fff] 
[    2.023354] pci 0000:03:00.0:   bridge window [mem 0x4048100000-0x40484fffff] 
[    2.030572] pci 0000:02:0e.0: PCI bridge to [bus 03-08] 
[    2.035833] pci 0000:02:0e.0:   bridge window [io  0x1000-0x4fff] 
[    2.041981] pci 0000:02:0e.0:   bridge window [mem 0x4048100000-0x40484fffff] 
[    2.049195] pci 0000:01:00.0: PCI bridge to [bus 02-08] 
[    2.054456] pci 0000:01:00.0:   bridge window [io  0x1000-0x4fff] 
[    2.060602] pci 0000:01:00.0:   bridge window [mem 0x4040000000-0x404bffffff] 
[    2.067815] pci 0000:00:00.0: PCI bridge to [bus 01-ff] 
[    2.073071] pci 0000:00:00.0:   bridge window [io  0x1000-0x4fff] 
[    2.079200] pci 0000:00:00.0:   bridge window [mem 0x4040000000-0x404bffffff] 
[    2.086378] pci 0000:00:00.0:   bridge window [mem 0x404c000000-0x404c0fffff 64bit pref] 
[    2.094686] pcieport 0000:00:00.0: Signaling PME with IRQ 57 
[    2.100483] pcieport 0000:00:00.0: AER enabled with IRQ 57 
[    2.107579] PCI: OF: host bridge /soc/pcie@3500000 ranges: 
[    2.113111] PCI: OF:    IO 0x4800010000..0x480001ffff -> 0x00000000 
[    2.119420] PCI: OF:   MEM 0x4840000000..0x487fffffff -> 0x40000000 
[    2.125830] layerscape-pcie 3500000.pcie: PCI host bridge to bus 0001:00 
[    2.132574] pci_bus 0001:00: root bus resource [bus 00-ff] 
[    2.138095] pci_bus 0001:00: root bus resource [io  0x10000-0x1ffff] (bus address [0x0000-0xffff]) 
[    2.147108] pci_bus 0001:00: root bus resource [mem 0x4840000000-0x487fffffff] (bus address [0x40000000-0x7fffffff]) 
[    2.160966] pci 0001:00:00.0: BAR 6: assigned [mem 0x4840000000-0x48400007ff pref] 
[    2.168583] pci 0001:00:00.0: PCI bridge to [bus 01-ff] 
[    2.173972] pcieport 0001:00:00.0: Signaling PME with IRQ 59 
[    2.179745] pcieport 0001:00:00.0: AER enabled with IRQ 59 
[    2.185415] PCI: OF: host bridge /soc/pcie@3600000 ranges: 
[    2.190943] PCI: OF:    IO 0x5000010000..0x500001ffff -> 0x00000000 
[    2.197252] PCI: OF:   MEM 0x5040000000..0x507fffffff -> 0x40000000 
[    2.203654] layerscape-pcie 3600000.pcie: PCI host bridge to bus 0002:00 
[    2.210399] pci_bus 0002:00: root bus resource [bus 00-ff] 
[    2.215919] pci_bus 0002:00: root bus resource [io  0x20000-0x2ffff] (bus address [0x0000-0xffff]) 
[    2.224933] pci_bus 0002:00: root bus resource [mem 0x5040000000-0x507fffffff] (bus address [0x40000000-0x7fffffff]) 
[    2.238783] pci 0002:00:00.0: BAR 6: assigned [mem 0x5040000000-0x50400007ff pref] 
[    2.246402] pci 0002:00:00.0: PCI bridge to [bus 01-ff] 
[    2.251784] pcieport 0002:00:00.0: Signaling PME with IRQ 60 
[    2.257557] pcieport 0002:00:00.0: AER enabled with IRQ 60 
[    2.267620] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled 
[    2.275326] console [ttyS0] disabled 
[    2.278950] 21c0500.serial: ttyS0 at MMIO 0x21c0500 (irq = 18, base_baud = 25000000) is a 16550A 
[    2.287803] console [ttyS0] enabled 
[    2.287803] console [ttyS0] enabled 
[    2.294787] bootconsole [uart8250] disabled 
[    2.294787] bootconsole [uart8250] disabled 
[    2.303458] 21c0600.serial: ttyS1 at MMIO 0x21c0600 (irq = 18, base_baud = 25000000) is a 16550A 
[    2.312534] 21d0500.serial: ttyS2 at MMIO 0x21d0500 (irq = 19, base_baud = 25000000) is a 16550A 
[    2.321614] 21d0600.serial: ttyS3 at MMIO 0x21d0600 (irq = 19, base_baud = 25000000) is a 16550A 
[    2.330898] msm_serial: driver initialized 
[    2.336074] cacheinfo: Unable to detect cache hierarchy for CPU 0 
[    2.346640] brd: module loaded 
[    2.353874] loop: module loaded 
[    2.357203] WARNING: CPU: 1 PID: 1 at mm/slab_common.c:996 kmalloc_slab+0x60/0x68 
[    2.364675] Modules linked in: 
[    2.367726] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.17.0-rc1 #3 
[    2.373983] Hardware name: VM6103 Board (DT) 
[    2.378245] pstate: 20000005 (nzCv daif -PAN -UAO) 
[    2.383028] pc : kmalloc_slab+0x60/0x68 
[    2.386858] lr : __kmalloc_track_caller+0x18/0x10c 
[    2.391637] sp : ffff00000801ba10 
[    2.394942] x29: ffff00000801ba10 x28: 0000000000000000  
[    2.400246] x27: 0000000000000001 x26: 00000000088814a8  
[    2.405551] x25: 0000000000000001 x24: ffff800876e97020  
[    2.410855] x23: ffff00000887ff20 x22: 0000000000000000  
[    2.416159] x21: 00000000014080c0 x20: ffff800876e97020  
[    2.421463] x19: ffff800877086c00 x18: 0000000000000000  
[    2.426767] x17: 0000000000000001 x16: 0000000000000011  
[    2.432071] x15: 0000000000000cb0 x14: 0000000000000000  
[    2.437375] x13: 0000000000000000 x12: 0000000000000000  
[    2.442679] x11: 0000000000000013 x10: 0101010101010101  
[    2.447984] x9 : 0000000000000000 x8 : ffff8008770ae280  
[    2.453289] x7 : 0000000000000000 x6 : 000000000000003f  
[    2.458593] x5 : 0000000000000040 x4 : 00000000014080c0  
[    2.463897] x3 : 00000000008881b0 x2 : 0000000000000000  
[    2.469201] x1 : 00000000014080c0 x0 : 00000000008881b0  
[    2.474506] Call trace: 
[    2.476945]  kmalloc_slab+0x60/0x68 
[    2.480427]  devm_kmalloc+0x28/0x70 
[    2.483909]  at24_probe+0x140/0x58c 
[    2.487392]  i2c_device_probe+0x14c/0x25c 
[    2.491394]  driver_probe_device+0x224/0x308 
[    2.495657]  __driver_attach+0xa4/0xa8 
[    2.499398]  bus_for_each_dev+0x50/0x98 
[    2.503225]  driver_attach+0x20/0x28 
[    2.506793]  bus_add_driver+0x1c0/0x224 
[    2.510620]  driver_register+0x60/0xf4 
[    2.514360]  i2c_register_driver+0x44/0x84 
[    2.518450]  at24_init+0x54/0x5c 
[    2.521671]  do_one_initcall+0x44/0x130 
[    2.525501]  kernel_init_freeable+0x13c/0x1e0 
[    2.529850]  kernel_init+0x10/0xfc 
[    2.533243]  ret_from_fork+0x10/0x18 
[    2.536812] ---[ end trace e7b0ed154d15d001 ]--- 
[    2.541454] at24: probe of 0-0052 failed with error -12 
[    2.548180] ahci-qoriq 3200000.sata: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl platform mode 
[    2.557151] ahci-qoriq 3200000.sata: flags: 64bit ncq sntf pm clo only pmp fbs pio slum part ccc sds apst  
[    2.567315] scsi host0: ahci-qoriq 
[    2.570862] ata1: SATA max UDMA/133 mmio [mem 0x03200000-0x0320ffff] port 0x100 irq 30 
[    2.579815] fsl-quadspi 1550000.quadspi: n25q128a11 (16384 Kbytes) 
[    2.586009] 3 cmdlinepart partitions found on MTD device 1550000.quadspi 
[    2.592710] Creating 3 MTD partitions on "1550000.quadspi": 
[    2.598283] 0x000000000000-0x000000200000 : "uboot" 
[    2.603632] 0x000000200000-0x000000240000 : "boot-env" 
[    2.609203] 0x000000240000-0x000001000000 : "User_Data" 
[    2.615713] libphy: Fixed MDIO Bus: probed 
[    2.620048] tun: Universal TUN/TAP device driver, 1.6 
[    2.625680] libphy: Freescale XGMAC MDIO Bus: probed 
[    2.631398] libphy: Freescale XGMAC MDIO Bus: probed 
[    2.636476] libphy: Freescale XGMAC MDIO Bus: probed 
[    2.641551] libphy: Freescale XGMAC MDIO Bus: probed 
[    2.646627] libphy: Freescale XGMAC MDIO Bus: probed 
[    2.651702] libphy: Freescale XGMAC MDIO Bus: probed 
[    2.656775] libphy: Freescale XGMAC MDIO Bus: probed 
[    2.661847] libphy: Freescale XGMAC MDIO Bus: probed 
[    2.666921] libphy: Freescale XGMAC MDIO Bus: probed 
[    2.672000] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI 
[    2.679048] e1000: Copyright (c) 1999-2006 Intel Corporation. 
[    2.684842] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k 
[    2.690674] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. 
[    2.696983] e1000e 0000:05:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    2.706344] e1000e 0000:05:00.0 0000:05:00.0 (uninitialized): Failed to initialize MSI-X interrupts.  Falling back to MSI interrupts. 
[    2.718376] e1000e 0000:05:00.0 0000:05:00.0 (uninitialized): Failed to initialize MSI interrupts.  Falling back to legacy interrupts. 
[    2.790309] e1000e 0000:05:00.0 0000:05:00.0 (uninitialized): registered PHC clock 
[    2.860240] e1000e 0000:05:00.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:03 
[    2.868158] e1000e 0000:05:00.0 eth0: Intel(R) PRO/1000 Network Connection 
[    2.875122] e1000e 0000:05:00.0 eth0: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    2.882204] e1000e 0000:06:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    2.890490] ata1: SATA link down (SStatus 0 SControl 300) 
[    2.891560] e1000e 0000:06:00.0 0000:06:00.0 (uninitialized): Failed to initialize MSI-X interrupts.  Falling back to MSI interrupts. 
[    2.908920] e1000e 0000:06:00.0 0000:06:00.0 (uninitialized): Failed to initialize MSI interrupts.  Falling back to legacy interrupts. 
[    2.982303] e1000e 0000:06:00.0 0000:06:00.0 (uninitialized): registered PHC clock 
[    3.052190] e1000e 0000:06:00.0 eth1: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:02 
[    3.060109] e1000e 0000:06:00.0 eth1: Intel(R) PRO/1000 Network Connection 
[    3.067074] e1000e 0000:06:00.0 eth1: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    3.074120] e1000e 0000:07:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    3.083474] e1000e 0000:07:00.0 0000:07:00.0 (uninitialized): Failed to initialize MSI-X interrupts.  Falling back to MSI interrupts. 
[    3.095502] e1000e 0000:07:00.0 0000:07:00.0 (uninitialized): Failed to initialize MSI interrupts.  Falling back to legacy interrupts. 
[    3.170277] e1000e 0000:07:00.0 0000:07:00.0 (uninitialized): registered PHC clock 
[    3.240171] e1000e 0000:07:00.0 eth2: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:01 
[    3.248091] e1000e 0000:07:00.0 eth2: Intel(R) PRO/1000 Network Connection 
[    3.255055] e1000e 0000:07:00.0 eth2: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    3.262124] e1000e 0000:08:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode 
[    3.271478] e1000e 0000:08:00.0 0000:08:00.0 (uninitialized): Failed to initialize MSI-X interrupts.  Falling back to MSI interrupts. 
[    3.283507] e1000e 0000:08:00.0 0000:08:00.0 (uninitialized): Failed to initialize MSI interrupts.  Falling back to legacy interrupts. 
[    3.358277] e1000e 0000:08:00.0 0000:08:00.0 (uninitialized): registered PHC clock 
[    3.428173] e1000e 0000:08:00.0 eth3: (PCI Express:2.5GT/s:Width x1) 00:01:06:00:43:00 
[    3.436092] e1000e 0000:08:00.0 eth3: Intel(R) PRO/1000 Network Connection 
[    3.443055] e1000e 0000:08:00.0 eth3: MAC: 3, PHY: 8, PBA No: FFFFFF-0FF 
[    3.449808] sky2: driver version 1.30 
[    3.454259] VFIO - User Level meta-driver version: 0.3 
[    3.461035] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver 
[    3.467562] ehci-pci: EHCI PCI platform driver 
[    3.472039] ehci-platform: EHCI generic platform driver 
[    3.477448] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver 
[    3.483631] ohci-pci: OHCI PCI platform driver 
[    3.488105] ohci-platform: OHCI generic platform driver 
[    3.493933] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller 
[    3.499431] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1 
[    3.507337] xhci-hcd xhci-hcd.0.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x02010010 
[    3.516066] xhci-hcd xhci-hcd.0.auto: irq 27, io mem 0x02f00000 
[    3.522481] hub 1-0:1.0: USB hub found 
[    3.526253] hub 1-0:1.0: 1 port detected 
[    3.530393] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller 
[    3.535889] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2 
[    3.543551] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0  SuperSpeed 
[    3.550210] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. 
[    3.558649] hub 2-0:1.0: USB hub found 
[    3.562417] hub 2-0:1.0: 1 port detected 
[    3.566614] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller 
[    3.572109] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 3 
[    3.579997] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x02010010 
[    3.588718] xhci-hcd xhci-hcd.1.auto: irq 28, io mem 0x03000000 
[    3.595069] hub 3-0:1.0: USB hub found 
[    3.598839] hub 3-0:1.0: 1 port detected 
[    3.602957] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller 
[    3.608451] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 4 
[    3.616112] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0  SuperSpeed 
[    3.622765] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM. 
[    3.631195] hub 4-0:1.0: USB hub found 
[    3.635009] hub 4-0:1.0: 1 port detected 
[    3.639205] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller 
[    3.644701] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 5 
[    3.652590] xhci-hcd xhci-hcd.2.auto: hcc params 0x0220f66d hci version 0x100 quirks 0x02010010 
[    3.661310] xhci-hcd xhci-hcd.2.auto: irq 29, io mem 0x03100000 
[    3.667653] hub 5-0:1.0: USB hub found 
[    3.671469] hub 5-0:1.0: 1 port detected 
[    3.675589] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller 
[    3.681086] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 6 
[    3.688748] xhci-hcd xhci-hcd.2.auto: Host supports USB 3.0  SuperSpeed 
[    3.695401] usb usb6: We don't know the algorithms for LPM for this host, disabling LPM. 
[    3.703839] hub 6-0:1.0: USB hub found 
[    3.707641] hub 6-0:1.0: 1 port detected 
[    3.711916] usbcore: registered new interface driver usb-storage 
[    3.718084] mousedev: PS/2 mouse device common for all mice 
[    3.730702] rtc-pcf8563 0-0051: rtc core: registered rtc-pcf8563 as rtc0 
[    3.738529] i2c /dev entries driver 
[    3.744869] ina2xx 0-0040: power monitor ina220 (Rshunt = 1000 uOhm) 
[    3.751341] lm90 0-004c: 0-004c supply vcc not found, using dummy regulator 
[    3.760360] qoriq_cpufreq: Freescale QorIQ CPU frequency scaling driver 
[    3.767261] sdhci: Secure Digital Host Controller Interface driver 
[    3.773439] sdhci: Copyright(c) Pierre Ossman 
[    3.777814] sdhci-pltfm: SDHCI platform and OF driver helper 
[    3.808229] mmc0: SDHCI controller on 1560000.esdhc [1560000.esdhc] using ADMA 64-bit 
[    3.817666] caam 1700000.crypto: Instantiated RNG4 SH1 
[    3.822811] caam 1700000.crypto: device ID = 0x0a12060000000000 (Era 8) 
[    3.829427] caam 1700000.crypto: job rings = 4, qi = 1, dpaa2 = no 
[    3.840297] caam algorithms registered in /proc/crypto 
[    3.846700] caam_jr 1710000.jr: registering rng-caam 
[    3.851772] caam 1700000.crypto: caam pkc algorithms registered in /proc/crypto 
[    3.859506] usbcore: registered new interface driver usbhid 
[    3.865077] usbhid: USB HID core driver 
[    3.869476] Initializing XFRM netlink socket 
[    3.873837] NET: Registered protocol family 10 
[    3.878959] Segment Routing with IPv6 
[    3.882667] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver 
[    3.888935] NET: Registered protocol family 17 
[    3.893401] NET: Registered protocol family 15 
[    3.897875] 8021q: 802.1Q VLAN Support v1.8 
[    3.902083] 9pnet: Installing 9P2000 support 
[    3.906386] Key type dns_resolver registered 
[    3.911252] registered taskstats version 1 
[    3.917707] rtc-pcf8563 0-0051: setting system clock to 2018-05-09 09:52:54 UTC (1525859574) 
[    3.927187] Waiting for root device /dev/mmcblk0p1... 
[    3.952156] mmc0: new high speed MMC card at address 0001 
[    3.958109] mmcblk0: mmc0:0001 R1J58L 55.1 GiB  
[    3.963091] mmcblk0boot0: mmc0:0001 R1J58L partition 1 16.0 MiB 
[    3.969449] mmcblk0boot1: mmc0:0001 R1J58L partition 2 16.0 MiB 
[    3.975452] mmcblk0rpmb: mmc0:0001 R1J58L partition 3 128 KiB, chardev (243:0) 
[    3.983464]  mmcblk0: p1 
[    4.001029] EXT4-fs (mmcblk0p1): mounted filesystem with ordered data mode. Opts: (null) 
[    4.009139] VFS: Mounted root (ext4 filesystem) on device 179:1. 
[    4.016046] devtmpfs: mounted 
[    4.019249] Freeing unused kernel memory: 704K 
[    4.036230] usb 5-1: new full-speed USB device number 2 using xhci-hcd 
[    4.189478] alloc_contig_range: [f7c84, f7c85) PFNs busy 
[    4.194825] alloc_contig_range: [f7c85, f7c86) PFNs busy 
[    4.200199] alloc_contig_range: [f7c86, f7c87) PFNs busy 
[    4.205576] alloc_contig_range: [f7c87, f7c88) PFNs busy 
[    4.211087] alloc_contig_range: [f7c84, f7c85) PFNs busy 
[    4.216424] alloc_contig_range: [f7c85, f7c86) PFNs busy 
[    4.221791] alloc_contig_range: [f7c86, f7c87) PFNs busy 
[    4.227148] alloc_contig_range: [f7c87, f7c88) PFNs busy 
[    4.232536] alloc_contig_range: [f7c89, f7c8a) PFNs busy 
[    4.237900] alloc_contig_range: [f7c8a, f7c8b) PFNs busy 
[    4.248655] systemd[1]: systemd 215 running in system mode. (+PAM +AUDIT +SELINUX +IMA +SYSVINIT +LIBCRYPTSETUP +GCRYPT +ACL +XZ -SECCOMP -APPARMOR) 
[    4.262081] systemd[1]: Detected architecture 'arm64'. 
 
Welcome to 
   Debian GNU/Linux 8 (jessie)
   ! 
 
[    4.300921] systemd[1]: Set hostname to <debian>. 
[    4.459214] hid-generic 0003:064F:2AF9.0001: device has no listeners, quitting 
[    4.472429] systemd[1]: Cannot add dependency job for unit dbus.socket, ignoring: Unit dbus.socket failed to load: No such file or directory. 
[    4.485224] systemd[1]: Cannot add dependency job for unit display-manager.service, ignoring: Unit display-manager.service failed to load: No such file or directory. 
[    4.500952] systemd[1]: Starting Forward Password Requests to Wall Directory Watch. 
[    4.508804] systemd[1]: Started Forward Password Requests to Wall Directory Watch. 
[    4.516429] systemd[1]: Expecting device dev-ttyS0.device... 
         Expecting device dev-ttyS0.device... 
[    4.536275] systemd[1]: Starting Remote File Systems (Pre). 
[
      OK  
   ] Reached target Remote File Systems (Pre). 
[    4.556264] systemd[1]: Reached target Remote File Systems (Pre). 
[
      OK  
   ] Reached target Paths. 
[
      OK  
   ] Reached target Encrypted Volumes. 
[
      OK  
   ] Reached target Swap. 
[
      OK  
   ] Created slice Root Slice. 
[
      OK  
   ] Created slice User and Session Slice. 
[
      OK  
   ] Listening on Delayed Shutdown Socket. 
[
      OK  
   ] Listening on /dev/initctl Compatibility Named Pipe. 
[
      OK  
   ] Listening on Journal Socket (/dev/log). 
[
      OK  
   ] Listening on udev Control Socket. 
[
      OK  
   ] Listening on udev Kernel Socket. 
[
      OK  
   ] Listening on Journal Socket. 
[
      OK  
   ] Reached target Sockets. 
[
      OK  
   ] Created slice System Slice. 
[
      OK  
   ] Created slice system-getty.slice. 
[
      OK  
   ] Created slice system-serial\x2dgetty.slice. 
         Starting Load Kernel Modules... 
         Mounting POSIX Message Queue File System... 
         Starting Create Static Device Nodes in /dev... 
         Mounting Huge Pages File System... 
         Mounting Debug File System... 
         Starting udev Coldplug all Devices... 
         Starting Remount Root and Kernel File Systems... 
         Starting Journal Service... 
[
      OK  
   ] Started Journal Service. 
[
      OK  
   ] Reached target Slices. 
[
      OK  
   ] Mounted Debug File System. 
[
      OK  
   ] Mounted Huge Pages File System. 
[
      OK  
   ] Mounted POSIX Message Queue File System. 
[
      FAILED
   ] Failed to start Load Kernel Modules. 
See 'systemctl status systemd-modules-load.service' for details. 
[
      OK  
   ] Started Create Static Device Nodes in /dev. 
[
      OK  
   ] Started Remount Root and Kernel File Systems. 
[
      OK  
   ] Started udev Coldplug all Devices. 
         Starting Load/Save Random Seed... 
         Starting udev Kernel Device Manager... 
[
      OK  
   ] Reached target Local File Systems (Pre). 
         [    5.206345] systemd-udevd[2012]: starting version 215 
Mounting /var/tmp... 
         Mounting /tmp... 
         Starting Apply Kernel Variables... 
         Mounting FUSE Control File System... 
[
      OK  
   ] Mounted /tmp. 
[
      OK  
   ] Mounted /var/tmp. 
[
      OK  
   ] Mounted FUSE Control File System. 
[
      OK  
   ] Started udev Kernel Device Manager. 
[
      OK  
   ] Started Load/Save Random Seed. 
[
      OK  
   ] Started Apply Kernel Variables. 
         Starting Copy rules generated while the root was ro... 
         Starting LSB: Tune IDE hard disks... 
[
      OK  
   ] Reached target Local File Systems. 
[
      OK  
   ] Reached target Remote File Systems. 
         Starting Trigger Flushing of Journal to Persistent Storage... 
         Starting Create Volatile Files and Directories... 
         Starting LSB: Raise network interfaces.... 
[
      OK  
   ] Started Copy rules generated while the root was ro. 
[
      OK  
   ] Found device /dev/ttyS0. 
[
      OK  
   ] Started Create Volatile Files and Directories. 
[    5.603301] systemd-journald[1273]: Received request to flush runtime journal from PID 1 
         Starting Update UTMP about System Boot/Shutdown... 
[
      OK  
   ] Started Trigger Flushing of Journal to Persistent Storage. 
[
      OK  
   ] Started LSB: Tune IDE hard disks. 
[
      OK  
   ] Started Update UTMP about System Boot/Shutdown. 
[    5.717430] e1000e 0000:06:00.0 rename3: renamed from eth1 
[    5.736529] systemd-udevd[2024]: renamed network interface eth1 to rename3 
[    5.736762] e1000e 0000:08:00.0 eth5: renamed from eth3 
[    5.760591] e1000e 0000:07:00.0 eth4: renamed from eth2 
[    5.765332] systemd-udevd[2029]: renamed network interface eth3 to eth5 
[    5.784479] e1000e 0000:05:00.0 rename2: renamed from eth0 
[    5.784505] systemd-udevd[2026]: renamed network interface eth2 to eth4 
[    5.804562] systemd-udevd[2021]: renamed network interface eth0 to rename2 
[    5.804893] e1000e 0000:06:00.0 eth3: renamed from rename3 
[    5.820568] systemd-udevd[2024]: renamed network interface eth1 to eth3 
[    5.863309] e1000e 0000:05:00.0 eth2: renamed from rename2 
[    5.888461] systemd-udevd[2021]: renamed network interface eth0 to eth2 
[
      OK  
   ] Started LSB: Raise network interfaces.. 
[
      OK  
   ] Reached target Network. 
[
      OK  
   ] Reached target Network is Online. 
[
      OK  
   ] Reached target System Initialization. 
[
      OK  
   ] Reached target Timers. 
[
      OK  
   ] Reached target Basic System. 
         Starting Internet superserver... 
[
      OK  
   ] Started Internet superserver. 
         Starting Self Monitoring and Reporting Technology (SMART) Daemon... 
[
      OK  
   ] Started Self Monitoring and Reporting Technology (SMART) Daemon. 
         Starting OpenBSD Secure Shell server... 
         Starting Kontron KVX BSP Service... 
         Starting Kontron RTC2 Service... 
         Starting Initialize hardware monitoring sensors... 
         Starting /etc/rc.local Compatibility... 
         Starting getty on tty2-tty6 if dbus and logind are not available... 
         Starting LSB: disk temperature monitoring daemon... 
         Starting Permit User Sessions... 
[
      OK  
   ] Started /etc/rc.local Compatibility. 
[
      OK  
   ] Started LSB: disk temperature monitoring daemon. 
[
      OK  
   ] Started Permit User Sessions. 
[
      OK  
   ] Started getty on tty2-tty6 if dbus and logind are not available. 
[
      OK  
   ] Started Kontron RTC2 Service. 
[
      OK  
   ] Started Initialize hardware monitoring sensors. 
         Starting Getty on tty6... 
[
      OK  
   ] Started Getty on tty6. 
         Starting Getty on tty5... 
[
      OK  
   ] Started Getty on tty5. 
         Starting Getty on tty4... 
[
      OK  
   ] Started Getty on tty4. 
         Starting Getty on tty3... 
[
      OK  
   ] Started Getty on tty3. 
         Starting Getty on tty2... 
[
      OK  
   ] Started Getty on tty2. 
         Starting Getty on tty1... 
[
      OK  
   ] Started Getty on tty1. 
         Starting Serial Getty on ttyS0... 
[
      OK  
   ] Started Serial Getty on ttyS0. 
[
      OK  
   ] Reached target Login Prompts. 
[
      OK  
   ] Started OpenBSD Secure Shell server. 
[
      OK  
   ] Started Kontron KVX BSP Service. 
[
      OK  
   ] Reached target Multi-User System. 
[
      OK  
   ] Reached target Graphical Interface. 
         Starting Update UTMP about System Runlevel Changes... 
[
      OK  
   ] Started Update UTMP about System Runlevel Changes. 
  
Debian GNU/Linux 8 debian ttyS0 
 
debian login: root  
Password:  
Last login: Wed May  9 09:48:56 UTC 2018 on ttyS0 
Linux debian 4.17.0-rc1 #3 SMP Fri May 4 10:03:38 UTC 2018 aarch64 
 
The programs included with the Debian GNU/Linux system are free software; 
the exact distribution terms for each program are described in the 
individual files in /usr/share/doc/*/copyright. 
 
Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent 
permitted by applicable law. 
root@debian:~#  
root@debian:~# lspci -vv 
0000:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0 
 I/O behind bridge: 00001000-00004fff 
 Memory behind bridge: 40000000-4bffffff 
 Prefetchable memory behind bridge: 000000004c000000-000000004c0fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
 Expansion ROM at 404c100000 [disabled] [size=2K] 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 3 
  Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag- RBE+ 
  DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited 
   ClockPM- Surprise- LLActRep+ BwNot+ 
  LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
  RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- 
  RootCap: CRSVisible- 
  RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
  DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd- 
  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- 
  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- 
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
    Compliance De-emphasis: -6dB 
  LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- 
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- 
 Capabilities: [100 v2] Advanced Error Reporting 
  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- 
  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- 
  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ 
  AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- 
 Capabilities: [148 v1] #19 
 Kernel driver in use: pcieport 
 
0000:01:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Region 0: Memory at 404c000000 (64-bit, prefetchable) [size=64K] 
 Bus: primary=01, secondary=02, subordinate=08, sec-latency=0 
 I/O behind bridge: 00001000-00004fff 
 Memory behind bridge: 40000000-4bffffff 
 Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 2 
  Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [60] Express (v1) PCI-Express to PCI/PCI-X Bridge, MSI 00 
  DevCap: MaxPayload 128 bytes, PhantFunc 0 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry- 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <16us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [100 v1] Power Budgeting <?> 
 
0000:02:09.0 Bridge: Kontron Device 9035 (rev 46) 
 Subsystem: Kontron Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 128 
 Interrupt: pin A routed to IRQ 0 
 Region 0: Memory at 4048000000 (32-bit, non-prefetchable) [size=1M] 
 Region 1: Memory at 4040000000 (32-bit, non-prefetchable) [size=128M] 
 Capabilities: [78] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 
0000:02:0e.0 PCI bridge: Pericom Semiconductor PCI Express to PCI-XPI7C9X130 PCI-X Bridge (rev 04) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 128, Cache Line Size: 32 bytes 
 Bus: primary=02, secondary=03, subordinate=08, sec-latency=0 
 I/O behind bridge: 00001000-00004fff 
 Memory behind bridge: 48100000-484fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [80] PCI-X bridge device 
  Secondary Status: 64bit- 133MHz- SCD- USC- SCO- SRD- Freq=conv 
  Status: Dev=ff:1f.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- 
  Upstream: Capacity=16 CommitmentLimit=16 
  Downstream: Capacity=16 CommitmentLimit=16 
 Capabilities: [90] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [a8] Subsystem: Device 0000:0000 
 Capabilities: [b0] Express (v1) PCI/PCI-X to PCI-Express Bridge, MSI 00 
  DevCap: MaxPayload 512 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend+ 
  LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <512ns, L1 <1us 
   ClockPM- Surprise- LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [f0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 
0000:03:00.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=03, secondary=04, subordinate=08, sec-latency=0 
 I/O behind bridge: 00001000-00004fff 
 Memory behind bridge: 48100000-484fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Upstream Port, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 0.000W 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Kernel driver in use: pcieport 
 
0000:04:02.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=04, secondary=05, subordinate=05, sec-latency=0 
 I/O behind bridge: 00001000-00001fff 
 Memory behind bridge: 48100000-481fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Downstream Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <4us 
   ClockPM- Surprise+ LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk+ 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Kernel driver in use: pcieport 
 
0000:04:03.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=04, secondary=06, subordinate=06, sec-latency=0 
 I/O behind bridge: 00002000-00002fff 
 Memory behind bridge: 48200000-482fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Downstream Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <4us 
   ClockPM- Surprise+ LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk+ 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Kernel driver in use: pcieport 
 
0000:04:04.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=04, secondary=07, subordinate=07, sec-latency=0 
 I/O behind bridge: 00003000-00003fff 
 Memory behind bridge: 48300000-483fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Downstream Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <4us 
   ClockPM- Surprise+ LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk+ 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Kernel driver in use: pcieport 
 
0000:04:05.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=04, secondary=08, subordinate=08, sec-latency=0 
 I/O behind bridge: 00004000-00004fff 
 Memory behind bridge: 48400000-484fffff 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Express (v1) Downstream Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag+ RBE+ 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd- ExtTag+ PhantFunc- AuxPwr- NoSnoop- 
   MaxPayload 128 bytes, MaxReadReq 128 bytes 
  DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- 
  LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <512ns, L1 <4us 
   ClockPM- Surprise+ LLActRep+ BwNot- 
  LnkCtl: ASPM Disabled; Disabled- CommClk+ 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- 
 Capabilities: [c0] Power Management version 3 
  Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) 
  Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Kernel driver in use: pcieport 
 
0000:05:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
 Subsystem: Intel Corporation Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 64 bytes 
 Interrupt: pin A routed to IRQ 57 
 Region 0: Memory at 4048100000 (32-bit, non-prefetchable) [size=128K] 
 Region 2: I/O ports at 1000 [disabled] [size=32] 
 Region 3: Memory at 4048120000 (32-bit, non-prefetchable) [size=16K] 
 Capabilities: [c8] Power Management version 2 
  Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [e0] Express (v1) Endpoint, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L0s <128ns, L1 <64us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [a0] MSI-X: Enable- Count=5 Masked- 
  Vector table: BAR=3 offset=00000000 
  PBA: BAR=3 offset=00002000 
 Kernel driver in use: e1000e 
 
0000:06:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
 Subsystem: Intel Corporation Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 64 bytes 
 Interrupt: pin A routed to IRQ 61 
 Region 0: Memory at 4048200000 (32-bit, non-prefetchable) [size=128K] 
 Region 2: I/O ports at 2000 [disabled] [size=32] 
 Region 3: Memory at 4048220000 (32-bit, non-prefetchable) [size=16K] 
 Capabilities: [c8] Power Management version 2 
  Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [e0] Express (v1) Endpoint, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L0s <128ns, L1 <64us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [a0] MSI-X: Enable- Count=5 Masked- 
  Vector table: BAR=3 offset=00000000 
  PBA: BAR=3 offset=00002000 
 Kernel driver in use: e1000e 
 
0000:07:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
 Subsystem: Intel Corporation Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 64 bytes 
 Interrupt: pin A routed to IRQ 58 
 Region 0: Memory at 4048300000 (32-bit, non-prefetchable) [size=128K] 
 Region 2: I/O ports at 3000 [disabled] [size=32] 
 Region 3: Memory at 4048320000 (32-bit, non-prefetchable) [size=16K] 
 Capabilities: [c8] Power Management version 2 
  Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [e0] Express (v1) Endpoint, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L0s <128ns, L1 <64us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [a0] MSI-X: Enable- Count=5 Masked- 
  Vector table: BAR=3 offset=00000000 
  PBA: BAR=3 offset=00002000 
 Kernel driver in use: e1000e 
 
0000:08:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
 Subsystem: Intel Corporation Device 0000 
 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 64 bytes 
 Interrupt: pin A routed to IRQ 62 
 Region 0: Memory at 4048400000 (32-bit, non-prefetchable) [size=128K] 
 Region 2: I/O ports at 4000 [disabled] [size=32] 
 Region 3: Memory at 4048420000 (32-bit, non-prefetchable) [size=16K] 
 Capabilities: [c8] Power Management version 2 
  Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- 
 Capabilities: [d0] MSI: Enable- Count=1/1 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [e0] Express (v1) Endpoint, MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us 
   ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- 
  DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L0s <128ns, L1 <64us 
   ClockPM- Surprise- LLActRep- BwNot- 
  LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
 Capabilities: [a0] MSI-X: Enable- Count=5 Masked- 
  Vector table: BAR=3 offset=00000000 
  PBA: BAR=3 offset=00002000 
 Kernel driver in use: e1000e 
 
0001:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 Expansion ROM at 4840000000 [disabled] [size=2K] 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 3 
  Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag- RBE+ 
  DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited 
   ClockPM- Surprise- LLActRep+ BwNot+ 
  LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
  RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- 
  RootCap: CRSVisible- 
  RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
  DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd- 
  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- 
  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- 
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
    Compliance De-emphasis: -6dB 
  LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- 
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- 
 Capabilities: [100 v2] Advanced Error Reporting 
  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- 
  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- 
  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ 
  AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- 
 Capabilities: [148 v1] #19 
 Kernel driver in use: pcieport 
 
0002:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) (prog-if 00 [Normal decode]) 
 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- 
 Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 
 Latency: 0, Cache Line Size: 32 bytes 
 Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0 
 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- 
 Expansion ROM at 5040000000 [disabled] [size=2K] 
 BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- 
  PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 
 Capabilities: [40] Power Management version 3 
  Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) 
  Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 
 Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+ 
  Address: 0000000000000000  Data: 0000 
 Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00 
  DevCap: MaxPayload 256 bytes, PhantFunc 0 
   ExtTag- RBE+ 
  DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ 
   RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ 
   MaxPayload 128 bytes, MaxReadReq 512 bytes 
  DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- 
  LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited 
   ClockPM- Surprise- LLActRep+ BwNot+ 
  LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- 
   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- 
  LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- 
  RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- 
  RootCap: CRSVisible- 
  RootSta: PME ReqID 0000, PMEStatus- PMEPending- 
  DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd- 
  DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd- 
  LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- 
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- 
    Compliance De-emphasis: -6dB 
  LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- 
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- 
 Capabilities: [100 v2] Advanced Error Reporting 
  UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- 
  UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- 
  CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- 
  CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ 
  AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- 
 Capabilities: [148 v1] #19 
 Kernel driver in use: pcieport 
 
root@debian:~# lspci 
0000:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) 
0000:01:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) 
0000:02:09.0 Bridge: Kontron Device 9035 (rev 46) 
0000:02:0e.0 PCI bridge: Pericom Semiconductor PCI Express to PCI-XPI7C9X130 PCI-X Bridge (rev 04) 
0000:03:00.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:04:02.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:04:03.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:04:04.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:04:05.0 PCI bridge: Integrated Device Technology, Inc. [IDT] Device 803e (rev 0e) 
0000:05:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
0000:06:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
0000:07:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
0000:08:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection 
0001:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) 
0002:00:00.0 PCI bridge: Freescale Semiconductor Inc Device 808a (rev 10) 
root@debian:~#  
root@debian:~# lspci -t 
-+-[0002:00]---00.0-[01-ff]-- 
 +-[0001:00]---00.0-[01-ff]-- 
 \-[0000:00]---00.0-[01-ff]----00.0-[02-08]--+-09.0 
                                             \-0e.0-[03-08]----00.0-[04-08]--+-02.0-[05]----00.0 
                                                                             +-03.0-[06]----00.0 
                                                                             +-04.0-[07]----00.0 
                                                                             \-05.0-[08]----00.0 
root@debian:~# 

Re: [PATCH] PCI: Check whether bridges allow access to extended config space

[Frederick Lawler]

Hi,

Gilles Buloz wrote:
> Here are full dmesg + lspci -vv + ... for the following cases :
> - 4.17-rc1_probe_failed_without_pcieaspmoff.txt : I get a broken PCI config at most boots, without pcie_aspm=off
> - 4.17-rc1_probe_ok_without_pcieaspmoff.txt : I get a correct PCI config at some boots, even without pcie_aspm=off
> - 4.17-rc1_probe_always_ok_with_pcieaspmoff.txt : I get a correct PCI config at all boots when using pcie_aspm=off
> - 4.1.35_probe_always_ok_without_pcieaspmoff.txt : I get a correct PCI config at all boots when using kernel 4.1.35-rt41 (from NXP
> Yocto BSP), even without pcie_aspm=off
> 
> I noticed these strange things :
> - with 4.17-rc1, without pcie_aspm=off, the kernel is hanging during ~1 second :
>     - before line "ASPM: Could not configure common clock" when PCI config is OK
>     - or before line "bridge configuration invalid ([bus ff-ff]), reconfiguring" when PCI config is NOT OK
>       (the FFs in "[bus ff-ff]" seems side effects of read returning ~0 because device is off)
> - no such hang when pcie_aspm=off is used
> - applying reverse patch for "PCI/ASPM: Don't warn if already in common clock mode"
>     (commit 04875177dbe034055f23960981ecf6fb8ea1d638) does not give more message

I submitted this as a bug here:
https://bugzilla.kernel.org/show_bug.cgi?id=199671

Thanks,
Fred

[PATCH] PCI: Check whether bridges allow access to extended config space

[Frederick Lawler]

Hi,

Gilles Buloz wrote:
> Here are full dmesg + lspci -vv + ... for the following cases :
> - 4.17-rc1_probe_failed_without_pcieaspmoff.txt : I get a broken PCI config at most boots, without pcie_aspm=off
> - 4.17-rc1_probe_ok_without_pcieaspmoff.txt : I get a correct PCI config at some boots, even without pcie_aspm=off
> - 4.17-rc1_probe_always_ok_with_pcieaspmoff.txt : I get a correct PCI config at all boots when using pcie_aspm=off
> - 4.1.35_probe_always_ok_without_pcieaspmoff.txt : I get a correct PCI config at all boots when using kernel 4.1.35-rt41 (from NXP
> Yocto BSP), even without pcie_aspm=off
> 
> I noticed these strange things :
> - with 4.17-rc1, without pcie_aspm=off, the kernel is hanging during ~1 second :
>     - before line "ASPM: Could not configure common clock" when PCI config is OK
>     - or before line "bridge configuration invalid ([bus ff-ff]), reconfiguring" when PCI config is NOT OK
>       (the FFs in "[bus ff-ff]" seems side effects of read returning ~0 because device is off)
> - no such hang when pcie_aspm=off is used
> - applying reverse patch for "PCI/ASPM: Don't warn if already in common clock mode"
>     (commit 04875177dbe034055f23960981ecf6fb8ea1d638) does not give more message

I submitted this as a bug here:
https://bugzilla.kernel.org/show_bug.cgi?id=199671

Thanks,
Fred