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* [PATCH 0/3] spi: meson-axg: add few enhanced features
@ 2018-05-03 21:36 ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: Mark Brown
  Cc: Yixun Lan, Neil Armstrong, Jerome Brunet, Kevin Hilman,
	Carlo Caione, Sunny Luo, linux-spi, linux-amlogic,
	linux-arm-kernel, linux-kernel

  Add a few enhanced features for the SPICC controller of Meson-AXG SoC.

  These patches are actually quite independent from each other, I send them
together in case to avoid the file conflicts.

Sunny Luo (3):
  spi: meson-axg: support MAX 80M clock
  spi: meson-axg: enhance output enable feature
  spi: meson-axg: add a linear clock divider support

 drivers/spi/spi-meson-spicc.c | 270 ++++++++++++++++++++++++++++------
 1 file changed, 222 insertions(+), 48 deletions(-)

-- 
2.17.0

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 0/3] spi: meson-axg: add few enhanced features
@ 2018-05-03 21:36 ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: linux-arm-kernel

  Add a few enhanced features for the SPICC controller of Meson-AXG SoC.

  These patches are actually quite independent from each other, I send them
together in case to avoid the file conflicts.

Sunny Luo (3):
  spi: meson-axg: support MAX 80M clock
  spi: meson-axg: enhance output enable feature
  spi: meson-axg: add a linear clock divider support

 drivers/spi/spi-meson-spicc.c | 270 ++++++++++++++++++++++++++++------
 1 file changed, 222 insertions(+), 48 deletions(-)

-- 
2.17.0

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 0/3] spi: meson-axg: add few enhanced features
@ 2018-05-03 21:36 ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: linus-amlogic

  Add a few enhanced features for the SPICC controller of Meson-AXG SoC.

  These patches are actually quite independent from each other, I send them
together in case to avoid the file conflicts.

Sunny Luo (3):
  spi: meson-axg: support MAX 80M clock
  spi: meson-axg: enhance output enable feature
  spi: meson-axg: add a linear clock divider support

 drivers/spi/spi-meson-spicc.c | 270 ++++++++++++++++++++++++++++------
 1 file changed, 222 insertions(+), 48 deletions(-)

-- 
2.17.0

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 1/3] spi: meson-axg: support MAX 80M clock
  2018-05-03 21:36 ` Yixun Lan
  (?)
@ 2018-05-03 21:36   ` Yixun Lan
  -1 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: Mark Brown
  Cc: Sunny Luo, Yixun Lan, Neil Armstrong, Jerome Brunet,
	Kevin Hilman, Carlo Caione, linux-spi, linux-amlogic,
	linux-arm-kernel, linux-kernel

From: Sunny Luo <sunny.luo@amlogic.com>

The SPICC controller in Meson-AXG is capable of running at 80M clock.
The ASIC IP is improved and the clock is actually running higher than
previous old SoCs.

Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 drivers/spi/spi-meson-spicc.c | 37 +++++++++++++++++++++++++++--------
 1 file changed, 29 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 5c82910e3480..8489f4c9f465 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -9,11 +9,13 @@
 
 #include <linux/bitfield.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/types.h>
@@ -34,7 +36,6 @@
  *   to have a CS go down over the full transfer
  */
 
-#define SPICC_MAX_FREQ	30000000
 #define SPICC_MAX_BURST	128
 
 /* Register Map */
@@ -120,6 +121,10 @@
 #define SPICC_BURST_MAX	16
 #define SPICC_FIFO_HALF 10
 
+struct meson_spicc_data {
+	unsigned int			max_speed_hz;
+};
+
 struct meson_spicc_device {
 	struct spi_master		*master;
 	struct platform_device		*pdev;
@@ -127,6 +132,7 @@ struct meson_spicc_device {
 	struct clk			*core;
 	struct spi_message		*message;
 	struct spi_transfer		*xfer;
+	const struct meson_spicc_data	*data;
 	u8				*tx_buf;
 	u8				*rx_buf;
 	unsigned int			bytes_per_word;
@@ -517,6 +523,9 @@ static int meson_spicc_probe(struct platform_device *pdev)
 	spicc->pdev = pdev;
 	platform_set_drvdata(pdev, spicc);
 
+	spicc->data = (const struct meson_spicc_data *)
+		of_device_get_match_data(&pdev->dev);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	spicc->base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(spicc->base)) {
@@ -567,11 +576,9 @@ static int meson_spicc_probe(struct platform_device *pdev)
 	master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
 	master->transfer_one = meson_spicc_transfer_one;
 
-	/* Setup max rate according to the Meson GX datasheet */
-	if ((rate >> 2) > SPICC_MAX_FREQ)
-		master->max_speed_hz = SPICC_MAX_FREQ;
-	else
-		master->max_speed_hz = rate >> 2;
+	/* Setup max rate according to the Meson datasheet */
+	master->max_speed_hz = min_t(unsigned int, rate >> 1,
+			spicc->data->max_speed_hz);
 
 	ret = devm_spi_register_master(&pdev->dev, master);
 	if (!ret)
@@ -597,9 +604,23 @@ static int meson_spicc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct meson_spicc_data meson_spicc_gx_data = {
+	.max_speed_hz	= 30000000,
+};
+
+static const struct meson_spicc_data meson_spicc_axg_data = {
+	.max_speed_hz	= 80000000,
+};
+
 static const struct of_device_id meson_spicc_of_match[] = {
-	{ .compatible = "amlogic,meson-gx-spicc", },
-	{ .compatible = "amlogic,meson-axg-spicc", },
+	{
+		.compatible	= "amlogic,meson-gx-spicc",
+		.data		= &meson_spicc_gx_data,
+	},
+	{
+		.compatible = "amlogic,meson-axg-spicc",
+		.data		= &meson_spicc_axg_data,
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH 1/3] spi: meson-axg: support MAX 80M clock
@ 2018-05-03 21:36   ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: linux-arm-kernel

From: Sunny Luo <sunny.luo@amlogic.com>

The SPICC controller in Meson-AXG is capable of running at 80M clock.
The ASIC IP is improved and the clock is actually running higher than
previous old SoCs.

Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 drivers/spi/spi-meson-spicc.c | 37 +++++++++++++++++++++++++++--------
 1 file changed, 29 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 5c82910e3480..8489f4c9f465 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -9,11 +9,13 @@
 
 #include <linux/bitfield.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/types.h>
@@ -34,7 +36,6 @@
  *   to have a CS go down over the full transfer
  */
 
-#define SPICC_MAX_FREQ	30000000
 #define SPICC_MAX_BURST	128
 
 /* Register Map */
@@ -120,6 +121,10 @@
 #define SPICC_BURST_MAX	16
 #define SPICC_FIFO_HALF 10
 
+struct meson_spicc_data {
+	unsigned int			max_speed_hz;
+};
+
 struct meson_spicc_device {
 	struct spi_master		*master;
 	struct platform_device		*pdev;
@@ -127,6 +132,7 @@ struct meson_spicc_device {
 	struct clk			*core;
 	struct spi_message		*message;
 	struct spi_transfer		*xfer;
+	const struct meson_spicc_data	*data;
 	u8				*tx_buf;
 	u8				*rx_buf;
 	unsigned int			bytes_per_word;
@@ -517,6 +523,9 @@ static int meson_spicc_probe(struct platform_device *pdev)
 	spicc->pdev = pdev;
 	platform_set_drvdata(pdev, spicc);
 
+	spicc->data = (const struct meson_spicc_data *)
+		of_device_get_match_data(&pdev->dev);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	spicc->base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(spicc->base)) {
@@ -567,11 +576,9 @@ static int meson_spicc_probe(struct platform_device *pdev)
 	master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
 	master->transfer_one = meson_spicc_transfer_one;
 
-	/* Setup max rate according to the Meson GX datasheet */
-	if ((rate >> 2) > SPICC_MAX_FREQ)
-		master->max_speed_hz = SPICC_MAX_FREQ;
-	else
-		master->max_speed_hz = rate >> 2;
+	/* Setup max rate according to the Meson datasheet */
+	master->max_speed_hz = min_t(unsigned int, rate >> 1,
+			spicc->data->max_speed_hz);
 
 	ret = devm_spi_register_master(&pdev->dev, master);
 	if (!ret)
@@ -597,9 +604,23 @@ static int meson_spicc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct meson_spicc_data meson_spicc_gx_data = {
+	.max_speed_hz	= 30000000,
+};
+
+static const struct meson_spicc_data meson_spicc_axg_data = {
+	.max_speed_hz	= 80000000,
+};
+
 static const struct of_device_id meson_spicc_of_match[] = {
-	{ .compatible = "amlogic,meson-gx-spicc", },
-	{ .compatible = "amlogic,meson-axg-spicc", },
+	{
+		.compatible	= "amlogic,meson-gx-spicc",
+		.data		= &meson_spicc_gx_data,
+	},
+	{
+		.compatible = "amlogic,meson-axg-spicc",
+		.data		= &meson_spicc_axg_data,
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH 1/3] spi: meson-axg: support MAX 80M clock
@ 2018-05-03 21:36   ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: linus-amlogic

From: Sunny Luo <sunny.luo@amlogic.com>

The SPICC controller in Meson-AXG is capable of running at 80M clock.
The ASIC IP is improved and the clock is actually running higher than
previous old SoCs.

Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 drivers/spi/spi-meson-spicc.c | 37 +++++++++++++++++++++++++++--------
 1 file changed, 29 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 5c82910e3480..8489f4c9f465 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -9,11 +9,13 @@
 
 #include <linux/bitfield.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/types.h>
@@ -34,7 +36,6 @@
  *   to have a CS go down over the full transfer
  */
 
-#define SPICC_MAX_FREQ	30000000
 #define SPICC_MAX_BURST	128
 
 /* Register Map */
@@ -120,6 +121,10 @@
 #define SPICC_BURST_MAX	16
 #define SPICC_FIFO_HALF 10
 
+struct meson_spicc_data {
+	unsigned int			max_speed_hz;
+};
+
 struct meson_spicc_device {
 	struct spi_master		*master;
 	struct platform_device		*pdev;
@@ -127,6 +132,7 @@ struct meson_spicc_device {
 	struct clk			*core;
 	struct spi_message		*message;
 	struct spi_transfer		*xfer;
+	const struct meson_spicc_data	*data;
 	u8				*tx_buf;
 	u8				*rx_buf;
 	unsigned int			bytes_per_word;
@@ -517,6 +523,9 @@ static int meson_spicc_probe(struct platform_device *pdev)
 	spicc->pdev = pdev;
 	platform_set_drvdata(pdev, spicc);
 
+	spicc->data = (const struct meson_spicc_data *)
+		of_device_get_match_data(&pdev->dev);
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	spicc->base = devm_ioremap_resource(&pdev->dev, res);
 	if (IS_ERR(spicc->base)) {
@@ -567,11 +576,9 @@ static int meson_spicc_probe(struct platform_device *pdev)
 	master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
 	master->transfer_one = meson_spicc_transfer_one;
 
-	/* Setup max rate according to the Meson GX datasheet */
-	if ((rate >> 2) > SPICC_MAX_FREQ)
-		master->max_speed_hz = SPICC_MAX_FREQ;
-	else
-		master->max_speed_hz = rate >> 2;
+	/* Setup max rate according to the Meson datasheet */
+	master->max_speed_hz = min_t(unsigned int, rate >> 1,
+			spicc->data->max_speed_hz);
 
 	ret = devm_spi_register_master(&pdev->dev, master);
 	if (!ret)
@@ -597,9 +604,23 @@ static int meson_spicc_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct meson_spicc_data meson_spicc_gx_data = {
+	.max_speed_hz	= 30000000,
+};
+
+static const struct meson_spicc_data meson_spicc_axg_data = {
+	.max_speed_hz	= 80000000,
+};
+
 static const struct of_device_id meson_spicc_of_match[] = {
-	{ .compatible = "amlogic,meson-gx-spicc", },
-	{ .compatible = "amlogic,meson-axg-spicc", },
+	{
+		.compatible	= "amlogic,meson-gx-spicc",
+		.data		= &meson_spicc_gx_data,
+	},
+	{
+		.compatible = "amlogic,meson-axg-spicc",
+		.data		= &meson_spicc_axg_data,
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH 2/3] spi: meson-axg: enhance output enable feature
  2018-05-03 21:36 ` Yixun Lan
  (?)
@ 2018-05-03 21:36   ` Yixun Lan
  -1 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: Mark Brown
  Cc: Sunny Luo, Yixun Lan, Neil Armstrong, Jerome Brunet,
	Kevin Hilman, Carlo Caione, linux-spi, linux-amlogic,
	linux-arm-kernel, linux-kernel

From: Sunny Luo <sunny.luo@amlogic.com>

The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in unexpected state.

Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 drivers/spi/spi-meson-spicc.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 8489f4c9f465..90b15f7d50dd 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -115,6 +115,13 @@
 
 #define SPICC_DWADDR	0x24	/* Write Address of DMA */
 
+#define SPICC_ENH_CTL0	0x38	/* Enhanced Feature */
+#define SPICC_ENH_MOSI_OEN		BIT(25)
+#define SPICC_ENH_CLK_OEN		BIT(26)
+#define SPICC_ENH_CS_OEN		BIT(27)
+#define SPICC_ENH_CLK_CS_DELAY_EN	BIT(28)
+#define SPICC_ENH_MAIN_CLK_AO		BIT(29)
+
 #define writel_bits_relaxed(mask, val, addr) \
 	writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
 
@@ -123,6 +130,7 @@
 
 struct meson_spicc_data {
 	unsigned int			max_speed_hz;
+	bool				has_oen;
 };
 
 struct meson_spicc_device {
@@ -145,6 +153,19 @@ struct meson_spicc_device {
 	bool				is_last_burst;
 };
 
+static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
+{
+	u32 conf;
+
+	if (!spicc->data->has_oen)
+		return;
+
+	conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
+		SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
+
+	writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
+}
+
 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
 {
 	return !!FIELD_GET(SPICC_TF,
@@ -453,6 +474,8 @@ static int meson_spicc_prepare_message(struct spi_master *master,
 
 	writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
 
+	meson_spicc_oen_enable(spicc);
+
 	return 0;
 }
 
@@ -605,11 +628,12 @@ static int meson_spicc_remove(struct platform_device *pdev)
 }
 
 static const struct meson_spicc_data meson_spicc_gx_data = {
-	.max_speed_hz	= 30000000,
+	.max_speed_hz		= 30000000,
 };
 
 static const struct meson_spicc_data meson_spicc_axg_data = {
-	.max_speed_hz	= 80000000,
+	.max_speed_hz		= 80000000,
+	.has_oen		= true,
 };
 
 static const struct of_device_id meson_spicc_of_match[] = {
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH 2/3] spi: meson-axg: enhance output enable feature
@ 2018-05-03 21:36   ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: linux-arm-kernel

From: Sunny Luo <sunny.luo@amlogic.com>

The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in unexpected state.

Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 drivers/spi/spi-meson-spicc.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 8489f4c9f465..90b15f7d50dd 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -115,6 +115,13 @@
 
 #define SPICC_DWADDR	0x24	/* Write Address of DMA */
 
+#define SPICC_ENH_CTL0	0x38	/* Enhanced Feature */
+#define SPICC_ENH_MOSI_OEN		BIT(25)
+#define SPICC_ENH_CLK_OEN		BIT(26)
+#define SPICC_ENH_CS_OEN		BIT(27)
+#define SPICC_ENH_CLK_CS_DELAY_EN	BIT(28)
+#define SPICC_ENH_MAIN_CLK_AO		BIT(29)
+
 #define writel_bits_relaxed(mask, val, addr) \
 	writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
 
@@ -123,6 +130,7 @@
 
 struct meson_spicc_data {
 	unsigned int			max_speed_hz;
+	bool				has_oen;
 };
 
 struct meson_spicc_device {
@@ -145,6 +153,19 @@ struct meson_spicc_device {
 	bool				is_last_burst;
 };
 
+static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
+{
+	u32 conf;
+
+	if (!spicc->data->has_oen)
+		return;
+
+	conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
+		SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
+
+	writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
+}
+
 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
 {
 	return !!FIELD_GET(SPICC_TF,
@@ -453,6 +474,8 @@ static int meson_spicc_prepare_message(struct spi_master *master,
 
 	writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
 
+	meson_spicc_oen_enable(spicc);
+
 	return 0;
 }
 
@@ -605,11 +628,12 @@ static int meson_spicc_remove(struct platform_device *pdev)
 }
 
 static const struct meson_spicc_data meson_spicc_gx_data = {
-	.max_speed_hz	= 30000000,
+	.max_speed_hz		= 30000000,
 };
 
 static const struct meson_spicc_data meson_spicc_axg_data = {
-	.max_speed_hz	= 80000000,
+	.max_speed_hz		= 80000000,
+	.has_oen		= true,
 };
 
 static const struct of_device_id meson_spicc_of_match[] = {
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH 2/3] spi: meson-axg: enhance output enable feature
@ 2018-05-03 21:36   ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: linus-amlogic

From: Sunny Luo <sunny.luo@amlogic.com>

The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in unexpected state.

Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 drivers/spi/spi-meson-spicc.c | 28 ++++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 8489f4c9f465..90b15f7d50dd 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -115,6 +115,13 @@
 
 #define SPICC_DWADDR	0x24	/* Write Address of DMA */
 
+#define SPICC_ENH_CTL0	0x38	/* Enhanced Feature */
+#define SPICC_ENH_MOSI_OEN		BIT(25)
+#define SPICC_ENH_CLK_OEN		BIT(26)
+#define SPICC_ENH_CS_OEN		BIT(27)
+#define SPICC_ENH_CLK_CS_DELAY_EN	BIT(28)
+#define SPICC_ENH_MAIN_CLK_AO		BIT(29)
+
 #define writel_bits_relaxed(mask, val, addr) \
 	writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
 
@@ -123,6 +130,7 @@
 
 struct meson_spicc_data {
 	unsigned int			max_speed_hz;
+	bool				has_oen;
 };
 
 struct meson_spicc_device {
@@ -145,6 +153,19 @@ struct meson_spicc_device {
 	bool				is_last_burst;
 };
 
+static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
+{
+	u32 conf;
+
+	if (!spicc->data->has_oen)
+		return;
+
+	conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
+		SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
+
+	writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
+}
+
 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
 {
 	return !!FIELD_GET(SPICC_TF,
@@ -453,6 +474,8 @@ static int meson_spicc_prepare_message(struct spi_master *master,
 
 	writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
 
+	meson_spicc_oen_enable(spicc);
+
 	return 0;
 }
 
@@ -605,11 +628,12 @@ static int meson_spicc_remove(struct platform_device *pdev)
 }
 
 static const struct meson_spicc_data meson_spicc_gx_data = {
-	.max_speed_hz	= 30000000,
+	.max_speed_hz		= 30000000,
 };
 
 static const struct meson_spicc_data meson_spicc_axg_data = {
-	.max_speed_hz	= 80000000,
+	.max_speed_hz		= 80000000,
+	.has_oen		= true,
 };
 
 static const struct of_device_id meson_spicc_of_match[] = {
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
  2018-05-03 21:36 ` Yixun Lan
  (?)
@ 2018-05-03 21:36   ` Yixun Lan
  -1 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: Mark Brown
  Cc: Sunny Luo, Yixun Lan, Neil Armstrong, Jerome Brunet,
	Kevin Hilman, Carlo Caione, linux-spi, linux-amlogic,
	linux-arm-kernel, linux-kernel

From: Sunny Luo <sunny.luo@amlogic.com>

The SPICC controller in Meson-AXG SoC is capable of using
a linear clock divider to reach a much fine tuned range of clocks,
while the old controller only use a power of two clock divider,
result at a more coarse clock range.

Also convert the clock registeration into Common Clock Framework.

Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 drivers/spi/spi-meson-spicc.c | 209 +++++++++++++++++++++++++++-------
 1 file changed, 169 insertions(+), 40 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 90b15f7d50dd..e8389d7e62e5 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -116,6 +116,9 @@
 #define SPICC_DWADDR	0x24	/* Write Address of DMA */
 
 #define SPICC_ENH_CTL0	0x38	/* Enhanced Feature */
+#define SPICC_ENH_CLK_CS_DELAY_MASK	GENMASK(15, 0)
+#define SPICC_ENH_DATARATE_MASK		GENMASK(23, 16)
+#define SPICC_ENH_DATARATE_EN		BIT(24)
 #define SPICC_ENH_MOSI_OEN		BIT(25)
 #define SPICC_ENH_CLK_OEN		BIT(26)
 #define SPICC_ENH_CS_OEN		BIT(27)
@@ -131,6 +134,7 @@
 struct meson_spicc_data {
 	unsigned int			max_speed_hz;
 	bool				has_oen;
+	bool				has_enhance_clk_div;
 };
 
 struct meson_spicc_device {
@@ -138,6 +142,7 @@ struct meson_spicc_device {
 	struct platform_device		*pdev;
 	void __iomem			*base;
 	struct clk			*core;
+	struct clk			*clk;
 	struct spi_message		*message;
 	struct spi_transfer		*xfer;
 	const struct meson_spicc_data	*data;
@@ -325,40 +330,6 @@ static irqreturn_t meson_spicc_irq(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-static u32 meson_spicc_setup_speed(struct meson_spicc_device *spicc, u32 conf,
-				   u32 speed)
-{
-	unsigned long parent, value;
-	unsigned int i, div;
-
-	parent = clk_get_rate(spicc->core);
-
-	/* Find closest inferior/equal possible speed */
-	for (i = 0 ; i < 7 ; ++i) {
-		/* 2^(data_rate+2) */
-		value = parent >> (i + 2);
-
-		if (value <= speed)
-			break;
-	}
-
-	/* If provided speed it lower than max divider, use max divider */
-	if (i > 7) {
-		div = 7;
-		dev_warn_once(&spicc->pdev->dev, "unable to get close to speed %u\n",
-			      speed);
-	} else
-		div = i;
-
-	dev_dbg(&spicc->pdev->dev, "parent %lu, speed %u -> %lu (%u)\n",
-		parent, speed, value, div);
-
-	conf &= ~SPICC_DATARATE_MASK;
-	conf |= FIELD_PREP(SPICC_DATARATE_MASK, div);
-
-	return conf;
-}
-
 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 				   struct spi_transfer *xfer)
 {
@@ -367,9 +338,6 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 	/* Read original configuration */
 	conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
 
-	/* Select closest divider */
-	conf = meson_spicc_setup_speed(spicc, conf, xfer->speed_hz);
-
 	/* Setup word width */
 	conf &= ~SPICC_BITLENGTH_MASK;
 	conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
@@ -378,6 +346,8 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 	/* Ignore if unchanged */
 	if (conf != conf_orig)
 		writel_relaxed(conf, spicc->base + SPICC_CONREG);
+
+	clk_set_rate(spicc->clk, xfer->speed_hz);
 }
 
 static int meson_spicc_transfer_one(struct spi_master *master,
@@ -486,9 +456,6 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master)
 	/* Disable all IRQs */
 	writel(0, spicc->base + SPICC_INTREG);
 
-	/* Disable controller */
-	writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG);
-
 	device_reset_optional(&spicc->pdev->dev);
 
 	return 0;
@@ -528,6 +495,157 @@ static void meson_spicc_cleanup(struct spi_device *spi)
 	spi->controller_state = NULL;
 }
 
+/*
+ * The Clock Mux
+ *            x-----------------x   x------------x    x------\
+ *        |---| 0) fixed factor |---| 1) old div |----|      |
+ *        |   x-----------------x   x------------x    |      |
+ * src ---|                                           |5) mux|-- out
+ *        |   x-----------------x   x------------x    |      |
+ *        |---| 2) fixed factor |---| 3) new div |0---|      |
+ *            x-----------------x   x------------x    x------/
+ *
+ * Clk path for GX series:
+ *    src -> 0 -> 1 -> out
+ *
+ * Clk path for AXG series:
+ *    src -> 0 -> 1 -> 5 -> out
+ *    src -> 2 -> 3 -> 5 -> out
+ */
+
+/* algorithm for div0 + div1: rate = freq / 4 / (2 ^ N) */
+static struct clk_fixed_factor meson_spicc_div0 = {
+	.mult	= 1,
+	.div	= 4,
+};
+
+static struct clk_divider meson_spicc_div1 = {
+	.reg	= (void *) SPICC_CONREG,
+	.shift	= 16,
+	.width	= 3,
+	.flags	= CLK_DIVIDER_POWER_OF_TWO,
+};
+
+/* algorithm for div2 + div3: rate = freq / 2 / (N + 1) */
+static struct clk_fixed_factor meson_spicc_div2 = {
+	.mult	= 1,
+	.div	= 2,
+};
+
+static struct clk_divider meson_spicc_div3 = {
+	.reg	= (void *) SPICC_ENH_CTL0,
+	.shift	= 16,
+	.width	= 8,
+};
+
+static struct clk_mux meson_spicc_sel = {
+	.reg	= (void *) SPICC_ENH_CTL0,
+	.mask	= 0x1,
+	.shift	= 24,
+};
+
+static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
+{
+	struct device *dev = &spicc->pdev->dev;
+	struct clk_fixed_factor *div0;
+	struct clk_divider *div1;
+	struct clk_mux *mux;
+	struct clk_init_data init;
+	struct clk *clk;
+	const char *parent_names[1];
+	const char *mux_parent_names[2];
+	char name[32];
+
+	div0 = &meson_spicc_div0;
+	snprintf(name, sizeof(name), "%s#_div0", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_fixed_factor_ops;
+	init.flags = 0;
+	parent_names[0] = __clk_get_name(spicc->core);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div0->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div0->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	div1 = &meson_spicc_div1;
+	snprintf(name, sizeof(name), "%s#_div1", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_divider_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	parent_names[0] = __clk_get_name(clk);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div1->reg = spicc->base + (u64) div1->reg;
+	div1->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div1->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	if (spicc->data->has_enhance_clk_div == false) {
+		spicc->clk = clk;
+		return 0;
+	}
+
+	mux_parent_names[0] = __clk_get_name(clk);
+
+	div0 = &meson_spicc_div2;
+	snprintf(name, sizeof(name), "%s#_div2", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_fixed_factor_ops;
+	init.flags = 0;
+	parent_names[0] = __clk_get_name(spicc->core);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div0->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div0->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	div1 = &meson_spicc_div3;
+	snprintf(name, sizeof(name), "%s#_div3", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_divider_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	parent_names[0] = __clk_get_name(clk);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div1->reg = spicc->base + (u64) div1->reg;
+	div1->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div1->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	mux_parent_names[1] = __clk_get_name(clk);
+
+	mux = &meson_spicc_sel;
+	snprintf(name, sizeof(name), "%s#_sel", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_mux_ops;
+	init.parent_names = mux_parent_names;
+	init.num_parents = 2;
+	init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
+
+	mux->reg = spicc->base + (u64) mux->reg;
+	mux->hw.init = &init;
+
+	spicc->clk = devm_clk_register(dev, &mux->hw);
+	if (WARN_ON(IS_ERR(spicc->clk)))
+		return PTR_ERR(spicc->clk);
+
+	clk_set_parent(spicc->clk, clk);
+	return 0;
+}
+
 static int meson_spicc_probe(struct platform_device *pdev)
 {
 	struct spi_master *master;
@@ -557,6 +675,10 @@ static int meson_spicc_probe(struct platform_device *pdev)
 		goto out_master;
 	}
 
+	/* Set master mode and enable controller */
+	writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
+			spicc->base + SPICC_CONREG);
+
 	/* Disable all IRQs */
 	writel_relaxed(0, spicc->base + SPICC_INTREG);
 
@@ -603,6 +725,12 @@ static int meson_spicc_probe(struct platform_device *pdev)
 	master->max_speed_hz = min_t(unsigned int, rate >> 1,
 			spicc->data->max_speed_hz);
 
+	ret = meson_spicc_clk_init(spicc);
+	if (ret) {
+		dev_err(&pdev->dev, "clock registration failed\n");
+		goto out_master;
+	}
+
 	ret = devm_spi_register_master(&pdev->dev, master);
 	if (!ret)
 		return 0;
@@ -634,6 +762,7 @@ static const struct meson_spicc_data meson_spicc_gx_data = {
 static const struct meson_spicc_data meson_spicc_axg_data = {
 	.max_speed_hz		= 80000000,
 	.has_oen		= true,
+	.has_enhance_clk_div 	= true,
 };
 
 static const struct of_device_id meson_spicc_of_match[] = {
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-03 21:36   ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: linux-arm-kernel

From: Sunny Luo <sunny.luo@amlogic.com>

The SPICC controller in Meson-AXG SoC is capable of using
a linear clock divider to reach a much fine tuned range of clocks,
while the old controller only use a power of two clock divider,
result at a more coarse clock range.

Also convert the clock registeration into Common Clock Framework.

Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 drivers/spi/spi-meson-spicc.c | 209 +++++++++++++++++++++++++++-------
 1 file changed, 169 insertions(+), 40 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 90b15f7d50dd..e8389d7e62e5 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -116,6 +116,9 @@
 #define SPICC_DWADDR	0x24	/* Write Address of DMA */
 
 #define SPICC_ENH_CTL0	0x38	/* Enhanced Feature */
+#define SPICC_ENH_CLK_CS_DELAY_MASK	GENMASK(15, 0)
+#define SPICC_ENH_DATARATE_MASK		GENMASK(23, 16)
+#define SPICC_ENH_DATARATE_EN		BIT(24)
 #define SPICC_ENH_MOSI_OEN		BIT(25)
 #define SPICC_ENH_CLK_OEN		BIT(26)
 #define SPICC_ENH_CS_OEN		BIT(27)
@@ -131,6 +134,7 @@
 struct meson_spicc_data {
 	unsigned int			max_speed_hz;
 	bool				has_oen;
+	bool				has_enhance_clk_div;
 };
 
 struct meson_spicc_device {
@@ -138,6 +142,7 @@ struct meson_spicc_device {
 	struct platform_device		*pdev;
 	void __iomem			*base;
 	struct clk			*core;
+	struct clk			*clk;
 	struct spi_message		*message;
 	struct spi_transfer		*xfer;
 	const struct meson_spicc_data	*data;
@@ -325,40 +330,6 @@ static irqreturn_t meson_spicc_irq(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-static u32 meson_spicc_setup_speed(struct meson_spicc_device *spicc, u32 conf,
-				   u32 speed)
-{
-	unsigned long parent, value;
-	unsigned int i, div;
-
-	parent = clk_get_rate(spicc->core);
-
-	/* Find closest inferior/equal possible speed */
-	for (i = 0 ; i < 7 ; ++i) {
-		/* 2^(data_rate+2) */
-		value = parent >> (i + 2);
-
-		if (value <= speed)
-			break;
-	}
-
-	/* If provided speed it lower than max divider, use max divider */
-	if (i > 7) {
-		div = 7;
-		dev_warn_once(&spicc->pdev->dev, "unable to get close to speed %u\n",
-			      speed);
-	} else
-		div = i;
-
-	dev_dbg(&spicc->pdev->dev, "parent %lu, speed %u -> %lu (%u)\n",
-		parent, speed, value, div);
-
-	conf &= ~SPICC_DATARATE_MASK;
-	conf |= FIELD_PREP(SPICC_DATARATE_MASK, div);
-
-	return conf;
-}
-
 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 				   struct spi_transfer *xfer)
 {
@@ -367,9 +338,6 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 	/* Read original configuration */
 	conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
 
-	/* Select closest divider */
-	conf = meson_spicc_setup_speed(spicc, conf, xfer->speed_hz);
-
 	/* Setup word width */
 	conf &= ~SPICC_BITLENGTH_MASK;
 	conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
@@ -378,6 +346,8 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 	/* Ignore if unchanged */
 	if (conf != conf_orig)
 		writel_relaxed(conf, spicc->base + SPICC_CONREG);
+
+	clk_set_rate(spicc->clk, xfer->speed_hz);
 }
 
 static int meson_spicc_transfer_one(struct spi_master *master,
@@ -486,9 +456,6 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master)
 	/* Disable all IRQs */
 	writel(0, spicc->base + SPICC_INTREG);
 
-	/* Disable controller */
-	writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG);
-
 	device_reset_optional(&spicc->pdev->dev);
 
 	return 0;
@@ -528,6 +495,157 @@ static void meson_spicc_cleanup(struct spi_device *spi)
 	spi->controller_state = NULL;
 }
 
+/*
+ * The Clock Mux
+ *            x-----------------x   x------------x    x------\
+ *        |---| 0) fixed factor |---| 1) old div |----|      |
+ *        |   x-----------------x   x------------x    |      |
+ * src ---|                                           |5) mux|-- out
+ *        |   x-----------------x   x------------x    |      |
+ *        |---| 2) fixed factor |---| 3) new div |0---|      |
+ *            x-----------------x   x------------x    x------/
+ *
+ * Clk path for GX series:
+ *    src -> 0 -> 1 -> out
+ *
+ * Clk path for AXG series:
+ *    src -> 0 -> 1 -> 5 -> out
+ *    src -> 2 -> 3 -> 5 -> out
+ */
+
+/* algorithm for div0 + div1: rate = freq / 4 / (2 ^ N) */
+static struct clk_fixed_factor meson_spicc_div0 = {
+	.mult	= 1,
+	.div	= 4,
+};
+
+static struct clk_divider meson_spicc_div1 = {
+	.reg	= (void *) SPICC_CONREG,
+	.shift	= 16,
+	.width	= 3,
+	.flags	= CLK_DIVIDER_POWER_OF_TWO,
+};
+
+/* algorithm for div2 + div3: rate = freq / 2 / (N + 1) */
+static struct clk_fixed_factor meson_spicc_div2 = {
+	.mult	= 1,
+	.div	= 2,
+};
+
+static struct clk_divider meson_spicc_div3 = {
+	.reg	= (void *) SPICC_ENH_CTL0,
+	.shift	= 16,
+	.width	= 8,
+};
+
+static struct clk_mux meson_spicc_sel = {
+	.reg	= (void *) SPICC_ENH_CTL0,
+	.mask	= 0x1,
+	.shift	= 24,
+};
+
+static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
+{
+	struct device *dev = &spicc->pdev->dev;
+	struct clk_fixed_factor *div0;
+	struct clk_divider *div1;
+	struct clk_mux *mux;
+	struct clk_init_data init;
+	struct clk *clk;
+	const char *parent_names[1];
+	const char *mux_parent_names[2];
+	char name[32];
+
+	div0 = &meson_spicc_div0;
+	snprintf(name, sizeof(name), "%s#_div0", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_fixed_factor_ops;
+	init.flags = 0;
+	parent_names[0] = __clk_get_name(spicc->core);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div0->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div0->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	div1 = &meson_spicc_div1;
+	snprintf(name, sizeof(name), "%s#_div1", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_divider_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	parent_names[0] = __clk_get_name(clk);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div1->reg = spicc->base + (u64) div1->reg;
+	div1->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div1->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	if (spicc->data->has_enhance_clk_div == false) {
+		spicc->clk = clk;
+		return 0;
+	}
+
+	mux_parent_names[0] = __clk_get_name(clk);
+
+	div0 = &meson_spicc_div2;
+	snprintf(name, sizeof(name), "%s#_div2", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_fixed_factor_ops;
+	init.flags = 0;
+	parent_names[0] = __clk_get_name(spicc->core);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div0->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div0->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	div1 = &meson_spicc_div3;
+	snprintf(name, sizeof(name), "%s#_div3", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_divider_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	parent_names[0] = __clk_get_name(clk);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div1->reg = spicc->base + (u64) div1->reg;
+	div1->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div1->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	mux_parent_names[1] = __clk_get_name(clk);
+
+	mux = &meson_spicc_sel;
+	snprintf(name, sizeof(name), "%s#_sel", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_mux_ops;
+	init.parent_names = mux_parent_names;
+	init.num_parents = 2;
+	init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
+
+	mux->reg = spicc->base + (u64) mux->reg;
+	mux->hw.init = &init;
+
+	spicc->clk = devm_clk_register(dev, &mux->hw);
+	if (WARN_ON(IS_ERR(spicc->clk)))
+		return PTR_ERR(spicc->clk);
+
+	clk_set_parent(spicc->clk, clk);
+	return 0;
+}
+
 static int meson_spicc_probe(struct platform_device *pdev)
 {
 	struct spi_master *master;
@@ -557,6 +675,10 @@ static int meson_spicc_probe(struct platform_device *pdev)
 		goto out_master;
 	}
 
+	/* Set master mode and enable controller */
+	writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
+			spicc->base + SPICC_CONREG);
+
 	/* Disable all IRQs */
 	writel_relaxed(0, spicc->base + SPICC_INTREG);
 
@@ -603,6 +725,12 @@ static int meson_spicc_probe(struct platform_device *pdev)
 	master->max_speed_hz = min_t(unsigned int, rate >> 1,
 			spicc->data->max_speed_hz);
 
+	ret = meson_spicc_clk_init(spicc);
+	if (ret) {
+		dev_err(&pdev->dev, "clock registration failed\n");
+		goto out_master;
+	}
+
 	ret = devm_spi_register_master(&pdev->dev, master);
 	if (!ret)
 		return 0;
@@ -634,6 +762,7 @@ static const struct meson_spicc_data meson_spicc_gx_data = {
 static const struct meson_spicc_data meson_spicc_axg_data = {
 	.max_speed_hz		= 80000000,
 	.has_oen		= true,
+	.has_enhance_clk_div 	= true,
 };
 
 static const struct of_device_id meson_spicc_of_match[] = {
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-03 21:36   ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-03 21:36 UTC (permalink / raw)
  To: linus-amlogic

From: Sunny Luo <sunny.luo@amlogic.com>

The SPICC controller in Meson-AXG SoC is capable of using
a linear clock divider to reach a much fine tuned range of clocks,
while the old controller only use a power of two clock divider,
result at a more coarse clock range.

Also convert the clock registeration into Common Clock Framework.

Signed-off-by: Sunny Luo <sunny.luo@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 drivers/spi/spi-meson-spicc.c | 209 +++++++++++++++++++++++++++-------
 1 file changed, 169 insertions(+), 40 deletions(-)

diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 90b15f7d50dd..e8389d7e62e5 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -116,6 +116,9 @@
 #define SPICC_DWADDR	0x24	/* Write Address of DMA */
 
 #define SPICC_ENH_CTL0	0x38	/* Enhanced Feature */
+#define SPICC_ENH_CLK_CS_DELAY_MASK	GENMASK(15, 0)
+#define SPICC_ENH_DATARATE_MASK		GENMASK(23, 16)
+#define SPICC_ENH_DATARATE_EN		BIT(24)
 #define SPICC_ENH_MOSI_OEN		BIT(25)
 #define SPICC_ENH_CLK_OEN		BIT(26)
 #define SPICC_ENH_CS_OEN		BIT(27)
@@ -131,6 +134,7 @@
 struct meson_spicc_data {
 	unsigned int			max_speed_hz;
 	bool				has_oen;
+	bool				has_enhance_clk_div;
 };
 
 struct meson_spicc_device {
@@ -138,6 +142,7 @@ struct meson_spicc_device {
 	struct platform_device		*pdev;
 	void __iomem			*base;
 	struct clk			*core;
+	struct clk			*clk;
 	struct spi_message		*message;
 	struct spi_transfer		*xfer;
 	const struct meson_spicc_data	*data;
@@ -325,40 +330,6 @@ static irqreturn_t meson_spicc_irq(int irq, void *data)
 	return IRQ_HANDLED;
 }
 
-static u32 meson_spicc_setup_speed(struct meson_spicc_device *spicc, u32 conf,
-				   u32 speed)
-{
-	unsigned long parent, value;
-	unsigned int i, div;
-
-	parent = clk_get_rate(spicc->core);
-
-	/* Find closest inferior/equal possible speed */
-	for (i = 0 ; i < 7 ; ++i) {
-		/* 2^(data_rate+2) */
-		value = parent >> (i + 2);
-
-		if (value <= speed)
-			break;
-	}
-
-	/* If provided speed it lower than max divider, use max divider */
-	if (i > 7) {
-		div = 7;
-		dev_warn_once(&spicc->pdev->dev, "unable to get close to speed %u\n",
-			      speed);
-	} else
-		div = i;
-
-	dev_dbg(&spicc->pdev->dev, "parent %lu, speed %u -> %lu (%u)\n",
-		parent, speed, value, div);
-
-	conf &= ~SPICC_DATARATE_MASK;
-	conf |= FIELD_PREP(SPICC_DATARATE_MASK, div);
-
-	return conf;
-}
-
 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 				   struct spi_transfer *xfer)
 {
@@ -367,9 +338,6 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 	/* Read original configuration */
 	conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
 
-	/* Select closest divider */
-	conf = meson_spicc_setup_speed(spicc, conf, xfer->speed_hz);
-
 	/* Setup word width */
 	conf &= ~SPICC_BITLENGTH_MASK;
 	conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
@@ -378,6 +346,8 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
 	/* Ignore if unchanged */
 	if (conf != conf_orig)
 		writel_relaxed(conf, spicc->base + SPICC_CONREG);
+
+	clk_set_rate(spicc->clk, xfer->speed_hz);
 }
 
 static int meson_spicc_transfer_one(struct spi_master *master,
@@ -486,9 +456,6 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master)
 	/* Disable all IRQs */
 	writel(0, spicc->base + SPICC_INTREG);
 
-	/* Disable controller */
-	writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG);
-
 	device_reset_optional(&spicc->pdev->dev);
 
 	return 0;
@@ -528,6 +495,157 @@ static void meson_spicc_cleanup(struct spi_device *spi)
 	spi->controller_state = NULL;
 }
 
+/*
+ * The Clock Mux
+ *            x-----------------x   x------------x    x------\
+ *        |---| 0) fixed factor |---| 1) old div |----|      |
+ *        |   x-----------------x   x------------x    |      |
+ * src ---|                                           |5) mux|-- out
+ *        |   x-----------------x   x------------x    |      |
+ *        |---| 2) fixed factor |---| 3) new div |0---|      |
+ *            x-----------------x   x------------x    x------/
+ *
+ * Clk path for GX series:
+ *    src -> 0 -> 1 -> out
+ *
+ * Clk path for AXG series:
+ *    src -> 0 -> 1 -> 5 -> out
+ *    src -> 2 -> 3 -> 5 -> out
+ */
+
+/* algorithm for div0 + div1: rate = freq / 4 / (2 ^ N) */
+static struct clk_fixed_factor meson_spicc_div0 = {
+	.mult	= 1,
+	.div	= 4,
+};
+
+static struct clk_divider meson_spicc_div1 = {
+	.reg	= (void *) SPICC_CONREG,
+	.shift	= 16,
+	.width	= 3,
+	.flags	= CLK_DIVIDER_POWER_OF_TWO,
+};
+
+/* algorithm for div2 + div3: rate = freq / 2 / (N + 1) */
+static struct clk_fixed_factor meson_spicc_div2 = {
+	.mult	= 1,
+	.div	= 2,
+};
+
+static struct clk_divider meson_spicc_div3 = {
+	.reg	= (void *) SPICC_ENH_CTL0,
+	.shift	= 16,
+	.width	= 8,
+};
+
+static struct clk_mux meson_spicc_sel = {
+	.reg	= (void *) SPICC_ENH_CTL0,
+	.mask	= 0x1,
+	.shift	= 24,
+};
+
+static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
+{
+	struct device *dev = &spicc->pdev->dev;
+	struct clk_fixed_factor *div0;
+	struct clk_divider *div1;
+	struct clk_mux *mux;
+	struct clk_init_data init;
+	struct clk *clk;
+	const char *parent_names[1];
+	const char *mux_parent_names[2];
+	char name[32];
+
+	div0 = &meson_spicc_div0;
+	snprintf(name, sizeof(name), "%s#_div0", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_fixed_factor_ops;
+	init.flags = 0;
+	parent_names[0] = __clk_get_name(spicc->core);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div0->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div0->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	div1 = &meson_spicc_div1;
+	snprintf(name, sizeof(name), "%s#_div1", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_divider_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	parent_names[0] = __clk_get_name(clk);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div1->reg = spicc->base + (u64) div1->reg;
+	div1->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div1->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	if (spicc->data->has_enhance_clk_div == false) {
+		spicc->clk = clk;
+		return 0;
+	}
+
+	mux_parent_names[0] = __clk_get_name(clk);
+
+	div0 = &meson_spicc_div2;
+	snprintf(name, sizeof(name), "%s#_div2", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_fixed_factor_ops;
+	init.flags = 0;
+	parent_names[0] = __clk_get_name(spicc->core);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div0->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div0->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	div1 = &meson_spicc_div3;
+	snprintf(name, sizeof(name), "%s#_div3", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_divider_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	parent_names[0] = __clk_get_name(clk);
+	init.parent_names = parent_names;
+	init.num_parents = 1;
+
+	div1->reg = spicc->base + (u64) div1->reg;
+	div1->hw.init = &init;
+
+	clk = devm_clk_register(dev, &div1->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		return PTR_ERR(clk);
+
+	mux_parent_names[1] = __clk_get_name(clk);
+
+	mux = &meson_spicc_sel;
+	snprintf(name, sizeof(name), "%s#_sel", dev_name(dev));
+	init.name = name;
+	init.ops = &clk_mux_ops;
+	init.parent_names = mux_parent_names;
+	init.num_parents = 2;
+	init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
+
+	mux->reg = spicc->base + (u64) mux->reg;
+	mux->hw.init = &init;
+
+	spicc->clk = devm_clk_register(dev, &mux->hw);
+	if (WARN_ON(IS_ERR(spicc->clk)))
+		return PTR_ERR(spicc->clk);
+
+	clk_set_parent(spicc->clk, clk);
+	return 0;
+}
+
 static int meson_spicc_probe(struct platform_device *pdev)
 {
 	struct spi_master *master;
@@ -557,6 +675,10 @@ static int meson_spicc_probe(struct platform_device *pdev)
 		goto out_master;
 	}
 
+	/* Set master mode and enable controller */
+	writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
+			spicc->base + SPICC_CONREG);
+
 	/* Disable all IRQs */
 	writel_relaxed(0, spicc->base + SPICC_INTREG);
 
@@ -603,6 +725,12 @@ static int meson_spicc_probe(struct platform_device *pdev)
 	master->max_speed_hz = min_t(unsigned int, rate >> 1,
 			spicc->data->max_speed_hz);
 
+	ret = meson_spicc_clk_init(spicc);
+	if (ret) {
+		dev_err(&pdev->dev, "clock registration failed\n");
+		goto out_master;
+	}
+
 	ret = devm_spi_register_master(&pdev->dev, master);
 	if (!ret)
 		return 0;
@@ -634,6 +762,7 @@ static const struct meson_spicc_data meson_spicc_gx_data = {
 static const struct meson_spicc_data meson_spicc_axg_data = {
 	.max_speed_hz		= 80000000,
 	.has_oen		= true,
+	.has_enhance_clk_div 	= true,
 };
 
 static const struct of_device_id meson_spicc_of_match[] = {
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 34+ messages in thread
* Re: [PATCH 1/3] spi: meson-axg: support MAX 80M clock
  2018-05-03 21:36   ` Yixun Lan
  (?)
@ 2018-05-03 23:13     ` Mark Brown
  -1 siblings, 0 replies; 34+ messages in thread
From: Mark Brown @ 2018-05-03 23:13 UTC (permalink / raw)
  To: Yixun Lan
  Cc: Sunny Luo, Neil Armstrong, Jerome Brunet, Kevin Hilman,
	Carlo Caione, linux-spi, linux-amlogic, linux-arm-kernel,
	linux-kernel

[-- Attachment #1: Type: text/plain, Size: 608 bytes --]

On Thu, May 03, 2018 at 09:36:42PM +0000, Yixun Lan wrote:

>  static const struct of_device_id meson_spicc_of_match[] = {
> -	{ .compatible = "amlogic,meson-gx-spicc", },
> -	{ .compatible = "amlogic,meson-axg-spicc", },
> +	{
> +		.compatible	= "amlogic,meson-gx-spicc",
> +		.data		= &meson_spicc_gx_data,
> +	},
> +	{
> +		.compatible = "amlogic,meson-axg-spicc",
> +		.data		= &meson_spicc_axg_data,
> +	},
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, meson_spicc_of_match);

This is changing the DT bindings but there's no update to the DT binding
documentation, please add an update there.

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^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 1/3] spi: meson-axg: support MAX 80M clock
@ 2018-05-03 23:13     ` Mark Brown
  0 siblings, 0 replies; 34+ messages in thread
From: Mark Brown @ 2018-05-03 23:13 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, May 03, 2018 at 09:36:42PM +0000, Yixun Lan wrote:

>  static const struct of_device_id meson_spicc_of_match[] = {
> -	{ .compatible = "amlogic,meson-gx-spicc", },
> -	{ .compatible = "amlogic,meson-axg-spicc", },
> +	{
> +		.compatible	= "amlogic,meson-gx-spicc",
> +		.data		= &meson_spicc_gx_data,
> +	},
> +	{
> +		.compatible = "amlogic,meson-axg-spicc",
> +		.data		= &meson_spicc_axg_data,
> +	},
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, meson_spicc_of_match);

This is changing the DT bindings but there's no update to the DT binding
documentation, please add an update there.
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 1/3] spi: meson-axg: support MAX 80M clock
@ 2018-05-03 23:13     ` Mark Brown
  0 siblings, 0 replies; 34+ messages in thread
From: Mark Brown @ 2018-05-03 23:13 UTC (permalink / raw)
  To: linus-amlogic

On Thu, May 03, 2018 at 09:36:42PM +0000, Yixun Lan wrote:

>  static const struct of_device_id meson_spicc_of_match[] = {
> -	{ .compatible = "amlogic,meson-gx-spicc", },
> -	{ .compatible = "amlogic,meson-axg-spicc", },
> +	{
> +		.compatible	= "amlogic,meson-gx-spicc",
> +		.data		= &meson_spicc_gx_data,
> +	},
> +	{
> +		.compatible = "amlogic,meson-axg-spicc",
> +		.data		= &meson_spicc_axg_data,
> +	},
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, meson_spicc_of_match);

This is changing the DT bindings but there's no update to the DT binding
documentation, please add an update there.
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH 3/3] spi: meson-axg: add a linear clock divider support
  2018-05-03 21:36   ` Yixun Lan
  (?)
@ 2018-05-03 23:16     ` Mark Brown
  -1 siblings, 0 replies; 34+ messages in thread
From: Mark Brown @ 2018-05-03 23:16 UTC (permalink / raw)
  To: Yixun Lan
  Cc: Sunny Luo, Neil Armstrong, Jerome Brunet, Kevin Hilman,
	Carlo Caione, linux-spi, linux-amlogic, linux-arm-kernel,
	linux-kernel

[-- Attachment #1: Type: text/plain, Size: 659 bytes --]

On Thu, May 03, 2018 at 09:36:44PM +0000, Yixun Lan wrote:
> From: Sunny Luo <sunny.luo@amlogic.com>
> 
> The SPICC controller in Meson-AXG SoC is capable of using
> a linear clock divider to reach a much fine tuned range of clocks,
> while the old controller only use a power of two clock divider,
> result at a more coarse clock range.
> 
> Also convert the clock registeration into Common Clock Framework.

This would be better split into two patches - one adding the new linear
clock divider and the other one doing the CCF conversion.  Splitting
things out like that makes them much easier to review as each change is
only doing one thing.

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^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-03 23:16     ` Mark Brown
  0 siblings, 0 replies; 34+ messages in thread
From: Mark Brown @ 2018-05-03 23:16 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, May 03, 2018 at 09:36:44PM +0000, Yixun Lan wrote:
> From: Sunny Luo <sunny.luo@amlogic.com>
> 
> The SPICC controller in Meson-AXG SoC is capable of using
> a linear clock divider to reach a much fine tuned range of clocks,
> while the old controller only use a power of two clock divider,
> result at a more coarse clock range.
> 
> Also convert the clock registeration into Common Clock Framework.

This would be better split into two patches - one adding the new linear
clock divider and the other one doing the CCF conversion.  Splitting
things out like that makes them much easier to review as each change is
only doing one thing.
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-03 23:16     ` Mark Brown
  0 siblings, 0 replies; 34+ messages in thread
From: Mark Brown @ 2018-05-03 23:16 UTC (permalink / raw)
  To: linus-amlogic

On Thu, May 03, 2018 at 09:36:44PM +0000, Yixun Lan wrote:
> From: Sunny Luo <sunny.luo@amlogic.com>
> 
> The SPICC controller in Meson-AXG SoC is capable of using
> a linear clock divider to reach a much fine tuned range of clocks,
> while the old controller only use a power of two clock divider,
> result at a more coarse clock range.
> 
> Also convert the clock registeration into Common Clock Framework.

This would be better split into two patches - one adding the new linear
clock divider and the other one doing the CCF conversion.  Splitting
things out like that makes them much easier to review as each change is
only doing one thing.
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH 1/3] spi: meson-axg: support MAX 80M clock
  2018-05-03 23:13     ` Mark Brown
  (?)
@ 2018-05-04  1:56       ` Yixun Lan
  -1 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-04  1:56 UTC (permalink / raw)
  To: Mark Brown
  Cc: yixun.lan, Sunny Luo, Neil Armstrong, Jerome Brunet,
	Kevin Hilman, Carlo Caione, linux-spi, linux-amlogic,
	linux-arm-kernel, linux-kernel

Hi Mark

On 05/04/18 07:13, Mark Brown wrote:
> On Thu, May 03, 2018 at 09:36:42PM +0000, Yixun Lan wrote:
> 
>>  static const struct of_device_id meson_spicc_of_match[] = {
>> -	{ .compatible = "amlogic,meson-gx-spicc", },
>> -	{ .compatible = "amlogic,meson-axg-spicc", },
>> +	{
>> +		.compatible	= "amlogic,meson-gx-spicc",
>> +		.data		= &meson_spicc_gx_data,
>> +	},
>> +	{
>> +		.compatible = "amlogic,meson-axg-spicc",
>> +		.data		= &meson_spicc_axg_data,
>> +	},
>>  	{ /* sentinel */ }
>>  };
>>  MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
> 
> This is changing the DT bindings but there's no update to the DT binding
> documentation, please add an update there.
> 

thanks for your comments, but I actually didn't get what's your point here.

Here I only introduce the dt compatible data to differentiate the
old/new controller, the compatible name is not changed, and none of the
property is introduced.

Yixun

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 1/3] spi: meson-axg: support MAX 80M clock
@ 2018-05-04  1:56       ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-04  1:56 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Mark

On 05/04/18 07:13, Mark Brown wrote:
> On Thu, May 03, 2018 at 09:36:42PM +0000, Yixun Lan wrote:
> 
>>  static const struct of_device_id meson_spicc_of_match[] = {
>> -	{ .compatible = "amlogic,meson-gx-spicc", },
>> -	{ .compatible = "amlogic,meson-axg-spicc", },
>> +	{
>> +		.compatible	= "amlogic,meson-gx-spicc",
>> +		.data		= &meson_spicc_gx_data,
>> +	},
>> +	{
>> +		.compatible = "amlogic,meson-axg-spicc",
>> +		.data		= &meson_spicc_axg_data,
>> +	},
>>  	{ /* sentinel */ }
>>  };
>>  MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
> 
> This is changing the DT bindings but there's no update to the DT binding
> documentation, please add an update there.
> 

thanks for your comments, but I actually didn't get what's your point here.

Here I only introduce the dt compatible data to differentiate the
old/new controller, the compatible name is not changed, and none of the
property is introduced.

Yixun

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 1/3] spi: meson-axg: support MAX 80M clock
@ 2018-05-04  1:56       ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-04  1:56 UTC (permalink / raw)
  To: linus-amlogic

Hi Mark

On 05/04/18 07:13, Mark Brown wrote:
> On Thu, May 03, 2018 at 09:36:42PM +0000, Yixun Lan wrote:
> 
>>  static const struct of_device_id meson_spicc_of_match[] = {
>> -	{ .compatible = "amlogic,meson-gx-spicc", },
>> -	{ .compatible = "amlogic,meson-axg-spicc", },
>> +	{
>> +		.compatible	= "amlogic,meson-gx-spicc",
>> +		.data		= &meson_spicc_gx_data,
>> +	},
>> +	{
>> +		.compatible = "amlogic,meson-axg-spicc",
>> +		.data		= &meson_spicc_axg_data,
>> +	},
>>  	{ /* sentinel */ }
>>  };
>>  MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
> 
> This is changing the DT bindings but there's no update to the DT binding
> documentation, please add an update there.
> 

thanks for your comments, but I actually didn't get what's your point here.

Here I only introduce the dt compatible data to differentiate the
old/new controller, the compatible name is not changed, and none of the
property is introduced.

Yixun

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH 3/3] spi: meson-axg: add a linear clock divider support
  2018-05-03 23:16     ` Mark Brown
  (?)
  (?)
@ 2018-05-04  2:07       ` Yixun Lan
  -1 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-04  2:07 UTC (permalink / raw)
  To: Mark Brown
  Cc: yixun.lan, Sunny Luo, Neil Armstrong, Jerome Brunet,
	Kevin Hilman, Carlo Caione, linux-spi, linux-amlogic,
	linux-arm-kernel, linux-kernel

Hi Mark

On 05/04/18 07:16, Mark Brown wrote:
> On Thu, May 03, 2018 at 09:36:44PM +0000, Yixun Lan wrote:
>> From: Sunny Luo <sunny.luo@amlogic.com>
>>
>> The SPICC controller in Meson-AXG SoC is capable of using
>> a linear clock divider to reach a much fine tuned range of clocks,
>> while the old controller only use a power of two clock divider,
>> result at a more coarse clock range.
>>
>> Also convert the clock registeration into Common Clock Framework.
> 
> This would be better split into two patches - one adding the new linear
> clock divider and the other one doing the CCF conversion.  Splitting
> things out like that makes them much easier to review as each change is
> only doing one thing.
> 

it's maybe obscure in my previous commit message, the clock divider
support is actually achieved via CCF framework, it can be split as two
independent patches..

I'm CCing clock mailing list (will do if I need to send a v2)

Yixun

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-04  2:07       ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-04  2:07 UTC (permalink / raw)
  To: Mark Brown
  Cc: Neil Armstrong, Kevin Hilman, yixun.lan, linux-kernel, linux-spi,
	Carlo Caione, linux-amlogic, Sunny Luo, linux-arm-kernel,
	Jerome Brunet

Hi Mark

On 05/04/18 07:16, Mark Brown wrote:
> On Thu, May 03, 2018 at 09:36:44PM +0000, Yixun Lan wrote:
>> From: Sunny Luo <sunny.luo@amlogic.com>
>>
>> The SPICC controller in Meson-AXG SoC is capable of using
>> a linear clock divider to reach a much fine tuned range of clocks,
>> while the old controller only use a power of two clock divider,
>> result at a more coarse clock range.
>>
>> Also convert the clock registeration into Common Clock Framework.
> 
> This would be better split into two patches - one adding the new linear
> clock divider and the other one doing the CCF conversion.  Splitting
> things out like that makes them much easier to review as each change is
> only doing one thing.
> 

it's maybe obscure in my previous commit message, the clock divider
support is actually achieved via CCF framework, it can be split as two
independent patches..

I'm CCing clock mailing list (will do if I need to send a v2)

Yixun

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-04  2:07       ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-04  2:07 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Mark

On 05/04/18 07:16, Mark Brown wrote:
> On Thu, May 03, 2018 at 09:36:44PM +0000, Yixun Lan wrote:
>> From: Sunny Luo <sunny.luo@amlogic.com>
>>
>> The SPICC controller in Meson-AXG SoC is capable of using
>> a linear clock divider to reach a much fine tuned range of clocks,
>> while the old controller only use a power of two clock divider,
>> result at a more coarse clock range.
>>
>> Also convert the clock registeration into Common Clock Framework.
> 
> This would be better split into two patches - one adding the new linear
> clock divider and the other one doing the CCF conversion.  Splitting
> things out like that makes them much easier to review as each change is
> only doing one thing.
> 

it's maybe obscure in my previous commit message, the clock divider
support is actually achieved via CCF framework, it can be split as two
independent patches..

I'm CCing clock mailing list (will do if I need to send a v2)

Yixun

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-04  2:07       ` Yixun Lan
  0 siblings, 0 replies; 34+ messages in thread
From: Yixun Lan @ 2018-05-04  2:07 UTC (permalink / raw)
  To: linus-amlogic

Hi Mark

On 05/04/18 07:16, Mark Brown wrote:
> On Thu, May 03, 2018 at 09:36:44PM +0000, Yixun Lan wrote:
>> From: Sunny Luo <sunny.luo@amlogic.com>
>>
>> The SPICC controller in Meson-AXG SoC is capable of using
>> a linear clock divider to reach a much fine tuned range of clocks,
>> while the old controller only use a power of two clock divider,
>> result at a more coarse clock range.
>>
>> Also convert the clock registeration into Common Clock Framework.
> 
> This would be better split into two patches - one adding the new linear
> clock divider and the other one doing the CCF conversion.  Splitting
> things out like that makes them much easier to review as each change is
> only doing one thing.
> 

it's maybe obscure in my previous commit message, the clock divider
support is actually achieved via CCF framework, it can be split as two
independent patches..

I'm CCing clock mailing list (will do if I need to send a v2)

Yixun

^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH 3/3] spi: meson-axg: add a linear clock divider support
  2018-05-03 21:36   ` Yixun Lan
  (?)
@ 2018-05-04  2:22     ` kbuild test robot
  -1 siblings, 0 replies; 34+ messages in thread
From: kbuild test robot @ 2018-05-04  2:22 UTC (permalink / raw)
  To: Yixun Lan
  Cc: kbuild-all, Mark Brown, Sunny Luo, Yixun Lan, Neil Armstrong,
	Jerome Brunet, Kevin Hilman, Carlo Caione, linux-spi,
	linux-amlogic, linux-arm-kernel, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 13031 bytes --]

Hi Sunny,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on v4.17-rc3]
[also build test ERROR on next-20180503]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Yixun-Lan/spi-meson-axg-add-few-enhanced-features/20180504-083512
config: sparc64-allmodconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=sparc64 

All error/warnings (new ones prefixed by >>):

>> drivers//spi/spi-meson-spicc.c:517:15: error: variable 'meson_spicc_div0' has initializer but incomplete type
    static struct clk_fixed_factor meson_spicc_div0 = {
                  ^~~~~~~~~~~~~~~~
>> drivers//spi/spi-meson-spicc.c:518:3: error: 'struct clk_fixed_factor' has no member named 'mult'
     .mult = 1,
      ^~~~
>> drivers//spi/spi-meson-spicc.c:518:10: warning: excess elements in struct initializer
     .mult = 1,
             ^
   drivers//spi/spi-meson-spicc.c:518:10: note: (near initialization for 'meson_spicc_div0')
>> drivers//spi/spi-meson-spicc.c:519:3: error: 'struct clk_fixed_factor' has no member named 'div'
     .div = 4,
      ^~~
   drivers//spi/spi-meson-spicc.c:519:9: warning: excess elements in struct initializer
     .div = 4,
            ^
   drivers//spi/spi-meson-spicc.c:519:9: note: (near initialization for 'meson_spicc_div0')
>> drivers//spi/spi-meson-spicc.c:522:15: error: variable 'meson_spicc_div1' has initializer but incomplete type
    static struct clk_divider meson_spicc_div1 = {
                  ^~~~~~~~~~~
>> drivers//spi/spi-meson-spicc.c:523:3: error: 'struct clk_divider' has no member named 'reg'
     .reg = (void *) SPICC_CONREG,
      ^~~
   drivers//spi/spi-meson-spicc.c:523:9: warning: excess elements in struct initializer
     .reg = (void *) SPICC_CONREG,
            ^
   drivers//spi/spi-meson-spicc.c:523:9: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:524:3: error: 'struct clk_divider' has no member named 'shift'
     .shift = 16,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:524:11: warning: excess elements in struct initializer
     .shift = 16,
              ^~
   drivers//spi/spi-meson-spicc.c:524:11: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:525:3: error: 'struct clk_divider' has no member named 'width'
     .width = 3,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:525:11: warning: excess elements in struct initializer
     .width = 3,
              ^
   drivers//spi/spi-meson-spicc.c:525:11: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:526:3: error: 'struct clk_divider' has no member named 'flags'
     .flags = CLK_DIVIDER_POWER_OF_TWO,
      ^~~~~
>> drivers//spi/spi-meson-spicc.c:526:11: error: 'CLK_DIVIDER_POWER_OF_TWO' undeclared here (not in a function)
     .flags = CLK_DIVIDER_POWER_OF_TWO,
              ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers//spi/spi-meson-spicc.c:526:11: warning: excess elements in struct initializer
   drivers//spi/spi-meson-spicc.c:526:11: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:530:15: error: variable 'meson_spicc_div2' has initializer but incomplete type
    static struct clk_fixed_factor meson_spicc_div2 = {
                  ^~~~~~~~~~~~~~~~
   drivers//spi/spi-meson-spicc.c:531:3: error: 'struct clk_fixed_factor' has no member named 'mult'
     .mult = 1,
      ^~~~
   drivers//spi/spi-meson-spicc.c:531:10: warning: excess elements in struct initializer
     .mult = 1,
             ^
   drivers//spi/spi-meson-spicc.c:531:10: note: (near initialization for 'meson_spicc_div2')
   drivers//spi/spi-meson-spicc.c:532:3: error: 'struct clk_fixed_factor' has no member named 'div'
     .div = 2,
      ^~~
   drivers//spi/spi-meson-spicc.c:532:9: warning: excess elements in struct initializer
     .div = 2,
            ^
   drivers//spi/spi-meson-spicc.c:532:9: note: (near initialization for 'meson_spicc_div2')
>> drivers//spi/spi-meson-spicc.c:535:15: error: variable 'meson_spicc_div3' has initializer but incomplete type
    static struct clk_divider meson_spicc_div3 = {
                  ^~~~~~~~~~~
   drivers//spi/spi-meson-spicc.c:536:3: error: 'struct clk_divider' has no member named 'reg'
     .reg = (void *) SPICC_ENH_CTL0,
      ^~~
   drivers//spi/spi-meson-spicc.c:536:9: warning: excess elements in struct initializer
     .reg = (void *) SPICC_ENH_CTL0,
            ^
   drivers//spi/spi-meson-spicc.c:536:9: note: (near initialization for 'meson_spicc_div3')
   drivers//spi/spi-meson-spicc.c:537:3: error: 'struct clk_divider' has no member named 'shift'
     .shift = 16,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:537:11: warning: excess elements in struct initializer
     .shift = 16,
              ^~
   drivers//spi/spi-meson-spicc.c:537:11: note: (near initialization for 'meson_spicc_div3')
   drivers//spi/spi-meson-spicc.c:538:3: error: 'struct clk_divider' has no member named 'width'
     .width = 8,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:538:11: warning: excess elements in struct initializer
     .width = 8,
              ^
   drivers//spi/spi-meson-spicc.c:538:11: note: (near initialization for 'meson_spicc_div3')
>> drivers//spi/spi-meson-spicc.c:541:15: error: variable 'meson_spicc_sel' has initializer but incomplete type
    static struct clk_mux meson_spicc_sel = {
                  ^~~~~~~
>> drivers//spi/spi-meson-spicc.c:542:3: error: 'struct clk_mux' has no member named 'reg'
     .reg = (void *) SPICC_ENH_CTL0,
      ^~~
   drivers//spi/spi-meson-spicc.c:542:9: warning: excess elements in struct initializer
     .reg = (void *) SPICC_ENH_CTL0,
            ^
   drivers//spi/spi-meson-spicc.c:542:9: note: (near initialization for 'meson_spicc_sel')
>> drivers//spi/spi-meson-spicc.c:543:3: error: 'struct clk_mux' has no member named 'mask'
     .mask = 0x1,
      ^~~~
   drivers//spi/spi-meson-spicc.c:543:10: warning: excess elements in struct initializer
     .mask = 0x1,
             ^~~
   drivers//spi/spi-meson-spicc.c:543:10: note: (near initialization for 'meson_spicc_sel')
>> drivers//spi/spi-meson-spicc.c:544:3: error: 'struct clk_mux' has no member named 'shift'
     .shift = 24,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:544:11: warning: excess elements in struct initializer
     .shift = 24,
              ^~
   drivers//spi/spi-meson-spicc.c:544:11: note: (near initialization for 'meson_spicc_sel')
   drivers//spi/spi-meson-spicc.c: In function 'meson_spicc_clk_init':
>> drivers//spi/spi-meson-spicc.c:553:23: error: storage size of 'init' isn't known
     struct clk_init_data init;
                          ^~~~
>> drivers//spi/spi-meson-spicc.c:562:14: error: 'clk_fixed_factor_ops' undeclared (first use in this function); did you mean 'clk_fixed_factor'?
     init.ops = &clk_fixed_factor_ops;
                 ^~~~~~~~~~~~~~~~~~~~
                 clk_fixed_factor
   drivers//spi/spi-meson-spicc.c:562:14: note: each undeclared identifier is reported only once for each function it appears in
>> drivers//spi/spi-meson-spicc.c:564:20: error: implicit declaration of function '__clk_get_name'; did you mean 'clk_get_rate'? [-Werror=implicit-function-declaration]
     parent_names[0] = __clk_get_name(spicc->core);
                       ^~~~~~~~~~~~~~
                       clk_get_rate
>> drivers//spi/spi-meson-spicc.c:564:18: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
     parent_names[0] = __clk_get_name(spicc->core);
                     ^

vim +/meson_spicc_div0 +517 drivers//spi/spi-meson-spicc.c

   497	
   498	/*
   499	 * The Clock Mux
   500	 *            x-----------------x   x------------x    x------\
   501	 *        |---| 0) fixed factor |---| 1) old div |----|      |
   502	 *        |   x-----------------x   x------------x    |      |
   503	 * src ---|                                           |5) mux|-- out
   504	 *        |   x-----------------x   x------------x    |      |
   505	 *        |---| 2) fixed factor |---| 3) new div |0---|      |
   506	 *            x-----------------x   x------------x    x------/
   507	 *
   508	 * Clk path for GX series:
   509	 *    src -> 0 -> 1 -> out
   510	 *
   511	 * Clk path for AXG series:
   512	 *    src -> 0 -> 1 -> 5 -> out
   513	 *    src -> 2 -> 3 -> 5 -> out
   514	 */
   515	
   516	/* algorithm for div0 + div1: rate = freq / 4 / (2 ^ N) */
 > 517	static struct clk_fixed_factor meson_spicc_div0 = {
 > 518		.mult	= 1,
 > 519		.div	= 4,
   520	};
   521	
 > 522	static struct clk_divider meson_spicc_div1 = {
 > 523		.reg	= (void *) SPICC_CONREG,
 > 524		.shift	= 16,
 > 525		.width	= 3,
 > 526		.flags	= CLK_DIVIDER_POWER_OF_TWO,
   527	};
   528	
   529	/* algorithm for div2 + div3: rate = freq / 2 / (N + 1) */
 > 530	static struct clk_fixed_factor meson_spicc_div2 = {
 > 531		.mult	= 1,
   532		.div	= 2,
   533	};
   534	
 > 535	static struct clk_divider meson_spicc_div3 = {
   536		.reg	= (void *) SPICC_ENH_CTL0,
 > 537		.shift	= 16,
 > 538		.width	= 8,
   539	};
   540	
 > 541	static struct clk_mux meson_spicc_sel = {
 > 542		.reg	= (void *) SPICC_ENH_CTL0,
 > 543		.mask	= 0x1,
 > 544		.shift	= 24,
   545	};
   546	
   547	static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
   548	{
   549		struct device *dev = &spicc->pdev->dev;
   550		struct clk_fixed_factor *div0;
   551		struct clk_divider *div1;
   552		struct clk_mux *mux;
 > 553		struct clk_init_data init;
   554		struct clk *clk;
   555		const char *parent_names[1];
   556		const char *mux_parent_names[2];
   557		char name[32];
   558	
   559		div0 = &meson_spicc_div0;
   560		snprintf(name, sizeof(name), "%s#_div0", dev_name(dev));
   561		init.name = name;
 > 562		init.ops = &clk_fixed_factor_ops;
   563		init.flags = 0;
 > 564		parent_names[0] = __clk_get_name(spicc->core);
   565		init.parent_names = parent_names;
   566		init.num_parents = 1;
   567	
 > 568		div0->hw.init = &init;
   569	
 > 570		clk = devm_clk_register(dev, &div0->hw);
   571		if (WARN_ON(IS_ERR(clk)))
   572			return PTR_ERR(clk);
   573	
   574		div1 = &meson_spicc_div1;
   575		snprintf(name, sizeof(name), "%s#_div1", dev_name(dev));
   576		init.name = name;
 > 577		init.ops = &clk_divider_ops;
 > 578		init.flags = CLK_SET_RATE_PARENT;
   579		parent_names[0] = __clk_get_name(clk);
   580		init.parent_names = parent_names;
   581		init.num_parents = 1;
   582	
 > 583		div1->reg = spicc->base + (u64) div1->reg;
   584		div1->hw.init = &init;
   585	
   586		clk = devm_clk_register(dev, &div1->hw);
   587		if (WARN_ON(IS_ERR(clk)))
   588			return PTR_ERR(clk);
   589	
   590		if (spicc->data->has_enhance_clk_div == false) {
   591			spicc->clk = clk;
   592			return 0;
   593		}
   594	
   595		mux_parent_names[0] = __clk_get_name(clk);
   596	
   597		div0 = &meson_spicc_div2;
   598		snprintf(name, sizeof(name), "%s#_div2", dev_name(dev));
   599		init.name = name;
   600		init.ops = &clk_fixed_factor_ops;
   601		init.flags = 0;
 > 602		parent_names[0] = __clk_get_name(spicc->core);
   603		init.parent_names = parent_names;
   604		init.num_parents = 1;
   605	
   606		div0->hw.init = &init;
   607	
   608		clk = devm_clk_register(dev, &div0->hw);
   609		if (WARN_ON(IS_ERR(clk)))
   610			return PTR_ERR(clk);
   611	
   612		div1 = &meson_spicc_div3;
   613		snprintf(name, sizeof(name), "%s#_div3", dev_name(dev));
   614		init.name = name;
   615		init.ops = &clk_divider_ops;
   616		init.flags = CLK_SET_RATE_PARENT;
   617		parent_names[0] = __clk_get_name(clk);
   618		init.parent_names = parent_names;
   619		init.num_parents = 1;
   620	
   621		div1->reg = spicc->base + (u64) div1->reg;
   622		div1->hw.init = &init;
   623	
   624		clk = devm_clk_register(dev, &div1->hw);
   625		if (WARN_ON(IS_ERR(clk)))
   626			return PTR_ERR(clk);
   627	
 > 628		mux_parent_names[1] = __clk_get_name(clk);
   629	
   630		mux = &meson_spicc_sel;
   631		snprintf(name, sizeof(name), "%s#_sel", dev_name(dev));
   632		init.name = name;
 > 633		init.ops = &clk_mux_ops;
   634		init.parent_names = mux_parent_names;
   635		init.num_parents = 2;
 > 636		init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
   637	
 > 638		mux->reg = spicc->base + (u64) mux->reg;
   639		mux->hw.init = &init;
   640	
   641		spicc->clk = devm_clk_register(dev, &mux->hw);
   642		if (WARN_ON(IS_ERR(spicc->clk)))
   643			return PTR_ERR(spicc->clk);
   644	
   645		clk_set_parent(spicc->clk, clk);
   646		return 0;
   647	}
   648	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 53170 bytes --]

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-04  2:22     ` kbuild test robot
  0 siblings, 0 replies; 34+ messages in thread
From: kbuild test robot @ 2018-05-04  2:22 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Sunny,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on v4.17-rc3]
[also build test ERROR on next-20180503]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Yixun-Lan/spi-meson-axg-add-few-enhanced-features/20180504-083512
config: sparc64-allmodconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=sparc64 

All error/warnings (new ones prefixed by >>):

>> drivers//spi/spi-meson-spicc.c:517:15: error: variable 'meson_spicc_div0' has initializer but incomplete type
    static struct clk_fixed_factor meson_spicc_div0 = {
                  ^~~~~~~~~~~~~~~~
>> drivers//spi/spi-meson-spicc.c:518:3: error: 'struct clk_fixed_factor' has no member named 'mult'
     .mult = 1,
      ^~~~
>> drivers//spi/spi-meson-spicc.c:518:10: warning: excess elements in struct initializer
     .mult = 1,
             ^
   drivers//spi/spi-meson-spicc.c:518:10: note: (near initialization for 'meson_spicc_div0')
>> drivers//spi/spi-meson-spicc.c:519:3: error: 'struct clk_fixed_factor' has no member named 'div'
     .div = 4,
      ^~~
   drivers//spi/spi-meson-spicc.c:519:9: warning: excess elements in struct initializer
     .div = 4,
            ^
   drivers//spi/spi-meson-spicc.c:519:9: note: (near initialization for 'meson_spicc_div0')
>> drivers//spi/spi-meson-spicc.c:522:15: error: variable 'meson_spicc_div1' has initializer but incomplete type
    static struct clk_divider meson_spicc_div1 = {
                  ^~~~~~~~~~~
>> drivers//spi/spi-meson-spicc.c:523:3: error: 'struct clk_divider' has no member named 'reg'
     .reg = (void *) SPICC_CONREG,
      ^~~
   drivers//spi/spi-meson-spicc.c:523:9: warning: excess elements in struct initializer
     .reg = (void *) SPICC_CONREG,
            ^
   drivers//spi/spi-meson-spicc.c:523:9: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:524:3: error: 'struct clk_divider' has no member named 'shift'
     .shift = 16,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:524:11: warning: excess elements in struct initializer
     .shift = 16,
              ^~
   drivers//spi/spi-meson-spicc.c:524:11: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:525:3: error: 'struct clk_divider' has no member named 'width'
     .width = 3,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:525:11: warning: excess elements in struct initializer
     .width = 3,
              ^
   drivers//spi/spi-meson-spicc.c:525:11: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:526:3: error: 'struct clk_divider' has no member named 'flags'
     .flags = CLK_DIVIDER_POWER_OF_TWO,
      ^~~~~
>> drivers//spi/spi-meson-spicc.c:526:11: error: 'CLK_DIVIDER_POWER_OF_TWO' undeclared here (not in a function)
     .flags = CLK_DIVIDER_POWER_OF_TWO,
              ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers//spi/spi-meson-spicc.c:526:11: warning: excess elements in struct initializer
   drivers//spi/spi-meson-spicc.c:526:11: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:530:15: error: variable 'meson_spicc_div2' has initializer but incomplete type
    static struct clk_fixed_factor meson_spicc_div2 = {
                  ^~~~~~~~~~~~~~~~
   drivers//spi/spi-meson-spicc.c:531:3: error: 'struct clk_fixed_factor' has no member named 'mult'
     .mult = 1,
      ^~~~
   drivers//spi/spi-meson-spicc.c:531:10: warning: excess elements in struct initializer
     .mult = 1,
             ^
   drivers//spi/spi-meson-spicc.c:531:10: note: (near initialization for 'meson_spicc_div2')
   drivers//spi/spi-meson-spicc.c:532:3: error: 'struct clk_fixed_factor' has no member named 'div'
     .div = 2,
      ^~~
   drivers//spi/spi-meson-spicc.c:532:9: warning: excess elements in struct initializer
     .div = 2,
            ^
   drivers//spi/spi-meson-spicc.c:532:9: note: (near initialization for 'meson_spicc_div2')
>> drivers//spi/spi-meson-spicc.c:535:15: error: variable 'meson_spicc_div3' has initializer but incomplete type
    static struct clk_divider meson_spicc_div3 = {
                  ^~~~~~~~~~~
   drivers//spi/spi-meson-spicc.c:536:3: error: 'struct clk_divider' has no member named 'reg'
     .reg = (void *) SPICC_ENH_CTL0,
      ^~~
   drivers//spi/spi-meson-spicc.c:536:9: warning: excess elements in struct initializer
     .reg = (void *) SPICC_ENH_CTL0,
            ^
   drivers//spi/spi-meson-spicc.c:536:9: note: (near initialization for 'meson_spicc_div3')
   drivers//spi/spi-meson-spicc.c:537:3: error: 'struct clk_divider' has no member named 'shift'
     .shift = 16,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:537:11: warning: excess elements in struct initializer
     .shift = 16,
              ^~
   drivers//spi/spi-meson-spicc.c:537:11: note: (near initialization for 'meson_spicc_div3')
   drivers//spi/spi-meson-spicc.c:538:3: error: 'struct clk_divider' has no member named 'width'
     .width = 8,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:538:11: warning: excess elements in struct initializer
     .width = 8,
              ^
   drivers//spi/spi-meson-spicc.c:538:11: note: (near initialization for 'meson_spicc_div3')
>> drivers//spi/spi-meson-spicc.c:541:15: error: variable 'meson_spicc_sel' has initializer but incomplete type
    static struct clk_mux meson_spicc_sel = {
                  ^~~~~~~
>> drivers//spi/spi-meson-spicc.c:542:3: error: 'struct clk_mux' has no member named 'reg'
     .reg = (void *) SPICC_ENH_CTL0,
      ^~~
   drivers//spi/spi-meson-spicc.c:542:9: warning: excess elements in struct initializer
     .reg = (void *) SPICC_ENH_CTL0,
            ^
   drivers//spi/spi-meson-spicc.c:542:9: note: (near initialization for 'meson_spicc_sel')
>> drivers//spi/spi-meson-spicc.c:543:3: error: 'struct clk_mux' has no member named 'mask'
     .mask = 0x1,
      ^~~~
   drivers//spi/spi-meson-spicc.c:543:10: warning: excess elements in struct initializer
     .mask = 0x1,
             ^~~
   drivers//spi/spi-meson-spicc.c:543:10: note: (near initialization for 'meson_spicc_sel')
>> drivers//spi/spi-meson-spicc.c:544:3: error: 'struct clk_mux' has no member named 'shift'
     .shift = 24,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:544:11: warning: excess elements in struct initializer
     .shift = 24,
              ^~
   drivers//spi/spi-meson-spicc.c:544:11: note: (near initialization for 'meson_spicc_sel')
   drivers//spi/spi-meson-spicc.c: In function 'meson_spicc_clk_init':
>> drivers//spi/spi-meson-spicc.c:553:23: error: storage size of 'init' isn't known
     struct clk_init_data init;
                          ^~~~
>> drivers//spi/spi-meson-spicc.c:562:14: error: 'clk_fixed_factor_ops' undeclared (first use in this function); did you mean 'clk_fixed_factor'?
     init.ops = &clk_fixed_factor_ops;
                 ^~~~~~~~~~~~~~~~~~~~
                 clk_fixed_factor
   drivers//spi/spi-meson-spicc.c:562:14: note: each undeclared identifier is reported only once for each function it appears in
>> drivers//spi/spi-meson-spicc.c:564:20: error: implicit declaration of function '__clk_get_name'; did you mean 'clk_get_rate'? [-Werror=implicit-function-declaration]
     parent_names[0] = __clk_get_name(spicc->core);
                       ^~~~~~~~~~~~~~
                       clk_get_rate
>> drivers//spi/spi-meson-spicc.c:564:18: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
     parent_names[0] = __clk_get_name(spicc->core);
                     ^

vim +/meson_spicc_div0 +517 drivers//spi/spi-meson-spicc.c

   497	
   498	/*
   499	 * The Clock Mux
   500	 *            x-----------------x   x------------x    x------\
   501	 *        |---| 0) fixed factor |---| 1) old div |----|      |
   502	 *        |   x-----------------x   x------------x    |      |
   503	 * src ---|                                           |5) mux|-- out
   504	 *        |   x-----------------x   x------------x    |      |
   505	 *        |---| 2) fixed factor |---| 3) new div |0---|      |
   506	 *            x-----------------x   x------------x    x------/
   507	 *
   508	 * Clk path for GX series:
   509	 *    src -> 0 -> 1 -> out
   510	 *
   511	 * Clk path for AXG series:
   512	 *    src -> 0 -> 1 -> 5 -> out
   513	 *    src -> 2 -> 3 -> 5 -> out
   514	 */
   515	
   516	/* algorithm for div0 + div1: rate = freq / 4 / (2 ^ N) */
 > 517	static struct clk_fixed_factor meson_spicc_div0 = {
 > 518		.mult	= 1,
 > 519		.div	= 4,
   520	};
   521	
 > 522	static struct clk_divider meson_spicc_div1 = {
 > 523		.reg	= (void *) SPICC_CONREG,
 > 524		.shift	= 16,
 > 525		.width	= 3,
 > 526		.flags	= CLK_DIVIDER_POWER_OF_TWO,
   527	};
   528	
   529	/* algorithm for div2 + div3: rate = freq / 2 / (N + 1) */
 > 530	static struct clk_fixed_factor meson_spicc_div2 = {
 > 531		.mult	= 1,
   532		.div	= 2,
   533	};
   534	
 > 535	static struct clk_divider meson_spicc_div3 = {
   536		.reg	= (void *) SPICC_ENH_CTL0,
 > 537		.shift	= 16,
 > 538		.width	= 8,
   539	};
   540	
 > 541	static struct clk_mux meson_spicc_sel = {
 > 542		.reg	= (void *) SPICC_ENH_CTL0,
 > 543		.mask	= 0x1,
 > 544		.shift	= 24,
   545	};
   546	
   547	static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
   548	{
   549		struct device *dev = &spicc->pdev->dev;
   550		struct clk_fixed_factor *div0;
   551		struct clk_divider *div1;
   552		struct clk_mux *mux;
 > 553		struct clk_init_data init;
   554		struct clk *clk;
   555		const char *parent_names[1];
   556		const char *mux_parent_names[2];
   557		char name[32];
   558	
   559		div0 = &meson_spicc_div0;
   560		snprintf(name, sizeof(name), "%s#_div0", dev_name(dev));
   561		init.name = name;
 > 562		init.ops = &clk_fixed_factor_ops;
   563		init.flags = 0;
 > 564		parent_names[0] = __clk_get_name(spicc->core);
   565		init.parent_names = parent_names;
   566		init.num_parents = 1;
   567	
 > 568		div0->hw.init = &init;
   569	
 > 570		clk = devm_clk_register(dev, &div0->hw);
   571		if (WARN_ON(IS_ERR(clk)))
   572			return PTR_ERR(clk);
   573	
   574		div1 = &meson_spicc_div1;
   575		snprintf(name, sizeof(name), "%s#_div1", dev_name(dev));
   576		init.name = name;
 > 577		init.ops = &clk_divider_ops;
 > 578		init.flags = CLK_SET_RATE_PARENT;
   579		parent_names[0] = __clk_get_name(clk);
   580		init.parent_names = parent_names;
   581		init.num_parents = 1;
   582	
 > 583		div1->reg = spicc->base + (u64) div1->reg;
   584		div1->hw.init = &init;
   585	
   586		clk = devm_clk_register(dev, &div1->hw);
   587		if (WARN_ON(IS_ERR(clk)))
   588			return PTR_ERR(clk);
   589	
   590		if (spicc->data->has_enhance_clk_div == false) {
   591			spicc->clk = clk;
   592			return 0;
   593		}
   594	
   595		mux_parent_names[0] = __clk_get_name(clk);
   596	
   597		div0 = &meson_spicc_div2;
   598		snprintf(name, sizeof(name), "%s#_div2", dev_name(dev));
   599		init.name = name;
   600		init.ops = &clk_fixed_factor_ops;
   601		init.flags = 0;
 > 602		parent_names[0] = __clk_get_name(spicc->core);
   603		init.parent_names = parent_names;
   604		init.num_parents = 1;
   605	
   606		div0->hw.init = &init;
   607	
   608		clk = devm_clk_register(dev, &div0->hw);
   609		if (WARN_ON(IS_ERR(clk)))
   610			return PTR_ERR(clk);
   611	
   612		div1 = &meson_spicc_div3;
   613		snprintf(name, sizeof(name), "%s#_div3", dev_name(dev));
   614		init.name = name;
   615		init.ops = &clk_divider_ops;
   616		init.flags = CLK_SET_RATE_PARENT;
   617		parent_names[0] = __clk_get_name(clk);
   618		init.parent_names = parent_names;
   619		init.num_parents = 1;
   620	
   621		div1->reg = spicc->base + (u64) div1->reg;
   622		div1->hw.init = &init;
   623	
   624		clk = devm_clk_register(dev, &div1->hw);
   625		if (WARN_ON(IS_ERR(clk)))
   626			return PTR_ERR(clk);
   627	
 > 628		mux_parent_names[1] = __clk_get_name(clk);
   629	
   630		mux = &meson_spicc_sel;
   631		snprintf(name, sizeof(name), "%s#_sel", dev_name(dev));
   632		init.name = name;
 > 633		init.ops = &clk_mux_ops;
   634		init.parent_names = mux_parent_names;
   635		init.num_parents = 2;
 > 636		init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
   637	
 > 638		mux->reg = spicc->base + (u64) mux->reg;
   639		mux->hw.init = &init;
   640	
   641		spicc->clk = devm_clk_register(dev, &mux->hw);
   642		if (WARN_ON(IS_ERR(spicc->clk)))
   643			return PTR_ERR(spicc->clk);
   644	
   645		clk_set_parent(spicc->clk, clk);
   646		return 0;
   647	}
   648	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-04  2:22     ` kbuild test robot
  0 siblings, 0 replies; 34+ messages in thread
From: kbuild test robot @ 2018-05-04  2:22 UTC (permalink / raw)
  To: linus-amlogic

Hi Sunny,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on v4.17-rc3]
[also build test ERROR on next-20180503]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Yixun-Lan/spi-meson-axg-add-few-enhanced-features/20180504-083512
config: sparc64-allmodconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=sparc64 

All error/warnings (new ones prefixed by >>):

>> drivers//spi/spi-meson-spicc.c:517:15: error: variable 'meson_spicc_div0' has initializer but incomplete type
    static struct clk_fixed_factor meson_spicc_div0 = {
                  ^~~~~~~~~~~~~~~~
>> drivers//spi/spi-meson-spicc.c:518:3: error: 'struct clk_fixed_factor' has no member named 'mult'
     .mult = 1,
      ^~~~
>> drivers//spi/spi-meson-spicc.c:518:10: warning: excess elements in struct initializer
     .mult = 1,
             ^
   drivers//spi/spi-meson-spicc.c:518:10: note: (near initialization for 'meson_spicc_div0')
>> drivers//spi/spi-meson-spicc.c:519:3: error: 'struct clk_fixed_factor' has no member named 'div'
     .div = 4,
      ^~~
   drivers//spi/spi-meson-spicc.c:519:9: warning: excess elements in struct initializer
     .div = 4,
            ^
   drivers//spi/spi-meson-spicc.c:519:9: note: (near initialization for 'meson_spicc_div0')
>> drivers//spi/spi-meson-spicc.c:522:15: error: variable 'meson_spicc_div1' has initializer but incomplete type
    static struct clk_divider meson_spicc_div1 = {
                  ^~~~~~~~~~~
>> drivers//spi/spi-meson-spicc.c:523:3: error: 'struct clk_divider' has no member named 'reg'
     .reg = (void *) SPICC_CONREG,
      ^~~
   drivers//spi/spi-meson-spicc.c:523:9: warning: excess elements in struct initializer
     .reg = (void *) SPICC_CONREG,
            ^
   drivers//spi/spi-meson-spicc.c:523:9: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:524:3: error: 'struct clk_divider' has no member named 'shift'
     .shift = 16,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:524:11: warning: excess elements in struct initializer
     .shift = 16,
              ^~
   drivers//spi/spi-meson-spicc.c:524:11: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:525:3: error: 'struct clk_divider' has no member named 'width'
     .width = 3,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:525:11: warning: excess elements in struct initializer
     .width = 3,
              ^
   drivers//spi/spi-meson-spicc.c:525:11: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:526:3: error: 'struct clk_divider' has no member named 'flags'
     .flags = CLK_DIVIDER_POWER_OF_TWO,
      ^~~~~
>> drivers//spi/spi-meson-spicc.c:526:11: error: 'CLK_DIVIDER_POWER_OF_TWO' undeclared here (not in a function)
     .flags = CLK_DIVIDER_POWER_OF_TWO,
              ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers//spi/spi-meson-spicc.c:526:11: warning: excess elements in struct initializer
   drivers//spi/spi-meson-spicc.c:526:11: note: (near initialization for 'meson_spicc_div1')
>> drivers//spi/spi-meson-spicc.c:530:15: error: variable 'meson_spicc_div2' has initializer but incomplete type
    static struct clk_fixed_factor meson_spicc_div2 = {
                  ^~~~~~~~~~~~~~~~
   drivers//spi/spi-meson-spicc.c:531:3: error: 'struct clk_fixed_factor' has no member named 'mult'
     .mult = 1,
      ^~~~
   drivers//spi/spi-meson-spicc.c:531:10: warning: excess elements in struct initializer
     .mult = 1,
             ^
   drivers//spi/spi-meson-spicc.c:531:10: note: (near initialization for 'meson_spicc_div2')
   drivers//spi/spi-meson-spicc.c:532:3: error: 'struct clk_fixed_factor' has no member named 'div'
     .div = 2,
      ^~~
   drivers//spi/spi-meson-spicc.c:532:9: warning: excess elements in struct initializer
     .div = 2,
            ^
   drivers//spi/spi-meson-spicc.c:532:9: note: (near initialization for 'meson_spicc_div2')
>> drivers//spi/spi-meson-spicc.c:535:15: error: variable 'meson_spicc_div3' has initializer but incomplete type
    static struct clk_divider meson_spicc_div3 = {
                  ^~~~~~~~~~~
   drivers//spi/spi-meson-spicc.c:536:3: error: 'struct clk_divider' has no member named 'reg'
     .reg = (void *) SPICC_ENH_CTL0,
      ^~~
   drivers//spi/spi-meson-spicc.c:536:9: warning: excess elements in struct initializer
     .reg = (void *) SPICC_ENH_CTL0,
            ^
   drivers//spi/spi-meson-spicc.c:536:9: note: (near initialization for 'meson_spicc_div3')
   drivers//spi/spi-meson-spicc.c:537:3: error: 'struct clk_divider' has no member named 'shift'
     .shift = 16,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:537:11: warning: excess elements in struct initializer
     .shift = 16,
              ^~
   drivers//spi/spi-meson-spicc.c:537:11: note: (near initialization for 'meson_spicc_div3')
   drivers//spi/spi-meson-spicc.c:538:3: error: 'struct clk_divider' has no member named 'width'
     .width = 8,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:538:11: warning: excess elements in struct initializer
     .width = 8,
              ^
   drivers//spi/spi-meson-spicc.c:538:11: note: (near initialization for 'meson_spicc_div3')
>> drivers//spi/spi-meson-spicc.c:541:15: error: variable 'meson_spicc_sel' has initializer but incomplete type
    static struct clk_mux meson_spicc_sel = {
                  ^~~~~~~
>> drivers//spi/spi-meson-spicc.c:542:3: error: 'struct clk_mux' has no member named 'reg'
     .reg = (void *) SPICC_ENH_CTL0,
      ^~~
   drivers//spi/spi-meson-spicc.c:542:9: warning: excess elements in struct initializer
     .reg = (void *) SPICC_ENH_CTL0,
            ^
   drivers//spi/spi-meson-spicc.c:542:9: note: (near initialization for 'meson_spicc_sel')
>> drivers//spi/spi-meson-spicc.c:543:3: error: 'struct clk_mux' has no member named 'mask'
     .mask = 0x1,
      ^~~~
   drivers//spi/spi-meson-spicc.c:543:10: warning: excess elements in struct initializer
     .mask = 0x1,
             ^~~
   drivers//spi/spi-meson-spicc.c:543:10: note: (near initialization for 'meson_spicc_sel')
>> drivers//spi/spi-meson-spicc.c:544:3: error: 'struct clk_mux' has no member named 'shift'
     .shift = 24,
      ^~~~~
   drivers//spi/spi-meson-spicc.c:544:11: warning: excess elements in struct initializer
     .shift = 24,
              ^~
   drivers//spi/spi-meson-spicc.c:544:11: note: (near initialization for 'meson_spicc_sel')
   drivers//spi/spi-meson-spicc.c: In function 'meson_spicc_clk_init':
>> drivers//spi/spi-meson-spicc.c:553:23: error: storage size of 'init' isn't known
     struct clk_init_data init;
                          ^~~~
>> drivers//spi/spi-meson-spicc.c:562:14: error: 'clk_fixed_factor_ops' undeclared (first use in this function); did you mean 'clk_fixed_factor'?
     init.ops = &clk_fixed_factor_ops;
                 ^~~~~~~~~~~~~~~~~~~~
                 clk_fixed_factor
   drivers//spi/spi-meson-spicc.c:562:14: note: each undeclared identifier is reported only once for each function it appears in
>> drivers//spi/spi-meson-spicc.c:564:20: error: implicit declaration of function '__clk_get_name'; did you mean 'clk_get_rate'? [-Werror=implicit-function-declaration]
     parent_names[0] = __clk_get_name(spicc->core);
                       ^~~~~~~~~~~~~~
                       clk_get_rate
>> drivers//spi/spi-meson-spicc.c:564:18: warning: assignment makes pointer from integer without a cast [-Wint-conversion]
     parent_names[0] = __clk_get_name(spicc->core);
                     ^

vim +/meson_spicc_div0 +517 drivers//spi/spi-meson-spicc.c

   497	
   498	/*
   499	 * The Clock Mux
   500	 *            x-----------------x   x------------x    x------\
   501	 *        |---| 0) fixed factor |---| 1) old div |----|      |
   502	 *        |   x-----------------x   x------------x    |      |
   503	 * src ---|                                           |5) mux|-- out
   504	 *        |   x-----------------x   x------------x    |      |
   505	 *        |---| 2) fixed factor |---| 3) new div |0---|      |
   506	 *            x-----------------x   x------------x    x------/
   507	 *
   508	 * Clk path for GX series:
   509	 *    src -> 0 -> 1 -> out
   510	 *
   511	 * Clk path for AXG series:
   512	 *    src -> 0 -> 1 -> 5 -> out
   513	 *    src -> 2 -> 3 -> 5 -> out
   514	 */
   515	
   516	/* algorithm for div0 + div1: rate = freq / 4 / (2 ^ N) */
 > 517	static struct clk_fixed_factor meson_spicc_div0 = {
 > 518		.mult	= 1,
 > 519		.div	= 4,
   520	};
   521	
 > 522	static struct clk_divider meson_spicc_div1 = {
 > 523		.reg	= (void *) SPICC_CONREG,
 > 524		.shift	= 16,
 > 525		.width	= 3,
 > 526		.flags	= CLK_DIVIDER_POWER_OF_TWO,
   527	};
   528	
   529	/* algorithm for div2 + div3: rate = freq / 2 / (N + 1) */
 > 530	static struct clk_fixed_factor meson_spicc_div2 = {
 > 531		.mult	= 1,
   532		.div	= 2,
   533	};
   534	
 > 535	static struct clk_divider meson_spicc_div3 = {
   536		.reg	= (void *) SPICC_ENH_CTL0,
 > 537		.shift	= 16,
 > 538		.width	= 8,
   539	};
   540	
 > 541	static struct clk_mux meson_spicc_sel = {
 > 542		.reg	= (void *) SPICC_ENH_CTL0,
 > 543		.mask	= 0x1,
 > 544		.shift	= 24,
   545	};
   546	
   547	static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
   548	{
   549		struct device *dev = &spicc->pdev->dev;
   550		struct clk_fixed_factor *div0;
   551		struct clk_divider *div1;
   552		struct clk_mux *mux;
 > 553		struct clk_init_data init;
   554		struct clk *clk;
   555		const char *parent_names[1];
   556		const char *mux_parent_names[2];
   557		char name[32];
   558	
   559		div0 = &meson_spicc_div0;
   560		snprintf(name, sizeof(name), "%s#_div0", dev_name(dev));
   561		init.name = name;
 > 562		init.ops = &clk_fixed_factor_ops;
   563		init.flags = 0;
 > 564		parent_names[0] = __clk_get_name(spicc->core);
   565		init.parent_names = parent_names;
   566		init.num_parents = 1;
   567	
 > 568		div0->hw.init = &init;
   569	
 > 570		clk = devm_clk_register(dev, &div0->hw);
   571		if (WARN_ON(IS_ERR(clk)))
   572			return PTR_ERR(clk);
   573	
   574		div1 = &meson_spicc_div1;
   575		snprintf(name, sizeof(name), "%s#_div1", dev_name(dev));
   576		init.name = name;
 > 577		init.ops = &clk_divider_ops;
 > 578		init.flags = CLK_SET_RATE_PARENT;
   579		parent_names[0] = __clk_get_name(clk);
   580		init.parent_names = parent_names;
   581		init.num_parents = 1;
   582	
 > 583		div1->reg = spicc->base + (u64) div1->reg;
   584		div1->hw.init = &init;
   585	
   586		clk = devm_clk_register(dev, &div1->hw);
   587		if (WARN_ON(IS_ERR(clk)))
   588			return PTR_ERR(clk);
   589	
   590		if (spicc->data->has_enhance_clk_div == false) {
   591			spicc->clk = clk;
   592			return 0;
   593		}
   594	
   595		mux_parent_names[0] = __clk_get_name(clk);
   596	
   597		div0 = &meson_spicc_div2;
   598		snprintf(name, sizeof(name), "%s#_div2", dev_name(dev));
   599		init.name = name;
   600		init.ops = &clk_fixed_factor_ops;
   601		init.flags = 0;
 > 602		parent_names[0] = __clk_get_name(spicc->core);
   603		init.parent_names = parent_names;
   604		init.num_parents = 1;
   605	
   606		div0->hw.init = &init;
   607	
   608		clk = devm_clk_register(dev, &div0->hw);
   609		if (WARN_ON(IS_ERR(clk)))
   610			return PTR_ERR(clk);
   611	
   612		div1 = &meson_spicc_div3;
   613		snprintf(name, sizeof(name), "%s#_div3", dev_name(dev));
   614		init.name = name;
   615		init.ops = &clk_divider_ops;
   616		init.flags = CLK_SET_RATE_PARENT;
   617		parent_names[0] = __clk_get_name(clk);
   618		init.parent_names = parent_names;
   619		init.num_parents = 1;
   620	
   621		div1->reg = spicc->base + (u64) div1->reg;
   622		div1->hw.init = &init;
   623	
   624		clk = devm_clk_register(dev, &div1->hw);
   625		if (WARN_ON(IS_ERR(clk)))
   626			return PTR_ERR(clk);
   627	
 > 628		mux_parent_names[1] = __clk_get_name(clk);
   629	
   630		mux = &meson_spicc_sel;
   631		snprintf(name, sizeof(name), "%s#_sel", dev_name(dev));
   632		init.name = name;
 > 633		init.ops = &clk_mux_ops;
   634		init.parent_names = mux_parent_names;
   635		init.num_parents = 2;
 > 636		init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
   637	
 > 638		mux->reg = spicc->base + (u64) mux->reg;
   639		mux->hw.init = &init;
   640	
   641		spicc->clk = devm_clk_register(dev, &mux->hw);
   642		if (WARN_ON(IS_ERR(spicc->clk)))
   643			return PTR_ERR(spicc->clk);
   644	
   645		clk_set_parent(spicc->clk, clk);
   646		return 0;
   647	}
   648	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH 3/3] spi: meson-axg: add a linear clock divider support
  2018-05-03 21:36   ` Yixun Lan
  (?)
@ 2018-05-04  2:46     ` kbuild test robot
  -1 siblings, 0 replies; 34+ messages in thread
From: kbuild test robot @ 2018-05-04  2:46 UTC (permalink / raw)
  To: Yixun Lan
  Cc: kbuild-all, Mark Brown, Sunny Luo, Yixun Lan, Neil Armstrong,
	Jerome Brunet, Kevin Hilman, Carlo Caione, linux-spi,
	linux-amlogic, linux-arm-kernel, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 4956 bytes --]

Hi Sunny,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on v4.17-rc3]
[also build test WARNING on next-20180503]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Yixun-Lan/spi-meson-axg-add-few-enhanced-features/20180504-083512
config: xtensa-allmodconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=xtensa 

All warnings (new ones prefixed by >>):

   drivers/spi/spi-meson-spicc.c: In function 'meson_spicc_clk_init':
>> drivers/spi/spi-meson-spicc.c:583:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
     div1->reg = spicc->base + (u64) div1->reg;
                               ^
   drivers/spi/spi-meson-spicc.c:621:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
     div1->reg = spicc->base + (u64) div1->reg;
                               ^
   drivers/spi/spi-meson-spicc.c:638:27: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
     mux->reg = spicc->base + (u64) mux->reg;
                              ^

vim +583 drivers/spi/spi-meson-spicc.c

   546	
   547	static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
   548	{
   549		struct device *dev = &spicc->pdev->dev;
   550		struct clk_fixed_factor *div0;
   551		struct clk_divider *div1;
   552		struct clk_mux *mux;
   553		struct clk_init_data init;
   554		struct clk *clk;
   555		const char *parent_names[1];
   556		const char *mux_parent_names[2];
   557		char name[32];
   558	
   559		div0 = &meson_spicc_div0;
   560		snprintf(name, sizeof(name), "%s#_div0", dev_name(dev));
   561		init.name = name;
   562		init.ops = &clk_fixed_factor_ops;
   563		init.flags = 0;
   564		parent_names[0] = __clk_get_name(spicc->core);
   565		init.parent_names = parent_names;
   566		init.num_parents = 1;
   567	
   568		div0->hw.init = &init;
   569	
   570		clk = devm_clk_register(dev, &div0->hw);
   571		if (WARN_ON(IS_ERR(clk)))
   572			return PTR_ERR(clk);
   573	
   574		div1 = &meson_spicc_div1;
   575		snprintf(name, sizeof(name), "%s#_div1", dev_name(dev));
   576		init.name = name;
   577		init.ops = &clk_divider_ops;
   578		init.flags = CLK_SET_RATE_PARENT;
   579		parent_names[0] = __clk_get_name(clk);
   580		init.parent_names = parent_names;
   581		init.num_parents = 1;
   582	
 > 583		div1->reg = spicc->base + (u64) div1->reg;
   584		div1->hw.init = &init;
   585	
   586		clk = devm_clk_register(dev, &div1->hw);
   587		if (WARN_ON(IS_ERR(clk)))
   588			return PTR_ERR(clk);
   589	
   590		if (spicc->data->has_enhance_clk_div == false) {
   591			spicc->clk = clk;
   592			return 0;
   593		}
   594	
   595		mux_parent_names[0] = __clk_get_name(clk);
   596	
   597		div0 = &meson_spicc_div2;
   598		snprintf(name, sizeof(name), "%s#_div2", dev_name(dev));
   599		init.name = name;
   600		init.ops = &clk_fixed_factor_ops;
   601		init.flags = 0;
   602		parent_names[0] = __clk_get_name(spicc->core);
   603		init.parent_names = parent_names;
   604		init.num_parents = 1;
   605	
   606		div0->hw.init = &init;
   607	
   608		clk = devm_clk_register(dev, &div0->hw);
   609		if (WARN_ON(IS_ERR(clk)))
   610			return PTR_ERR(clk);
   611	
   612		div1 = &meson_spicc_div3;
   613		snprintf(name, sizeof(name), "%s#_div3", dev_name(dev));
   614		init.name = name;
   615		init.ops = &clk_divider_ops;
   616		init.flags = CLK_SET_RATE_PARENT;
   617		parent_names[0] = __clk_get_name(clk);
   618		init.parent_names = parent_names;
   619		init.num_parents = 1;
   620	
   621		div1->reg = spicc->base + (u64) div1->reg;
   622		div1->hw.init = &init;
   623	
   624		clk = devm_clk_register(dev, &div1->hw);
   625		if (WARN_ON(IS_ERR(clk)))
   626			return PTR_ERR(clk);
   627	
   628		mux_parent_names[1] = __clk_get_name(clk);
   629	
   630		mux = &meson_spicc_sel;
   631		snprintf(name, sizeof(name), "%s#_sel", dev_name(dev));
   632		init.name = name;
   633		init.ops = &clk_mux_ops;
   634		init.parent_names = mux_parent_names;
   635		init.num_parents = 2;
   636		init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
   637	
   638		mux->reg = spicc->base + (u64) mux->reg;
   639		mux->hw.init = &init;
   640	
   641		spicc->clk = devm_clk_register(dev, &mux->hw);
   642		if (WARN_ON(IS_ERR(spicc->clk)))
   643			return PTR_ERR(spicc->clk);
   644	
   645		clk_set_parent(spicc->clk, clk);
   646		return 0;
   647	}
   648	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 52913 bytes --]

^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-04  2:46     ` kbuild test robot
  0 siblings, 0 replies; 34+ messages in thread
From: kbuild test robot @ 2018-05-04  2:46 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Sunny,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on v4.17-rc3]
[also build test WARNING on next-20180503]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Yixun-Lan/spi-meson-axg-add-few-enhanced-features/20180504-083512
config: xtensa-allmodconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=xtensa 

All warnings (new ones prefixed by >>):

   drivers/spi/spi-meson-spicc.c: In function 'meson_spicc_clk_init':
>> drivers/spi/spi-meson-spicc.c:583:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
     div1->reg = spicc->base + (u64) div1->reg;
                               ^
   drivers/spi/spi-meson-spicc.c:621:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
     div1->reg = spicc->base + (u64) div1->reg;
                               ^
   drivers/spi/spi-meson-spicc.c:638:27: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
     mux->reg = spicc->base + (u64) mux->reg;
                              ^

vim +583 drivers/spi/spi-meson-spicc.c

   546	
   547	static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
   548	{
   549		struct device *dev = &spicc->pdev->dev;
   550		struct clk_fixed_factor *div0;
   551		struct clk_divider *div1;
   552		struct clk_mux *mux;
   553		struct clk_init_data init;
   554		struct clk *clk;
   555		const char *parent_names[1];
   556		const char *mux_parent_names[2];
   557		char name[32];
   558	
   559		div0 = &meson_spicc_div0;
   560		snprintf(name, sizeof(name), "%s#_div0", dev_name(dev));
   561		init.name = name;
   562		init.ops = &clk_fixed_factor_ops;
   563		init.flags = 0;
   564		parent_names[0] = __clk_get_name(spicc->core);
   565		init.parent_names = parent_names;
   566		init.num_parents = 1;
   567	
   568		div0->hw.init = &init;
   569	
   570		clk = devm_clk_register(dev, &div0->hw);
   571		if (WARN_ON(IS_ERR(clk)))
   572			return PTR_ERR(clk);
   573	
   574		div1 = &meson_spicc_div1;
   575		snprintf(name, sizeof(name), "%s#_div1", dev_name(dev));
   576		init.name = name;
   577		init.ops = &clk_divider_ops;
   578		init.flags = CLK_SET_RATE_PARENT;
   579		parent_names[0] = __clk_get_name(clk);
   580		init.parent_names = parent_names;
   581		init.num_parents = 1;
   582	
 > 583		div1->reg = spicc->base + (u64) div1->reg;
   584		div1->hw.init = &init;
   585	
   586		clk = devm_clk_register(dev, &div1->hw);
   587		if (WARN_ON(IS_ERR(clk)))
   588			return PTR_ERR(clk);
   589	
   590		if (spicc->data->has_enhance_clk_div == false) {
   591			spicc->clk = clk;
   592			return 0;
   593		}
   594	
   595		mux_parent_names[0] = __clk_get_name(clk);
   596	
   597		div0 = &meson_spicc_div2;
   598		snprintf(name, sizeof(name), "%s#_div2", dev_name(dev));
   599		init.name = name;
   600		init.ops = &clk_fixed_factor_ops;
   601		init.flags = 0;
   602		parent_names[0] = __clk_get_name(spicc->core);
   603		init.parent_names = parent_names;
   604		init.num_parents = 1;
   605	
   606		div0->hw.init = &init;
   607	
   608		clk = devm_clk_register(dev, &div0->hw);
   609		if (WARN_ON(IS_ERR(clk)))
   610			return PTR_ERR(clk);
   611	
   612		div1 = &meson_spicc_div3;
   613		snprintf(name, sizeof(name), "%s#_div3", dev_name(dev));
   614		init.name = name;
   615		init.ops = &clk_divider_ops;
   616		init.flags = CLK_SET_RATE_PARENT;
   617		parent_names[0] = __clk_get_name(clk);
   618		init.parent_names = parent_names;
   619		init.num_parents = 1;
   620	
   621		div1->reg = spicc->base + (u64) div1->reg;
   622		div1->hw.init = &init;
   623	
   624		clk = devm_clk_register(dev, &div1->hw);
   625		if (WARN_ON(IS_ERR(clk)))
   626			return PTR_ERR(clk);
   627	
   628		mux_parent_names[1] = __clk_get_name(clk);
   629	
   630		mux = &meson_spicc_sel;
   631		snprintf(name, sizeof(name), "%s#_sel", dev_name(dev));
   632		init.name = name;
   633		init.ops = &clk_mux_ops;
   634		init.parent_names = mux_parent_names;
   635		init.num_parents = 2;
   636		init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
   637	
   638		mux->reg = spicc->base + (u64) mux->reg;
   639		mux->hw.init = &init;
   640	
   641		spicc->clk = devm_clk_register(dev, &mux->hw);
   642		if (WARN_ON(IS_ERR(spicc->clk)))
   643			return PTR_ERR(spicc->clk);
   644	
   645		clk_set_parent(spicc->clk, clk);
   646		return 0;
   647	}
   648	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 3/3] spi: meson-axg: add a linear clock divider support
@ 2018-05-04  2:46     ` kbuild test robot
  0 siblings, 0 replies; 34+ messages in thread
From: kbuild test robot @ 2018-05-04  2:46 UTC (permalink / raw)
  To: linus-amlogic

Hi Sunny,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on v4.17-rc3]
[also build test WARNING on next-20180503]
[cannot apply to spi/for-next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Yixun-Lan/spi-meson-axg-add-few-enhanced-features/20180504-083512
config: xtensa-allmodconfig (attached as .config)
compiler: xtensa-linux-gcc (GCC) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=xtensa 

All warnings (new ones prefixed by >>):

   drivers/spi/spi-meson-spicc.c: In function 'meson_spicc_clk_init':
>> drivers/spi/spi-meson-spicc.c:583:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
     div1->reg = spicc->base + (u64) div1->reg;
                               ^
   drivers/spi/spi-meson-spicc.c:621:28: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
     div1->reg = spicc->base + (u64) div1->reg;
                               ^
   drivers/spi/spi-meson-spicc.c:638:27: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
     mux->reg = spicc->base + (u64) mux->reg;
                              ^

vim +583 drivers/spi/spi-meson-spicc.c

   546	
   547	static int meson_spicc_clk_init(struct meson_spicc_device *spicc)
   548	{
   549		struct device *dev = &spicc->pdev->dev;
   550		struct clk_fixed_factor *div0;
   551		struct clk_divider *div1;
   552		struct clk_mux *mux;
   553		struct clk_init_data init;
   554		struct clk *clk;
   555		const char *parent_names[1];
   556		const char *mux_parent_names[2];
   557		char name[32];
   558	
   559		div0 = &meson_spicc_div0;
   560		snprintf(name, sizeof(name), "%s#_div0", dev_name(dev));
   561		init.name = name;
   562		init.ops = &clk_fixed_factor_ops;
   563		init.flags = 0;
   564		parent_names[0] = __clk_get_name(spicc->core);
   565		init.parent_names = parent_names;
   566		init.num_parents = 1;
   567	
   568		div0->hw.init = &init;
   569	
   570		clk = devm_clk_register(dev, &div0->hw);
   571		if (WARN_ON(IS_ERR(clk)))
   572			return PTR_ERR(clk);
   573	
   574		div1 = &meson_spicc_div1;
   575		snprintf(name, sizeof(name), "%s#_div1", dev_name(dev));
   576		init.name = name;
   577		init.ops = &clk_divider_ops;
   578		init.flags = CLK_SET_RATE_PARENT;
   579		parent_names[0] = __clk_get_name(clk);
   580		init.parent_names = parent_names;
   581		init.num_parents = 1;
   582	
 > 583		div1->reg = spicc->base + (u64) div1->reg;
   584		div1->hw.init = &init;
   585	
   586		clk = devm_clk_register(dev, &div1->hw);
   587		if (WARN_ON(IS_ERR(clk)))
   588			return PTR_ERR(clk);
   589	
   590		if (spicc->data->has_enhance_clk_div == false) {
   591			spicc->clk = clk;
   592			return 0;
   593		}
   594	
   595		mux_parent_names[0] = __clk_get_name(clk);
   596	
   597		div0 = &meson_spicc_div2;
   598		snprintf(name, sizeof(name), "%s#_div2", dev_name(dev));
   599		init.name = name;
   600		init.ops = &clk_fixed_factor_ops;
   601		init.flags = 0;
   602		parent_names[0] = __clk_get_name(spicc->core);
   603		init.parent_names = parent_names;
   604		init.num_parents = 1;
   605	
   606		div0->hw.init = &init;
   607	
   608		clk = devm_clk_register(dev, &div0->hw);
   609		if (WARN_ON(IS_ERR(clk)))
   610			return PTR_ERR(clk);
   611	
   612		div1 = &meson_spicc_div3;
   613		snprintf(name, sizeof(name), "%s#_div3", dev_name(dev));
   614		init.name = name;
   615		init.ops = &clk_divider_ops;
   616		init.flags = CLK_SET_RATE_PARENT;
   617		parent_names[0] = __clk_get_name(clk);
   618		init.parent_names = parent_names;
   619		init.num_parents = 1;
   620	
   621		div1->reg = spicc->base + (u64) div1->reg;
   622		div1->hw.init = &init;
   623	
   624		clk = devm_clk_register(dev, &div1->hw);
   625		if (WARN_ON(IS_ERR(clk)))
   626			return PTR_ERR(clk);
   627	
   628		mux_parent_names[1] = __clk_get_name(clk);
   629	
   630		mux = &meson_spicc_sel;
   631		snprintf(name, sizeof(name), "%s#_sel", dev_name(dev));
   632		init.name = name;
   633		init.ops = &clk_mux_ops;
   634		init.parent_names = mux_parent_names;
   635		init.num_parents = 2;
   636		init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
   637	
   638		mux->reg = spicc->base + (u64) mux->reg;
   639		mux->hw.init = &init;
   640	
   641		spicc->clk = devm_clk_register(dev, &mux->hw);
   642		if (WARN_ON(IS_ERR(spicc->clk)))
   643			return PTR_ERR(spicc->clk);
   644	
   645		clk_set_parent(spicc->clk, clk);
   646		return 0;
   647	}
   648	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* Re: [PATCH 1/3] spi: meson-axg: support MAX 80M clock
  2018-05-04  1:56       ` Yixun Lan
  (?)
@ 2018-05-05  0:58         ` Mark Brown
  -1 siblings, 0 replies; 34+ messages in thread
From: Mark Brown @ 2018-05-05  0:58 UTC (permalink / raw)
  To: Yixun Lan
  Cc: Sunny Luo, Neil Armstrong, Jerome Brunet, Kevin Hilman,
	Carlo Caione, linux-spi, linux-amlogic, linux-arm-kernel,
	linux-kernel

[-- Attachment #1: Type: text/plain, Size: 262 bytes --]

On Fri, May 04, 2018 at 09:56:10AM +0800, Yixun Lan wrote:

> Here I only introduce the dt compatible data to differentiate the
> old/new controller, the compatible name is not changed, and none of the
> property is introduced.

Right, sorry - this bit is fine.

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 1/3] spi: meson-axg: support MAX 80M clock
@ 2018-05-05  0:58         ` Mark Brown
  0 siblings, 0 replies; 34+ messages in thread
From: Mark Brown @ 2018-05-05  0:58 UTC (permalink / raw)
  To: linux-arm-kernel

On Fri, May 04, 2018 at 09:56:10AM +0800, Yixun Lan wrote:

> Here I only introduce the dt compatible data to differentiate the
> old/new controller, the compatible name is not changed, and none of the
> property is introduced.

Right, sorry - this bit is fine.
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^ permalink raw reply	[flat|nested] 34+ messages in thread
* [PATCH 1/3] spi: meson-axg: support MAX 80M clock
@ 2018-05-05  0:58         ` Mark Brown
  0 siblings, 0 replies; 34+ messages in thread
From: Mark Brown @ 2018-05-05  0:58 UTC (permalink / raw)
  To: linus-amlogic

On Fri, May 04, 2018 at 09:56:10AM +0800, Yixun Lan wrote:

> Here I only introduce the dt compatible data to differentiate the
> old/new controller, the compatible name is not changed, and none of the
> property is introduced.

Right, sorry - this bit is fine.
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^ permalink raw reply	[flat|nested] 34+ messages in thread
end of thread, other threads:[~2018-05-05  0:59 UTC | newest]

Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-03 21:36 [PATCH 0/3] spi: meson-axg: add few enhanced features Yixun Lan
2018-05-03 21:36 ` Yixun Lan
2018-05-03 21:36 ` Yixun Lan
2018-05-03 21:36 ` [PATCH 1/3] spi: meson-axg: support MAX 80M clock Yixun Lan
2018-05-03 21:36   ` Yixun Lan
2018-05-03 21:36   ` Yixun Lan
2018-05-03 23:13   ` Mark Brown
2018-05-03 23:13     ` Mark Brown
2018-05-03 23:13     ` Mark Brown
2018-05-04  1:56     ` Yixun Lan
2018-05-04  1:56       ` Yixun Lan
2018-05-04  1:56       ` Yixun Lan
2018-05-05  0:58       ` Mark Brown
2018-05-05  0:58         ` Mark Brown
2018-05-05  0:58         ` Mark Brown
2018-05-03 21:36 ` [PATCH 2/3] spi: meson-axg: enhance output enable feature Yixun Lan
2018-05-03 21:36   ` Yixun Lan
2018-05-03 21:36   ` Yixun Lan
2018-05-03 21:36 ` [PATCH 3/3] spi: meson-axg: add a linear clock divider support Yixun Lan
2018-05-03 21:36   ` Yixun Lan
2018-05-03 21:36   ` Yixun Lan
2018-05-03 23:16   ` Mark Brown
2018-05-03 23:16     ` Mark Brown
2018-05-03 23:16     ` Mark Brown
2018-05-04  2:07     ` Yixun Lan
2018-05-04  2:07       ` Yixun Lan
2018-05-04  2:07       ` Yixun Lan
2018-05-04  2:07       ` Yixun Lan
2018-05-04  2:22   ` kbuild test robot
2018-05-04  2:22     ` kbuild test robot
2018-05-04  2:22     ` kbuild test robot
2018-05-04  2:46   ` kbuild test robot
2018-05-04  2:46     ` kbuild test robot
2018-05-04  2:46     ` kbuild test robot

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