* [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
@ 2018-05-09 21:54 Dhinakaran Pandiyan
2018-05-09 23:10 ` ✓ Fi.CI.BAT: success for " Patchwork
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-09 21:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
By moving the check from psr_compute_config() to psr_init_dpcd(), we get
to set the dev_priv->psr.sink_support flag only when the panel is
capable of changing power state. An additional benefit is that the check
will be performed only at init time instead of every atomic_check.
This should change the psr_basic IGT failures on HSW to skips.
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
drivers/gpu/drm/i915/intel_psr.c | 12 +++++-------
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..f1747dff9ca3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
- intel_psr_init_dpcd(intel_dp);
-
/*
* Read the eDP display control registers.
*
@@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
intel_dp->edp_dpcd);
+ /*
+ * This has to be called after initializing intel_dp->edp_dpcd, PSR
+ * checks for the SET_POWER_CAPABLE bit.
+ */
+ intel_psr_init_dpcd(intel_dp);
+
/* Read the eDP 1.4+ supported link rates. */
if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2faa1de..9e6534d57479 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -251,8 +251,11 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
sizeof(intel_dp->psr_dpcd));
if (intel_dp->psr_dpcd[0]) {
- dev_priv->psr.sink_support = true;
- DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
+ DRM_DEBUG_KMS("Detected EDP PSR panel\n");
+ if (intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)
+ dev_priv->psr.sink_support = true;
+ else
+ DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
}
if (INTEL_GEN(dev_priv) >= 9 &&
@@ -640,11 +643,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
- DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n");
- return;
- }
-
crtc_state->has_psr = true;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
2018-05-09 21:54 [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
@ 2018-05-09 23:10 ` Patchwork
2018-05-09 23:58 ` [PATCH] " Souza, Jose
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-05-09 23:10 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
URL : https://patchwork.freedesktop.org/series/42971/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8966 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42971/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_8966 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-cnl-psr: PASS -> FAIL (fdo#100368, fdo#103928)
igt@kms_frontbuffer_tracking@basic:
{fi-hsw-peppy}: PASS -> DMESG-FAIL (fdo#102614, fdo#106103)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
==== Possible fixes ====
igt@drv_module_reload@basic-reload-inject:
fi-glk-j4005: DMESG-WARN (fdo#106248) -> PASS
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-hsw-4770r: FAIL (fdo#100368) -> PASS
igt@kms_psr_sink_crc@psr_basic:
fi-hsw-4200u: FAIL (fdo#106217, fdo#106346) -> SKIP
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
fdo#106217 https://bugs.freedesktop.org/show_bug.cgi?id=106217
fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
fdo#106346 https://bugs.freedesktop.org/show_bug.cgi?id=106346
== Participating hosts (41 -> 37) ==
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4163 -> Patchwork_8966
CI_DRM_4163: 8e1dab6e913be7d014eb9bc355ec65b6b56dcd56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4468: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8966: a31dc6baa24c65225c8f09d05a4823ea6cd9aa40 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4468: 1e60f1499e5b71b6d5a747189d7c28f57359a87f @ git://anongit.freedesktop.org/piglit
== Linux commits ==
a31dc6baa24c drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8966/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
2018-05-09 21:54 [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
2018-05-09 23:10 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-05-09 23:58 ` Souza, Jose
2018-05-10 0:25 ` [PATCH v2] " Dhinakaran Pandiyan
2018-05-10 1:02 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2) Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Souza, Jose @ 2018-05-09 23:58 UTC (permalink / raw)
To: intel-gfx, Pandiyan, Dhinakaran; +Cc: Vivi, Rodrigo
On Wed, 2018-05-09 at 14:54 -0700, Dhinakaran Pandiyan wrote:
> By moving the check from psr_compute_config() to psr_init_dpcd(), we
> get
> to set the dev_priv->psr.sink_support flag only when the panel is
> capable of changing power state. An additional benefit is that the
> check
> will be performed only at init time instead of every atomic_check.
>
> This should change the psr_basic IGT failures on HSW to skips.
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_psr.c | 12 +++++-------
> 2 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..f1747dff9ca3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
> dev_priv->no_aux_handshake = intel_dp-
> >dpcd[DP_MAX_DOWNSPREAD] &
> DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
>
> - intel_psr_init_dpcd(intel_dp);
> -
> /*
> * Read the eDP display control registers.
> *
> @@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
> DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int)
> sizeof(intel_dp->edp_dpcd),
> intel_dp->edp_dpcd);
>
> + /*
> + * This has to be called after initializing intel_dp-
> >edp_dpcd, PSR
> + * checks for the SET_POWER_CAPABLE bit.
> + */
> + intel_psr_init_dpcd(intel_dp);
> +
> /* Read the eDP 1.4+ supported link rates. */
> if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2faa1de..9e6534d57479 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -251,8 +251,11 @@ void intel_psr_init_dpcd(struct intel_dp
> *intel_dp)
> sizeof(intel_dp->psr_dpcd));
>
> if (intel_dp->psr_dpcd[0]) {
> - dev_priv->psr.sink_support = true;
> - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
> + DRM_DEBUG_KMS("Detected EDP PSR panel\n");
> + if (intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)
> + dev_priv->psr.sink_support = true;
> + else
> + DRM_DEBUG_KMS("Panel lacks power state
> control, PSR cannot be enabled\n");
'return' is missing here, to avoid any attempt to detect PSR2. It will
save some DPCD reads also avoid being in a state where
sink_psr2_support=true and psr.sink_support=false.
Adding that:
Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
Nice catch :D
> }
>
> if (INTEL_GEN(dev_priv) >= 9 &&
> @@ -640,11 +643,6 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> return;
> }
>
> - if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
> - DRM_DEBUG_KMS("PSR condition failed: panel lacks
> power state control\n");
> - return;
> - }
> -
> crtc_state->has_psr = true;
> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> crtc_state);
> DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2"
> : "");
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
2018-05-09 23:58 ` [PATCH] " Souza, Jose
@ 2018-05-10 0:25 ` Dhinakaran Pandiyan
0 siblings, 0 replies; 9+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-10 0:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan, Rodrigo Vivi
By moving the check from psr_compute_config() to psr_init_dpcd(), we get
to set the dev_priv->psr.sink_support flag only when the panel is
capable of changing power state. An additional benefit is that the check
will be performed only at init time instead of every atomic_check.
This should change the psr_basic IGT failures on HSW to skips.
v2: Return early when SET_POWER_CAPABLE bit is 0 (Jose)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
drivers/gpu/drm/i915/intel_psr.c | 12 ++++++------
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..f1747dff9ca3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
- intel_psr_init_dpcd(intel_dp);
-
/*
* Read the eDP display control registers.
*
@@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
intel_dp->edp_dpcd);
+ /*
+ * This has to be called after initializing intel_dp->edp_dpcd, PSR
+ * checks for the SET_POWER_CAPABLE bit.
+ */
+ intel_psr_init_dpcd(intel_dp);
+
/* Read the eDP 1.4+ supported link rates. */
if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index db27f2faa1de..7e52e2ea1624 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -251,8 +251,13 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
sizeof(intel_dp->psr_dpcd));
if (intel_dp->psr_dpcd[0]) {
+ DRM_DEBUG_KMS("Detected EDP PSR panel\n");
+
+ if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
+ DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
+ return;
+ }
dev_priv->psr.sink_support = true;
- DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
}
if (INTEL_GEN(dev_priv) >= 9 &&
@@ -640,11 +645,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
- DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n");
- return;
- }
-
crtc_state->has_psr = true;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2)
2018-05-09 21:54 [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
2018-05-09 23:10 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-05-09 23:58 ` [PATCH] " Souza, Jose
@ 2018-05-10 1:02 ` Patchwork
2018-05-10 2:38 ` ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-05-10 1:02 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2)
URL : https://patchwork.freedesktop.org/series/42971/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163 -> Patchwork_8968 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42971/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_8968 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@read-crc-pipe-c:
fi-cnl-y3: PASS -> INCOMPLETE (fdo#105086)
==== Possible fixes ====
igt@drv_module_reload@basic-reload-inject:
fi-glk-j4005: DMESG-WARN (fdo#106248) -> PASS
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-hsw-4770r: FAIL (fdo#100368) -> PASS
igt@kms_psr_sink_crc@psr_basic:
fi-hsw-4200u: FAIL (fdo#106346, fdo#106217) -> SKIP
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086
fdo#106217 https://bugs.freedesktop.org/show_bug.cgi?id=106217
fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248
fdo#106346 https://bugs.freedesktop.org/show_bug.cgi?id=106346
== Participating hosts (41 -> 37) ==
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4163 -> Patchwork_8968
CI_DRM_4163: 8e1dab6e913be7d014eb9bc355ec65b6b56dcd56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4468: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8968: 45ebe900d240cdecc703ba951d13562fa1fc6cca @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4468: 1e60f1499e5b71b6d5a747189d7c28f57359a87f @ git://anongit.freedesktop.org/piglit
== Linux commits ==
45ebe900d240 drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8968/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
2018-05-09 21:54 [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
` (2 preceding siblings ...)
2018-05-10 1:02 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2) Patchwork
@ 2018-05-10 2:38 ` Patchwork
2018-05-10 3:56 ` ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2) Patchwork
2018-05-11 12:24 ` [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Ville Syrjälä
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-05-10 2:38 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
URL : https://patchwork.freedesktop.org/series/42971/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8966_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8966_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8966_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42971/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8966_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: SKIP -> PASS +2
igt@kms_force_connector_basic@force-connector-state:
shard-snb: PASS -> SKIP
igt@kms_properties@plane-properties-legacy:
shard-snb: SKIP -> PASS +4
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_8966_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@blocking-absolute-wf_vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#106134)
igt@kms_flip@plain-flip-ts-check-interruptible:
shard-glk: PASS -> FAIL (fdo#100368) +2
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
shard-apl: PASS -> FAIL (fdo#104724, fdo#103167) +1
igt@kms_vblank@pipe-a-accuracy-idle:
shard-kbl: PASS -> FAIL (fdo#102583)
==== Possible fixes ====
igt@kms_flip@absolute-wf_vblank-interruptible:
shard-glk: FAIL (fdo#106087) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-apl: FAIL (fdo#102887, fdo#105363) -> PASS
shard-glk: FAIL (fdo#102887) -> PASS
igt@kms_flip@wf_vblank-ts-check-interruptible:
shard-glk: FAIL (fdo#100368) -> PASS
shard-apl: FAIL (fdo#100368) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
fdo#106134 https://bugs.freedesktop.org/show_bug.cgi?id=106134
== Participating hosts (9 -> 9) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4163 -> Patchwork_8966
CI_DRM_4163: 8e1dab6e913be7d014eb9bc355ec65b6b56dcd56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4468: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8966: a31dc6baa24c65225c8f09d05a4823ea6cd9aa40 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4468: 1e60f1499e5b71b6d5a747189d7c28f57359a87f @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8966/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2)
2018-05-09 21:54 [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
` (3 preceding siblings ...)
2018-05-10 2:38 ` ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Patchwork
@ 2018-05-10 3:56 ` Patchwork
2018-05-11 12:24 ` [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Ville Syrjälä
5 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-05-10 3:56 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2)
URL : https://patchwork.freedesktop.org/series/42971/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4163_full -> Patchwork_8968_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_8968_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8968_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/42971/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8968_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: SKIP -> PASS +3
igt@kms_force_connector_basic@force-connector-state:
shard-snb: PASS -> SKIP
igt@kms_properties@plane-properties-legacy:
shard-snb: SKIP -> PASS +4
igt@pm_rc6_residency@rc6-accuracy:
shard-kbl: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_8968_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#100368)
igt@kms_flip@flip-vs-expired-vblank:
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_rotation_crc@primary-rotation-180:
shard-apl: PASS -> FAIL (fdo#104724, fdo#103925)
==== Possible fixes ====
igt@kms_flip@absolute-wf_vblank-interruptible:
shard-glk: FAIL (fdo#106087) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-apl: FAIL (fdo#105363, fdo#102887) -> PASS
shard-glk: FAIL (fdo#102887) -> PASS
igt@kms_flip@wf_vblank-ts-check-interruptible:
shard-apl: FAIL (fdo#100368) -> PASS
igt@kms_setmode@basic:
shard-glk: FAIL (fdo#99912) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#106087 https://bugs.freedesktop.org/show_bug.cgi?id=106087
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (9 -> 9) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4163 -> Patchwork_8968
CI_DRM_4163: 8e1dab6e913be7d014eb9bc355ec65b6b56dcd56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4468: 548a894dc904c4628522dbbc77cb179a4c965ebc @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8968: 45ebe900d240cdecc703ba951d13562fa1fc6cca @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4468: 1e60f1499e5b71b6d5a747189d7c28f57359a87f @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8968/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
2018-05-09 21:54 [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
` (4 preceding siblings ...)
2018-05-10 3:56 ` ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2) Patchwork
@ 2018-05-11 12:24 ` Ville Syrjälä
2018-05-11 17:05 ` Dhinakaran Pandiyan
5 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2018-05-11 12:24 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx, Rodrigo Vivi
On Wed, May 09, 2018 at 02:54:01PM -0700, Dhinakaran Pandiyan wrote:
> By moving the check from psr_compute_config() to psr_init_dpcd(), we get
> to set the dev_priv->psr.sink_support flag only when the panel is
> capable of changing power state. An additional benefit is that the check
> will be performed only at init time instead of every atomic_check.
>
> This should change the psr_basic IGT failures on HSW to skips.
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_psr.c | 12 +++++-------
> 2 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..f1747dff9ca3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
> dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
>
> - intel_psr_init_dpcd(intel_dp);
> -
> /*
> * Read the eDP display control registers.
> *
> @@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
> DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
> intel_dp->edp_dpcd);
>
> + /*
> + * This has to be called after initializing intel_dp->edp_dpcd, PSR
> + * checks for the SET_POWER_CAPABLE bit.
> + */
> + intel_psr_init_dpcd(intel_dp);
> +
> /* Read the eDP 1.4+ supported link rates. */
> if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index db27f2faa1de..9e6534d57479 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -251,8 +251,11 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> sizeof(intel_dp->psr_dpcd));
>
> if (intel_dp->psr_dpcd[0]) {
> - dev_priv->psr.sink_support = true;
> - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
> + DRM_DEBUG_KMS("Detected EDP PSR panel\n");
> + if (intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)
> + dev_priv->psr.sink_support = true;
> + else
> + DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");
> }
This function looks a bit crazy. Why are we going on to parse other
things after psr_dpcd[0] was already deemed to be zero?
Wouldn't it make much more sense to invert the first psr_dpcd[0] check
and bail out entirely?
>
> if (INTEL_GEN(dev_priv) >= 9 &&
> @@ -640,11 +643,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> return;
> }
>
> - if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
> - DRM_DEBUG_KMS("PSR condition failed: panel lacks power state control\n");
> - return;
> - }
> -
> crtc_state->has_psr = true;
> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
> --
> 2.14.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time.
2018-05-11 12:24 ` [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Ville Syrjälä
@ 2018-05-11 17:05 ` Dhinakaran Pandiyan
0 siblings, 0 replies; 9+ messages in thread
From: Dhinakaran Pandiyan @ 2018-05-11 17:05 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Rodrigo Vivi
On Fri, 2018-05-11 at 15:24 +0300, Ville Syrjälä wrote:
> On Wed, May 09, 2018 at 02:54:01PM -0700, Dhinakaran Pandiyan wrote:
> >
> > By moving the check from psr_compute_config() to psr_init_dpcd(),
> > we get
> > to set the dev_priv->psr.sink_support flag only when the panel is
> > capable of changing power state. An additional benefit is that the
> > check
> > will be performed only at init time instead of every atomic_check.
> >
> > This should change the psr_basic IGT failures on HSW to skips.
> >
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> > drivers/gpu/drm/i915/intel_psr.c | 12 +++++-------
> > 2 files changed, 11 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index dde92e4af5d3..f1747dff9ca3 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3762,8 +3762,6 @@ intel_edp_init_dpcd(struct intel_dp
> > *intel_dp)
> > dev_priv->no_aux_handshake = intel_dp-
> > >dpcd[DP_MAX_DOWNSPREAD] &
> > DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
> >
> > - intel_psr_init_dpcd(intel_dp);
> > -
> > /*
> > * Read the eDP display control registers.
> > *
> > @@ -3779,6 +3777,12 @@ intel_edp_init_dpcd(struct intel_dp
> > *intel_dp)
> > DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int)
> > sizeof(intel_dp->edp_dpcd),
> > intel_dp->edp_dpcd);
> >
> > + /*
> > + * This has to be called after initializing intel_dp-
> > >edp_dpcd, PSR
> > + * checks for the SET_POWER_CAPABLE bit.
> > + */
> > + intel_psr_init_dpcd(intel_dp);
> > +
> > /* Read the eDP 1.4+ supported link rates. */
> > if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
> > __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index db27f2faa1de..9e6534d57479 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -251,8 +251,11 @@ void intel_psr_init_dpcd(struct intel_dp
> > *intel_dp)
> > sizeof(intel_dp->psr_dpcd));
> >
> > if (intel_dp->psr_dpcd[0]) {
> > - dev_priv->psr.sink_support = true;
> > - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
> > + DRM_DEBUG_KMS("Detected EDP PSR panel\n");
> > + if (intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)
> > + dev_priv->psr.sink_support = true;
> > + else
> > + DRM_DEBUG_KMS("Panel lacks power state
> > control, PSR cannot be enabled\n");
> > }
> This function looks a bit crazy. Why are we going on to parse other
> things after psr_dpcd[0] was already deemed to be zero?
>
> Wouldn't it make much more sense to invert the first psr_dpcd[0]
> check
> and bail out entirely?
>
Yeah, this is wasteful. We did have the dpcd reads bounded by PSR
capability checks until recently. I'll fix it up, thanks!
-DK
> >
> >
> > if (INTEL_GEN(dev_priv) >= 9 &&
> > @@ -640,11 +643,6 @@ void intel_psr_compute_config(struct intel_dp
> > *intel_dp,
> > return;
> > }
> >
> > - if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
> > - DRM_DEBUG_KMS("PSR condition failed: panel lacks
> > power state control\n");
> > - return;
> > - }
> > -
> > crtc_state->has_psr = true;
> > crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> > crtc_state);
> > DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ?
> > "2" : "");
> > --
> > 2.14.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-05-11 16:40 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-09 21:54 [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Dhinakaran Pandiyan
2018-05-09 23:10 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-05-09 23:58 ` [PATCH] " Souza, Jose
2018-05-10 0:25 ` [PATCH v2] " Dhinakaran Pandiyan
2018-05-10 1:02 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2) Patchwork
2018-05-10 2:38 ` ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Patchwork
2018-05-10 3:56 ` ✓ Fi.CI.IGT: success for drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time. (rev2) Patchwork
2018-05-11 12:24 ` [PATCH] drm/i915/psr: Check for SET_POWER_CAPABLE bit at PSR init time Ville Syrjälä
2018-05-11 17:05 ` Dhinakaran Pandiyan
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