* [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps
@ 2018-05-12 5:02 Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 1/9] target/m68k: Use DISAS_NORETURN for exceptions Richard Henderson
` (11 more replies)
0 siblings, 12 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
[ Ho, hum. I didn't clear out my scratch directory before sending v1.0. ]
FYI, I've only tested this with linux-user-test-0.3 and
our qemu coldfire testing kernel.
r~
Richard Henderson (9):
target/m68k: Use DISAS_NORETURN for exceptions
target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN
target/m68k: Remove DISAS_JUMP_NEXT as unused
target/m68k: Use lookup_and_goto_tb for DISAS_JUMP
target/m68k: Rename DISAS_UPDATE and gen_lookup_tb
target/m68k: Convert to DisasContextBase
target/m68k: Convert to TranslatorOps
target/m68k: Improve ending TB at page boundaries
target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn
target/m68k/translate.c | 354 ++++++++++++++++++++--------------------
1 file changed, 179 insertions(+), 175 deletions(-)
--
2.17.0
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 1/9] target/m68k: Use DISAS_NORETURN for exceptions
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
@ 2018-05-12 5:02 ` Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 2/9] target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN Richard Henderson
` (10 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
The raise_exception helper does not return. Do not generate
any code following that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 44a0ac4e2e..86404906e0 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -291,18 +291,18 @@ static void gen_jmp(DisasContext *s, TCGv dest)
s->is_jmp = DISAS_JUMP;
}
-static void gen_raise_exception(int nr)
+static void gen_exception(DisasContext *s, uint32_t dest, int nr)
{
- TCGv_i32 tmp = tcg_const_i32(nr);
+ TCGv_i32 tmp;
+ update_cc_op(s);
+ tcg_gen_movi_i32(QREG_PC, dest);
+
+ tmp = tcg_const_i32(nr);
gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
-}
-static void gen_exception(DisasContext *s, uint32_t where, int nr)
-{
- gen_jmp_im(s, where);
- gen_raise_exception(nr);
+ s->is_jmp = DISAS_NORETURN;
}
static inline void gen_addr_fault(DisasContext *s)
@@ -6106,7 +6106,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
gen_exception(dc, dc->pc, EXCP_DEBUG);
- dc->is_jmp = DISAS_JUMP;
/* The address covered by the breakpoint must be included in
[tb->pc, tb->pc + tb->size) in order to for it to be
properly cleared -- thus we increment the PC here so that
@@ -6150,6 +6149,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
tcg_gen_exit_tb(0);
break;
case DISAS_TB_JUMP:
+ case DISAS_NORETURN:
/* nothing more to generate */
break;
}
--
2.17.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 2/9] target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 1/9] target/m68k: Use DISAS_NORETURN for exceptions Richard Henderson
@ 2018-05-12 5:02 ` Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 3/9] target/m68k: Remove DISAS_JUMP_NEXT as unused Richard Henderson
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
We have exited the TB after using goto_tb; there is no
distinction from DISAS_NORETURN.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 86404906e0..6ab24fac0b 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -199,7 +199,6 @@ static void do_writebacks(DisasContext *s)
/* is_jmp field values */
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
-#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
#define DISAS_JUMP_NEXT DISAS_TARGET_3
#if defined(CONFIG_USER_ONLY)
@@ -1496,7 +1495,7 @@ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
gen_jmp_im(s, dest);
tcg_gen_exit_tb(0);
}
- s->is_jmp = DISAS_TB_JUMP;
+ s->is_jmp = DISAS_NORETURN;
}
DISAS_INSN(scc)
@@ -6148,7 +6147,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
/* indicate that the hash table must be used to find the next TB */
tcg_gen_exit_tb(0);
break;
- case DISAS_TB_JUMP:
case DISAS_NORETURN:
/* nothing more to generate */
break;
--
2.17.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 3/9] target/m68k: Remove DISAS_JUMP_NEXT as unused
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 1/9] target/m68k: Use DISAS_NORETURN for exceptions Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 2/9] target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN Richard Henderson
@ 2018-05-12 5:02 ` Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 4/9] target/m68k: Use lookup_and_goto_tb for DISAS_JUMP Richard Henderson
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 6ab24fac0b..c795d8e64f 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -199,7 +199,6 @@ static void do_writebacks(DisasContext *s)
/* is_jmp field values */
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
-#define DISAS_JUMP_NEXT DISAS_TARGET_3
#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
--
2.17.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 4/9] target/m68k: Use lookup_and_goto_tb for DISAS_JUMP
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (2 preceding siblings ...)
2018-05-12 5:02 ` [Qemu-devel] [PATCH 3/9] target/m68k: Remove DISAS_JUMP_NEXT as unused Richard Henderson
@ 2018-05-12 5:02 ` Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 5/9] target/m68k: Rename DISAS_UPDATE and gen_lookup_tb Richard Henderson
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
These are all indirect or out-of-page direct jumps.
We can indirectly chain to the next TB without going
back to the main loop.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index c795d8e64f..80712ed0af 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6139,8 +6139,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
update_cc_op(dc);
gen_jmp_tb(dc, 0, dc->pc);
break;
- default:
case DISAS_JUMP:
+ /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
+ tcg_gen_lookup_and_goto_ptr();
+ break;
+ default:
case DISAS_UPDATE:
update_cc_op(dc);
/* indicate that the hash table must be used to find the next TB */
--
2.17.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 5/9] target/m68k: Rename DISAS_UPDATE and gen_lookup_tb
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (3 preceding siblings ...)
2018-05-12 5:02 ` [Qemu-devel] [PATCH 4/9] target/m68k: Use lookup_and_goto_tb for DISAS_JUMP Richard Henderson
@ 2018-05-12 5:02 ` Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 6/9] target/m68k: Convert to DisasContextBase Richard Henderson
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
The name gen_lookup_tb is at odds with tcg_gen_lookup_and_goto_tb.
For these cases, we do indeed want to exit back to the main loop.
Similarly, DISAS_UPDATE performs no actual update, whereas DISAS_EXIT
does what it says.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 80712ed0af..ff1a8d58f4 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -198,7 +198,7 @@ static void do_writebacks(DisasContext *s)
/* is_jmp field values */
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
-#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
+#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
@@ -1446,11 +1446,11 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
}
/* Force a TB lookup after an instruction that changes the CPU state. */
-static void gen_lookup_tb(DisasContext *s)
+static void gen_exit_tb(DisasContext *s)
{
update_cc_op(s);
tcg_gen_movi_i32(QREG_PC, s->pc);
- s->is_jmp = DISAS_UPDATE;
+ s->is_jmp = DISAS_EXIT;
}
#define SRC_EA(env, result, opsize, op_sign, addrp) do { \
@@ -4604,7 +4604,7 @@ DISAS_INSN(move_to_sr)
return;
}
gen_move_to_sr(env, s, insn, false);
- gen_lookup_tb(s);
+ gen_exit_tb(s);
}
DISAS_INSN(move_from_usp)
@@ -4680,7 +4680,7 @@ DISAS_INSN(cf_movec)
reg = DREG(ext, 12);
}
gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
- gen_lookup_tb(s);
+ gen_exit_tb(s);
}
DISAS_INSN(m68k_movec)
@@ -4705,7 +4705,7 @@ DISAS_INSN(m68k_movec)
} else {
gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
}
- gen_lookup_tb(s);
+ gen_exit_tb(s);
}
DISAS_INSN(intouch)
@@ -5749,7 +5749,7 @@ DISAS_INSN(to_macsr)
TCGv val;
SRC_EA(env, val, OS_LONG, 0, NULL);
gen_helper_set_macsr(cpu_env, val);
- gen_lookup_tb(s);
+ gen_exit_tb(s);
}
DISAS_INSN(to_mask)
@@ -6144,9 +6144,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
tcg_gen_lookup_and_goto_ptr();
break;
default:
- case DISAS_UPDATE:
- update_cc_op(dc);
- /* indicate that the hash table must be used to find the next TB */
+ case DISAS_EXIT:
+ /* We updated CC_OP and PC in gen_exit_tb, but also modified
+ other state that may require returning to the main loop. */
tcg_gen_exit_tb(0);
break;
case DISAS_NORETURN:
--
2.17.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 6/9] target/m68k: Convert to DisasContextBase
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (4 preceding siblings ...)
2018-05-12 5:02 ` [Qemu-devel] [PATCH 5/9] target/m68k: Rename DISAS_UPDATE and gen_lookup_tb Richard Henderson
@ 2018-05-12 5:02 ` Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 7/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (5 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
Removed ctx->insn_pc in favour of ctx->base.pc_next.
Yes, it is annoying, but didn't want to waste its 4 bytes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 137 ++++++++++++++++++++--------------------
1 file changed, 67 insertions(+), 70 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index ff1a8d58f4..01d3265437 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -111,14 +111,11 @@ void m68k_tcg_init(void)
/* internal defines */
typedef struct DisasContext {
+ DisasContextBase base;
CPUM68KState *env;
- target_ulong insn_pc; /* Start of the current instruction. */
target_ulong pc;
- int is_jmp;
CCOp cc_op; /* Current CC operation */
int cc_op_synced;
- struct TranslationBlock *tb;
- int singlestep_enabled;
TCGv_i64 mactmp;
int done_mac;
int writeback_mask;
@@ -203,10 +200,10 @@ static void do_writebacks(DisasContext *s)
#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
#else
-#define IS_USER(s) (!(s->tb->flags & TB_FLAGS_MSR_S))
-#define SFC_INDEX(s) ((s->tb->flags & TB_FLAGS_SFC_S) ? \
+#define IS_USER(s) (!(s->base.tb->flags & TB_FLAGS_MSR_S))
+#define SFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_SFC_S) ? \
MMU_KERNEL_IDX : MMU_USER_IDX)
-#define DFC_INDEX(s) ((s->tb->flags & TB_FLAGS_DFC_S) ? \
+#define DFC_INDEX(s) ((s->base.tb->flags & TB_FLAGS_DFC_S) ? \
MMU_KERNEL_IDX : MMU_USER_IDX)
#endif
@@ -278,7 +275,7 @@ static void gen_jmp_im(DisasContext *s, uint32_t dest)
{
update_cc_op(s);
tcg_gen_movi_i32(QREG_PC, dest);
- s->is_jmp = DISAS_JUMP;
+ s->base.is_jmp = DISAS_JUMP;
}
/* Generate a jump to the address in qreg DEST. */
@@ -286,7 +283,7 @@ static void gen_jmp(DisasContext *s, TCGv dest)
{
update_cc_op(s);
tcg_gen_mov_i32(QREG_PC, dest);
- s->is_jmp = DISAS_JUMP;
+ s->base.is_jmp = DISAS_JUMP;
}
static void gen_exception(DisasContext *s, uint32_t dest, int nr)
@@ -300,12 +297,12 @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
- s->is_jmp = DISAS_NORETURN;
+ s->base.is_jmp = DISAS_NORETURN;
}
static inline void gen_addr_fault(DisasContext *s)
{
- gen_exception(s, s->insn_pc, EXCP_ADDRESS);
+ gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
}
/* Generate a load from the specified address. Narrow values are
@@ -1003,7 +1000,7 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
- gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
+ gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
}
tcg_gen_qemu_ld32u(tmp, addr, index);
@@ -1017,7 +1014,7 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
/* unimplemented data type on 68040/ColdFire
* FIXME if needed for another FPU
*/
- gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
+ gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
default:
g_assert_not_reached();
@@ -1057,7 +1054,7 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
- gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
+ gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
}
tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
@@ -1071,7 +1068,7 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
/* unimplemented data type on 68040/ColdFire
* FIXME if needed for another FPU
*/
- gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
+ gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
default:
g_assert_not_reached();
@@ -1203,7 +1200,7 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
- gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
+ gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
}
tmp = tcg_const_i32(read_im32(env, s) >> 16);
@@ -1217,7 +1214,7 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
/* unimplemented data type on 68040/ColdFire
* FIXME if needed for another FPU
*/
- gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
+ gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
default:
g_assert_not_reached();
@@ -1450,7 +1447,7 @@ static void gen_exit_tb(DisasContext *s)
{
update_cc_op(s);
tcg_gen_movi_i32(QREG_PC, s->pc);
- s->is_jmp = DISAS_EXIT;
+ s->base.is_jmp = DISAS_EXIT;
}
#define SRC_EA(env, result, opsize, op_sign, addrp) do { \
@@ -1474,8 +1471,8 @@ static void gen_exit_tb(DisasContext *s)
static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
{
#ifndef CONFIG_USER_ONLY
- return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
- (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
+ return (s->base.pc_first & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)
+ || (s->base.pc_next & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
#else
return true;
#endif
@@ -1484,17 +1481,17 @@ static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
/* Generate a jump to an immediate address. */
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
{
- if (unlikely(s->singlestep_enabled)) {
+ if (unlikely(s->base.singlestep_enabled)) {
gen_exception(s, dest, EXCP_DEBUG);
} else if (use_goto_tb(s, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_i32(QREG_PC, dest);
- tcg_gen_exit_tb((uintptr_t)s->tb + n);
+ tcg_gen_exit_tb((uintptr_t)s->base.tb + n);
} else {
gen_jmp_im(s, dest);
tcg_gen_exit_tb(0);
}
- s->is_jmp = DISAS_NORETURN;
+ s->base.is_jmp = DISAS_NORETURN;
}
DISAS_INSN(scc)
@@ -1541,12 +1538,12 @@ DISAS_INSN(dbcc)
DISAS_INSN(undef_mac)
{
- gen_exception(s, s->insn_pc, EXCP_LINEA);
+ gen_exception(s, s->base.pc_next, EXCP_LINEA);
}
DISAS_INSN(undef_fpu)
{
- gen_exception(s, s->insn_pc, EXCP_LINEF);
+ gen_exception(s, s->base.pc_next, EXCP_LINEF);
}
DISAS_INSN(undef)
@@ -1555,8 +1552,8 @@ DISAS_INSN(undef)
for the 680x0 series, as well as those that are implemented
but actually illegal for CPU32 or pre-68020. */
qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x",
- insn, s->insn_pc);
- gen_exception(s, s->insn_pc, EXCP_UNSUPPORTED);
+ insn, s->base.pc_next);
+ gen_exception(s, s->base.pc_next, EXCP_UNSUPPORTED);
}
DISAS_INSN(mulw)
@@ -1616,7 +1613,7 @@ DISAS_INSN(divl)
if (ext & 0x400) {
if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
- gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
@@ -2310,7 +2307,7 @@ DISAS_INSN(arith_im)
break;
case OS_WORD:
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
src1 = gen_get_sr(s);
@@ -2479,7 +2476,7 @@ DISAS_INSN(cas2w)
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
- if (tb_cflags(s->tb) & CF_PARALLEL) {
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
} else {
gen_helper_cas2w(cpu_env, regs, addr1, addr2);
@@ -2529,7 +2526,7 @@ DISAS_INSN(cas2l)
(REG(ext1, 6) << 3) |
(REG(ext2, 0) << 6) |
(REG(ext1, 0) << 9));
- if (tb_cflags(s->tb) & CF_PARALLEL) {
+ if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
} else {
gen_helper_cas2l(cpu_env, regs, addr1, addr2);
@@ -2720,7 +2717,7 @@ DISAS_INSN(swap)
DISAS_INSN(bkpt)
{
- gen_exception(s, s->insn_pc, EXCP_DEBUG);
+ gen_exception(s, s->base.pc_next, EXCP_DEBUG);
}
DISAS_INSN(pea)
@@ -2773,7 +2770,7 @@ DISAS_INSN(pulse)
DISAS_INSN(illegal)
{
- gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
}
/* ??? This should be atomic. */
@@ -2803,7 +2800,7 @@ DISAS_INSN(mull)
if (ext & 0x400) {
if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
- gen_exception(s, s->insn_pc, EXCP_UNSUPPORTED);
+ gen_exception(s, s->base.pc_next, EXCP_UNSUPPORTED);
return;
}
@@ -2904,7 +2901,7 @@ DISAS_INSN(unlk)
DISAS_INSN(reset)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
@@ -4375,7 +4372,7 @@ DISAS_INSN(chk)
}
/* fallthru */
default:
- gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
SRC_EA(env, src, opsize, 1, NULL);
@@ -4402,13 +4399,13 @@ DISAS_INSN(chk2)
opsize = OS_LONG;
break;
default:
- gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
ext = read_im16(env, s);
if ((ext & 0x0800) == 0) {
- gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
@@ -4468,7 +4465,7 @@ DISAS_INSN(move16_reg)
ext = read_im16(env, s);
if ((ext & (1 << 15)) == 0) {
- gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
}
m68k_copy_line(AREG(ext, 12), AREG(insn, 0), index);
@@ -4530,7 +4527,7 @@ DISAS_INSN(move_from_sr)
TCGv sr;
if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
sr = gen_get_sr(s);
@@ -4547,7 +4544,7 @@ DISAS_INSN(moves)
int extend;
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
@@ -4600,7 +4597,7 @@ DISAS_INSN(moves)
DISAS_INSN(move_to_sr)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
gen_move_to_sr(env, s, insn, false);
@@ -4610,7 +4607,7 @@ DISAS_INSN(move_to_sr)
DISAS_INSN(move_from_usp)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
@@ -4620,7 +4617,7 @@ DISAS_INSN(move_from_usp)
DISAS_INSN(move_to_usp)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
tcg_gen_st_i32(AREG(insn, 0), cpu_env,
@@ -4630,7 +4627,7 @@ DISAS_INSN(move_to_usp)
DISAS_INSN(halt)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
@@ -4642,7 +4639,7 @@ DISAS_INSN(stop)
uint16_t ext;
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
@@ -4656,10 +4653,10 @@ DISAS_INSN(stop)
DISAS_INSN(rte)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
- gen_exception(s, s->insn_pc, EXCP_RTE);
+ gen_exception(s, s->base.pc_next, EXCP_RTE);
}
DISAS_INSN(cf_movec)
@@ -4668,7 +4665,7 @@ DISAS_INSN(cf_movec)
TCGv reg;
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
@@ -4689,7 +4686,7 @@ DISAS_INSN(m68k_movec)
TCGv reg;
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
@@ -4711,7 +4708,7 @@ DISAS_INSN(m68k_movec)
DISAS_INSN(intouch)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
/* ICache fetch. Implement as no-op. */
@@ -4720,7 +4717,7 @@ DISAS_INSN(intouch)
DISAS_INSN(cpushl)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
/* Cache push/invalidate. Implement as no-op. */
@@ -4729,7 +4726,7 @@ DISAS_INSN(cpushl)
DISAS_INSN(cpush)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
/* Cache push/invalidate. Implement as no-op. */
@@ -4738,7 +4735,7 @@ DISAS_INSN(cpush)
DISAS_INSN(cinv)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
/* Invalidate cache line. Implement as no-op. */
@@ -4750,7 +4747,7 @@ DISAS_INSN(pflush)
TCGv opmode;
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
@@ -4764,7 +4761,7 @@ DISAS_INSN(ptest)
TCGv is_read;
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
is_read = tcg_const_i32((insn >> 5) & 1);
@@ -4775,7 +4772,7 @@ DISAS_INSN(ptest)
DISAS_INSN(wddata)
{
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
}
DISAS_INSN(wdebug)
@@ -4783,7 +4780,7 @@ DISAS_INSN(wdebug)
M68kCPU *cpu = m68k_env_get_cpu(env);
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
/* TODO: Implement wdebug. */
@@ -4793,7 +4790,7 @@ DISAS_INSN(wdebug)
DISAS_INSN(trap)
{
- gen_exception(s, s->insn_pc, EXCP_TRAP0 + (insn & 0xf));
+ gen_exception(s, s->base.pc_next, EXCP_TRAP0 + (insn & 0xf));
}
static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
@@ -4860,7 +4857,7 @@ static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
switch (mode) {
case 0: /* Dn */
if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
- gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
if (is_write) {
@@ -4871,7 +4868,7 @@ static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
return;
case 1: /* An, only with FPIAR */
if (mask != M68K_FPIAR) {
- gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
return;
}
if (is_write) {
@@ -5429,7 +5426,7 @@ DISAS_INSN(frestore)
TCGv addr;
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
@@ -5443,7 +5440,7 @@ DISAS_INSN(frestore)
DISAS_INSN(fsave)
{
if (IS_USER(s)) {
- gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
@@ -6075,14 +6072,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
/* generate intermediate code */
pc_start = tb->pc;
- dc->tb = tb;
+ dc->base.tb = tb;
dc->env = env;
- dc->is_jmp = DISAS_NEXT;
+ dc->base.is_jmp = DISAS_NEXT;
dc->pc = pc_start;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_synced = 1;
- dc->singlestep_enabled = cs->singlestep_enabled;
+ dc->base.singlestep_enabled = cs->singlestep_enabled;
dc->done_mac = 0;
dc->writeback_mask = 0;
num_insns = 0;
@@ -6116,9 +6113,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
gen_io_start();
}
- dc->insn_pc = dc->pc;
+ dc->base.pc_next = dc->pc;
disas_m68k_insn(env, dc);
- } while (!dc->is_jmp && !tcg_op_buf_full() &&
+ } while (!dc->base.is_jmp && !tcg_op_buf_full() &&
!cs->singlestep_enabled &&
!singlestep &&
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&
@@ -6128,13 +6125,13 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
gen_io_end();
if (unlikely(cs->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
- if (!dc->is_jmp) {
+ if (!dc->base.is_jmp) {
update_cc_op(dc);
tcg_gen_movi_i32(QREG_PC, dc->pc);
}
gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
} else {
- switch(dc->is_jmp) {
+ switch(dc->base.is_jmp) {
case DISAS_NEXT:
update_cc_op(dc);
gen_jmp_tb(dc, 0, dc->pc);
--
2.17.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 7/9] target/m68k: Convert to TranslatorOps
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (5 preceding siblings ...)
2018-05-12 5:02 ` [Qemu-devel] [PATCH 6/9] target/m68k: Convert to DisasContextBase Richard Henderson
@ 2018-05-12 5:02 ` Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 8/9] target/m68k: Improve ending TB at page boundaries Richard Henderson
` (4 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 176 ++++++++++++++++++++--------------------
1 file changed, 86 insertions(+), 90 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 01d3265437..0ab9ab1148 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6059,113 +6059,109 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
do_release(s);
}
-/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
- CPUM68KState *env = cs->env_ptr;
- DisasContext dc1, *dc = &dc1;
- target_ulong pc_start;
- int pc_offset;
- int num_insns;
- int max_insns;
-
- /* generate intermediate code */
- pc_start = tb->pc;
-
- dc->base.tb = tb;
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ CPUM68KState *env = cpu->env_ptr;
dc->env = env;
- dc->base.is_jmp = DISAS_NEXT;
- dc->pc = pc_start;
+ dc->pc = dc->base.pc_first;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_synced = 1;
- dc->base.singlestep_enabled = cs->singlestep_enabled;
dc->done_mac = 0;
dc->writeback_mask = 0;
- num_insns = 0;
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
-
init_release_array(dc);
+}
- gen_tb_start(tb);
- do {
- pc_offset = dc->pc - pc_start;
- tcg_gen_insn_start(dc->pc, dc->cc_op);
- num_insns++;
+static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
+{
+}
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
- gen_exception(dc, dc->pc, EXCP_DEBUG);
- /* The address covered by the breakpoint must be included in
- [tb->pc, tb->pc + tb->size) in order to for it to be
- properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
- dc->pc += 2;
- break;
- }
+static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
+}
- if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
+static bool m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- dc->base.pc_next = dc->pc;
- disas_m68k_insn(env, dc);
- } while (!dc->base.is_jmp && !tcg_op_buf_full() &&
- !cs->singlestep_enabled &&
- !singlestep &&
- (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
- num_insns < max_insns);
+ gen_exception(dc, dc->base.pc_next, EXCP_DEBUG);
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ dc->base.pc_next += 2;
- if (tb_cflags(tb) & CF_LAST_IO)
- gen_io_end();
- if (unlikely(cs->singlestep_enabled)) {
- /* Make sure the pc is updated, and raise a debug exception. */
- if (!dc->base.is_jmp) {
- update_cc_op(dc);
- tcg_gen_movi_i32(QREG_PC, dc->pc);
- }
+ return true;
+}
+
+static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ disas_m68k_insn(cpu->env_ptr, dc);
+ dc->base.pc_next = dc->pc;
+
+ if (dc->base.is_jmp == DISAS_NEXT
+ && dc->pc - dc->base.pc_first >= TARGET_PAGE_SIZE - 32) {
+ dc->base.is_jmp = DISAS_TOO_MANY;
+ }
+}
+
+static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ if (dc->base.is_jmp == DISAS_NORETURN) {
+ return;
+ }
+ if (dc->base.singlestep_enabled) {
gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
- } else {
- switch(dc->base.is_jmp) {
- case DISAS_NEXT:
- update_cc_op(dc);
- gen_jmp_tb(dc, 0, dc->pc);
- break;
- case DISAS_JUMP:
- /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
- tcg_gen_lookup_and_goto_ptr();
- break;
- default:
- case DISAS_EXIT:
- /* We updated CC_OP and PC in gen_exit_tb, but also modified
- other state that may require returning to the main loop. */
- tcg_gen_exit_tb(0);
- break;
- case DISAS_NORETURN:
- /* nothing more to generate */
- break;
- }
+ return;
}
- gen_tb_end(tb, num_insns);
-#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
- qemu_log_lock();
- qemu_log("----------------\n");
- qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start);
- qemu_log("\n");
- qemu_log_unlock();
+ switch (dc->base.is_jmp) {
+ case DISAS_TOO_MANY:
+ update_cc_op(dc);
+ gen_jmp_tb(dc, 0, dc->pc);
+ break;
+ case DISAS_JUMP:
+ /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
+ tcg_gen_lookup_and_goto_ptr();
+ break;
+ case DISAS_EXIT:
+ /* We updated CC_OP and PC in gen_exit_tb, but also modified
+ other state that may require returning to the main loop. */
+ tcg_gen_exit_tb(0);
+ break;
+ default:
+ g_assert_not_reached();
}
-#endif
- tb->size = dc->pc - pc_start;
- tb->icount = num_insns;
+}
+
+static void m68k_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
+{
+ qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+ log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
+}
+
+static const TranslatorOps m68k_tr_ops = {
+ .init_disas_context = m68k_tr_init_disas_context,
+ .tb_start = m68k_tr_tb_start,
+ .insn_start = m68k_tr_insn_start,
+ .breakpoint_check = m68k_tr_breakpoint_check,
+ .translate_insn = m68k_tr_translate_insn,
+ .tb_stop = m68k_tr_tb_stop,
+ .disas_log = m68k_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
+{
+ DisasContext dc;
+ translator_loop(&m68k_tr_ops, &dc.base, cpu, tb);
}
static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
--
2.17.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 8/9] target/m68k: Improve ending TB at page boundaries
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (6 preceding siblings ...)
2018-05-12 5:02 ` [Qemu-devel] [PATCH 7/9] target/m68k: Convert to TranslatorOps Richard Henderson
@ 2018-05-12 5:02 ` Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 9/9] target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn Richard Henderson
` (3 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
Rather than limit total TB size to PAGE-32 bytes, end the TB when
near the end of a page. This should provide proper semantics of
SIGSEGV when executing near the end of a page.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 0ab9ab1148..069558bc28 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6105,9 +6105,25 @@ static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
disas_m68k_insn(cpu->env_ptr, dc);
dc->base.pc_next = dc->pc;
- if (dc->base.is_jmp == DISAS_NEXT
- && dc->pc - dc->base.pc_first >= TARGET_PAGE_SIZE - 32) {
- dc->base.is_jmp = DISAS_TOO_MANY;
+ if (dc->base.is_jmp == DISAS_NEXT) {
+ /* Stop translation when the next insn might touch a new page.
+ * This ensures that prefetch aborts at the right place.
+ *
+ * We cannot determine the size of the next insn without
+ * completely decoding it. However, the maximum insn size
+ * is 32 bytes, so end if we do not have that much remaining.
+ * This may produce several small TBs at the end of each page,
+ * but they will all be linked with goto_tb.
+ *
+ * ??? ColdFire maximum is 4 bytes; MC68000's maximum is also
+ * smaller than MC68020's.
+ */
+ target_ulong start_page_offset
+ = dc->pc - (dc->base.pc_first & TARGET_PAGE_MASK);
+
+ if (start_page_offset >= TARGET_PAGE_SIZE - 32) {
+ dc->base.is_jmp = DISAS_TOO_MANY;
+ }
}
}
--
2.17.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH 9/9] target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (7 preceding siblings ...)
2018-05-12 5:02 ` [Qemu-devel] [PATCH 8/9] target/m68k: Improve ending TB at page boundaries Richard Henderson
@ 2018-05-12 5:02 ` Richard Henderson
2018-05-12 5:24 ` [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps no-reply
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Richard Henderson @ 2018-05-12 5:02 UTC (permalink / raw)
To: qemu-devel; +Cc: laurent
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 069558bc28..21eeebf4df 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6049,16 +6049,6 @@ void register_m68k_insns (CPUM68KState *env)
#undef INSN
}
-/* ??? Some of this implementation is not exception safe. We should always
- write back the result to memory before setting the condition codes. */
-static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
-{
- uint16_t insn = read_im16(env, s);
- opcode_table[insn](env, s, insn);
- do_writebacks(s);
- do_release(s);
-}
-
static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
@@ -6101,8 +6091,13 @@ static bool m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
+ CPUM68KState *env = cpu->env_ptr;
+ uint16_t insn = read_im16(env, dc);
+
+ opcode_table[insn](env, dc, insn);
+ do_writebacks(dc);
+ do_release(dc);
- disas_m68k_insn(cpu->env_ptr, dc);
dc->base.pc_next = dc->pc;
if (dc->base.is_jmp == DISAS_NEXT) {
--
2.17.0
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (8 preceding siblings ...)
2018-05-12 5:02 ` [Qemu-devel] [PATCH 9/9] target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn Richard Henderson
@ 2018-05-12 5:24 ` no-reply
2018-05-13 10:16 ` Laurent Vivier
2018-06-07 20:25 ` Laurent Vivier
11 siblings, 0 replies; 15+ messages in thread
From: no-reply @ 2018-05-12 5:24 UTC (permalink / raw)
To: richard.henderson; +Cc: famz, qemu-devel, laurent
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180512050250.12774-1-richard.henderson@linaro.org
Subject: [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20180512050250.12774-1-richard.henderson@linaro.org -> patchew/20180512050250.12774-1-richard.henderson@linaro.org
Switched to a new branch 'test'
b396d1ea56 target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn
1454f7ac75 target/m68k: Improve ending TB at page boundaries
180209d486 target/m68k: Convert to TranslatorOps
838e40004e target/m68k: Convert to DisasContextBase
88f0d5dff1 target/m68k: Rename DISAS_UPDATE and gen_lookup_tb
78920794cd target/m68k: Use lookup_and_goto_tb for DISAS_JUMP
0ae1c99c4a target/m68k: Remove DISAS_JUMP_NEXT as unused
127bfcf989 target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN
836179eaad target/m68k: Use DISAS_NORETURN for exceptions
=== OUTPUT BEGIN ===
Checking PATCH 1/9: target/m68k: Use DISAS_NORETURN for exceptions...
Checking PATCH 2/9: target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN...
Checking PATCH 3/9: target/m68k: Remove DISAS_JUMP_NEXT as unused...
Checking PATCH 4/9: target/m68k: Use lookup_and_goto_tb for DISAS_JUMP...
Checking PATCH 5/9: target/m68k: Rename DISAS_UPDATE and gen_lookup_tb...
Checking PATCH 6/9: target/m68k: Convert to DisasContextBase...
ERROR: space required before the open parenthesis '('
#559: FILE: target/m68k/translate.c:6134:
+ switch(dc->base.is_jmp) {
total: 1 errors, 0 warnings, 494 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/9: target/m68k: Convert to TranslatorOps...
Checking PATCH 8/9: target/m68k: Improve ending TB at page boundaries...
Checking PATCH 9/9: target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (9 preceding siblings ...)
2018-05-12 5:24 ` [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps no-reply
@ 2018-05-13 10:16 ` Laurent Vivier
2018-06-07 20:25 ` Laurent Vivier
11 siblings, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2018-05-13 10:16 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 12/05/2018 à 07:02, Richard Henderson a écrit :
> [ Ho, hum. I didn't clear out my scratch directory before sending v1.0. ]
>
> FYI, I've only tested this with linux-user-test-0.3 and
> our qemu coldfire testing kernel.
I've tested m68k-softmmu with Q800 emulation and started an LXC
container with m68k-linux-user:
Tested-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
` (10 preceding siblings ...)
2018-05-13 10:16 ` Laurent Vivier
@ 2018-06-07 20:25 ` Laurent Vivier
2018-06-08 17:48 ` Richard Henderson
11 siblings, 1 reply; 15+ messages in thread
From: Laurent Vivier @ 2018-06-07 20:25 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 12/05/2018 à 07:02, Richard Henderson a écrit :
> [ Ho, hum. I didn't clear out my scratch directory before sending v1.0. ]
>
> FYI, I've only tested this with linux-user-test-0.3 and
> our qemu coldfire testing kernel.
>
>
> r~
>
>
> Richard Henderson (9):
> target/m68k: Use DISAS_NORETURN for exceptions
> target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN
> target/m68k: Remove DISAS_JUMP_NEXT as unused
> target/m68k: Use lookup_and_goto_tb for DISAS_JUMP
> target/m68k: Rename DISAS_UPDATE and gen_lookup_tb
> target/m68k: Convert to DisasContextBase
> target/m68k: Convert to TranslatorOps
> target/m68k: Improve ending TB at page boundaries
> target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn
>
> target/m68k/translate.c | 354 ++++++++++++++++++++--------------------
> 1 file changed, 179 insertions(+), 175 deletions(-)
>
Richard,
do you want I take this through my m68k tree or do you take this in a
TCG pull requests?
Thanks,
Laurent
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps
2018-06-07 20:25 ` Laurent Vivier
@ 2018-06-08 17:48 ` Richard Henderson
2018-06-08 17:51 ` Laurent Vivier
0 siblings, 1 reply; 15+ messages in thread
From: Richard Henderson @ 2018-06-08 17:48 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel
On 06/07/2018 10:25 AM, Laurent Vivier wrote:
> do you want I take this through my m68k tree or do you take this in a
> TCG pull requests?
Would you take it through your m68k tree please?
r~
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps
2018-06-08 17:48 ` Richard Henderson
@ 2018-06-08 17:51 ` Laurent Vivier
0 siblings, 0 replies; 15+ messages in thread
From: Laurent Vivier @ 2018-06-08 17:51 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 08/06/2018 à 19:48, Richard Henderson a écrit :
> On 06/07/2018 10:25 AM, Laurent Vivier wrote:
>> do you want I take this through my m68k tree or do you take this in a
>> TCG pull requests?
>
> Would you take it through your m68k tree please?
OK, I take.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-06-08 17:52 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-12 5:02 [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 1/9] target/m68k: Use DISAS_NORETURN for exceptions Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 2/9] target/m68k: Replace DISAS_TB_JUMP with DISAS_NORETURN Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 3/9] target/m68k: Remove DISAS_JUMP_NEXT as unused Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 4/9] target/m68k: Use lookup_and_goto_tb for DISAS_JUMP Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 5/9] target/m68k: Rename DISAS_UPDATE and gen_lookup_tb Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 6/9] target/m68k: Convert to DisasContextBase Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 7/9] target/m68k: Convert to TranslatorOps Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 8/9] target/m68k: Improve ending TB at page boundaries Richard Henderson
2018-05-12 5:02 ` [Qemu-devel] [PATCH 9/9] target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn Richard Henderson
2018-05-12 5:24 ` [Qemu-devel] [PATCH v1.1 0/9] target/m68k: Convert to TranslatorOps no-reply
2018-05-13 10:16 ` Laurent Vivier
2018-06-07 20:25 ` Laurent Vivier
2018-06-08 17:48 ` Richard Henderson
2018-06-08 17:51 ` Laurent Vivier
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