* [U-Boot] [PATCH] x86: tsc: add support for reading CPU freq from cpuid
@ 2018-05-14 9:32 Christian Gmeiner
2018-05-21 15:36 ` Christian Gmeiner
2018-05-23 9:48 ` Bin Meng
0 siblings, 2 replies; 5+ messages in thread
From: Christian Gmeiner @ 2018-05-14 9:32 UTC (permalink / raw)
To: u-boot
Starting with cpuid level 0x16 (Skylake-based processors)
it is possible to get CPU base freq via cpuid.
This fixes booting on a skylake based system.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
---
drivers/timer/tsc_timer.c | 31 +++++++++++++++++++++++++------
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index c7fefd2031..96a3e55513 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -21,6 +21,17 @@
DECLARE_GLOBAL_DATA_PTR;
+static unsigned long cpu_mhz_from_cpuid(void)
+{
+ if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
+ return 0;
+
+ if (cpuid_eax(0) < 0x16)
+ return 0;
+
+ return cpuid_eax(0x16);
+}
+
/*
* According to Intel 64 and IA-32 System Programming Guide,
* if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
@@ -343,14 +354,22 @@ static void tsc_timer_ensure_setup(void)
if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
+ fast_calibrate = cpu_mhz_from_cpuid();
+ if (fast_calibrate)
+ goto done;
+
fast_calibrate = cpu_mhz_from_msr();
- if (!fast_calibrate) {
- fast_calibrate = quick_pit_calibrate();
- if (!fast_calibrate)
- panic("TSC frequency is ZERO");
- }
+ if (fast_calibrate)
+ goto done;
+
+ fast_calibrate = quick_pit_calibrate();
+ if (fast_calibrate)
+ goto done;
+
+ panic("TSC frequency is ZERO");
- gd->arch.clock_rate = fast_calibrate * 1000000;
+ done:
+ gd->arch.clock_rate = fast_calibrate * 1000000;
}
}
--
2.17.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] x86: tsc: add support for reading CPU freq from cpuid
2018-05-14 9:32 [U-Boot] [PATCH] x86: tsc: add support for reading CPU freq from cpuid Christian Gmeiner
@ 2018-05-21 15:36 ` Christian Gmeiner
2018-05-23 9:48 ` Bin Meng
1 sibling, 0 replies; 5+ messages in thread
From: Christian Gmeiner @ 2018-05-21 15:36 UTC (permalink / raw)
To: u-boot
ping
Am Mo., 14. Mai 2018 um 11:32 Uhr schrieb Christian Gmeiner <
christian.gmeiner@gmail.com>:
> Starting with cpuid level 0x16 (Skylake-based processors)
> it is possible to get CPU base freq via cpuid.
> This fixes booting on a skylake based system.
> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> ---
> drivers/timer/tsc_timer.c | 31 +++++++++++++++++++++++++------
> 1 file changed, 25 insertions(+), 6 deletions(-)
> diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> index c7fefd2031..96a3e55513 100644
> --- a/drivers/timer/tsc_timer.c
> +++ b/drivers/timer/tsc_timer.c
> @@ -21,6 +21,17 @@
> DECLARE_GLOBAL_DATA_PTR;
> +static unsigned long cpu_mhz_from_cpuid(void)
> +{
> + if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
> + return 0;
> +
> + if (cpuid_eax(0) < 0x16)
> + return 0;
> +
> + return cpuid_eax(0x16);
> +}
> +
> /*
> * According to Intel 64 and IA-32 System Programming Guide,
> * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
> @@ -343,14 +354,22 @@ static void tsc_timer_ensure_setup(void)
> if (!gd->arch.clock_rate) {
> unsigned long fast_calibrate;
> + fast_calibrate = cpu_mhz_from_cpuid();
> + if (fast_calibrate)
> + goto done;
> +
> fast_calibrate = cpu_mhz_from_msr();
> - if (!fast_calibrate) {
> - fast_calibrate = quick_pit_calibrate();
> - if (!fast_calibrate)
> - panic("TSC frequency is ZERO");
> - }
> + if (fast_calibrate)
> + goto done;
> +
> + fast_calibrate = quick_pit_calibrate();
> + if (fast_calibrate)
> + goto done;
> +
> + panic("TSC frequency is ZERO");
> - gd->arch.clock_rate = fast_calibrate * 1000000;
> + done:
> + gd->arch.clock_rate = fast_calibrate * 1000000;
> }
> }
> --
> 2.17.0
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] x86: tsc: add support for reading CPU freq from cpuid
2018-05-14 9:32 [U-Boot] [PATCH] x86: tsc: add support for reading CPU freq from cpuid Christian Gmeiner
2018-05-21 15:36 ` Christian Gmeiner
@ 2018-05-23 9:48 ` Bin Meng
2018-05-23 12:01 ` Christian Gmeiner
2018-05-25 3:57 ` Bin Meng
1 sibling, 2 replies; 5+ messages in thread
From: Bin Meng @ 2018-05-23 9:48 UTC (permalink / raw)
To: u-boot
On Mon, May 14, 2018 at 5:32 PM, Christian Gmeiner
<christian.gmeiner@gmail.com> wrote:
> Starting with cpuid level 0x16 (Skylake-based processors)
> it is possible to get CPU base freq via cpuid.
>
> This fixes booting on a skylake based system.
>
> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> ---
> drivers/timer/tsc_timer.c | 31 +++++++++++++++++++++++++------
> 1 file changed, 25 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> index c7fefd2031..96a3e55513 100644
> --- a/drivers/timer/tsc_timer.c
> +++ b/drivers/timer/tsc_timer.c
> @@ -21,6 +21,17 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +static unsigned long cpu_mhz_from_cpuid(void)
> +{
> + if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
> + return 0;
> +
> + if (cpuid_eax(0) < 0x16)
> + return 0;
> +
> + return cpuid_eax(0x16);
> +}
> +
> /*
> * According to Intel 64 and IA-32 System Programming Guide,
> * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
> @@ -343,14 +354,22 @@ static void tsc_timer_ensure_setup(void)
> if (!gd->arch.clock_rate) {
> unsigned long fast_calibrate;
>
> + fast_calibrate = cpu_mhz_from_cpuid();
> + if (fast_calibrate)
> + goto done;
> +
> fast_calibrate = cpu_mhz_from_msr();
> - if (!fast_calibrate) {
> - fast_calibrate = quick_pit_calibrate();
> - if (!fast_calibrate)
> - panic("TSC frequency is ZERO");
> - }
> + if (fast_calibrate)
> + goto done;
> +
> + fast_calibrate = quick_pit_calibrate();
> + if (fast_calibrate)
> + goto done;
> +
> + panic("TSC frequency is ZERO");
>
> - gd->arch.clock_rate = fast_calibrate * 1000000;
> + done:
nits: this indention is wrong, and will cause checkpatch warnings.
> + gd->arch.clock_rate = fast_calibrate * 1000000;
> }
> }
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
I can fix the nits when applying.
Regards,
Bin
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] x86: tsc: add support for reading CPU freq from cpuid
2018-05-23 9:48 ` Bin Meng
@ 2018-05-23 12:01 ` Christian Gmeiner
2018-05-25 3:57 ` Bin Meng
1 sibling, 0 replies; 5+ messages in thread
From: Christian Gmeiner @ 2018-05-23 12:01 UTC (permalink / raw)
To: u-boot
Am Mi., 23. Mai 2018 um 11:48 Uhr schrieb Bin Meng <bmeng.cn@gmail.com>:
> On Mon, May 14, 2018 at 5:32 PM, Christian Gmeiner
> <christian.gmeiner@gmail.com> wrote:
> > Starting with cpuid level 0x16 (Skylake-based processors)
> > it is possible to get CPU base freq via cpuid.
> >
> > This fixes booting on a skylake based system.
> >
> > Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
> > ---
> > drivers/timer/tsc_timer.c | 31 +++++++++++++++++++++++++------
> > 1 file changed, 25 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
> > index c7fefd2031..96a3e55513 100644
> > --- a/drivers/timer/tsc_timer.c
> > +++ b/drivers/timer/tsc_timer.c
> > @@ -21,6 +21,17 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +static unsigned long cpu_mhz_from_cpuid(void)
> > +{
> > + if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
> > + return 0;
> > +
> > + if (cpuid_eax(0) < 0x16)
> > + return 0;
> > +
> > + return cpuid_eax(0x16);
> > +}
> > +
> > /*
> > * According to Intel 64 and IA-32 System Programming Guide,
> > * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
> > @@ -343,14 +354,22 @@ static void tsc_timer_ensure_setup(void)
> > if (!gd->arch.clock_rate) {
> > unsigned long fast_calibrate;
> >
> > + fast_calibrate = cpu_mhz_from_cpuid();
> > + if (fast_calibrate)
> > + goto done;
> > +
> > fast_calibrate = cpu_mhz_from_msr();
> > - if (!fast_calibrate) {
> > - fast_calibrate = quick_pit_calibrate();
> > - if (!fast_calibrate)
> > - panic("TSC frequency is ZERO");
> > - }
> > + if (fast_calibrate)
> > + goto done;
> > +
> > + fast_calibrate = quick_pit_calibrate();
> > + if (fast_calibrate)
> > + goto done;
> > +
> > + panic("TSC frequency is ZERO");
> >
> > - gd->arch.clock_rate = fast_calibrate * 1000000;
> > + done:
> nits: this indention is wrong, and will cause checkpatch warnings.
Oops.
> > + gd->arch.clock_rate = fast_calibrate * 1000000;
> > }
> > }
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> I can fix the nits when applying.
That would be great - thanks!
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] x86: tsc: add support for reading CPU freq from cpuid
2018-05-23 9:48 ` Bin Meng
2018-05-23 12:01 ` Christian Gmeiner
@ 2018-05-25 3:57 ` Bin Meng
1 sibling, 0 replies; 5+ messages in thread
From: Bin Meng @ 2018-05-25 3:57 UTC (permalink / raw)
To: u-boot
On Wed, May 23, 2018 at 5:48 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, May 14, 2018 at 5:32 PM, Christian Gmeiner
> <christian.gmeiner@gmail.com> wrote:
>> Starting with cpuid level 0x16 (Skylake-based processors)
>> it is possible to get CPU base freq via cpuid.
>>
>> This fixes booting on a skylake based system.
>>
>> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
>> ---
>> drivers/timer/tsc_timer.c | 31 +++++++++++++++++++++++++------
>> 1 file changed, 25 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
>> index c7fefd2031..96a3e55513 100644
>> --- a/drivers/timer/tsc_timer.c
>> +++ b/drivers/timer/tsc_timer.c
>> @@ -21,6 +21,17 @@
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> +static unsigned long cpu_mhz_from_cpuid(void)
>> +{
>> + if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
>> + return 0;
>> +
>> + if (cpuid_eax(0) < 0x16)
>> + return 0;
>> +
>> + return cpuid_eax(0x16);
>> +}
>> +
>> /*
>> * According to Intel 64 and IA-32 System Programming Guide,
>> * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
>> @@ -343,14 +354,22 @@ static void tsc_timer_ensure_setup(void)
>> if (!gd->arch.clock_rate) {
>> unsigned long fast_calibrate;
>>
>> + fast_calibrate = cpu_mhz_from_cpuid();
>> + if (fast_calibrate)
>> + goto done;
>> +
>> fast_calibrate = cpu_mhz_from_msr();
>> - if (!fast_calibrate) {
>> - fast_calibrate = quick_pit_calibrate();
>> - if (!fast_calibrate)
>> - panic("TSC frequency is ZERO");
>> - }
>> + if (fast_calibrate)
>> + goto done;
>> +
>> + fast_calibrate = quick_pit_calibrate();
>> + if (fast_calibrate)
>> + goto done;
>> +
>> + panic("TSC frequency is ZERO");
>>
>> - gd->arch.clock_rate = fast_calibrate * 1000000;
>> + done:
>
> nits: this indention is wrong, and will cause checkpatch warnings.
>
>> + gd->arch.clock_rate = fast_calibrate * 1000000;
>> }
>> }
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>
> I can fix the nits when applying.
Fixed the nits and
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-05-25 3:57 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-14 9:32 [U-Boot] [PATCH] x86: tsc: add support for reading CPU freq from cpuid Christian Gmeiner
2018-05-21 15:36 ` Christian Gmeiner
2018-05-23 9:48 ` Bin Meng
2018-05-23 12:01 ` Christian Gmeiner
2018-05-25 3:57 ` Bin Meng
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.