[igt-dev] [PATCH i-g-t v3 0/2] intel: per context powergating tests & benchmark

[igt-dev] [PATCH i-g-t v3 0/2] intel: per context powergating tests & benchmark

[Lionel Landwerlin]

Hi,

This series includes a new tests to verify the new approach in i915
disabling powergating when perf is on.

Cheers,

Lionel Landwerlin (2):
  headers: bump
  tests: add slice power programming test

 include/drm-uapi/amdgpu_drm.h  |   3 +
 include/drm-uapi/drm_mode.h    |   9 +-
 include/drm-uapi/etnaviv_drm.h |   6 +
 include/drm-uapi/i915_drm.h    |  38 ++
 include/drm-uapi/msm_drm.h     |   2 +
 include/drm-uapi/virtgpu_drm.h |   1 +
 tests/Makefile.sources         |   1 +
 tests/gem_ctx_param.c          |   4 +-
 tests/gem_ctx_rpcs.c           | 883 +++++++++++++++++++++++++++++++++
 tests/meson.build              |   1 +
 10 files changed, 944 insertions(+), 4 deletions(-)
 create mode 100644 tests/gem_ctx_rpcs.c

--
2.17.0
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[igt-dev] [PATCH i-g-t v3 1/2] headers: bump

[Lionel Landwerlin]

---
 include/drm-uapi/amdgpu_drm.h  |  3 +++
 include/drm-uapi/drm_mode.h    |  9 +++++---
 include/drm-uapi/etnaviv_drm.h |  6 ++++++
 include/drm-uapi/i915_drm.h    | 38 ++++++++++++++++++++++++++++++++++
 include/drm-uapi/msm_drm.h     |  2 ++
 include/drm-uapi/virtgpu_drm.h |  1 +
 6 files changed, 56 insertions(+), 3 deletions(-)

diff --git a/include/drm-uapi/amdgpu_drm.h b/include/drm-uapi/amdgpu_drm.h
index 1816bd82..c363b67f 100644
--- a/include/drm-uapi/amdgpu_drm.h
+++ b/include/drm-uapi/amdgpu_drm.h
@@ -618,6 +618,8 @@ struct drm_amdgpu_cs_chunk_data {
 	#define AMDGPU_INFO_FW_SOS		0x0c
 	/* Subquery id: Query PSP ASD firmware version */
 	#define AMDGPU_INFO_FW_ASD		0x0d
+	/* Subquery id: Query VCN firmware version */
+	#define AMDGPU_INFO_FW_VCN		0x0e
 /* number of bytes moved for TTM migration */
 #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
 /* the used VRAM size */
@@ -806,6 +808,7 @@ struct drm_amdgpu_info_firmware {
 #define AMDGPU_VRAM_TYPE_GDDR5 5
 #define AMDGPU_VRAM_TYPE_HBM   6
 #define AMDGPU_VRAM_TYPE_DDR3  7
+#define AMDGPU_VRAM_TYPE_DDR4  8
 
 struct drm_amdgpu_info_device {
 	/** PCI Device ID */
diff --git a/include/drm-uapi/drm_mode.h b/include/drm-uapi/drm_mode.h
index 2c575794..50bcf421 100644
--- a/include/drm-uapi/drm_mode.h
+++ b/include/drm-uapi/drm_mode.h
@@ -363,7 +363,7 @@ struct drm_mode_get_connector {
 	__u32 pad;
 };
 
-#define DRM_MODE_PROP_PENDING	(1<<0)
+#define DRM_MODE_PROP_PENDING	(1<<0) /* deprecated, do not use */
 #define DRM_MODE_PROP_RANGE	(1<<1)
 #define DRM_MODE_PROP_IMMUTABLE	(1<<2)
 #define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
@@ -598,8 +598,11 @@ struct drm_mode_crtc_lut {
 };
 
 struct drm_color_ctm {
-	/* Conversion matrix in S31.32 format. */
-	__s64 matrix[9];
+	/*
+	 * Conversion matrix in S31.32 sign-magnitude
+	 * (not two's complement!) format.
+	 */
+	__u64 matrix[9];
 };
 
 struct drm_color_lut {
diff --git a/include/drm-uapi/etnaviv_drm.h b/include/drm-uapi/etnaviv_drm.h
index e9b997a0..0d5c49dc 100644
--- a/include/drm-uapi/etnaviv_drm.h
+++ b/include/drm-uapi/etnaviv_drm.h
@@ -55,6 +55,12 @@ struct drm_etnaviv_timespec {
 #define ETNAVIV_PARAM_GPU_FEATURES_4                0x07
 #define ETNAVIV_PARAM_GPU_FEATURES_5                0x08
 #define ETNAVIV_PARAM_GPU_FEATURES_6                0x09
+#define ETNAVIV_PARAM_GPU_FEATURES_7                0x0a
+#define ETNAVIV_PARAM_GPU_FEATURES_8                0x0b
+#define ETNAVIV_PARAM_GPU_FEATURES_9                0x0c
+#define ETNAVIV_PARAM_GPU_FEATURES_10               0x0d
+#define ETNAVIV_PARAM_GPU_FEATURES_11               0x0e
+#define ETNAVIV_PARAM_GPU_FEATURES_12               0x0f
 
 #define ETNAVIV_PARAM_GPU_STREAM_COUNT              0x10
 #define ETNAVIV_PARAM_GPU_REGISTER_MAX              0x11
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 16e452aa..9ffb6158 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -1456,9 +1456,47 @@ struct drm_i915_gem_context_param {
 #define   I915_CONTEXT_MAX_USER_PRIORITY	1023 /* inclusive */
 #define   I915_CONTEXT_DEFAULT_PRIORITY		0
 #define   I915_CONTEXT_MIN_USER_PRIORITY	-1023 /* inclusive */
+	/*
+	 * When using the following param, value should be a pointer to
+	 * drm_i915_gem_context_param_sseu.
+	 */
+#define I915_CONTEXT_PARAM_SSEU		0x7
 	__u64 value;
 };
 
+struct drm_i915_gem_context_param_sseu {
+	/*
+	 * Engine class & instance to be configured or queried.
+	 */
+	__u32 class;
+	__u32 instance;
+
+	/*
+	 * Mask of slices to enable for the context. Valid values are a subset
+	 * of the bitmask value returned for I915_PARAM_SLICE_MASK.
+	 */
+	__u8 slice_mask;
+
+	/*
+	 * Mask of subslices to enable for the context. Valid values are a
+	 * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
+	 */
+	__u8 subslice_mask;
+
+	/*
+	 * Minimum/Maximum number of EUs to enable per subslice for the
+	 * context. min_eus_per_subslice must be inferior or equal to
+	 * max_eus_per_subslice.
+	 */
+	__u8 min_eus_per_subslice;
+	__u8 max_eus_per_subslice;
+
+	/*
+	 * Unused for now. Must be cleared to zero.
+	 */
+	__u32 rsvd;
+};
+
 enum drm_i915_oa_format {
 	I915_OA_FORMAT_A13 = 1,	    /* HSW only */
 	I915_OA_FORMAT_A29,	    /* HSW only */
diff --git a/include/drm-uapi/msm_drm.h b/include/drm-uapi/msm_drm.h
index bbbaffad..c06d0a5b 100644
--- a/include/drm-uapi/msm_drm.h
+++ b/include/drm-uapi/msm_drm.h
@@ -201,10 +201,12 @@ struct drm_msm_gem_submit_bo {
 #define MSM_SUBMIT_NO_IMPLICIT   0x80000000 /* disable implicit sync */
 #define MSM_SUBMIT_FENCE_FD_IN   0x40000000 /* enable input fence_fd */
 #define MSM_SUBMIT_FENCE_FD_OUT  0x20000000 /* enable output fence_fd */
+#define MSM_SUBMIT_SUDO          0x10000000 /* run submitted cmds from RB */
 #define MSM_SUBMIT_FLAGS                ( \
 		MSM_SUBMIT_NO_IMPLICIT   | \
 		MSM_SUBMIT_FENCE_FD_IN   | \
 		MSM_SUBMIT_FENCE_FD_OUT  | \
+		MSM_SUBMIT_SUDO          | \
 		0)
 
 /* Each cmdstream submit consists of a table of buffers involved, and
diff --git a/include/drm-uapi/virtgpu_drm.h b/include/drm-uapi/virtgpu_drm.h
index 91a31ffe..9a781f06 100644
--- a/include/drm-uapi/virtgpu_drm.h
+++ b/include/drm-uapi/virtgpu_drm.h
@@ -63,6 +63,7 @@ struct drm_virtgpu_execbuffer {
 };
 
 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
+#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
 
 struct drm_virtgpu_getparam {
 	__u64 param;
-- 
2.17.0

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[igt-dev] [PATCH i-g-t v3 2/2] tests: add slice power programming test

[Lionel Landwerlin]

Verifies that the kernel programs slices correctly based by reading
the value of PWR_CLK_STATE register or MI_SET_PREDICATE on platforms
before Cannonlake.

v2: Add subslice tests (Lionel)
    Use MI_SET_PREDICATE for further verification when available (Lionel)

v3: Rename to gem_ctx_rpcs (Lionel)

v4: Update kernel API (Lionel)
    Add 0 value test (Lionel)
    Exercise invalid values (Lionel)

v5: Add perf tests (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/Makefile.sources |   1 +
 tests/gem_ctx_param.c  |   4 +-
 tests/gem_ctx_rpcs.c   | 883 +++++++++++++++++++++++++++++++++++++++++
 tests/meson.build      |   1 +
 4 files changed, 888 insertions(+), 1 deletion(-)
 create mode 100644 tests/gem_ctx_rpcs.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 8066fb1a..11611c88 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -60,6 +60,7 @@ TESTS_progs = \
 	gem_ctx_exec \
 	gem_ctx_isolation \
 	gem_ctx_param \
+	gem_ctx_rpcs \
 	gem_ctx_switch \
 	gem_ctx_thrash \
 	gem_double_irq_loop \
diff --git a/tests/gem_ctx_param.c b/tests/gem_ctx_param.c
index c46fd709..b54eb539 100644
--- a/tests/gem_ctx_param.c
+++ b/tests/gem_ctx_param.c
@@ -294,11 +294,13 @@ igt_main
 			set_priority(fd);
 	}
 
+	/* I915_CONTEXT_PARAM_SSEU tests are located in gem_ctx_rpcs.c */
+
 	/* NOTE: This testcase intentionally tests for the next free parameter
 	 * to catch ABI extensions. Don't "fix" this testcase without adding all
 	 * the tests for the new param first.
 	 */
-	arg.param = I915_CONTEXT_PARAM_PRIORITY + 1;
+	arg.param = I915_CONTEXT_PARAM_SSEU + 1;
 
 	igt_subtest("invalid-param-get") {
 		arg.ctx_id = ctx;
diff --git a/tests/gem_ctx_rpcs.c b/tests/gem_ctx_rpcs.c
new file mode 100644
index 00000000..78a08a57
--- /dev/null
+++ b/tests/gem_ctx_rpcs.c
@@ -0,0 +1,883 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Lionel Landwerlin <lionel.g.landwerlin@intel.com>
+ *
+ */
+
+#include "igt.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <signal.h>
+#include <errno.h>
+#include <time.h>
+#include <sys/wait.h>
+
+#include "intel_bufmgr.h"
+
+IGT_TEST_DESCRIPTION("Test context render powergating programming.");
+
+#define MI_STORE_REGISTER_MEM (0x24 << 23)
+
+#define MI_SET_PREDICATE      (0x1 << 23)
+#define  MI_SET_PREDICATE_NOOP_NEVER (0)
+#define  MI_SET_PREDICATE_1_SLICES   (5)
+#define  MI_SET_PREDICATE_2_SLICES   (6)
+#define  MI_SET_PREDICATE_3_SLICES   (7)
+
+#define GEN8_R_PWR_CLK_STATE		0x20C8
+#define   GEN8_RPCS_ENABLE		(1 << 31)
+#define   GEN8_RPCS_S_CNT_ENABLE	(1 << 18)
+#define   GEN8_RPCS_S_CNT_SHIFT		15
+#define   GEN8_RPCS_S_CNT_MASK		(0x7 << GEN8_RPCS_S_CNT_SHIFT)
+#define   GEN8_RPCS_SS_CNT_ENABLE	(1 << 11)
+#define   GEN8_RPCS_SS_CNT_SHIFT	8
+#define   GEN8_RPCS_SS_CNT_MASK		(0x7 << GEN8_RPCS_SS_CNT_SHIFT)
+#define   GEN8_RPCS_EU_MAX_SHIFT	4
+#define   GEN8_RPCS_EU_MAX_MASK		(0xf << GEN8_RPCS_EU_MAX_SHIFT)
+#define   GEN8_RPCS_EU_MIN_SHIFT	0
+#define   GEN8_RPCS_EU_MIN_MASK		(0xf << GEN8_RPCS_EU_MIN_SHIFT)
+
+#define RCS_TIMESTAMP (0x2000 + 0x358)
+
+static int drm_fd;
+static int devid;
+static uint64_t device_slice_mask = 0;
+static uint64_t device_subslice_mask = 0;
+static uint32_t device_slice_count = 0;
+static uint32_t device_subslice_count = 0;
+
+static uint64_t mask_minus_one(uint64_t mask)
+{
+	int i;
+
+	for (i = 0; i < (sizeof(mask) * 8 - 1); i++) {
+		if ((1UL << i) & mask) {
+			return mask & ~(1UL << i);
+		}
+	}
+
+	igt_assert(!"reached");
+	return 0;
+}
+
+static uint64_t mask_plus_one(uint64_t mask)
+{
+	int i;
+
+	for (i = 0; i < (sizeof(mask) * 8 - 1); i++) {
+		if (((1UL << i) & mask) == 0) {
+			return mask | (1UL << i);
+		}
+	}
+
+	igt_assert(!"reached");
+	return 0;
+}
+
+static uint64_t mask_minus(uint64_t mask, int n)
+{
+	int i;
+
+	for (i = 0; i < n; i++)
+		mask = mask_minus_one(mask);
+
+	return mask;
+}
+
+static uint64_t mask_plus(uint64_t mask, int n)
+{
+	int i;
+
+	for (i = 0; i < n; i++)
+		mask = mask_plus_one(mask);
+
+	return mask;
+}
+
+static uint32_t
+read_rpcs_reg(drm_intel_bufmgr *bufmgr,
+	      drm_intel_context *context,
+	      uint32_t expected_slices)
+{
+	struct intel_batchbuffer *batch;
+	drm_intel_bo *dst_bo;
+	uint32_t rpcs;
+	unsigned dwords = 3 + 3, relocs = 1 + 1;
+	int ret;
+
+	batch = intel_batchbuffer_alloc(bufmgr, devid);
+	igt_assert(batch);
+
+	intel_batchbuffer_set_context(batch, context);
+
+	dst_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
+	igt_assert(dst_bo);
+
+	/* Clear destination buffer. */
+	ret = drm_intel_bo_map(dst_bo, true /* write enable */);
+	igt_assert_eq(ret, 0);
+	memset(dst_bo->virtual, 0, dst_bo->size);
+	drm_intel_bo_unmap(dst_bo);
+
+	/*
+	 * Prior to Gen10 we can use the predicate to further verify
+	 * that the hardware has been programmed correctly.
+	 */
+	if (expected_slices != 0 && intel_gen(devid) < 10) {
+		BEGIN_BATCH(dwords + 2, relocs);
+		OUT_BATCH(MI_SET_PREDICATE | (1 - 1) |
+			  (MI_SET_PREDICATE_1_SLICES + expected_slices - 1));
+	} else {
+		BEGIN_BATCH(dwords, relocs);
+	}
+
+	OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
+	OUT_BATCH(RCS_TIMESTAMP);
+	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
+
+	OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
+	OUT_BATCH(GEN8_R_PWR_CLK_STATE);
+	OUT_RELOC(dst_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 4);
+
+	if (expected_slices != 0 && intel_gen(devid) < 10)
+		OUT_BATCH(MI_SET_PREDICATE | (1 - 1) | MI_SET_PREDICATE_NOOP_NEVER);
+
+	ADVANCE_BATCH();
+
+	intel_batchbuffer_flush_on_ring(batch, I915_EXEC_RENDER);
+
+	drm_intel_bo_wait_rendering(dst_bo);
+
+	ret = drm_intel_bo_map(dst_bo, false /* write enable */);
+	igt_assert_eq(ret, 0);
+
+	uint32_t *ts = (uint32_t *) (dst_bo->virtual);
+
+	rpcs = *((uint32_t *) (dst_bo->virtual + 4));
+
+	igt_debug("rcs_timestamp=0x%x rpcs=0x%x\n", *ts, rpcs);
+
+	drm_intel_bo_unmap(dst_bo);
+
+	drm_intel_bo_unreference(dst_bo);
+
+	intel_batchbuffer_free(batch);
+
+	return rpcs;
+}
+
+static uint32_t
+read_slice_count(drm_intel_bufmgr *bufmgr,
+		 drm_intel_context *context,
+		 uint32_t expected_slice_count)
+{
+	return (read_rpcs_reg(bufmgr, context, expected_slice_count) & GEN8_RPCS_S_CNT_MASK)
+		>> GEN8_RPCS_S_CNT_SHIFT;
+}
+
+static uint32_t
+read_subslice_count(drm_intel_bufmgr *bufmgr,
+		    drm_intel_context *context)
+{
+	return (read_rpcs_reg(bufmgr, context, 0) & GEN8_RPCS_SS_CNT_MASK)
+		>> GEN8_RPCS_SS_CNT_SHIFT;
+}
+
+static bool
+kernel_has_per_context_sseu_support(void)
+{
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context;
+	struct drm_i915_gem_context_param arg;
+	struct drm_i915_gem_context_param_sseu sseu;
+	uint32_t context_id;
+	int ret;
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	igt_assert(bufmgr);
+
+	context = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context);
+
+	ret = drm_intel_gem_context_get_id(context, &context_id);
+	igt_assert_eq(ret, 0);
+
+	memset(&sseu, 0, sizeof(sseu));
+	sseu.class = 0; /* rcs */
+	sseu.instance = 0;
+
+	memset(&arg, 0, sizeof(arg));
+	arg.ctx_id = context_id;
+	arg.param = I915_CONTEXT_PARAM_SSEU;
+	arg.value = (uintptr_t) &sseu;
+
+	if (igt_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg))
+		return false;
+
+	drm_intel_gem_context_destroy(context);
+	drm_intel_bufmgr_destroy(bufmgr);
+
+	return true;
+}
+
+static bool
+platform_has_per_context_sseu_support(void)
+{
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context;
+	struct drm_i915_gem_context_param arg;
+	struct drm_i915_gem_context_param_sseu sseu;
+	uint32_t context_id;
+	int ret;
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	igt_assert(bufmgr);
+
+	context = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context);
+
+	ret = drm_intel_gem_context_get_id(context, &context_id);
+	igt_assert_eq(ret, 0);
+
+	memset(&sseu, 0, sizeof(sseu));
+	sseu.class = 0; /* rcs */
+	sseu.instance = 0;
+
+	memset(&arg, 0, sizeof(arg));
+	arg.ctx_id = context_id;
+	arg.param = I915_CONTEXT_PARAM_SSEU;
+	arg.value = (uintptr_t) &sseu;
+
+	if (igt_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg))
+		return false;
+
+	if (igt_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg))
+		return false;
+
+	drm_intel_gem_context_destroy(context);
+	drm_intel_bufmgr_destroy(bufmgr);
+
+	return true;
+}
+
+static void
+context_get_sseu_masks(drm_intel_context *context,
+		       uint32_t *slice_mask,
+		       uint32_t *subslice_mask)
+{
+	struct drm_i915_gem_context_param arg;
+	struct drm_i915_gem_context_param_sseu sseu;
+	uint32_t context_id;
+	int ret;
+
+	memset(&sseu, 0, sizeof(sseu));
+	sseu.class = 0; /* rcs */
+	sseu.instance = 0;
+
+	ret = drm_intel_gem_context_get_id(context, &context_id);
+	igt_assert_eq(ret, 0);
+
+	memset(&arg, 0, sizeof(arg));
+	arg.ctx_id = context_id;
+	arg.param = I915_CONTEXT_PARAM_SSEU;
+	arg.value = (uintptr_t) &sseu;
+
+	do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
+
+	if (slice_mask)
+		*slice_mask = sseu.slice_mask;
+	if (subslice_mask)
+		*subslice_mask = sseu.subslice_mask;
+}
+
+static void
+context_set_slice_mask(drm_intel_context *context, uint32_t slice_mask)
+{
+	struct drm_i915_gem_context_param arg;
+	struct drm_i915_gem_context_param_sseu sseu;
+	uint32_t context_id;
+	int ret;
+
+	memset(&sseu, 0, sizeof(sseu));
+	sseu.class = 0; /* rcs */
+	sseu.instance = 0;
+
+	ret = drm_intel_gem_context_get_id(context, &context_id);
+	igt_assert_eq(ret, 0);
+
+	memset(&arg, 0, sizeof(arg));
+	arg.ctx_id = context_id;
+	arg.param = I915_CONTEXT_PARAM_SSEU;
+	arg.value = (uintptr_t) &sseu;
+
+	do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
+
+	sseu.slice_mask = slice_mask;
+
+	do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg);
+}
+
+static void
+context_set_subslice_mask(drm_intel_context *context, uint32_t subslice_mask)
+{
+	struct drm_i915_gem_context_param arg;
+	struct drm_i915_gem_context_param_sseu sseu;
+	uint32_t context_id;
+	int ret;
+
+	memset(&sseu, 0, sizeof(sseu));
+	sseu.class = 0; /* rcs */
+	sseu.instance = 0;
+
+	ret = drm_intel_gem_context_get_id(context, &context_id);
+	igt_assert_eq(ret, 0);
+
+	memset(&arg, 0, sizeof(arg));
+	arg.ctx_id = context_id;
+	arg.param = I915_CONTEXT_PARAM_SSEU;
+	arg.value = (uintptr_t) &sseu;
+
+	do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
+
+	sseu.subslice_mask = subslice_mask;
+
+	do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg);
+}
+
+/*
+ * Verify that we can program the slice count.
+ */
+static void
+test_rpcs_slice_program_gt(uint32_t pg_slice_count)
+{
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *pg_contexts[2], *df_contexts[2];
+	uint32_t pg_slice_mask = mask_minus(device_slice_mask, pg_slice_count);
+	uint32_t slice_count = __builtin_popcount(pg_slice_mask);
+	uint32_t slice_mask;
+
+	igt_debug("Running with %i slices powergated\n", pg_slice_count);
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 10 * 4096);
+	igt_assert(bufmgr);
+
+	pg_contexts[0] = drm_intel_gem_context_create(bufmgr);
+	pg_contexts[1] = drm_intel_gem_context_create(bufmgr);
+	df_contexts[0] = drm_intel_gem_context_create(bufmgr);
+	df_contexts[1] = drm_intel_gem_context_create(bufmgr);
+
+	context_set_slice_mask(pg_contexts[0], pg_slice_mask);
+	context_set_slice_mask(pg_contexts[1], pg_slice_mask);
+	context_set_slice_mask(df_contexts[0], device_slice_mask);
+	context_set_slice_mask(df_contexts[1], device_slice_mask);
+
+	for (int i = 0; i < ARRAY_SIZE(pg_contexts); i++) {
+		context_get_sseu_masks(pg_contexts[i], &slice_mask, NULL);
+		igt_assert_eq(pg_slice_mask, slice_mask);
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(df_contexts); i++) {
+		context_get_sseu_masks(df_contexts[i], &slice_mask, NULL);
+		igt_assert_eq(device_slice_mask, slice_mask);
+	}
+
+	/*
+	 * Test false positives with predicates (only available on
+	 * before Gen10).
+	 */
+	if (intel_gen(devid) < 10) {
+		igt_assert_eq(0, read_slice_count(bufmgr, pg_contexts[0],
+						  device_slice_count));
+	}
+
+	igt_debug("pg_contexts:\n");
+	igt_assert_eq(slice_count, read_slice_count(bufmgr, pg_contexts[0],
+						    slice_count));
+	igt_assert_eq(slice_count, read_slice_count(bufmgr, pg_contexts[1],
+						    slice_count));
+	igt_assert_eq(slice_count, read_slice_count(bufmgr, pg_contexts[0],
+						    slice_count));
+	igt_assert_eq(slice_count, read_slice_count(bufmgr, pg_contexts[0],
+						    slice_count));
+
+	igt_debug("df_contexts:\n");
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, df_contexts[0],
+							   device_slice_count));
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, df_contexts[1],
+							   device_slice_count));
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, df_contexts[0],
+							   device_slice_count));
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, df_contexts[0],
+							   device_slice_count));
+
+	igt_debug("mixed:\n");
+	igt_assert_eq(slice_count, read_slice_count(bufmgr, pg_contexts[0],
+						    slice_count));
+
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, df_contexts[0],
+							   device_slice_count));
+
+
+	for (int i = 0; i < ARRAY_SIZE(pg_contexts); i++)
+		drm_intel_gem_context_destroy(pg_contexts[i]);
+	for (int i = 0; i < ARRAY_SIZE(df_contexts); i++)
+		drm_intel_gem_context_destroy(df_contexts[i]);
+
+	drm_intel_bufmgr_destroy(bufmgr);
+}
+
+/*
+ * Verify that we can program the subslice count.
+ */
+static void
+test_rpcs_subslice_program_gt(int pg_subslice_count)
+{
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context1, *context2;
+	uint32_t pg_subslice_mask =
+		mask_minus(device_subslice_mask, pg_subslice_count);
+	uint32_t subslice_count = __builtin_popcount(pg_subslice_mask);
+	uint32_t subslice_mask;
+
+	igt_debug("Running with %i subslices powergated\n", pg_subslice_count);
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	igt_assert(bufmgr);
+
+	context1 = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context1);
+
+	context2 = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context2);
+
+	context_set_subslice_mask(context1, pg_subslice_mask);
+	context_set_subslice_mask(context2, device_subslice_mask);
+
+	context_get_sseu_masks(context1, NULL, &subslice_mask);
+	igt_assert_eq(pg_subslice_mask, subslice_mask);
+	context_get_sseu_masks(context2, NULL, &subslice_mask);
+	igt_assert_eq(device_subslice_mask, subslice_mask);
+
+	igt_assert_eq(subslice_count, read_subslice_count(bufmgr, context1));
+	igt_assert_eq(device_subslice_count, read_subslice_count(bufmgr, context2));
+
+	context_set_subslice_mask(context1, device_subslice_mask);
+	context_set_subslice_mask(context2, pg_subslice_mask);
+
+	context_get_sseu_masks(context1, NULL, &subslice_mask);
+	igt_assert_eq(device_subslice_mask, subslice_mask);
+	context_get_sseu_masks(context2, NULL, &subslice_mask);
+	igt_assert_eq(pg_subslice_mask, subslice_mask);
+
+	igt_assert_eq(device_subslice_count, read_subslice_count(bufmgr, context1));
+	igt_assert_eq(subslice_count, read_subslice_count(bufmgr, context2));
+
+	drm_intel_gem_context_destroy(context1);
+	drm_intel_gem_context_destroy(context2);
+
+	drm_intel_bufmgr_destroy(bufmgr);
+}
+
+/*
+ * Verify that invalid engine class/instance is properly rejected.
+ */
+static void
+test_rpcs_invalid_engine(void)
+{
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context;
+	struct drm_i915_gem_context_param arg;
+	struct drm_i915_gem_context_param_sseu sseu;
+	uint32_t context_id;
+	int ret;
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	igt_assert(bufmgr);
+
+	context = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context);
+
+	memset(&sseu, 0, sizeof(sseu));
+
+	ret = drm_intel_gem_context_get_id(context, &context_id);
+	igt_assert_eq(ret, 0);
+
+	memset(&arg, 0, sizeof(arg));
+	arg.ctx_id = context_id;
+	arg.param = I915_CONTEXT_PARAM_SSEU;
+	arg.value = (uintptr_t) &sseu;
+
+	sseu.class = 0xffffffff; /* invalid */
+	sseu.instance = 0;
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg, EINVAL);
+
+	sseu.class = 0;
+	sseu.instance = 0xffffffff; /* invalid */
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg, EINVAL);
+
+	/*
+	 * Get some proper values before trying to reprogram them onto
+	 * an invalid engine.
+	 */
+	sseu.class = 0;
+	sseu.instance = 0;
+	do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
+
+
+	sseu.class = 0xffffffff; /* invalid */
+	sseu.instance = 0;
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, EINVAL);
+
+	sseu.class = 0;
+	sseu.instance = 0xffffffff; /* invalid */
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, EINVAL);
+
+}
+
+/*
+ * Verify that invalid values are rejected.
+ */
+static void
+test_rpcs_invalid_values(void)
+{
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context;
+	struct drm_i915_gem_context_param arg;
+	struct drm_i915_gem_context_param_sseu default_sseu, sseu;
+	uint32_t context_id;
+	int i, ret;
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	igt_assert(bufmgr);
+
+	context = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context);
+
+	ret = drm_intel_gem_context_get_id(context, &context_id);
+	igt_assert_eq(ret, 0);
+
+	memset(&sseu, 0, sizeof(sseu));
+	default_sseu.class = 0; /* rcs */
+	default_sseu.instance = 0;
+
+	memset(&arg, 0, sizeof(arg));
+	arg.ctx_id = context_id;
+	arg.param = I915_CONTEXT_PARAM_SSEU;
+	arg.value = (uintptr_t) &default_sseu;
+
+	do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
+
+	arg.value = (uintptr_t) &sseu;
+
+	/* Try all slice masks known to be invalid. */
+	sseu = default_sseu;
+	for (i = 1; i <= (8 - device_slice_count); i++) {
+		sseu.slice_mask = mask_plus(device_slice_mask, i);
+		do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, EINVAL);
+	}
+
+	/* 0 slices. */
+	sseu.slice_mask = 0;
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, EINVAL);
+
+	/* Try all subslice masks known to be invalid. */
+	sseu = default_sseu;
+	for (i = 1; i <= (8 - device_subslice_count); i++) {
+		sseu.subslice_mask = mask_plus(device_subslice_mask, i);
+		do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, EINVAL);
+	}
+
+	/* 0 subslices. */
+	sseu.subslice_mask = 0;
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, EINVAL);
+
+	/* Try number of EUs superior to the max available. */
+	sseu = default_sseu;
+	sseu.min_eus_per_subslice = default_sseu.max_eus_per_subslice + 1;
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, EINVAL);
+
+	sseu = default_sseu;
+	sseu.max_eus_per_subslice = default_sseu.max_eus_per_subslice + 1;
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, EINVAL);
+
+	/* Try to program 0 max EUs. */
+	sseu = default_sseu;
+	sseu.max_eus_per_subslice = 0;
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, EINVAL);
+
+
+	drm_intel_gem_context_destroy(context);
+	drm_intel_bufmgr_destroy(bufmgr);
+}
+
+/* Verify that the kernel returns a correct error value on Gen < 8. */
+static void
+test_no_rpcs_support(void)
+{
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context;
+	struct drm_i915_gem_context_param arg;
+	struct drm_i915_gem_context_param_sseu sseu;
+	uint32_t context_id;
+	int ret;
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	igt_assert(bufmgr);
+
+	context = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context);
+
+	ret = drm_intel_gem_context_get_id(context, &context_id);
+	igt_assert_eq(ret, 0);
+
+	memset(&sseu, 0, sizeof(sseu));
+	sseu.class = 0; /* rcs */
+	sseu.instance = 0;
+
+	memset(&arg, 0, sizeof(arg));
+	arg.ctx_id = context_id;
+	arg.param = I915_CONTEXT_PARAM_SSEU;
+	arg.value = (uintptr_t) &sseu;
+
+	do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
+
+	do_ioctl_err(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg, ENODEV);
+
+	drm_intel_gem_context_destroy(context);
+	drm_intel_bufmgr_destroy(bufmgr);
+}
+
+static void
+init_contexts(drm_intel_bufmgr *bufmgr,
+	      drm_intel_context **contexts,
+	      int n_contexts,
+	      uint32_t device_slice_mask,
+	      uint32_t pg_slice_mask)
+{
+	int i;
+
+	for (i = 0; i < n_contexts; i++)
+		contexts[i] = drm_intel_gem_context_create(bufmgr);
+
+	context_set_slice_mask(contexts[0], device_slice_mask);
+	context_set_slice_mask(contexts[1], pg_slice_mask);
+}
+
+/*
+ * Verify that powergating settings are put on hold while i915/perf is
+ * active.
+ */
+static void
+test_rpcs_perf(void)
+{
+	uint64_t properties[] = {
+		/* Include OA reports in samples */
+		DRM_I915_PERF_PROP_SAMPLE_OA, true,
+
+		/* OA unit configuration */
+		DRM_I915_PERF_PROP_OA_METRICS_SET, 1, /* test metric */
+		DRM_I915_PERF_PROP_OA_FORMAT, I915_OA_FORMAT_A32u40_A4u32_B8_C8,
+		DRM_I915_PERF_PROP_OA_EXPONENT, 20,
+	};
+	struct drm_i915_perf_open_param param = {
+		.flags = I915_PERF_FLAG_FD_CLOEXEC |
+		I915_PERF_FLAG_FD_NONBLOCK,
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *contexts[2];
+	uint32_t pg_slice_mask = mask_minus(device_slice_mask, 1);
+	uint32_t slice_count = __builtin_popcount(pg_slice_mask);
+	int perf_fd;
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 10 * 4096);
+	igt_assert(bufmgr);
+
+	init_contexts(bufmgr, contexts, 2, device_slice_mask, pg_slice_mask);
+
+	/*
+	 * Test false positives with predicates (only available on
+	 * before Gen10).
+	 */
+	if (intel_gen(devid) < 10) {
+		igt_assert_eq(0, read_slice_count(bufmgr, contexts[1],
+						  device_slice_count));
+	}
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, contexts[0],
+							   device_slice_count));
+	igt_assert_eq(slice_count, read_slice_count(bufmgr, contexts[1],
+						    slice_count));
+
+	/*
+	 * Now open i915/perf and verify that all contexts have been
+	 * reconfigured to the device's default.
+	 */
+	perf_fd = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, &param);
+	igt_assert(perf_fd >= 0);
+
+	if (intel_gen(devid) < 10) {
+		igt_assert_eq(0, read_slice_count(bufmgr, contexts[1], slice_count));
+	}
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, contexts[0],
+							   device_slice_count));
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, contexts[1],
+							   device_slice_count));
+
+	close(perf_fd);
+
+	/*
+	 * After closing the perf stream, configurations should be
+	 * back to the programmed values.
+	 */
+	if (intel_gen(devid) < 10) {
+		igt_assert_eq(0, read_slice_count(bufmgr, contexts[1],
+						  device_slice_count));
+	}
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, contexts[0],
+							   device_slice_count));
+	igt_assert_eq(slice_count, read_slice_count(bufmgr, contexts[1],
+						    slice_count));
+
+	for (int i = 0; i < ARRAY_SIZE(contexts); i++)
+		drm_intel_gem_context_destroy(contexts[i]);
+
+
+
+	/*
+	 * Open i915/perf first and verify that all contexts created
+	 * afterward are reconfigured to the device's default.
+	 */
+	perf_fd = igt_ioctl(drm_fd, DRM_IOCTL_I915_PERF_OPEN, &param);
+	igt_assert(perf_fd >= 0);
+
+	init_contexts(bufmgr, contexts, 2, device_slice_mask, pg_slice_mask);
+
+	/*
+	 * Check the device's default values, despite setting
+	 * otherwise.
+	 */
+	if (intel_gen(devid) < 10) {
+		igt_assert_eq(0, read_slice_count(bufmgr, contexts[1],
+						  slice_count));
+	}
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, contexts[0],
+							   device_slice_count));
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, contexts[1],
+							   device_slice_count));
+
+	close(perf_fd);
+
+	/*
+	 * After closing the perf stream, configurations should be
+	 * back to the programmed values.
+	 */
+	if (intel_gen(devid) < 10) {
+		igt_assert_eq(0, read_slice_count(bufmgr, contexts[1],
+						  device_slice_count));
+	}
+	igt_assert_eq(device_slice_count, read_slice_count(bufmgr, contexts[0],
+							   device_slice_count));
+	igt_assert_eq(slice_count, read_slice_count(bufmgr, contexts[1],
+						    slice_count));
+
+	drm_intel_bufmgr_destroy(bufmgr);
+}
+
+igt_main
+{
+	int i, max_slices = 3, max_subslices = 3;
+	drm_i915_getparam_t gp;
+
+	igt_fixture {
+		/* Use drm_open_driver to verify device existence */
+		drm_fd = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(drm_fd);
+
+		devid = intel_get_drm_devid(drm_fd);
+
+		/* Old kernel? */
+		igt_require(kernel_has_per_context_sseu_support());
+
+		gp.param = I915_PARAM_SLICE_MASK;
+		gp.value = (int *) &device_slice_mask;
+		do_ioctl(drm_fd, DRM_IOCTL_I915_GETPARAM, &gp);
+		device_slice_count = __builtin_popcount(device_slice_mask);
+
+		gp.param = I915_PARAM_SUBSLICE_MASK;
+		gp.value = (int *) &device_subslice_mask;
+		do_ioctl(drm_fd, DRM_IOCTL_I915_GETPARAM, &gp);
+		device_subslice_count = __builtin_popcount(device_subslice_mask);
+	}
+
+	igt_subtest("no-rpcs-support") {
+		igt_require(!platform_has_per_context_sseu_support());
+		test_no_rpcs_support();
+	}
+
+	igt_subtest("rpcs-invalid-engine") {
+		igt_require(platform_has_per_context_sseu_support());
+		test_rpcs_invalid_engine();
+	}
+
+	igt_subtest("rpcs-invalid-values") {
+		igt_require(platform_has_per_context_sseu_support());
+		test_rpcs_invalid_values();
+	}
+
+	for (i = 1; i < max_slices; i++) {
+		igt_subtest_f("rpcs-%i-pg-slice-program-rcs", i) {
+			igt_require(device_slice_count > i);
+			igt_require(platform_has_per_context_sseu_support());
+
+			test_rpcs_slice_program_gt(i);
+		}
+	}
+
+	for (i = 1; i < max_subslices; i++) {
+		igt_subtest_f("rpcs-%i-pg-subslice-program-rcs", i) {
+			igt_require(device_subslice_count >= 2);
+			igt_require(platform_has_per_context_sseu_support());
+
+			/* Only available on some Atom platforms and Gen10+. */
+			igt_require(IS_BROXTON(devid) || IS_GEMINILAKE(devid) ||
+				    intel_gen(devid) >= 10);
+
+			test_rpcs_subslice_program_gt(i);
+		}
+	}
+
+	igt_subtest("rpcs-perf") {
+		igt_require(platform_has_per_context_sseu_support());
+		igt_require(device_slice_count > 1);
+		test_rpcs_perf();
+	}
+
+	igt_fixture {
+		close(drm_fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 1f00fc4f..983d8fcc 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -37,6 +37,7 @@ test_progs = [
 	'gem_ctx_exec',
 	'gem_ctx_isolation',
 	'gem_ctx_param',
+	'gem_ctx_rpcs',
 	'gem_ctx_switch',
 	'gem_ctx_thrash',
 	'gem_double_irq_loop',
-- 
2.17.0

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[igt-dev] ✓ Fi.CI.BAT: success for intel: per context powergating tests & benchmark (rev3)

[Patchwork]

== Series Details ==

Series: intel: per context powergating tests & benchmark (rev3)
URL   : https://patchwork.freedesktop.org/series/42286/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4178 -> IGTPW_1357 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42286/revisions/3/mbox/

== Known issues ==

  Here are the changes found in IGTPW_1357 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-skl-6770hq:      PASS -> FAIL (fdo#103928, fdo#100368)

    igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
      fi-skl-6770hq:      PASS -> FAIL (fdo#103481)

    
    ==== Possible fixes ====

    igt@drv_module_reload@basic-reload:
      fi-glk-j4005:       DMESG-WARN (fdo#106248) -> PASS

    igt@kms_busy@basic-flip-c:
      fi-glk-j4005:       DMESG-WARN (fdo#106097) -> PASS +2

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103481 https://bugs.freedesktop.org/show_bug.cgi?id=103481
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248


== Participating hosts (41 -> 37) ==

  Missing    (4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq 


== Build changes ==

    * IGT: IGT_4478 -> IGTPW_1357
    * Piglit: piglit_4478 -> piglit_4479

  CI_DRM_4178: 8213a085ddd82871fab4bf94d1a3555fcdf9e6ac @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1357: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1357/
  IGT_4478: b871b10f2a6250d6dbe31665b267820fee829c84 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4478: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
  piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit



== Testlist changes ==

+igt@gem_ctx_rpcs@no-rpcs-support
+igt@gem_ctx_rpcs@rpcs-1-pg-slice-program-rcs
+igt@gem_ctx_rpcs@rpcs-1-pg-subslice-program-rcs
+igt@gem_ctx_rpcs@rpcs-2-pg-slice-program-rcs
+igt@gem_ctx_rpcs@rpcs-2-pg-subslice-program-rcs
+igt@gem_ctx_rpcs@rpcs-invalid-engine
+igt@gem_ctx_rpcs@rpcs-invalid-values
+igt@gem_ctx_rpcs@rpcs-perf

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1357/issues.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✗ Fi.CI.IGT: failure for intel: per context powergating tests & benchmark (rev3)

[Patchwork]

== Series Details ==

Series: intel: per context powergating tests & benchmark (rev3)
URL   : https://patchwork.freedesktop.org/series/42286/
State : failure

== Summary ==

= CI Bug Log - changes from IGT_4478_full -> IGTPW_1357_full =

== Summary - FAILURE ==

  Serious unknown changes coming with IGTPW_1357_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_1357_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42286/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1357_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@gem_eio@in-flight-1us:
      shard-apl:          PASS -> DMESG-WARN +3

    igt@gem_eio@throttle:
      shard-glk:          PASS -> DMESG-WARN

    igt@gem_eio@wait-wedge-immediate:
      shard-hsw:          PASS -> DMESG-WARN

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
      shard-glk:          PASS -> FAIL

    
== Known issues ==

  Here are the changes found in IGTPW_1357_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
      shard-glk:          PASS -> FAIL (fdo#105707)

    igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#100368) +1

    igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#103928) +1

    igt@kms_flip_tiling@flip-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#103822, fdo#104724) +1

    
    ==== Possible fixes ====

    igt@gem_eio@in-flight-internal-10ms:
      shard-glk:          DMESG-WARN -> PASS

    igt@gem_eio@suspend:
      shard-apl:          DMESG-WARN -> PASS +3

    igt@kms_flip@blocking-wf_vblank:
      shard-glk:          FAIL (fdo#100368) -> PASS

    igt@kms_flip@modeset-vs-vblank-race:
      shard-hsw:          FAIL (fdo#103060) -> PASS +1

    igt@kms_flip@plain-flip-fb-recreate:
      shard-hsw:          FAIL (fdo#100368) -> PASS

    igt@kms_flip_tiling@flip-y-tiled:
      shard-glk:          FAIL (fdo#104724) -> PASS

    igt@kms_rotation_crc@sprite-rotation-180:
      shard-snb:          FAIL (fdo#103925, fdo#104724) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707


== Participating hosts (5 -> 4) ==

  Missing    (1): shard-kbl 


== Build changes ==

    * IGT: IGT_4478 -> IGTPW_1357
    * Linux: CI_DRM_4177 -> CI_DRM_4178
    * Piglit: piglit_4478 -> piglit_4479

  CI_DRM_4177: 2a481dd2c319c85c0233d292c5d08a8dce0784cd @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_4178: 8213a085ddd82871fab4bf94d1a3555fcdf9e6ac @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1357: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1357/
  IGT_4478: b871b10f2a6250d6dbe31665b267820fee829c84 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4478: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
  piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1357/shards.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✓ Fi.CI.BAT: success for intel: per context powergating tests & benchmark (rev3)

[Patchwork]

== Series Details ==

Series: intel: per context powergating tests & benchmark (rev3)
URL   : https://patchwork.freedesktop.org/series/42286/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4182 -> IGTPW_1360 =

== Summary - WARNING ==

  Minor unknown changes coming with IGTPW_1360 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_1360, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42286/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1360:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        SKIP -> PASS

    
== Known issues ==

  Here are the changes found in IGTPW_1360 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      {fi-bsw-cyan}:      PASS -> FAIL (fdo#103928)
      fi-cnl-psr:         PASS -> FAIL (fdo#100368)
      fi-skl-6770hq:      PASS -> FAIL (fdo#103928, fdo#100368)

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       PASS -> DMESG-FAIL (fdo#102614, fdo#106103)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-ctg-p8600:       PASS -> INCOMPLETE (fdo#102997)

    igt@kms_psr_sink_crc@basic:
      fi-hsw-4200u:       NOTRUN -> FAIL (fdo#106346)

    
    ==== Possible fixes ====

    igt@kms_chamelium@dp-crc-fast:
      fi-kbl-7500u:       DMESG-FAIL (fdo#103841) -> PASS

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-cfl-s3:          FAIL (fdo#103928, fdo#100368) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102997 https://bugs.freedesktop.org/show_bug.cgi?id=102997
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
  fdo#106346 https://bugs.freedesktop.org/show_bug.cgi?id=106346


== Participating hosts (42 -> 42) ==

  No changes in participating hosts


== Build changes ==

    * IGT: IGT_4479 -> IGTPW_1360
    * Piglit: piglit_4479 -> piglit_4480

  CI_DRM_4182: 74146e495c113f6cf8721bb55feec6b459199cd4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1360: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1360/
  IGT_4479: 89ae332745e31a075747a63ac5acc5baccf75769 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
  piglit_4480: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit



== Testlist changes ==

+igt@gem_ctx_rpcs@no-rpcs-support
+igt@gem_ctx_rpcs@rpcs-1-pg-slice-program-rcs
+igt@gem_ctx_rpcs@rpcs-1-pg-subslice-program-rcs
+igt@gem_ctx_rpcs@rpcs-2-pg-slice-program-rcs
+igt@gem_ctx_rpcs@rpcs-2-pg-subslice-program-rcs
+igt@gem_ctx_rpcs@rpcs-invalid-engine
+igt@gem_ctx_rpcs@rpcs-invalid-values
+igt@gem_ctx_rpcs@rpcs-perf

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1360/issues.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✓ Fi.CI.IGT: success for intel: per context powergating tests & benchmark (rev3)

[Patchwork]

== Series Details ==

Series: intel: per context powergating tests & benchmark (rev3)
URL   : https://patchwork.freedesktop.org/series/42286/
State : success

== Summary ==

= CI Bug Log - changes from IGT_4479_full -> IGTPW_1360_full =

== Summary - WARNING ==

  Minor unknown changes coming with IGTPW_1360_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_1360_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42286/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1360_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_shrink@reclaim:
      shard-glk:          PASS -> SKIP
      shard-apl:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in IGTPW_1360_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_gtt:
      shard-glk:          PASS -> INCOMPLETE (k.org#198133, fdo#103359)

    igt@gem_eio@in-flight-internal-1us:
      shard-glk:          PASS -> DMESG-WARN (fdo#106523)

    igt@gem_eio@suspend:
      shard-apl:          PASS -> DMESG-WARN (fdo#106523) +2

    igt@kms_cursor_legacy@flip-vs-cursor-atomic:
      shard-hsw:          PASS -> FAIL (fdo#102670)

    igt@kms_flip@dpms-vs-vblank-race:
      shard-glk:          PASS -> FAIL (fdo#103060)

    igt@kms_flip@plain-flip-fb-recreate-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#103928)

    igt@kms_flip_tiling@flip-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724)

    igt@kms_flip_tiling@flip-y-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724, fdo#103822)

    
    ==== Possible fixes ====

    igt@gem_eio@hibernate:
      shard-hsw:          DMESG-WARN (fdo#106523) -> PASS +6

    igt@gem_eio@in-flight-contexts-1us:
      shard-apl:          DMESG-WARN (fdo#106523) -> PASS +3

    igt@gem_eio@in-flight-internal-immediate:
      shard-glk:          DMESG-WARN (fdo#106523) -> PASS +8

    igt@gem_eio@unwedge-stress:
      shard-snb:          DMESG-WARN (fdo#106523) -> PASS +6

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
      shard-glk:          FAIL (fdo#105703) -> PASS

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          FAIL (fdo#105454) -> PASS

    igt@kms_flip@plain-flip-fb-recreate-interruptible:
      shard-glk:          FAIL (fdo#100368) -> PASS +1

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-glk:          FAIL (fdo#104724) -> PASS

    igt@kms_flip_tiling@flip-to-y-tiled:
      shard-glk:          FAIL (fdo#104724, fdo#103822) -> PASS

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106523 https://bugs.freedesktop.org/show_bug.cgi?id=106523
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 4) ==

  Missing    (1): shard-kbl 


== Build changes ==

    * IGT: IGT_4479 -> IGTPW_1360
    * Linux: CI_DRM_4178 -> CI_DRM_4182
    * Piglit: piglit_4479 -> piglit_4480

  CI_DRM_4178: 8213a085ddd82871fab4bf94d1a3555fcdf9e6ac @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_4182: 74146e495c113f6cf8721bb55feec6b459199cd4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1360: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1360/
  IGT_4479: 89ae332745e31a075747a63ac5acc5baccf75769 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
  piglit_4480: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1360/shards.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
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