* [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits
@ 2018-05-14 17:24 Ville Syrjala
2018-05-14 17:24 ` [PATCH 2/5] drm/i915: Clean up LVDS " Ville Syrjala
` (9 more replies)
0 siblings, 10 replies; 14+ messages in thread
From: Ville Syrjala @ 2018-05-14 17:24 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Clean up the ADPA pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state()
and the port state asserts.
v2: Order the defines shift,mask,value (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++++-----
drivers/gpu/drm/i915/intel_crt.c | 40 ++++++++++++++++++------------------
drivers/gpu/drm/i915/intel_display.c | 24 +++++-----------------
drivers/gpu/drm/i915/intel_drv.h | 2 ++
4 files changed, 33 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f11bb213ec07..ae3c26216996 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4133,11 +4133,12 @@ enum {
#define ADPA_DAC_ENABLE (1<<31)
#define ADPA_DAC_DISABLE 0
-#define ADPA_PIPE_SELECT_MASK (1<<30)
-#define ADPA_PIPE_A_SELECT 0
-#define ADPA_PIPE_B_SELECT (1<<30)
-#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
-/* CPT uses bits 29:30 for pch transcoder select */
+#define ADPA_PIPE_SEL_SHIFT 30
+#define ADPA_PIPE_SEL_MASK (1<<30)
+#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
+#define ADPA_PIPE_SEL_SHIFT_CPT 29
+#define ADPA_PIPE_SEL_MASK_CPT (3<<29)
+#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index de0e22322c76..211d601cd1b1 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -63,33 +63,35 @@ static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
return intel_encoder_to_crt(intel_attached_encoder(connector));
}
+bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+ i915_reg_t adpa_reg, enum pipe *pipe)
+{
+ u32 val;
+
+ val = I915_READ(adpa_reg);
+
+ /* asserts want to know the pipe even if the port is disabled */
+ if (HAS_PCH_CPT(dev_priv))
+ *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
+ else
+ *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
+
+ return val & ADPA_DAC_ENABLE;
+}
+
static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
- u32 tmp;
bool ret;
if (!intel_display_power_get_if_enabled(dev_priv,
encoder->power_domain))
return false;
- ret = false;
-
- tmp = I915_READ(crt->adpa_reg);
-
- if (!(tmp & ADPA_DAC_ENABLE))
- goto out;
+ ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
- if (HAS_PCH_CPT(dev_priv))
- *pipe = PORT_TO_PIPE_CPT(tmp);
- else
- *pipe = PORT_TO_PIPE(tmp);
-
- ret = true;
-out:
intel_display_power_put(dev_priv, encoder->power_domain);
return ret;
@@ -168,11 +170,9 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
if (HAS_PCH_LPT(dev_priv))
; /* Those bits don't exist here */
else if (HAS_PCH_CPT(dev_priv))
- adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
- else if (crtc->pipe == 0)
- adpa |= ADPA_PIPE_A_SELECT;
+ adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
else
- adpa |= ADPA_PIPE_B_SELECT;
+ adpa |= ADPA_PIPE_SEL(crtc->pipe);
if (!HAS_PCH_SPLIT(dev_priv))
I915_WRITE(BCLRPAT(crtc->pipe), 0);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ad588d564198..6daa8d97a0aa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1360,21 +1360,6 @@ static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
return true;
}
-static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, u32 val)
-{
- if ((val & ADPA_DAC_ENABLE) == 0)
- return false;
- if (HAS_PCH_CPT(dev_priv)) {
- if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
- return false;
- } else {
- if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
- return false;
- }
- return true;
-}
-
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe, i915_reg_t reg,
u32 port_sel)
@@ -1405,16 +1390,17 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
+ enum pipe port_pipe;
u32 val;
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
- val = I915_READ(PCH_ADPA);
- I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
- "PCH VGA enabled on transcoder %c, should be disabled\n",
- pipe_name(pipe));
+ I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
+ port_pipe == pipe,
+ "PCH VGA enabled on transcoder %c, should be disabled\n",
+ pipe_name(pipe));
val = I915_READ(PCH_LVDS);
I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d7dbca1aabff..423795050970 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1377,6 +1377,8 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
/* intel_crt.c */
+bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+ i915_reg_t adpa_reg, enum pipe *pipe);
void intel_crt_init(struct drm_i915_private *dev_priv);
void intel_crt_reset(struct drm_encoder *encoder);
--
2.16.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/5] drm/i915: Clean up LVDS pipe select bits
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
@ 2018-05-14 17:24 ` Ville Syrjala
2018-05-14 18:28 ` [PATCH v3 " Ville Syrjala
2018-05-14 17:24 ` [PATCH 3/5] drm/i915: Clean up SDVO " Ville Syrjala
` (8 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjala @ 2018-05-14 17:24 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Clean up the LVDS pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state()
and the port state asserts.
v2: Order the defines shift,mask,value (Jani)
Drop ruperfluous braces and whitesapce changes (Jani)
Combine masks in compute_is_dual_link_lvds() (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 ++++---
drivers/gpu/drm/i915/intel_display.c | 33 +++++------------------
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_lvds.c | 52 +++++++++++++++++++-----------------
4 files changed, 42 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae3c26216996..2953fc2717fc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4392,9 +4392,12 @@ enum {
*/
#define LVDS_PORT_EN (1 << 31)
/* Selects pipe B for LVDS data. Must be set on pre-965. */
-#define LVDS_PIPEB_SELECT (1 << 30)
-#define LVDS_PIPE_MASK (1 << 30)
-#define LVDS_PIPE(pipe) ((pipe) << 30)
+#define LVDS_PIPE_SEL_SHIFT 30
+#define LVDS_PIPE_SEL_MASK (1 << 30)
+#define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
+#define LVDS_PIPE_SEL_SHIFT_CPT 29
+#define LVDS_PIPE_SEL_MASK_CPT (3 << 30)
+#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
/* LVDS dithering flag on 965/g4x platform */
#define LVDS_ENABLE_DITHER (1 << 25)
/* LVDS sync polarity flags. Set to invert (i.e. negative) */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6daa8d97a0aa..a1c6cc75f49c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1214,9 +1214,8 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
pp_reg = PP_CONTROL(0);
port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
- if (port_sel == PANEL_PORT_SELECT_LVDS &&
- I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
- panel_pipe = PIPE_B;
+ if (port_sel == PANEL_PORT_SELECT_LVDS)
+ intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
/* XXX: else fix for eDP */
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
/* presumably write lock depends on pipe, not port select */
@@ -1224,8 +1223,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
panel_pipe = pipe;
} else {
pp_reg = PP_CONTROL(0);
- if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
- panel_pipe = PIPE_B;
+ intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
}
val = I915_READ(pp_reg);
@@ -1344,22 +1342,6 @@ static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
return true;
}
-static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, u32 val)
-{
- if ((val & LVDS_PORT_EN) == 0)
- return false;
-
- if (HAS_PCH_CPT(dev_priv)) {
- if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
- return false;
- } else {
- if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
- return false;
- }
- return true;
-}
-
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe, i915_reg_t reg,
u32 port_sel)
@@ -1391,7 +1373,6 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
enum pipe port_pipe;
- u32 val;
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
@@ -1402,10 +1383,10 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
"PCH VGA enabled on transcoder %c, should be disabled\n",
pipe_name(pipe));
- val = I915_READ(PCH_LVDS);
- I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
- "PCH LVDS enabled on transcoder %c, should be disabled\n",
- pipe_name(pipe));
+ I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
+ port_pipe == pipe,
+ "PCH LVDS enabled on transcoder %c, should be disabled\n",
+ pipe_name(pipe));
assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 423795050970..911d4960ba7a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1824,6 +1824,8 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
/* intel_lvds.c */
+bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
+ i915_reg_t lvds_reg, enum pipe *pipe);
void intel_lvds_init(struct drm_i915_private *dev_priv);
struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
bool intel_is_dual_link_lvds(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 8691c86f579c..cc4cc8669af3 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -85,34 +85,35 @@ static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *conn
return container_of(connector, struct intel_lvds_connector, base.base);
}
+bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
+ i915_reg_t lvds_reg, enum pipe *pipe)
+{
+ u32 val;
+
+ val = I915_READ(lvds_reg);
+
+ /* asserts want to know the pipe even if the port is disabled */
+ if (HAS_PCH_CPT(dev_priv))
+ *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
+ else
+ *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
+
+ return val & LVDS_PORT_EN;
+}
+
static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
- u32 tmp;
bool ret;
if (!intel_display_power_get_if_enabled(dev_priv,
encoder->power_domain))
return false;
- ret = false;
+ ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
- tmp = I915_READ(lvds_encoder->reg);
-
- if (!(tmp & LVDS_PORT_EN))
- goto out;
-
- if (HAS_PCH_CPT(dev_priv))
- *pipe = PORT_TO_PIPE_CPT(tmp);
- else
- *pipe = PORT_TO_PIPE(tmp);
-
- ret = true;
-
-out:
intel_display_power_put(dev_priv, encoder->power_domain);
return ret;
@@ -255,14 +256,11 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
if (HAS_PCH_CPT(dev_priv)) {
- temp &= ~PORT_TRANS_SEL_MASK;
- temp |= PORT_TRANS_SEL_CPT(pipe);
+ temp &= ~LVDS_PIPE_SEL_MASK_CPT;
+ temp |= LVDS_PIPE_SEL_CPT(pipe);
} else {
- if (pipe == 1) {
- temp |= LVDS_PIPEB_SELECT;
- } else {
- temp &= ~LVDS_PIPEB_SELECT;
- }
+ temp &= ~LVDS_PIPE_SEL_MASK;
+ temp |= LVDS_PIPE_SEL(pipe);
}
/* set the corresponsding LVDS_BORDER bit */
@@ -908,7 +906,11 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
* register is uninitialized.
*/
val = I915_READ(lvds_encoder->reg);
- if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
+ if (HAS_PCH_CPT(dev_priv))
+ val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
+ else
+ val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
+ if (val == 0)
val = dev_priv->vbt.bios_lvds_val;
return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
--
2.16.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/5] drm/i915: Clean up SDVO pipe select bits
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
2018-05-14 17:24 ` [PATCH 2/5] drm/i915: Clean up LVDS " Ville Syrjala
@ 2018-05-14 17:24 ` Ville Syrjala
2018-05-14 17:24 ` [PATCH 4/5] drm/i915: Clean up TV " Ville Syrjala
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjala @ 2018-05-14 17:24 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Clean up the SDVO pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state()
and the port state asserts.
v2: Order the defines shift,mask,value (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++----
drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++-----------------------
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_hdmi.c | 25 ++++----------------
drivers/gpu/drm/i915/intel_sdvo.c | 38 ++++++++++++++++++-----------
5 files changed, 52 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2953fc2717fc..560168517918 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4297,9 +4297,9 @@ enum {
/* Gen 3 SDVO bits: */
#define SDVO_ENABLE (1 << 31)
-#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
+#define SDVO_PIPE_SEL_SHIFT 30
#define SDVO_PIPE_SEL_MASK (1 << 30)
-#define SDVO_PIPE_B_SELECT (1 << 30)
+#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
#define SDVO_STALL_SELECT (1 << 29)
#define SDVO_INTERRUPT_ENABLE (1 << 26)
/*
@@ -4339,12 +4339,14 @@ enum {
#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
/* Gen 6 (CPT) SDVO/HDMI bits: */
-#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
+#define SDVO_PIPE_SEL_SHIFT_CPT 29
#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
+#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
/* CHV SDVO/HDMI bits: */
-#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
+#define SDVO_PIPE_SEL_SHIFT_CHV 24
#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
+#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
/* DVO port control */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a1c6cc75f49c..817d5d3f65eb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1323,25 +1323,6 @@ static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
return true;
}
-static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, u32 val)
-{
- if ((val & SDVO_ENABLE) == 0)
- return false;
-
- if (HAS_PCH_CPT(dev_priv)) {
- if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
- return false;
- } else if (IS_CHERRYVIEW(dev_priv)) {
- if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
- return false;
- } else {
- if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
- return false;
- }
- return true;
-}
-
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe, i915_reg_t reg,
u32 port_sel)
@@ -1357,16 +1338,21 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
}
static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, i915_reg_t reg)
+ enum pipe pipe, enum port port,
+ i915_reg_t hdmi_reg)
{
- u32 val = I915_READ(reg);
- I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
- "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
- i915_mmio_reg_offset(reg), pipe_name(pipe));
+ enum pipe port_pipe;
+ bool state;
+
+ state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
+
+ I915_STATE_WARN(state && port_pipe == pipe,
+ "PCH HDMI %c enabled on transcoder %c, should be disabled\n",
+ port_name(port), pipe_name(pipe));
- I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
- && (val & SDVO_PIPE_B_SELECT),
- "IBX PCH hdmi port still using transcoder B\n");
+ I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
+ "IBX PCH HDMI %c still using transcoder B\n",
+ port_name(port));
}
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
@@ -1388,9 +1374,9 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
"PCH LVDS enabled on transcoder %c, should be disabled\n",
pipe_name(pipe));
- assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
- assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
- assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC);
+ assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID);
}
static void _vlv_enable_pll(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 911d4960ba7a..12002fc77235 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2064,6 +2064,8 @@ void intel_init_ipc(struct drm_i915_private *dev_priv);
void intel_enable_ipc(struct drm_i915_private *dev_priv);
/* intel_sdvo.c */
+bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
+ i915_reg_t sdvo_reg, enum pipe *pipe);
bool intel_sdvo_init(struct drm_i915_private *dev_priv,
i915_reg_t reg, enum port port);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index ee929f31f7db..ba5ea61fb7b9 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1161,33 +1161,16 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder,
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
- u32 tmp;
bool ret;
if (!intel_display_power_get_if_enabled(dev_priv,
encoder->power_domain))
return false;
- ret = false;
-
- tmp = I915_READ(intel_hdmi->hdmi_reg);
-
- if (!(tmp & SDVO_ENABLE))
- goto out;
-
- if (HAS_PCH_CPT(dev_priv))
- *pipe = PORT_TO_PIPE_CPT(tmp);
- else if (IS_CHERRYVIEW(dev_priv))
- *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
- else
- *pipe = PORT_TO_PIPE(tmp);
-
- ret = true;
+ ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
-out:
intel_display_power_put(dev_priv, encoder->power_domain);
return ret;
@@ -1421,8 +1404,8 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
- temp &= ~SDVO_PIPE_B_SELECT;
- temp |= SDVO_ENABLE;
+ temp &= ~SDVO_PIPE_SEL_MASK;
+ temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
/*
* HW workaround, need to write this twice for issue
* that may result in first write getting masked.
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 25005023c243..a02e4d73c7a4 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1403,27 +1403,37 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
return false;
}
+bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
+ i915_reg_t sdvo_reg, enum pipe *pipe)
+{
+ u32 val;
+
+ val = I915_READ(sdvo_reg);
+
+ /* asserts want to know the pipe even if the port is disabled */
+ if (HAS_PCH_CPT(dev_priv))
+ *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
+ else if (IS_CHERRYVIEW(dev_priv))
+ *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
+ else
+ *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
+
+ return val & SDVO_ENABLE;
+}
+
static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
u16 active_outputs = 0;
- u32 tmp;
+ bool ret;
- tmp = I915_READ(intel_sdvo->sdvo_reg);
intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
- if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
- return false;
-
- if (HAS_PCH_CPT(dev_priv))
- *pipe = PORT_TO_PIPE_CPT(tmp);
- else
- *pipe = PORT_TO_PIPE(tmp);
+ ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
- return true;
+ return ret || active_outputs;
}
static void intel_sdvo_get_config(struct intel_encoder *encoder,
@@ -1550,8 +1560,8 @@ static void intel_disable_sdvo(struct intel_encoder *encoder,
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
- temp &= ~SDVO_PIPE_B_SELECT;
- temp |= SDVO_ENABLE;
+ temp &= ~SDVO_PIPE_SEL_MASK;
+ temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
intel_sdvo_write_sdvox(intel_sdvo, temp);
temp &= ~SDVO_ENABLE;
--
2.16.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/5] drm/i915: Clean up TV pipe select bits
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
2018-05-14 17:24 ` [PATCH 2/5] drm/i915: Clean up LVDS " Ville Syrjala
2018-05-14 17:24 ` [PATCH 3/5] drm/i915: Clean up SDVO " Ville Syrjala
@ 2018-05-14 17:24 ` Ville Syrjala
2018-05-14 17:24 ` [PATCH 5/5] drm/i915: Clean up DVO " Ville Syrjala
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjala @ 2018-05-14 17:24 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Parametrize the TV pipe select bits.
For consistency with the new way of doing things, let's read out the
pipe select bits even when the port is disable, even though we don't
need that behaviour for asserts in this case.
v2: Order the defines shift,mask,value (Jani)
Clear the stale pipe select bit in load detection (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_tv.c | 20 ++++++--------------
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 560168517918..fd77d013c640 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4696,7 +4696,9 @@ enum {
/* Enables the TV encoder */
# define TV_ENC_ENABLE (1 << 31)
/* Sources the TV encoder input from pipe B instead of A. */
-# define TV_ENC_PIPEB_SELECT (1 << 30)
+# define TV_ENC_PIPE_SEL_SHIFT 30
+# define TV_ENC_PIPE_SEL_MASK (1 << 30)
+# define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30)
/* Outputs composite video (DAC A only) */
# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
/* Outputs SVideo video (DAC B/C) */
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 885fc3809f7f..99bc2368dda0 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -798,16 +798,12 @@ static struct intel_tv *intel_attached_tv(struct drm_connector *connector)
static bool
intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
u32 tmp = I915_READ(TV_CTL);
- if (!(tmp & TV_ENC_ENABLE))
- return false;
+ *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
- *pipe = PORT_TO_PIPE(tmp);
-
- return true;
+ return tmp & TV_ENC_ENABLE;
}
static void
@@ -1024,8 +1020,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder,
break;
}
- if (intel_crtc->pipe == 1)
- tv_ctl |= TV_ENC_PIPEB_SELECT;
+ tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);
tv_ctl |= tv_mode->oversample;
if (tv_mode->progressive)
@@ -1149,12 +1144,9 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
/* Poll for TV detection */
- tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK);
+ tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
- if (intel_crtc->pipe == 1)
- tv_ctl |= TV_ENC_PIPEB_SELECT;
- else
- tv_ctl &= ~TV_ENC_PIPEB_SELECT;
+ tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);
tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
tv_dac |= (TVDAC_STATE_CHG_EN |
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/5] drm/i915: Clean up DVO pipe select bits
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
` (2 preceding siblings ...)
2018-05-14 17:24 ` [PATCH 4/5] drm/i915: Clean up TV " Ville Syrjala
@ 2018-05-14 17:24 ` Ville Syrjala
2018-05-14 17:48 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Clean up ADPA " Patchwork
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjala @ 2018-05-14 17:24 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Parametrize the DVO pipe select bits.
For consistency with the new way of doing things, let's read out the
pipe select bits even when the port is disable, even though we don't
need that behaviour for asserts in this case.
v2: Order the defines shift,mask,value (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_dvo.c | 13 ++++---------
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fd77d013c640..9b57632be7dd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4357,7 +4357,9 @@ enum {
#define _DVOC 0x61160
#define DVOC _MMIO(_DVOC)
#define DVO_ENABLE (1 << 31)
-#define DVO_PIPE_B_SELECT (1 << 30)
+#define DVO_PIPE_SEL_SHIFT 30
+#define DVO_PIPE_SEL_MASK (1 << 30)
+#define DVO_PIPE_SEL(pipe) ((pipe) << 30)
#define DVO_PIPE_STALL_UNUSED (0 << 28)
#define DVO_PIPE_STALL (1 << 28)
#define DVO_PIPE_STALL_TV (2 << 28)
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index eb0c559b2715..a86f0398570f 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -137,19 +137,15 @@ static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
u32 tmp;
tmp = I915_READ(intel_dvo->dev.dvo_reg);
- if (!(tmp & DVO_ENABLE))
- return false;
-
- *pipe = PORT_TO_PIPE(tmp);
+ *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
- return true;
+ return tmp & DVO_ENABLE;
}
static void intel_dvo_get_config(struct intel_encoder *encoder,
@@ -276,8 +272,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder,
dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
DVO_BLANK_ACTIVE_HIGH;
- if (pipe == 1)
- dvo_val |= DVO_PIPE_B_SELECT;
+ dvo_val |= DVO_PIPE_SEL(pipe);
dvo_val |= DVO_PIPE_STALL;
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Clean up ADPA pipe select bits
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
` (3 preceding siblings ...)
2018-05-14 17:24 ` [PATCH 5/5] drm/i915: Clean up DVO " Ville Syrjala
@ 2018-05-14 17:48 ` Patchwork
2018-05-14 18:03 ` ✗ Fi.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-05-14 17:48 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915: Clean up ADPA pipe select bits
URL : https://patchwork.freedesktop.org/series/43151/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
afd2d93c4687 drm/i915: Clean up ADPA pipe select bits
-:32: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#32: FILE: drivers/gpu/drm/i915/i915_reg.h:4137:
+#define ADPA_PIPE_SEL_MASK (1<<30)
^
-:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:4140:
+#define ADPA_PIPE_SEL_MASK_CPT (3<<29)
^
total: 0 errors, 0 warnings, 2 checks, 131 lines checked
17bebe27c017 drm/i915: Clean up LVDS pipe select bits
be3c8193750e drm/i915: Clean up SDVO pipe select bits
0b3a16eec107 drm/i915: Clean up TV pipe select bits
c634a7255d97 drm/i915: Clean up DVO pipe select bits
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Clean up ADPA pipe select bits
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
` (4 preceding siblings ...)
2018-05-14 17:48 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Clean up ADPA " Patchwork
@ 2018-05-14 18:03 ` Patchwork
2018-05-14 18:51 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2) Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-05-14 18:03 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915: Clean up ADPA pipe select bits
URL : https://patchwork.freedesktop.org/series/43151/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4179 -> Patchwork_8996 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_8996 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8996, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43151/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8996:
=== IGT changes ===
==== Possible regressions ====
igt@core_auth@basic-auth:
fi-ivb-3520m: PASS -> INCOMPLETE
==== Warnings ====
igt@gem_exec_gttfill@basic:
fi-pnv-d510: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_8996 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@core_auth@basic-auth:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
==== Possible fixes ====
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: DMESG-WARN (fdo#105128) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2600: DMESG-WARN (fdo#102365) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
== Participating hosts (41 -> 37) ==
Additional (1): fi-byt-j1900
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4179 -> Patchwork_8996
CI_DRM_4179: be6d36ea8d6130f54ab5ec816555f1a46bd95f7b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4479: 89ae332745e31a075747a63ac5acc5baccf75769 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8996: c634a7255d9797834b6e7db10e43ec971a9517f1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
== Linux commits ==
c634a7255d97 drm/i915: Clean up DVO pipe select bits
0b3a16eec107 drm/i915: Clean up TV pipe select bits
be3c8193750e drm/i915: Clean up SDVO pipe select bits
17bebe27c017 drm/i915: Clean up LVDS pipe select bits
afd2d93c4687 drm/i915: Clean up ADPA pipe select bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8996/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v3 2/5] drm/i915: Clean up LVDS pipe select bits
2018-05-14 17:24 ` [PATCH 2/5] drm/i915: Clean up LVDS " Ville Syrjala
@ 2018-05-14 18:28 ` Ville Syrjala
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjala @ 2018-05-14 18:28 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Clean up the LVDS pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state()
and the port state asserts.
v2: Order the defines shift,mask,value (Jani)
Drop ruperfluous braces and whitesapce changes (Jani)
Combine masks in compute_is_dual_link_lvds() (Jani)
v3: Fix LVDS_PIPE_SEL_MASK_CPT
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 9 ++++---
drivers/gpu/drm/i915/intel_display.c | 33 +++++------------------
drivers/gpu/drm/i915/intel_drv.h | 2 ++
drivers/gpu/drm/i915/intel_lvds.c | 52 +++++++++++++++++++-----------------
4 files changed, 42 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae3c26216996..753b8f110e2e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4392,9 +4392,12 @@ enum {
*/
#define LVDS_PORT_EN (1 << 31)
/* Selects pipe B for LVDS data. Must be set on pre-965. */
-#define LVDS_PIPEB_SELECT (1 << 30)
-#define LVDS_PIPE_MASK (1 << 30)
-#define LVDS_PIPE(pipe) ((pipe) << 30)
+#define LVDS_PIPE_SEL_SHIFT 30
+#define LVDS_PIPE_SEL_MASK (1 << 30)
+#define LVDS_PIPE_SEL(pipe) ((pipe) << 30)
+#define LVDS_PIPE_SEL_SHIFT_CPT 29
+#define LVDS_PIPE_SEL_MASK_CPT (3 << 29)
+#define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29)
/* LVDS dithering flag on 965/g4x platform */
#define LVDS_ENABLE_DITHER (1 << 25)
/* LVDS sync polarity flags. Set to invert (i.e. negative) */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6daa8d97a0aa..a1c6cc75f49c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1214,9 +1214,8 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
pp_reg = PP_CONTROL(0);
port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
- if (port_sel == PANEL_PORT_SELECT_LVDS &&
- I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
- panel_pipe = PIPE_B;
+ if (port_sel == PANEL_PORT_SELECT_LVDS)
+ intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe);
/* XXX: else fix for eDP */
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
/* presumably write lock depends on pipe, not port select */
@@ -1224,8 +1223,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
panel_pipe = pipe;
} else {
pp_reg = PP_CONTROL(0);
- if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
- panel_pipe = PIPE_B;
+ intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe);
}
val = I915_READ(pp_reg);
@@ -1344,22 +1342,6 @@ static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
return true;
}
-static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, u32 val)
-{
- if ((val & LVDS_PORT_EN) == 0)
- return false;
-
- if (HAS_PCH_CPT(dev_priv)) {
- if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
- return false;
- } else {
- if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
- return false;
- }
- return true;
-}
-
static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe, i915_reg_t reg,
u32 port_sel)
@@ -1391,7 +1373,6 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
enum pipe port_pipe;
- u32 val;
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
@@ -1402,10 +1383,10 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
"PCH VGA enabled on transcoder %c, should be disabled\n",
pipe_name(pipe));
- val = I915_READ(PCH_LVDS);
- I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
- "PCH LVDS enabled on transcoder %c, should be disabled\n",
- pipe_name(pipe));
+ I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&
+ port_pipe == pipe,
+ "PCH LVDS enabled on transcoder %c, should be disabled\n",
+ pipe_name(pipe));
assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 423795050970..911d4960ba7a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1824,6 +1824,8 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
/* intel_lvds.c */
+bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
+ i915_reg_t lvds_reg, enum pipe *pipe);
void intel_lvds_init(struct drm_i915_private *dev_priv);
struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
bool intel_is_dual_link_lvds(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 8691c86f579c..cc4cc8669af3 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -85,34 +85,35 @@ static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *conn
return container_of(connector, struct intel_lvds_connector, base.base);
}
+bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
+ i915_reg_t lvds_reg, enum pipe *pipe)
+{
+ u32 val;
+
+ val = I915_READ(lvds_reg);
+
+ /* asserts want to know the pipe even if the port is disabled */
+ if (HAS_PCH_CPT(dev_priv))
+ *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
+ else
+ *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
+
+ return val & LVDS_PORT_EN;
+}
+
static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
- u32 tmp;
bool ret;
if (!intel_display_power_get_if_enabled(dev_priv,
encoder->power_domain))
return false;
- ret = false;
+ ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
- tmp = I915_READ(lvds_encoder->reg);
-
- if (!(tmp & LVDS_PORT_EN))
- goto out;
-
- if (HAS_PCH_CPT(dev_priv))
- *pipe = PORT_TO_PIPE_CPT(tmp);
- else
- *pipe = PORT_TO_PIPE(tmp);
-
- ret = true;
-
-out:
intel_display_power_put(dev_priv, encoder->power_domain);
return ret;
@@ -255,14 +256,11 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder,
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
if (HAS_PCH_CPT(dev_priv)) {
- temp &= ~PORT_TRANS_SEL_MASK;
- temp |= PORT_TRANS_SEL_CPT(pipe);
+ temp &= ~LVDS_PIPE_SEL_MASK_CPT;
+ temp |= LVDS_PIPE_SEL_CPT(pipe);
} else {
- if (pipe == 1) {
- temp |= LVDS_PIPEB_SELECT;
- } else {
- temp &= ~LVDS_PIPEB_SELECT;
- }
+ temp &= ~LVDS_PIPE_SEL_MASK;
+ temp |= LVDS_PIPE_SEL(pipe);
}
/* set the corresponsding LVDS_BORDER bit */
@@ -908,7 +906,11 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
* register is uninitialized.
*/
val = I915_READ(lvds_encoder->reg);
- if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
+ if (HAS_PCH_CPT(dev_priv))
+ val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
+ else
+ val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
+ if (val == 0)
val = dev_priv->vbt.bios_lvds_val;
return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2)
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
` (5 preceding siblings ...)
2018-05-14 18:03 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2018-05-14 18:51 ` Patchwork
2018-05-15 2:47 ` ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-05-14 18:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2)
URL : https://patchwork.freedesktop.org/series/43151/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
eedc0c805469 drm/i915: Clean up ADPA pipe select bits
-:32: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#32: FILE: drivers/gpu/drm/i915/i915_reg.h:4137:
+#define ADPA_PIPE_SEL_MASK (1<<30)
^
-:35: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:4140:
+#define ADPA_PIPE_SEL_MASK_CPT (3<<29)
^
total: 0 errors, 0 warnings, 2 checks, 131 lines checked
4791448a0def drm/i915: Clean up LVDS pipe select bits
2e5e4eaeb9da drm/i915: Clean up SDVO pipe select bits
077d5e8b84ad drm/i915: Clean up TV pipe select bits
004ffb58f527 drm/i915: Clean up DVO pipe select bits
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2)
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
` (6 preceding siblings ...)
2018-05-14 18:51 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2) Patchwork
@ 2018-05-15 2:47 ` Patchwork
2018-05-15 14:56 ` Ville Syrjälä
2018-05-15 14:33 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-17 9:31 ` [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Jani Nikula
9 siblings, 1 reply; 14+ messages in thread
From: Patchwork @ 2018-05-15 2:47 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2)
URL : https://patchwork.freedesktop.org/series/43151/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4179_full -> Patchwork_8997_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_8997_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_8997_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43151/revisions/2/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_8997_full:
=== IGT changes ===
==== Possible regressions ====
igt@gem_eio@in-flight-contexts-1us:
shard-apl: PASS -> DMESG-WARN +1
igt@gem_eio@unwedge-stress:
shard-glk: PASS -> DMESG-WARN +1
shard-snb: PASS -> DMESG-WARN +1
igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
shard-glk: PASS -> FAIL
==== Warnings ====
igt@gem_mocs_settings@mocs-rc6-blt:
shard-kbl: PASS -> SKIP
igt@gem_mocs_settings@mocs-rc6-dirty-render:
shard-kbl: SKIP -> PASS +1
== Known issues ==
Here are the changes found in Patchwork_8997_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_ppgtt@blt-vs-render-ctxn:
shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665)
igt@kms_3d:
shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558)
igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
shard-hsw: PASS -> FAIL (fdo#105707)
igt@kms_flip@basic-flip-vs-wf_vblank:
shard-hsw: PASS -> FAIL (fdo#103928)
igt@kms_flip@flip-vs-wf_vblank-interruptible:
shard-hsw: PASS -> FAIL (fdo#100368) +1
igt@kms_flip@plain-flip-fb-recreate-interruptible:
shard-glk: PASS -> FAIL (fdo#100368) +1
igt@kms_flip_tiling@flip-to-y-tiled:
shard-glk: PASS -> FAIL (fdo#104724)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103313, fdo#103558) +7
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
shard-kbl: PASS -> DMESG-WARN (fdo#106247)
igt@kms_frontbuffer_tracking@fbc-suspend:
shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558, fdo#103841)
igt@kms_setmode@basic:
shard-kbl: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@drv_suspend@fence-restore-untiled:
shard-glk: DMESG-WARN -> PASS +2
igt@gem_eio@in-flight-1us:
shard-hsw: DMESG-WARN -> PASS
igt@gem_eio@in-flight-suspend:
shard-snb: DMESG-WARN -> PASS
igt@gem_eio@wait-wedge-10ms:
shard-apl: DMESG-WARN -> PASS +1
igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
shard-glk: FAIL -> PASS +3
igt@kms_cursor_crc@cursor-64x21-sliding:
shard-kbl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +4
igt@kms_cursor_legacy@flip-vs-cursor-legacy:
shard-hsw: FAIL (fdo#102670) -> PASS
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-glk: FAIL (fdo#105363) -> PASS
igt@kms_flip_tiling@flip-y-tiled:
shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-snb: FAIL (fdo#103166, fdo#104724) -> PASS
igt@perf@polling:
shard-hsw: FAIL (fdo#102252) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4179 -> Patchwork_8997
CI_DRM_4179: be6d36ea8d6130f54ab5ec816555f1a46bd95f7b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4479: 89ae332745e31a075747a63ac5acc5baccf75769 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8997: 004ffb58f52776d11f993197577ea98baa95a019 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8997/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2)
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
` (7 preceding siblings ...)
2018-05-15 2:47 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-05-15 14:33 ` Patchwork
2018-05-17 9:31 ` [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Jani Nikula
9 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2018-05-15 14:33 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2)
URL : https://patchwork.freedesktop.org/series/43151/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4179 -> Patchwork_8997 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43151/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_8997 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-FAIL (fdo#106103, fdo#102614)
==== Possible fixes ====
igt@debugfs_test@read_all_entries:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: DMESG-WARN (fdo#105128) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2600: DMESG-WARN (fdo#102365) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103
== Participating hosts (41 -> 37) ==
Additional (1): fi-byt-j1900
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4179 -> Patchwork_8997
CI_DRM_4179: be6d36ea8d6130f54ab5ec816555f1a46bd95f7b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4479: 89ae332745e31a075747a63ac5acc5baccf75769 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_8997: 004ffb58f52776d11f993197577ea98baa95a019 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
== Linux commits ==
004ffb58f527 drm/i915: Clean up DVO pipe select bits
077d5e8b84ad drm/i915: Clean up TV pipe select bits
2e5e4eaeb9da drm/i915: Clean up SDVO pipe select bits
4791448a0def drm/i915: Clean up LVDS pipe select bits
eedc0c805469 drm/i915: Clean up ADPA pipe select bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8997/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2)
2018-05-15 2:47 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-05-15 14:56 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2018-05-15 14:56 UTC (permalink / raw)
To: intel-gfx
On Tue, May 15, 2018 at 02:47:48AM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2)
> URL : https://patchwork.freedesktop.org/series/43151/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4179_full -> Patchwork_8997_full =
>
> == Summary - FAILURE ==
>
> Serious unknown changes coming with Patchwork_8997_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_8997_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://patchwork.freedesktop.org/api/1.0/series/43151/revisions/2/mbox/
>
> == Possible new issues ==
>
> Here are the unknown changes that may have been introduced in Patchwork_8997_full:
>
> === IGT changes ===
>
> ==== Possible regressions ====
>
> igt@gem_eio@in-flight-contexts-1us:
> shard-apl: PASS -> DMESG-WARN +1
>
> igt@gem_eio@unwedge-stress:
> shard-glk: PASS -> DMESG-WARN +1
> shard-snb: PASS -> DMESG-WARN +1
kthread_park() WARNs from -rc5.
>
> igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
> shard-glk: PASS -> FAIL
(kms_cursor_legacy:4524) CRITICAL: Test assertion failure function two_screens_flip_vs_cursor, file ../tests/kms_cursor_legacy.c:1013:
(kms_cursor_legacy:4524) CRITICAL: Failed assertion: vblank_matches
(kms_cursor_legacy:4524) CRITICAL: Last errno: 25, Inappropriate ioctl for device
(kms_cursor_legacy:4524) CRITICAL: During modeset at least 1 page flip needs to match!
Looks ping-pongy already on glk.
>
>
> ==== Warnings ====
>
> igt@gem_mocs_settings@mocs-rc6-blt:
> shard-kbl: PASS -> SKIP
Test requirement not met in function rc6_wait, file ../tests/gem_mocs_settings.c:346:
Test requirement: igt_wait(rc6_residency(sysfs) != residency, 10000, 2)
Nothing in these look relevant for these patches.
>
> igt@gem_mocs_settings@mocs-rc6-dirty-render:
> shard-kbl: SKIP -> PASS +1
>
>
> == Known issues ==
>
> Here are the changes found in Patchwork_8997_full that come from known issues:
>
> === IGT changes ===
>
> ==== Issues hit ====
>
> igt@gem_ppgtt@blt-vs-render-ctxn:
> shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665)
>
> igt@kms_3d:
> shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558)
>
> igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
> shard-hsw: PASS -> FAIL (fdo#105707)
>
> igt@kms_flip@basic-flip-vs-wf_vblank:
> shard-hsw: PASS -> FAIL (fdo#103928)
>
> igt@kms_flip@flip-vs-wf_vblank-interruptible:
> shard-hsw: PASS -> FAIL (fdo#100368) +1
>
> igt@kms_flip@plain-flip-fb-recreate-interruptible:
> shard-glk: PASS -> FAIL (fdo#100368) +1
>
> igt@kms_flip_tiling@flip-to-y-tiled:
> shard-glk: PASS -> FAIL (fdo#104724)
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
> shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103313, fdo#103558) +7
>
> igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
> shard-kbl: PASS -> DMESG-WARN (fdo#106247)
>
> igt@kms_frontbuffer_tracking@fbc-suspend:
> shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558, fdo#103841)
>
> igt@kms_setmode@basic:
> shard-kbl: PASS -> FAIL (fdo#99912)
>
>
> ==== Possible fixes ====
>
> igt@drv_suspend@fence-restore-untiled:
> shard-glk: DMESG-WARN -> PASS +2
>
> igt@gem_eio@in-flight-1us:
> shard-hsw: DMESG-WARN -> PASS
>
> igt@gem_eio@in-flight-suspend:
> shard-snb: DMESG-WARN -> PASS
>
> igt@gem_eio@wait-wedge-10ms:
> shard-apl: DMESG-WARN -> PASS +1
>
> igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
> shard-glk: FAIL -> PASS +3
>
> igt@kms_cursor_crc@cursor-64x21-sliding:
> shard-kbl: DMESG-WARN (fdo#105602, fdo#103558) -> PASS +4
>
> igt@kms_cursor_legacy@flip-vs-cursor-legacy:
> shard-hsw: FAIL (fdo#102670) -> PASS
>
> igt@kms_flip@2x-flip-vs-expired-vblank:
> shard-glk: FAIL (fdo#105363) -> PASS
>
> igt@kms_flip_tiling@flip-y-tiled:
> shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS
>
> igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
> shard-snb: FAIL (fdo#103166, fdo#104724) -> PASS
>
> igt@perf@polling:
> shard-hsw: FAIL (fdo#102252) -> PASS
>
>
> fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
> fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
> fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
> fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
> fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
> fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
> fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
> fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
> fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
> fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
> fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
> fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
> fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
> fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
> fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
> fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
> fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
>
>
> == Participating hosts (5 -> 5) ==
>
> No changes in participating hosts
>
>
> == Build changes ==
>
> * Linux: CI_DRM_4179 -> Patchwork_8997
>
> CI_DRM_4179: be6d36ea8d6130f54ab5ec816555f1a46bd95f7b @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_4479: 89ae332745e31a075747a63ac5acc5baccf75769 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_8997: 004ffb58f52776d11f993197577ea98baa95a019 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8997/shards.html
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits
2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
` (8 preceding siblings ...)
2018-05-15 14:33 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-05-17 9:31 ` Jani Nikula
2018-05-17 17:03 ` Ville Syrjälä
9 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2018-05-17 9:31 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Mon, 14 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Clean up the ADPA pipe select bits. To make the whole situation a bit
> less ugly we'll start to share the same code between .get_hw_state()
> and the port state asserts.
>
> v2: Order the defines shift,mask,value (Jani)
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Yup, the series looks good.
BR,
Jani.
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 +++++-----
> drivers/gpu/drm/i915/intel_crt.c | 40 ++++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_display.c | 24 +++++-----------------
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 4 files changed, 33 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f11bb213ec07..ae3c26216996 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4133,11 +4133,12 @@ enum {
>
> #define ADPA_DAC_ENABLE (1<<31)
> #define ADPA_DAC_DISABLE 0
> -#define ADPA_PIPE_SELECT_MASK (1<<30)
> -#define ADPA_PIPE_A_SELECT 0
> -#define ADPA_PIPE_B_SELECT (1<<30)
> -#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
> -/* CPT uses bits 29:30 for pch transcoder select */
> +#define ADPA_PIPE_SEL_SHIFT 30
> +#define ADPA_PIPE_SEL_MASK (1<<30)
> +#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
> +#define ADPA_PIPE_SEL_SHIFT_CPT 29
> +#define ADPA_PIPE_SEL_MASK_CPT (3<<29)
> +#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
> #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
> #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
> #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index de0e22322c76..211d601cd1b1 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -63,33 +63,35 @@ static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
> return intel_encoder_to_crt(intel_attached_encoder(connector));
> }
>
> +bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> + i915_reg_t adpa_reg, enum pipe *pipe)
> +{
> + u32 val;
> +
> + val = I915_READ(adpa_reg);
> +
> + /* asserts want to know the pipe even if the port is disabled */
> + if (HAS_PCH_CPT(dev_priv))
> + *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
> + else
> + *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
> +
> + return val & ADPA_DAC_ENABLE;
> +}
> +
> static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
> enum pipe *pipe)
> {
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crt *crt = intel_encoder_to_crt(encoder);
> - u32 tmp;
> bool ret;
>
> if (!intel_display_power_get_if_enabled(dev_priv,
> encoder->power_domain))
> return false;
>
> - ret = false;
> -
> - tmp = I915_READ(crt->adpa_reg);
> -
> - if (!(tmp & ADPA_DAC_ENABLE))
> - goto out;
> + ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
>
> - if (HAS_PCH_CPT(dev_priv))
> - *pipe = PORT_TO_PIPE_CPT(tmp);
> - else
> - *pipe = PORT_TO_PIPE(tmp);
> -
> - ret = true;
> -out:
> intel_display_power_put(dev_priv, encoder->power_domain);
>
> return ret;
> @@ -168,11 +170,9 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
> if (HAS_PCH_LPT(dev_priv))
> ; /* Those bits don't exist here */
> else if (HAS_PCH_CPT(dev_priv))
> - adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
> - else if (crtc->pipe == 0)
> - adpa |= ADPA_PIPE_A_SELECT;
> + adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
> else
> - adpa |= ADPA_PIPE_B_SELECT;
> + adpa |= ADPA_PIPE_SEL(crtc->pipe);
>
> if (!HAS_PCH_SPLIT(dev_priv))
> I915_WRITE(BCLRPAT(crtc->pipe), 0);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ad588d564198..6daa8d97a0aa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1360,21 +1360,6 @@ static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
> return true;
> }
>
> -static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
> - enum pipe pipe, u32 val)
> -{
> - if ((val & ADPA_DAC_ENABLE) == 0)
> - return false;
> - if (HAS_PCH_CPT(dev_priv)) {
> - if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
> - return false;
> - } else {
> - if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
> - return false;
> - }
> - return true;
> -}
> -
> static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
> enum pipe pipe, i915_reg_t reg,
> u32 port_sel)
> @@ -1405,16 +1390,17 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
> static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> + enum pipe port_pipe;
> u32 val;
>
> assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
> assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
> assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
>
> - val = I915_READ(PCH_ADPA);
> - I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
> - "PCH VGA enabled on transcoder %c, should be disabled\n",
> - pipe_name(pipe));
> + I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
> + port_pipe == pipe,
> + "PCH VGA enabled on transcoder %c, should be disabled\n",
> + pipe_name(pipe));
>
> val = I915_READ(PCH_LVDS);
> I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d7dbca1aabff..423795050970 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1377,6 +1377,8 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
> void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
>
> /* intel_crt.c */
> +bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> + i915_reg_t adpa_reg, enum pipe *pipe);
> void intel_crt_init(struct drm_i915_private *dev_priv);
> void intel_crt_reset(struct drm_encoder *encoder);
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits
2018-05-17 9:31 ` [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Jani Nikula
@ 2018-05-17 17:03 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2018-05-17 17:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, May 17, 2018 at 12:31:59PM +0300, Jani Nikula wrote:
> On Mon, 14 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Clean up the ADPA pipe select bits. To make the whole situation a bit
> > less ugly we'll start to share the same code between .get_hw_state()
> > and the port state asserts.
> >
> > v2: Order the defines shift,mask,value (Jani)
> >
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Yup, the series looks good.
Cool. Pushed to dinq.
>
> BR,
> Jani.
>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 11 +++++-----
> > drivers/gpu/drm/i915/intel_crt.c | 40 ++++++++++++++++++------------------
> > drivers/gpu/drm/i915/intel_display.c | 24 +++++-----------------
> > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > 4 files changed, 33 insertions(+), 44 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f11bb213ec07..ae3c26216996 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4133,11 +4133,12 @@ enum {
> >
> > #define ADPA_DAC_ENABLE (1<<31)
> > #define ADPA_DAC_DISABLE 0
> > -#define ADPA_PIPE_SELECT_MASK (1<<30)
> > -#define ADPA_PIPE_A_SELECT 0
> > -#define ADPA_PIPE_B_SELECT (1<<30)
> > -#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
> > -/* CPT uses bits 29:30 for pch transcoder select */
> > +#define ADPA_PIPE_SEL_SHIFT 30
> > +#define ADPA_PIPE_SEL_MASK (1<<30)
> > +#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
> > +#define ADPA_PIPE_SEL_SHIFT_CPT 29
> > +#define ADPA_PIPE_SEL_MASK_CPT (3<<29)
> > +#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
> > #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
> > #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
> > #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
> > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> > index de0e22322c76..211d601cd1b1 100644
> > --- a/drivers/gpu/drm/i915/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/intel_crt.c
> > @@ -63,33 +63,35 @@ static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
> > return intel_encoder_to_crt(intel_attached_encoder(connector));
> > }
> >
> > +bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> > + i915_reg_t adpa_reg, enum pipe *pipe)
> > +{
> > + u32 val;
> > +
> > + val = I915_READ(adpa_reg);
> > +
> > + /* asserts want to know the pipe even if the port is disabled */
> > + if (HAS_PCH_CPT(dev_priv))
> > + *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
> > + else
> > + *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
> > +
> > + return val & ADPA_DAC_ENABLE;
> > +}
> > +
> > static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
> > enum pipe *pipe)
> > {
> > - struct drm_device *dev = encoder->base.dev;
> > - struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_crt *crt = intel_encoder_to_crt(encoder);
> > - u32 tmp;
> > bool ret;
> >
> > if (!intel_display_power_get_if_enabled(dev_priv,
> > encoder->power_domain))
> > return false;
> >
> > - ret = false;
> > -
> > - tmp = I915_READ(crt->adpa_reg);
> > -
> > - if (!(tmp & ADPA_DAC_ENABLE))
> > - goto out;
> > + ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
> >
> > - if (HAS_PCH_CPT(dev_priv))
> > - *pipe = PORT_TO_PIPE_CPT(tmp);
> > - else
> > - *pipe = PORT_TO_PIPE(tmp);
> > -
> > - ret = true;
> > -out:
> > intel_display_power_put(dev_priv, encoder->power_domain);
> >
> > return ret;
> > @@ -168,11 +170,9 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
> > if (HAS_PCH_LPT(dev_priv))
> > ; /* Those bits don't exist here */
> > else if (HAS_PCH_CPT(dev_priv))
> > - adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
> > - else if (crtc->pipe == 0)
> > - adpa |= ADPA_PIPE_A_SELECT;
> > + adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
> > else
> > - adpa |= ADPA_PIPE_B_SELECT;
> > + adpa |= ADPA_PIPE_SEL(crtc->pipe);
> >
> > if (!HAS_PCH_SPLIT(dev_priv))
> > I915_WRITE(BCLRPAT(crtc->pipe), 0);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index ad588d564198..6daa8d97a0aa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1360,21 +1360,6 @@ static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
> > return true;
> > }
> >
> > -static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
> > - enum pipe pipe, u32 val)
> > -{
> > - if ((val & ADPA_DAC_ENABLE) == 0)
> > - return false;
> > - if (HAS_PCH_CPT(dev_priv)) {
> > - if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
> > - return false;
> > - } else {
> > - if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
> > - return false;
> > - }
> > - return true;
> > -}
> > -
> > static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
> > enum pipe pipe, i915_reg_t reg,
> > u32 port_sel)
> > @@ -1405,16 +1390,17 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
> > static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> > enum pipe pipe)
> > {
> > + enum pipe port_pipe;
> > u32 val;
> >
> > assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
> > assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
> > assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
> >
> > - val = I915_READ(PCH_ADPA);
> > - I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
> > - "PCH VGA enabled on transcoder %c, should be disabled\n",
> > - pipe_name(pipe));
> > + I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
> > + port_pipe == pipe,
> > + "PCH VGA enabled on transcoder %c, should be disabled\n",
> > + pipe_name(pipe));
> >
> > val = I915_READ(PCH_LVDS);
> > I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index d7dbca1aabff..423795050970 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1377,6 +1377,8 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
> > void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
> >
> > /* intel_crt.c */
> > +bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> > + i915_reg_t adpa_reg, enum pipe *pipe);
> > void intel_crt_init(struct drm_i915_private *dev_priv);
> > void intel_crt_reset(struct drm_encoder *encoder);
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
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2018-05-14 17:24 [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Ville Syrjala
2018-05-14 17:24 ` [PATCH 2/5] drm/i915: Clean up LVDS " Ville Syrjala
2018-05-14 18:28 ` [PATCH v3 " Ville Syrjala
2018-05-14 17:24 ` [PATCH 3/5] drm/i915: Clean up SDVO " Ville Syrjala
2018-05-14 17:24 ` [PATCH 4/5] drm/i915: Clean up TV " Ville Syrjala
2018-05-14 17:24 ` [PATCH 5/5] drm/i915: Clean up DVO " Ville Syrjala
2018-05-14 17:48 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Clean up ADPA " Patchwork
2018-05-14 18:03 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-05-14 18:51 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2) Patchwork
2018-05-15 2:47 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-05-15 14:56 ` Ville Syrjälä
2018-05-15 14:33 ` ✓ Fi.CI.BAT: success " Patchwork
2018-05-17 9:31 ` [PATCH 1/5] drm/i915: Clean up ADPA pipe select bits Jani Nikula
2018-05-17 17:03 ` Ville Syrjälä
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