* [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
@ 2018-05-14 16:54 Michel Thierry
2018-05-14 17:43 ` ✗ Fi.CI.BAT: failure for drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk (rev2) Patchwork
2018-05-15 17:13 ` [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk Jani Nikula
0 siblings, 2 replies; 6+ messages in thread
From: Michel Thierry @ 2018-05-14 16:54 UTC (permalink / raw)
To: intel-gfx
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#1604444184
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: mesa-dev@lists.freedesktop.org
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
Cc: stable@vger.kernel.org
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e6a8c0ee7df1..8a69a9275e28 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7326,6 +7326,9 @@ enum {
#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
+#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
+#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
+
/* WaCatErrorRejectionIssue */
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 4ba139c27fba..f7c25828d3bb 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
+ /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
+ if (IS_GEN9_LP(dev_priv))
+ WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
+
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
if (ret)
--
2.17.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk (rev2)
2018-05-14 16:54 [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk Michel Thierry
@ 2018-05-14 17:43 ` Patchwork
2018-05-15 17:13 ` [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk Jani Nikula
1 sibling, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-05-14 17:43 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk (rev2)
URL : https://patchwork.freedesktop.org/series/43024/
State : failure
== Summary ==
Applying: drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_reg.h
M drivers/gpu/drm/i915/intel_engine_cs.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_engine_cs.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_engine_cs.c
Patch failed at 0001 drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
2018-05-14 16:54 [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk Michel Thierry
2018-05-14 17:43 ` ✗ Fi.CI.BAT: failure for drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk (rev2) Patchwork
@ 2018-05-15 17:13 ` Jani Nikula
2018-05-15 17:16 ` Michel Thierry
1 sibling, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2018-05-15 17:13 UTC (permalink / raw)
To: Michel Thierry, intel-gfx
On Mon, 14 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
> Factor in clear values wherever required while updating destination
> min/max.
Hi Michel, please elaborate what the intention here is.
BR,
Jani.
>
> References: HSDES#1604444184
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Cc: mesa-dev@lists.freedesktop.org
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
> Cc: stable@vger.kernel.org
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e6a8c0ee7df1..8a69a9275e28 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7326,6 +7326,9 @@ enum {
> #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
> #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
>
> +#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
> +#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
> +
> /* WaCatErrorRejectionIssue */
> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
> #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 4ba139c27fba..f7c25828d3bb 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>
> + /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
> + if (IS_GEN9_LP(dev_priv))
> + WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
> +
> /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
> ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
> if (ret)
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
2018-05-15 17:13 ` [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk Jani Nikula
@ 2018-05-15 17:16 ` Michel Thierry
2018-05-15 18:17 ` Jani Nikula
0 siblings, 1 reply; 6+ messages in thread
From: Michel Thierry @ 2018-05-15 17:16 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 5/15/2018 10:13 AM, Jani Nikula wrote:
> On Mon, 14 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
>> Factor in clear values wherever required while updating destination
>> min/max.
>
> Hi Michel, please elaborate what the intention here is.
>
Hi Jani, isn't the intention of all the workarounds to prevent gpu hangs?
> BR,
> Jani.
>
>
>
>>
>> References: HSDES#1604444184
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> Cc: mesa-dev@lists.freedesktop.org
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
>> Cc: stable@vger.kernel.org
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>> drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>> 2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e6a8c0ee7df1..8a69a9275e28 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7326,6 +7326,9 @@ enum {
>> #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
>> #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
>>
>> +#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
>> +#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
>> +
>> /* WaCatErrorRejectionIssue */
>> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
>> #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index 4ba139c27fba..f7c25828d3bb 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>> WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>>
>> + /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
>> + if (IS_GEN9_LP(dev_priv))
>> + WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
>> +
>> /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>> ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>> if (ret)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
2018-05-15 17:16 ` Michel Thierry
@ 2018-05-15 18:17 ` Jani Nikula
2018-05-15 18:20 ` Michel Thierry
0 siblings, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2018-05-15 18:17 UTC (permalink / raw)
To: Michel Thierry, intel-gfx
On Tue, 15 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
> On 5/15/2018 10:13 AM, Jani Nikula wrote:
>> On Mon, 14 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
>>> Factor in clear values wherever required while updating destination
>>> min/max.
>>
>> Hi Michel, please elaborate what the intention here is.
>>
>
> Hi Jani, isn't the intention of all the workarounds to prevent gpu
> hangs?
Err, sorry for the riddles, I meant with [BACKPORT v4.17-rc5] etc. :)
Is this in dinq already? Commit id?
BR,
Jani.
>
>> BR,
>> Jani.
>>
>>
>>
>>>
>>> References: HSDES#1604444184
>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>> Cc: mesa-dev@lists.freedesktop.org
>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
>>> Cc: stable@vger.kernel.org
>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>>> drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>>> 2 files changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index e6a8c0ee7df1..8a69a9275e28 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -7326,6 +7326,9 @@ enum {
>>> #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
>>> #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
>>>
>>> +#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
>>> +#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
>>> +
>>> /* WaCatErrorRejectionIssue */
>>> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
>>> #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
>>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>>> index 4ba139c27fba..f7c25828d3bb 100644
>>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>>> @@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>>> WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>>> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>>>
>>> + /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
>>> + if (IS_GEN9_LP(dev_priv))
>>> + WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
>>> +
>>> /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>>> ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>>> if (ret)
>>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
2018-05-15 18:17 ` Jani Nikula
@ 2018-05-15 18:20 ` Michel Thierry
0 siblings, 0 replies; 6+ messages in thread
From: Michel Thierry @ 2018-05-15 18:20 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 5/15/2018 11:17 AM, Jani Nikula wrote:
> On Tue, 15 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
>> On 5/15/2018 10:13 AM, Jani Nikula wrote:
>>> On Mon, 14 May 2018, Michel Thierry <michel.thierry@intel.com> wrote:
>>>> Factor in clear values wherever required while updating destination
>>>> min/max.
>>>
>>> Hi Michel, please elaborate what the intention here is.
>>>
>>
>> Hi Jani, isn't the intention of all the workarounds to prevent gpu
>> hangs?
>
> Err, sorry for the riddles, I meant with [BACKPORT v4.17-rc5] etc. :)
>
No worries,
> Is this in dinq already? Commit id?
It was merged only a couple of days ago,
https://cgit.freedesktop.org/drm-tip/commit/?id=0c79f9cb77eae28d48a4f9fc1b3341aacbbd260c
Joonas asked me to backport it (stable doesn't have the
intel_workarounds refactor yet).
>
> BR,
> Jani.
>
>
>
>>
>>> BR,
>>> Jani.
>>>
>>>
>>>
>>>>
>>>> References: HSDES#1604444184
>>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>>> Cc: mesa-dev@lists.freedesktop.org
>>>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>>>> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>>> Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
>>>> Cc: stable@vger.kernel.org
>>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/i915_reg.h | 3 +++
>>>> drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>>>> 2 files changed, 7 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>> index e6a8c0ee7df1..8a69a9275e28 100644
>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>> @@ -7326,6 +7326,9 @@ enum {
>>>> #define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
>>>> #define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
>>>>
>>>> +#define GEN9_WM_CHICKEN3 _MMIO(0x5588)
>>>> +#define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9)
>>>> +
>>>> /* WaCatErrorRejectionIssue */
>>>> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
>>>> #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
>>>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>>>> index 4ba139c27fba..f7c25828d3bb 100644
>>>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>>>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>>>> @@ -1149,6 +1149,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>>>> WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>>>> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>>>>
>>>> + /* WaClearHIZ_WM_CHICKEN3:bxt,glk */
>>>> + if (IS_GEN9_LP(dev_priv))
>>>> + WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ);
>>>> +
>>>> /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>>>> ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>>>> if (ret)
>>>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-05-15 18:20 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-14 16:54 [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk Michel Thierry
2018-05-14 17:43 ` ✗ Fi.CI.BAT: failure for drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk (rev2) Patchwork
2018-05-15 17:13 ` [BACKPORT v4.17-rc5] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk Jani Nikula
2018-05-15 17:16 ` Michel Thierry
2018-05-15 18:17 ` Jani Nikula
2018-05-15 18:20 ` Michel Thierry
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