[PATCH v2 0/4] DRM helpers for Display Stream Compression PPS infoframes

[PATCH v2 0/4] DRM helpers for Display Stream Compression PPS infoframes

[Manasi Navare]

VESA Display Stream Compression is a specification for visually losless
video compression over display links. The DSC standard also defines
a picture parameter set (PPS) which encoder must communicate to decoders.
This is done by encapsulating PPS header and payload bytes in an infoframe
that can be sent to the display sink using secondary data packets
as defined in DP 1.4 spec.

This patch series creates a new files drm_dsc.h and drm_dsc.c
which define all the DSC related structures and helpers that
can be called by drivers to form DSC PPS infoframes before
enabling Display Stream compression on eDP/DP/MIPI

v2:
*This is a v2 of the original patch series which adds kernel-doc
hooks for the new dsc files in drm-kms-helpers.rst. (Daniel Vetter)

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>

Gaurav K Singh (1):
  drm/dsc: Define VESA Display Stream Compression Capabilities

Manasi Navare (3):
  drm/dp: Define payload size for DP SDP PPS packet
  drm/dsc: Define Display Stream Compression PPS infoframe
  drm/dsc: Add helpers for DSC picture parameter set infoframes

 Documentation/gpu/drm-kms-helpers.rst |  12 +
 drivers/gpu/drm/Makefile              |   2 +-
 drivers/gpu/drm/drm_dsc.c             | 227 ++++++++++++++
 include/drm/drm_dp_helper.h           |   1 +
 include/drm/drm_dsc.h                 | 564 ++++++++++++++++++++++++++++++++++
 5 files changed, 805 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_dsc.c
 create mode 100644 include/drm/drm_dsc.h

-- 
2.7.4

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[PATCH v2 1/4] drm/dp: Define payload size for DP SDP PPS packet

[Manasi Navare]

DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: dri-devel@lists.freedesktop.org
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c015649..d13e512 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -992,6 +992,7 @@ struct dp_sdp_header {
 
 #define EDP_SDP_HEADER_REVISION_MASK		0x1F
 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES	0x1F
+#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
 
 struct edp_vsc_psr {
 	struct dp_sdp_header sdp_header;
-- 
2.7.4

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[PATCH v2 2/4] drm/dsc: Define Display Stream Compression PPS infoframe

[Manasi Navare]

This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.

v2:
* Fix the comments for kernel-doc

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 include/drm/drm_dsc.h | 437 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 437 insertions(+)
 create mode 100644 include/drm/drm_dsc.h

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index 0000000..5ee72e8
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,437 @@
+/*
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include <drm/drm_dp_helper.h>
+
+#define DSC_NUM_BUF_RANGES	15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display stream
+ * compression encoders must communicate to decoders. The PPS is encapsulated
+ * in 128 bytes (PPS 0 through PPS 127). The fields in this structure are as per
+ * Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big Endian
+ * format.
+ */
+struct picture_parameter_set {
+	/**
+	 * @dsc_version_minor:
+	 * PPS0[3:0] - Contains Minor version of DSC
+	 */
+	u8 dsc_version_minor:4;
+	/**
+	 * @dsc_version_major:
+	 * PPS0[7:4] - Contains major version of DSC
+	 */
+	u8 dsc_version_major:4;
+	/**
+	 * @pps_identifier:
+	 * PPS1[7:0] - Application specific identifier that can be
+	 * used to differentiate between different PPS tables.
+	 */
+	u8 pps_identifier;
+	/**
+	 * @pps2_reserved:
+	 * PPS2[7:0]- RESERVED Byte
+	 */
+	u8 pps2_reserved;
+	/**
+	 * @linebuf_depth:
+	 * PPS3[3:0] - Contains linebuffer bit depth used to generate
+	 * the bitstream. (0x0 - 16 bits for DSc 1.2, 0x8 - 8 bits,
+	 * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+	 * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+	 */
+	u8 linebuf_depth:4;
+	/**
+	 * @bits_per_component:
+	 * PPS3[7:4] - Bits per component fo rthe original pixels
+	 * of the encoded picture.
+	 */
+	u8 bits_per_component:4;
+	/**
+	 * @bpp_high:
+	 * PPS4[1:0] - These are the most significant 2 bits of
+	 * compressed BPP bits_per_pixel[9:0] syntax element.
+	 */
+	u8 bpp_high:2;
+	/**
+	 * @vbr_enable:
+	 * PPS4[2] - 0 = VBR disabled, 1 = VBR enabled
+	 */
+	u8 vbr_enable:1;
+	/**
+	 * @simple_422:
+	 * PPS4[3] - Indicates if decoder drops samples to
+	 * reconstruct the 4:2:2 picture.
+	 */
+	u8 simple_422:1;
+	/**
+	 * @convert_rgb:
+	 * PPS4[4] - Indicates if DSC color space conversion is active
+	 */
+	u8 convert_rgb:1;
+	/**
+	 * @block_pred_enable:
+	 * PPS4[5] - Indicates if BP is used to code any groups in picture
+	 */
+	u8 block_pred_enable:1;
+	/**
+	 * @pps4_reserved:
+	 * PPS4[7:6] - Reseved bits
+	 */
+	u8 pps4_reserved:2;
+	/**
+	 * @bpp_low:
+	 * PPS5[7:0] - This indicates the lower significant 8 bits of
+	 * the compressed BPP bits_per_pixel[9:0] element.
+	 */
+	u8 bpp_low;
+	/**
+	 * @pic_height:
+	 * PPS6[7:0], PPS7[7:0] -  Specifies the number of pixel rows within
+	 * the raster.
+	 */
+	u16 pic_height;
+	/**
+	 * @pic_width:
+	 * PPS8[7:0], PPS9[7:0] - Number of pixel columns within the raster.
+	 */
+	u16 pic_width;
+	/**
+	 * @slice_height:
+	 * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+	 */
+	u16 slice_height;
+	/**
+	 * @slice_width:
+	 * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+	 */
+	u16 slice_width;
+	/**
+	 * @chunk_size:
+	 * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+	 * that are used for slice multiplexing.
+	 */
+	u16 chunk_size;
+	/**
+	 * @initial_xmit_delay_high:
+	 * PPS16[1:0] - Most Significant two bits of initial transmission delay.
+	 * It specifies the number of pixel times that the encoder waits before
+	 * transmitting data from its rate buffer.
+	 */
+	u8 initial_xmit_delay_high:2;
+	/**
+	 * @pps16_reserved:
+	 * PPS16[7:2] - Reserved
+	 */
+	u8 pps16_reserved:6;
+	/**
+	 * @initial_xmit_delay_low:
+	 * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
+	 */
+	u8 initial_xmit_delay_low;
+	/**
+	 * @initial_dec_delay:
+	 *
+	 * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
+	 * of pixel times that the decoder accumulates data in its rate buffer
+	 * before starting to decode and output pixels.
+	 */
+	u16 initial_dec_delay;
+	/**
+	 * @pps20_reserved:
+	 *
+	 * PPS20[7:0] - Reserved
+	 */
+	u8 pps20_reserved;
+	/**
+	 * @initial_scale_value:
+	 * PPS21[5:0] - Initial rcXformScale factor used at beginning
+	 * of a slice.
+	 */
+	u8 initial_scale_value:6;
+	/**
+	 * @pps21_reserved:
+	 * PPS21[7:6] - Reserved
+	 */
+	u8 pps21_reserved:2;
+	/**
+	 * @scale_increment_interval:
+	 * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
+	 * the rcXformScale factor at end of a slice.
+	 */
+	u16 scale_increment_interval;
+	/**
+	 * @scale_decrement_interval_high:
+	 * PPS24[3:0] - Higher 4 bits indicating number of group times between
+	 * decrementing the rcXformScale factor at beginning of a slice.
+	 */
+	u8 scale_decrement_interval_high:4;
+	/**
+	 * @pps24_reserved:
+	 * PPS24[7:4] - Reserved
+	 */
+	u8 pps24_reserved:4;
+	/**
+	 * @scale_decrement_interval_low:
+	 * PPS25[7:0] - Lower 8 bits of scale decrement interval
+	 */
+	u8 scale_decrement_interval_low;
+	/**
+	 * @pps26_reserved:
+	 * PPS26[7:0]
+	 */
+	u8 pps26_reserved;
+	/**
+	 * @first_line_bpg_offset:
+	 * PPS27[4:0] - Number of additional bits that are allocated
+	 * for each group on first line of a slice.
+	 */
+	u8 first_line_bpg_offset:5;
+	/**
+	 * @pps27_reserved:
+	 * PPS27[7:5]
+	 */
+	u8 pps27_reserved:3;
+	/**
+	 * @nfl_bpg_offset:
+	 * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
+	 * deallocated for each group for groups after the first line of slice.
+	 */
+	u16 nfl_bpg_offset;
+	/**
+	 * @slice_bpg_offset:
+	 * PPS30, PPS31[7:0] - Number of bits that are deallocated for each group
+	 * to enforce the slice constraint.
+	 */
+	u16 slice_bpg_offset;
+	/**
+	 * @initial_offset:
+	 * PPS32,33[7:0] - Initial value for rcXformOffset
+	 */
+	u16 initial_offset;
+	/**
+	 * @final_offset:
+	 * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
+	 */
+	u16 final_offset;
+	/**
+	 * @flatness_min_qp:
+	 * PPS36[4:0] - Minimum QP at which flatness is signaled and
+	 * flatness QP adjustment is made.
+	 */
+	u8 flatness_min_qp:5;
+	/**
+	 * @pps36_reserved:
+	 * PPS36[7:5] - Reserved
+	 */
+	u8 pps36_reserved:3;
+	/**
+	 * @flatness_max_qp:
+	 * PPS37[4:0] - Max QP at which flatness is signalled and
+	 * the flatness adjustment is made.
+	 */
+	u8 flatness_max_qp:5;
+	/**
+	 * @pps37_reserved:
+	 * PPS37[7:5]
+	 */
+	u8 pps37_reserved:3;
+	/**
+	 * @rc_model_size:
+	 * PPS38,39[7:0] - Number of bits within RC Model.
+	 */
+	u16 rc_model_size;
+	/**
+	 * @rc_edge_factor:
+	 * PPS40[3:0] - Ratio of current activity vs, previous
+	 * activity to determine presence of edge.
+	 */
+	u8 rc_edge_factor:4;
+	/**
+	 * @pps40_reserved:
+	 * PPS40[7:4]
+	 */
+	u8 pps40_reserved:4;
+	/**
+	 * @rc_quant_incr_limit0:
+	 * PPS41[4:0] - QP threshold used in short term RC
+	 */
+	u8 rc_quant_incr_limit0:5;
+	/**
+	 * @pps41_reserved:
+	 * PPS41[7:5]
+	 */
+	u8 pps41_reserved:3;
+	/**
+	 * @rc_quant_incr_limit1:
+	 * PPS42[4:0] - QP threshold used in short term RC
+	 */
+	u8 rc_quant_incr_limit1:5;
+	/**
+	 * @pps42_reserved:
+	 * PPS42[7:5]
+	 */
+	u8 pps42_reserved:3;
+	/**
+	 * @rc_tgt_offset_lo:
+	 * Lower end of the variability range around the target
+	 * bits per group that is allowed by short term RC.
+	 */
+	u8 rc_tgt_offset_lo:4;
+	/**
+	 * @rc_tgt_offset_hi:
+	 * Upper end of the variability range around the target
+	 * bits per group that i allowed by short term rc.
+	 */
+	u8 rc_tgt_offset_hi:4;
+	/**
+	 * @rc_buf_thresh:
+	 * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
+	 * the 15 ranges defined by 14 thresholds.
+	 */
+	u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+	/**
+	 * @rc_range_parameters:
+	 * PPS58[7:0] - PPS87[7:0]
+	 * Parameters that correspond to each of the 15 ranges.
+	 */
+	u16 rc_range_parameters[DSC_NUM_BUF_RANGES];
+	/**
+	 * @native_422:
+	 * PPS88[0] - 0 = Native 4:2:2 not used
+	 * 1 = Native 4:2:2 used
+	 */
+	u8 native_422:1;
+	/**
+	 * @native_420:
+	 * PPS88[1] - 0 = Native 4:2:0 not used
+	 * 1 = Native 4:2:0 not used.
+	 */
+	u8 native_420:1;
+	/**
+	 * @pps88_reserved:
+	 * PPS[7:2] - Reserved 6 bits
+	 */
+	u8 pps88_reserved:6;
+	/**
+	 * @second_line_bpg_offset:
+	 * PPS89[4:0] - Additional bits/group budget for the
+	 * second line of a slice in Native 4:2:0 mode.
+	 * Set to 0 if DSC minor version is 1 or native420 is 0.
+	 */
+	u8 second_line_bpg_offset:5;
+	/**
+	 * @pps89_reserved:
+	 * PPS89[7:5] - Reserved
+	 */
+	u8 pps89_reserved:3;
+	/**
+	 * @nsl_bpg_offset:
+	 * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
+	 * for each group that is not in the second line of a slice.
+	 */
+	u16 nsl_bpg_offset;
+	/**
+	 * @second_line_offset_adj:
+	 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
+	 * line in Native 4:2:0 mode.
+	 */
+	u16 second_line_offset_adj;
+	/**
+	 * @pps_long_94_reserved:
+	 * PPS 94, 95, 96, 97 - Reserved
+	 */
+	u32 pps_long_94_reserved;
+	/**
+	 * @pps_long_98_reserved:
+	 * PPS 98, 99, 100, 101 - Reserved
+	 */
+	u32 pps_long_98_reserved;
+	/**
+	 * @pps_long_102_reserved:
+	 * PPS 102, 103, 104, 105 - Reserved
+	 */
+	u32 pps_long_102_reserved;
+	/**
+	 * @pps_long_106_reserved:
+	 * PPS 106, 107, 108, 109 - reserved
+	 */
+	u32 pps_long_106_reserved;
+	/**
+	 * @pps_long_110_reserved:
+	 * PPS 110, 111, 112, 113 - reserved
+	 */
+	u32 pps_long_110_reserved;
+	/**
+	 * @pps_long_114_reserved:
+	 * PPS 114 - 117 - reserved
+	 */
+	u32 pps_long_114_reserved;
+	/**
+	 * @pps_long_118_reserved:
+	 * PPS 118 - 121 - reserved
+	 */
+	u32 pps_long_118_reserved;
+	/**
+	 * @pps_long_122_reserved:
+	 * PPS 122- 125 - reserved
+	 */
+	u32 pps_long_122_reserved;
+	/**
+	 * @pps_short_126_reserved:
+	 * PPS 126, 127 - reserved
+	 */
+	u16 pps_short_126_reserved;
+};
+
+/**
+* struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter Set Metadata
+*
+* This structure represents the DSC PPS infoframe required to send the Picture Parameter Set
+* metadata required before enabling VESA Display Stream Compression. This is based on the
+* DP Secondary Data Packet structure and comprises of SDP Header as defined in drm_dp_helper.h
+* and PPS payload.
+*
+* @pps_header:
+*
+* Header for PPS as per DP SDP header format
+*
+* @pps_payload:
+*
+* PPS payload fields as per DSC specification Table 4-1
+*/
+struct drm_dsc_pps_infoframe {
+	struct dp_sdp_header pps_header;
+	struct picture_parameter_set pps_payload;
+} __packed;
+
+#endif /* _DRM_DSC_H_ */
-- 
2.7.4

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[PATCH v2 3/4] drm/dsc: Define VESA Display Stream Compression Capabilities

[Manasi Navare]

From: Gaurav K Singh <gaurav.k.singh@intel.com>

This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder

v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 include/drm/drm_dsc.h | 111 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 5ee72e8..04501e2 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -30,6 +30,117 @@
 
 #define DSC_NUM_BUF_RANGES	15
 
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES		15
+
+/* Configuration for a single Rate Control model range */
+struct dsc_rc_range_parameters {
+	/* Min Quantization Parameters allowed for this range */
+	u8 range_min_qp;
+	/* Max Quantization Parameters allowed for this range */
+	u8 range_max_qp;
+	/* Bits/group offset to apply to target for this group */
+	u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+	/* Bits / component for previous reconstructed line buffer */
+	u8 line_buf_depth;
+	/* Bits per component to code (must be 8, 10, or 12) */
+	u8 bits_per_component;
+	/*
+	 * Flag indicating to do RGB - YCoCg conversion
+	 * and back (should be 1 for RGB input)
+	 */
+	bool convert_rgb;
+	u8 slice_count;
+	/* Slice Width */
+	u16 slice_width;
+	/* Slice Height */
+	u16 slice_height;
+	/*
+	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+	 * outside of DSC encode/decode algorithm)
+	 */
+	bool enable422;
+	/* Picture Width */
+	u16 pic_width;
+	/* Picture Height */
+	u16 pic_height;
+	/* Offset to bits/group used by RC to determine QP adjustment */
+	u8 rc_tgt_offset_high;
+	/* Offset to bits/group used by RC to determine QP adjustment */
+	u8 rc_tgt_offset_low;
+	/* Bits/pixel target << 4 (ie., 4 fractional bits) */
+	u16 bits_per_pixel;
+	/*
+	 * Factor to determine if an edge is present based
+	 * on the bits produced
+	 */
+	u8 rc_edge_factor;
+	/* Slow down incrementing once the range reaches this value */
+	u8 rc_quant_incr_limit1;
+	/* Slow down incrementing once the range reaches this value */
+	u8 rc_quant_incr_limit0;
+	/* Number of pixels to delay the initial transmission */
+	u16 initial_xmit_delay;
+	/* Number of pixels to delay the VLD on the decoder,not including SSM */
+	u16  initial_dec_delay;
+	/* Block prediction enable */
+	bool block_pred_enable;
+	/* Bits/group offset to use for first line of the slice */
+	u8 first_line_bpg_offset;
+	/* Value to use for RC model offset at slice start */
+	u16 initial_offset;
+	/* Thresholds defining each of the buffer ranges */
+	u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+	/* Parameters for each of the RC ranges */
+	struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+	/* Total size of RC model */
+	u16 rc_model_size;
+	/* Minimum QP where flatness information is sent */
+	u8 flatness_min_qp;
+	/* Maximum QP where flatness information is sent */
+	u8 flatness_max_qp;
+	/* Initial value for scale factor */
+	u8 initial_scale_value;
+	/* Decrement scale factor every scale_decrement_interval groups */
+	u16 scale_decrement_interval;
+	/* Increment scale factor every scale_increment_interval groups */
+	u16 scale_increment_interval;
+	/* Non-first line BPG offset to use */
+	u16 nfl_bpg_offset;
+	/* BPG offset used to enforce slice bit */
+	u16 slice_bpg_offset;
+	/* Final RC linear transformation offset value */
+	u16 final_offset;
+	/* Enable on-off VBR (ie., disable stuffing bits) */
+	bool vbr_enable;
+	/* Mux word size (in bits) for SSM mode */
+	u8 mux_word_size;
+	/*
+	 * The (max) size in bytes of the "chunks" that are
+	 * used in slice multiplexing
+	 */
+	u16 slice_chunk_size;
+	/* Rate Control buffer siz in bits */
+	u16 rc_bits;
+	/* DSC Minor Version */
+	u8 dsc_version_minor;
+	/* DSC Major version */
+	u8 dsc_version_major;
+	/* Native 4:2:2 support */
+	bool native_422;
+	/* Native 4:2:0 support */
+	bool native_420;
+	/* Additional bits/grp for seconnd line of slice for native 4:2:0 */
+	u8 second_line_bpg_offset;
+	/* Num of bits deallocated for each grp that is not in second line of slice */
+	u16 nsl_bpg_offset;
+	/* Offset adj fr second line in Native 4:2:0 mode */
+	u16 second_line_offset_adj;
+};
+
 /**
  * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
  *
-- 
2.7.4

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[PATCH v2 4/4] drm/dsc: Add helpers for DSC picture parameter set infoframes

[Manasi Navare]

According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.

v3:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)

v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 Documentation/gpu/drm-kms-helpers.rst |  12 ++
 drivers/gpu/drm/Makefile              |   2 +-
 drivers/gpu/drm/drm_dsc.c             | 227 ++++++++++++++++++++++++++++++++++
 include/drm/drm_dsc.h                 |  16 +++
 4 files changed, 256 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_dsc.c

diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst
index e37557b..13837f7 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -205,6 +205,18 @@ MIPI DSI Helper Functions Reference
 .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
    :export:
 
+Display Stream Compression Helper Functions Reference
+=====================================================
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+   :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :export:
+
 Output Probing Helper Functions Reference
 =========================================
 
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index ef9f3da..02f1b2c 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -31,7 +31,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
 drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
 drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
 
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \
 		drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
 		drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
 		drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index 0000000..3bf8d42
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,227 @@
+/*
+ * Copyright © 2018 Intel Corp
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Author:
+ * Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_dsc.h>
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+	memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+	pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+	pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ * @is_big_endian:
+ * Flag to indicate if HW is Big Endian
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+				struct drm_dsc_config *dsc_cfg,
+				bool is_big_endian)
+{
+	u8 i = 0;
+
+	memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+	/* PPS 0 */
+	pps_sdp->pps_payload.dsc_version_minor = dsc_cfg->dsc_version_minor;
+	pps_sdp->pps_payload.dsc_version_major = dsc_cfg->dsc_version_major;
+
+	/* PPS 1, 2 is 0 */
+
+	/* PPS 3 */
+	pps_sdp->pps_payload.linebuf_depth = dsc_cfg->line_buf_depth;
+	pps_sdp->pps_payload.bits_per_component = dsc_cfg->bits_per_component;
+
+	/* PPS 4, 5 */
+	pps_sdp->pps_payload.block_pred_enable = (u8)dsc_cfg->block_pred_enable;
+	pps_sdp->pps_payload.convert_rgb = (u8)dsc_cfg->convert_rgb;
+	pps_sdp->pps_payload.simple_422 = (u8)dsc_cfg->enable422;
+	pps_sdp->pps_payload.vbr_enable = (u8)dsc_cfg->vbr_enable;
+	pps_sdp->pps_payload.bpp_high = (u8)((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
+					     DSC_PPS_MSB_SHIFT);
+	pps_sdp->pps_payload.bpp_low = (u8)(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
+
+	/*
+	 * The DSC panel expects the PPS packet to have big endian format
+	 * for data spanning 2 bytes. So if the HW does not store the data
+	 * in big endian format, it sets big_endian flag to false in which case
+	 * we need to convert from little endian to big endian.
+	 */
+
+	/* PPS 6, 7 */
+	pps_sdp->pps_payload.pic_height = DSC_PPS_SWAP_BYTES(dsc_cfg->pic_height,
+							     is_big_endian);
+
+	/* PPS 8, 9 */
+	pps_sdp->pps_payload.pic_width = DSC_PPS_SWAP_BYTES(dsc_cfg->pic_height,
+							    is_big_endian);
+
+	/* PPS 10, 11 */
+	pps_sdp->pps_payload.slice_height = DSC_PPS_SWAP_BYTES(dsc_cfg->slice_height,
+							       is_big_endian);
+
+	/* PPS 12, 13 */
+	pps_sdp->pps_payload.slice_width = DSC_PPS_SWAP_BYTES(dsc_cfg->slice_width,
+							      is_big_endian);
+
+	/* PPS 14, 15 */
+	pps_sdp->pps_payload.chunk_size = DSC_PPS_SWAP_BYTES(dsc_cfg->slice_chunk_size,
+							     is_big_endian);
+
+	/* PPS 16, 17 */
+	pps_sdp->pps_payload.initial_xmit_delay_high = (u8)((dsc_cfg->initial_xmit_delay &
+							     DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
+							    DSC_PPS_MSB_SHIFT);
+	pps_sdp->pps_payload.initial_xmit_delay_low = (u8)(dsc_cfg->initial_xmit_delay &
+							   DSC_PPS_LSB_MASK);
+
+	/* PPS 18, 19 */
+	pps_sdp->pps_payload.initial_dec_delay = DSC_PPS_SWAP_BYTES(dsc_cfg->initial_dec_delay,
+								    is_big_endian);
+
+	/* PPS 20 is 0 */
+
+	/* PPS 21 */
+	pps_sdp->pps_payload.initial_scale_value = (u8)dsc_cfg->initial_scale_value;
+
+	/* PPS 22, 23 */
+	pps_sdp->pps_payload.scale_increment_interval = DSC_PPS_SWAP_BYTES(dsc_cfg->scale_increment_interval,
+									   is_big_endian);
+
+	/* PPS 24, 25 */
+	pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval &
+								   DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
+								  DSC_PPS_MSB_SHIFT);
+	pps_sdp->pps_payload.scale_decrement_interval_low = (u8)(dsc_cfg->scale_decrement_interval &
+								 DSC_PPS_LSB_MASK);
+
+	/* PPS 27 */
+	pps_sdp->pps_payload.first_line_bpg_offset = (u8)dsc_cfg->first_line_bpg_offset;
+
+	/* PPS 28, 29 */
+	pps_sdp->pps_payload.nfl_bpg_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->nfl_bpg_offset,
+								 is_big_endian);
+
+	/* PPS 30, 31 */
+	pps_sdp->pps_payload.slice_bpg_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->slice_bpg_offset,
+								   is_big_endian);
+
+	/* PPS 32, 33 */
+	pps_sdp->pps_payload.initial_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->initial_offset,
+								 is_big_endian);
+
+	/* PPS 34, 35 */
+	pps_sdp->pps_payload.final_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->final_offset,
+							       is_big_endian);
+
+	/* PPS 36 */
+	pps_sdp->pps_payload.flatness_min_qp = (u8)dsc_cfg->flatness_min_qp;
+
+	/* PPS 37 */
+	pps_sdp->pps_payload.flatness_max_qp = (u8)dsc_cfg->flatness_max_qp;
+
+	/* PPS 38, 39 */
+	pps_sdp->pps_payload.rc_model_size = DSC_PPS_SWAP_BYTES(dsc_cfg->rc_model_size,
+								is_big_endian);
+
+	/* PPS 40 */
+	pps_sdp->pps_payload.rc_edge_factor = (u8)dsc_cfg->rc_edge_factor;
+
+	/* PPS 41 */
+	pps_sdp->pps_payload.rc_quant_incr_limit0 = (u8)dsc_cfg->rc_quant_incr_limit0;
+
+	/* PPS 42 */
+	pps_sdp->pps_payload.rc_quant_incr_limit1 = (u8)dsc_cfg->rc_quant_incr_limit1;
+
+	/* PPS 43 */
+	pps_sdp->pps_payload.rc_tgt_offset_lo = (u8)dsc_cfg->rc_tgt_offset_low;
+	pps_sdp->pps_payload.rc_tgt_offset_hi = (u8)dsc_cfg->rc_tgt_offset_high;
+
+	/* PPS 44 - 57 */
+	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
+		pps_sdp->pps_payload.rc_buf_thresh[i] = dsc_cfg->rc_buf_thresh[i];
+
+	/* PPS 58 - 87 */
+	/*
+	 * For DSC sink programming the RC Range parameter fields
+	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
+	 */
+	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+		pps_sdp->pps_payload.rc_range_parameters[i] =
+			(u16)((dsc_cfg->rc_range_params[i].range_min_qp << DSC_PPS_RC_RANGE_MINQP_SHIFT) |
+			      (dsc_cfg->rc_range_params[i].range_max_qp << DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
+			      (dsc_cfg->rc_range_params[i].range_bpg_offset));
+		pps_sdp->pps_payload.rc_range_parameters[i] = DSC_PPS_SWAP_BYTES(pps_sdp->pps_payload.rc_range_parameters[i],
+										 is_big_endian);
+	}
+
+	/* PPS 88 */
+	pps_sdp->pps_payload.native_422 = (u8)dsc_cfg->native_422;
+	pps_sdp->pps_payload.native_420 = (u8)dsc_cfg->native_420;
+
+	/* PPS 89 */
+	pps_sdp->pps_payload.second_line_bpg_offset = (u8)dsc_cfg->second_line_bpg_offset;
+
+	/* PPS 90, 91 */
+	pps_sdp->pps_payload.nsl_bpg_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->nsl_bpg_offset,
+								 is_big_endian);
+
+	/* PPS 92, 93 */
+	pps_sdp->pps_payload.second_line_offset_adj = DSC_PPS_SWAP_BYTES(dsc_cfg->second_line_offset_adj,
+									 is_big_endian);
+
+	/* PPS 94 - 127 are O */
+}
+EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 04501e2..846edaf 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -26,6 +26,7 @@
 #ifndef DRM_DSC_H_
 #define DRM_DSC_H_
 
+#include <linux/byteorder/generic.h>
 #include <drm/drm_dp_helper.h>
 
 #define DSC_NUM_BUF_RANGES	15
@@ -33,6 +34,16 @@
 /* VESA Display Stream Compression DSC 1.2 constants */
 #define DSC_NUM_BUF_RANGES		15
 
+/* DSC PPS constants and macros */
+#define DSC_PPS_MSB_SHIFT			8
+#define DSC_PPS_LSB_MASK			(0xFF << 0)
+#define DSC_PPS_BPP_HIGH_MASK			(0x3 << 8)
+#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK	(0x3 << 8)
+#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK		(0xF << 8)
+#define DSC_PPS_RC_RANGE_MINQP_SHIFT		11
+#define DSC_PPS_RC_RANGE_MAXQP_SHIFT		6
+#define DSC_PPS_SWAP_BYTES(val, swap)		((swap) ? val : cpu_to_be16(val))
+
 /* Configuration for a single Rate Control model range */
 struct dsc_rc_range_parameters {
 	/* Min Quantization Parameters allowed for this range */
@@ -545,4 +556,9 @@ struct drm_dsc_pps_infoframe {
 	struct picture_parameter_set pps_payload;
 } __packed;
 
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+				struct drm_dsc_config *dsc_cfg,
+				bool big_endian);
+
 #endif /* _DRM_DSC_H_ */
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for DRM helpers for Display Stream Compression PPS infoframes (rev3)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev3)
URL   : https://patchwork.freedesktop.org/series/42968/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7be7958fe7e4 drm/dp: Define payload size for DP SDP PPS packet
b02ff15cb266 drm/dsc: Define Display Stream Compression PPS infoframe
-:22: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#22: 
new file mode 100644

-:27: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#27: FILE: include/drm/drm_dsc.h:1:
+/*

-:443: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#443: FILE: include/drm/drm_dsc.h:417:
+/**
+* struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter Set Metadata

total: 0 errors, 3 warnings, 0 checks, 437 lines checked
a78445d01b83 drm/dsc: Define VESA Display Stream Compression Capabilities
a50a68c17031 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#14: 
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst

-:63: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#63: 
new file mode 100644

-:68: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#68: FILE: drivers/gpu/drm/drm_dsc.c:1:
+/*

-:207: WARNING:LONG_LINE: line over 100 characters
#207: FILE: drivers/gpu/drm/drm_dsc.c:140:
+	pps_sdp->pps_payload.scale_increment_interval = DSC_PPS_SWAP_BYTES(dsc_cfg->scale_increment_interval,

-:211: WARNING:LONG_LINE: line over 100 characters
#211: FILE: drivers/gpu/drm/drm_dsc.c:144:
+	pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval &

-:212: WARNING:LONG_LINE: line over 100 characters
#212: FILE: drivers/gpu/drm/drm_dsc.c:145:
+								   DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>

-:270: WARNING:LONG_LINE: line over 100 characters
#270: FILE: drivers/gpu/drm/drm_dsc.c:203:
+			(u16)((dsc_cfg->rc_range_params[i].range_min_qp << DSC_PPS_RC_RANGE_MINQP_SHIFT) |

-:271: WARNING:LONG_LINE: line over 100 characters
#271: FILE: drivers/gpu/drm/drm_dsc.c:204:
+			      (dsc_cfg->rc_range_params[i].range_max_qp << DSC_PPS_RC_RANGE_MAXQP_SHIFT) |

-:273: WARNING:LONG_LINE: line over 100 characters
#273: FILE: drivers/gpu/drm/drm_dsc.c:206:
+		pps_sdp->pps_payload.rc_range_parameters[i] = DSC_PPS_SWAP_BYTES(pps_sdp->pps_payload.rc_range_parameters[i],

-:289: WARNING:LONG_LINE: line over 100 characters
#289: FILE: drivers/gpu/drm/drm_dsc.c:222:
+	pps_sdp->pps_payload.second_line_offset_adj = DSC_PPS_SWAP_BYTES(dsc_cfg->second_line_offset_adj,

-:319: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'val' - possible side-effects?
#319: FILE: include/drm/drm_dsc.h:45:
+#define DSC_PPS_SWAP_BYTES(val, swap)		((swap) ? val : cpu_to_be16(val))

total: 0 errors, 10 warnings, 1 checks, 285 lines checked

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✗ Fi.CI.SPARSE: warning for DRM helpers for Display Stream Compression PPS infoframes (rev3)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev3)
URL   : https://patchwork.freedesktop.org/series/42968/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/dp: Define payload size for DP SDP PPS packet
Okay!

Commit: drm/dsc: Define Display Stream Compression PPS infoframe
Okay!

Commit: drm/dsc: Define VESA Display Stream Compression Capabilities
Okay!

Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes
-
+drivers/gpu/drm/drm_dsc.c:104:43: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:108:42: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:112:45: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:116:44: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:120:43: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:131:50: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:140:57: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:154:47: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:158:49: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:162:47: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:166:45: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:176:46: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:206:63: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:218:47: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:222:55: warning: restricted __be16 degrades to integer

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✓ Fi.CI.BAT: success for DRM helpers for Display Stream Compression PPS infoframes (rev3)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev3)
URL   : https://patchwork.freedesktop.org/series/42968/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4179 -> Patchwork_9003 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42968/revisions/3/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9003 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       DMESG-WARN (fdo#105128) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2600:        DMESG-WARN (fdo#102365) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    
  fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128


== Participating hosts (41 -> 37) ==

  Additional (1): fi-byt-j1900 
  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4179 -> Patchwork_9003

  CI_DRM_4179: be6d36ea8d6130f54ab5ec816555f1a46bd95f7b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4479: 89ae332745e31a075747a63ac5acc5baccf75769 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9003: a50a68c1703169f0d19b66432a61c3ff4d39ec32 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit


== Linux commits ==

a50a68c17031 drm/dsc: Add helpers for DSC picture parameter set infoframes
a78445d01b83 drm/dsc: Define VESA Display Stream Compression Capabilities
b02ff15cb266 drm/dsc: Define Display Stream Compression PPS infoframe
7be7958fe7e4 drm/dp: Define payload size for DP SDP PPS packet

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9003/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for DRM helpers for Display Stream Compression PPS infoframes (rev3)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev3)
URL   : https://patchwork.freedesktop.org/series/42968/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4179_full -> Patchwork_9003_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9003_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9003_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42968/revisions/3/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9003_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@gem_eio@in-flight-contexts-immediate:
      shard-hsw:          PASS -> DMESG-WARN +1

    igt@gem_eio@unwedge-stress:
      shard-snb:          PASS -> DMESG-WARN +1

    igt@gem_eio@wait-wedge-immediate:
      shard-apl:          PASS -> DMESG-WARN

    
    ==== Warnings ====

    igt@gem_mocs_settings@mocs-rc6-dirty-render:
      shard-kbl:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_9003_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@fence-restore-tiled2untiled:
      shard-apl:          PASS -> DMESG-WARN (fdo#105602)

    igt@gem_exec_basic@basic-bsd:
      shard-apl:          PASS -> INCOMPLETE (fdo#103927)

    igt@gem_ppgtt@blt-vs-render-ctxn:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665, fdo#106023)

    igt@kms_flip@2x-plain-flip-fb-recreate:
      shard-glk:          PASS -> FAIL (fdo#100368)

    igt@kms_flip@basic-flip-vs-wf_vblank:
      shard-hsw:          PASS -> FAIL (fdo#103928)

    igt@kms_flip@flip-vs-expired-vblank:
      shard-glk:          PASS -> FAIL (fdo#102887, fdo#105363)

    igt@kms_flip@plain-flip-ts-check-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#100368)

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724)

    igt@kms_setmode@basic:
      shard-kbl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@drv_suspend@fence-restore-untiled:
      shard-glk:          DMESG-WARN -> PASS

    igt@gem_eio@in-flight-immediate:
      shard-hsw:          DMESG-WARN -> PASS +1

    igt@gem_eio@in-flight-internal-10ms:
      shard-apl:          DMESG-WARN -> PASS

    igt@gem_eio@in-flight-suspend:
      shard-snb:          DMESG-WARN -> PASS +1

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
      shard-glk:          FAIL -> PASS +3

    igt@kms_cursor_crc@cursor-64x21-sliding:
      shard-kbl:          DMESG-WARN (fdo#105602, fdo#103558) -> PASS +4

    igt@kms_cursor_legacy@flip-vs-cursor-legacy:
      shard-hsw:          FAIL (fdo#102670) -> PASS

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          FAIL (fdo#105363) -> PASS

    igt@kms_flip_tiling@flip-x-tiled:
      shard-glk:          FAIL (fdo#104724, fdo#103822) -> PASS

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-snb:          FAIL (fdo#104724, fdo#103166) -> PASS

    igt@kms_rotation_crc@primary-rotation-180:
      shard-snb:          FAIL (fdo#104724, fdo#103925) -> PASS

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS
      shard-hsw:          FAIL (fdo#99912) -> PASS

    igt@perf@polling:
      shard-hsw:          FAIL (fdo#102252) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4179 -> Patchwork_9003

  CI_DRM_4179: be6d36ea8d6130f54ab5ec816555f1a46bd95f7b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4479: 89ae332745e31a075747a63ac5acc5baccf75769 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9003: a50a68c1703169f0d19b66432a61c3ff4d39ec32 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9003/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 2/4] drm/dsc: Define Display Stream Compression PPS infoframe

[Harry Wentland]

On 2018-05-14 10:05 PM, Manasi Navare wrote:
> This patch defines a new header file for all the DSC 1.2 structures
> and creates a structure for PPS infoframe which will be used to send
> picture parameter set secondary data packet for display stream compression.
> All the PPS infoframe syntax elements are taken from DSC 1.2 specification
> from VESA.
> 
> v2:
> * Fix the comments for kernel-doc
> 
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  include/drm/drm_dsc.h | 437 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 437 insertions(+)
>  create mode 100644 include/drm/drm_dsc.h
> 
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> new file mode 100644
> index 0000000..5ee72e8
> --- /dev/null
> +++ b/include/drm/drm_dsc.h
> @@ -0,0 +1,437 @@
> +/*
> + * Copyright (C) 2018 Intel Corp.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + * Manasi Navare <manasi.d.navare@intel.com>
> + */
> +
> +#ifndef DRM_DSC_H_
> +#define DRM_DSC_H_
> +
> +#include <drm/drm_dp_helper.h>
> +
> +#define DSC_NUM_BUF_RANGES	15
> +
> +/**
> + * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
> + *
> + * The VESA DSC standard defines picture parameter set (PPS) which display stream
> + * compression encoders must communicate to decoders. The PPS is encapsulated
> + * in 128 bytes (PPS 0 through PPS 127). The fields in this structure are as per
> + * Table 4.1 in Vesa DSC specification v1.1/v1.2.
> + * The PPS fields that span over more than a byte should be stored in Big Endian
> + * format.
> + */
> +struct picture_parameter_set {
> +	/**
> +	 * @dsc_version_minor:
> +	 * PPS0[3:0] - Contains Minor version of DSC
> +	 */
> +	u8 dsc_version_minor:4;
> +	/**
> +	 * @dsc_version_major:
> +	 * PPS0[7:4] - Contains major version of DSC
> +	 */
> +	u8 dsc_version_major:4;
> +	/**
> +	 * @pps_identifier:
> +	 * PPS1[7:0] - Application specific identifier that can be
> +	 * used to differentiate between different PPS tables.
> +	 */
> +	u8 pps_identifier;
> +	/**
> +	 * @pps2_reserved:
> +	 * PPS2[7:0]- RESERVED Byte
> +	 */
> +	u8 pps2_reserved;
> +	/**
> +	 * @linebuf_depth:
> +	 * PPS3[3:0] - Contains linebuffer bit depth used to generate
> +	 * the bitstream. (0x0 - 16 bits for DSc 1.2, 0x8 - 8 bits,
> +	 * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
> +	 * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
> +	 */
> +	u8 linebuf_depth:4;
> +	/**
> +	 * @bits_per_component:
> +	 * PPS3[7:4] - Bits per component fo rthe original pixels

typo: "for the"

> +	 * of the encoded picture.
> +	 */

Would it make sense to indicate in the comments what the values mean?

From the spec:
0x0 = 16bpc (allowed only when dsc_version_minor = 0x2).
0x8 = 8bpc.
0xA = 10bpc.
0xC = 12bpc.
0xE = 14bpc (allowed only when dsc_version_minor = 0x2).
All other encodings are RESERVED.

Harry

> +	u8 bits_per_component:4;
> +	/**
> +	 * @bpp_high:
> +	 * PPS4[1:0] - These are the most significant 2 bits of
> +	 * compressed BPP bits_per_pixel[9:0] syntax element.
> +	 */
> +	u8 bpp_high:2;
> +	/**
> +	 * @vbr_enable:
> +	 * PPS4[2] - 0 = VBR disabled, 1 = VBR enabled
> +	 */
> +	u8 vbr_enable:1;
> +	/**
> +	 * @simple_422:
> +	 * PPS4[3] - Indicates if decoder drops samples to
> +	 * reconstruct the 4:2:2 picture.
> +	 */
> +	u8 simple_422:1;
> +	/**
> +	 * @convert_rgb:
> +	 * PPS4[4] - Indicates if DSC color space conversion is active
> +	 */
> +	u8 convert_rgb:1;
> +	/**
> +	 * @block_pred_enable:
> +	 * PPS4[5] - Indicates if BP is used to code any groups in picture
> +	 */
> +	u8 block_pred_enable:1;
> +	/**
> +	 * @pps4_reserved:
> +	 * PPS4[7:6] - Reseved bits
> +	 */
> +	u8 pps4_reserved:2;
> +	/**
> +	 * @bpp_low:
> +	 * PPS5[7:0] - This indicates the lower significant 8 bits of
> +	 * the compressed BPP bits_per_pixel[9:0] element.
> +	 */
> +	u8 bpp_low;
> +	/**
> +	 * @pic_height:
> +	 * PPS6[7:0], PPS7[7:0] -  Specifies the number of pixel rows within
> +	 * the raster.
> +	 */
> +	u16 pic_height;
> +	/**
> +	 * @pic_width:
> +	 * PPS8[7:0], PPS9[7:0] - Number of pixel columns within the raster.
> +	 */
> +	u16 pic_width;
> +	/**
> +	 * @slice_height:
> +	 * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
> +	 */
> +	u16 slice_height;
> +	/**
> +	 * @slice_width:
> +	 * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
> +	 */
> +	u16 slice_width;
> +	/**
> +	 * @chunk_size:
> +	 * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
> +	 * that are used for slice multiplexing.
> +	 */
> +	u16 chunk_size;
> +	/**
> +	 * @initial_xmit_delay_high:
> +	 * PPS16[1:0] - Most Significant two bits of initial transmission delay.
> +	 * It specifies the number of pixel times that the encoder waits before
> +	 * transmitting data from its rate buffer.
> +	 */
> +	u8 initial_xmit_delay_high:2;
> +	/**
> +	 * @pps16_reserved:
> +	 * PPS16[7:2] - Reserved
> +	 */
> +	u8 pps16_reserved:6;
> +	/**
> +	 * @initial_xmit_delay_low:
> +	 * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
> +	 */
> +	u8 initial_xmit_delay_low;
> +	/**
> +	 * @initial_dec_delay:
> +	 *
> +	 * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
> +	 * of pixel times that the decoder accumulates data in its rate buffer
> +	 * before starting to decode and output pixels.
> +	 */
> +	u16 initial_dec_delay;
> +	/**
> +	 * @pps20_reserved:
> +	 *
> +	 * PPS20[7:0] - Reserved
> +	 */
> +	u8 pps20_reserved;
> +	/**
> +	 * @initial_scale_value:
> +	 * PPS21[5:0] - Initial rcXformScale factor used at beginning
> +	 * of a slice.
> +	 */
> +	u8 initial_scale_value:6;
> +	/**
> +	 * @pps21_reserved:
> +	 * PPS21[7:6] - Reserved
> +	 */
> +	u8 pps21_reserved:2;
> +	/**
> +	 * @scale_increment_interval:
> +	 * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
> +	 * the rcXformScale factor at end of a slice.
> +	 */
> +	u16 scale_increment_interval;
> +	/**
> +	 * @scale_decrement_interval_high:
> +	 * PPS24[3:0] - Higher 4 bits indicating number of group times between
> +	 * decrementing the rcXformScale factor at beginning of a slice.
> +	 */
> +	u8 scale_decrement_interval_high:4;
> +	/**
> +	 * @pps24_reserved:
> +	 * PPS24[7:4] - Reserved
> +	 */
> +	u8 pps24_reserved:4;
> +	/**
> +	 * @scale_decrement_interval_low:
> +	 * PPS25[7:0] - Lower 8 bits of scale decrement interval
> +	 */
> +	u8 scale_decrement_interval_low;
> +	/**
> +	 * @pps26_reserved:
> +	 * PPS26[7:0]
> +	 */
> +	u8 pps26_reserved;
> +	/**
> +	 * @first_line_bpg_offset:
> +	 * PPS27[4:0] - Number of additional bits that are allocated
> +	 * for each group on first line of a slice.
> +	 */
> +	u8 first_line_bpg_offset:5;
> +	/**
> +	 * @pps27_reserved:
> +	 * PPS27[7:5]
> +	 */
> +	u8 pps27_reserved:3;
> +	/**
> +	 * @nfl_bpg_offset:
> +	 * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
> +	 * deallocated for each group for groups after the first line of slice.
> +	 */
> +	u16 nfl_bpg_offset;
> +	/**
> +	 * @slice_bpg_offset:
> +	 * PPS30, PPS31[7:0] - Number of bits that are deallocated for each group
> +	 * to enforce the slice constraint.
> +	 */
> +	u16 slice_bpg_offset;
> +	/**
> +	 * @initial_offset:
> +	 * PPS32,33[7:0] - Initial value for rcXformOffset
> +	 */
> +	u16 initial_offset;
> +	/**
> +	 * @final_offset:
> +	 * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
> +	 */
> +	u16 final_offset;
> +	/**
> +	 * @flatness_min_qp:
> +	 * PPS36[4:0] - Minimum QP at which flatness is signaled and
> +	 * flatness QP adjustment is made.
> +	 */
> +	u8 flatness_min_qp:5;
> +	/**
> +	 * @pps36_reserved:
> +	 * PPS36[7:5] - Reserved
> +	 */
> +	u8 pps36_reserved:3;
> +	/**
> +	 * @flatness_max_qp:
> +	 * PPS37[4:0] - Max QP at which flatness is signalled and
> +	 * the flatness adjustment is made.
> +	 */
> +	u8 flatness_max_qp:5;
> +	/**
> +	 * @pps37_reserved:
> +	 * PPS37[7:5]
> +	 */
> +	u8 pps37_reserved:3;
> +	/**
> +	 * @rc_model_size:
> +	 * PPS38,39[7:0] - Number of bits within RC Model.
> +	 */
> +	u16 rc_model_size;
> +	/**
> +	 * @rc_edge_factor:
> +	 * PPS40[3:0] - Ratio of current activity vs, previous
> +	 * activity to determine presence of edge.
> +	 */
> +	u8 rc_edge_factor:4;
> +	/**
> +	 * @pps40_reserved:
> +	 * PPS40[7:4]
> +	 */
> +	u8 pps40_reserved:4;
> +	/**
> +	 * @rc_quant_incr_limit0:
> +	 * PPS41[4:0] - QP threshold used in short term RC
> +	 */
> +	u8 rc_quant_incr_limit0:5;
> +	/**
> +	 * @pps41_reserved:
> +	 * PPS41[7:5]
> +	 */
> +	u8 pps41_reserved:3;
> +	/**
> +	 * @rc_quant_incr_limit1:
> +	 * PPS42[4:0] - QP threshold used in short term RC
> +	 */
> +	u8 rc_quant_incr_limit1:5;
> +	/**
> +	 * @pps42_reserved:
> +	 * PPS42[7:5]
> +	 */
> +	u8 pps42_reserved:3;
> +	/**
> +	 * @rc_tgt_offset_lo:
> +	 * Lower end of the variability range around the target
> +	 * bits per group that is allowed by short term RC.
> +	 */
> +	u8 rc_tgt_offset_lo:4;
> +	/**
> +	 * @rc_tgt_offset_hi:
> +	 * Upper end of the variability range around the target
> +	 * bits per group that i allowed by short term rc.
> +	 */
> +	u8 rc_tgt_offset_hi:4;
> +	/**
> +	 * @rc_buf_thresh:
> +	 * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
> +	 * the 15 ranges defined by 14 thresholds.
> +	 */
> +	u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
> +	/**
> +	 * @rc_range_parameters:
> +	 * PPS58[7:0] - PPS87[7:0]
> +	 * Parameters that correspond to each of the 15 ranges.
> +	 */
> +	u16 rc_range_parameters[DSC_NUM_BUF_RANGES];
> +	/**
> +	 * @native_422:
> +	 * PPS88[0] - 0 = Native 4:2:2 not used
> +	 * 1 = Native 4:2:2 used
> +	 */
> +	u8 native_422:1;
> +	/**
> +	 * @native_420:
> +	 * PPS88[1] - 0 = Native 4:2:0 not used
> +	 * 1 = Native 4:2:0 not used.
> +	 */
> +	u8 native_420:1;
> +	/**
> +	 * @pps88_reserved:
> +	 * PPS[7:2] - Reserved 6 bits
> +	 */
> +	u8 pps88_reserved:6;
> +	/**
> +	 * @second_line_bpg_offset:
> +	 * PPS89[4:0] - Additional bits/group budget for the
> +	 * second line of a slice in Native 4:2:0 mode.
> +	 * Set to 0 if DSC minor version is 1 or native420 is 0.
> +	 */
> +	u8 second_line_bpg_offset:5;
> +	/**
> +	 * @pps89_reserved:
> +	 * PPS89[7:5] - Reserved
> +	 */
> +	u8 pps89_reserved:3;
> +	/**
> +	 * @nsl_bpg_offset:
> +	 * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
> +	 * for each group that is not in the second line of a slice.
> +	 */
> +	u16 nsl_bpg_offset;
> +	/**
> +	 * @second_line_offset_adj:
> +	 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
> +	 * line in Native 4:2:0 mode.
> +	 */
> +	u16 second_line_offset_adj;
> +	/**
> +	 * @pps_long_94_reserved:
> +	 * PPS 94, 95, 96, 97 - Reserved
> +	 */
> +	u32 pps_long_94_reserved;
> +	/**
> +	 * @pps_long_98_reserved:
> +	 * PPS 98, 99, 100, 101 - Reserved
> +	 */
> +	u32 pps_long_98_reserved;
> +	/**
> +	 * @pps_long_102_reserved:
> +	 * PPS 102, 103, 104, 105 - Reserved
> +	 */
> +	u32 pps_long_102_reserved;
> +	/**
> +	 * @pps_long_106_reserved:
> +	 * PPS 106, 107, 108, 109 - reserved
> +	 */
> +	u32 pps_long_106_reserved;
> +	/**
> +	 * @pps_long_110_reserved:
> +	 * PPS 110, 111, 112, 113 - reserved
> +	 */
> +	u32 pps_long_110_reserved;
> +	/**
> +	 * @pps_long_114_reserved:
> +	 * PPS 114 - 117 - reserved
> +	 */
> +	u32 pps_long_114_reserved;
> +	/**
> +	 * @pps_long_118_reserved:
> +	 * PPS 118 - 121 - reserved
> +	 */
> +	u32 pps_long_118_reserved;
> +	/**
> +	 * @pps_long_122_reserved:
> +	 * PPS 122- 125 - reserved
> +	 */
> +	u32 pps_long_122_reserved;
> +	/**
> +	 * @pps_short_126_reserved:
> +	 * PPS 126, 127 - reserved
> +	 */
> +	u16 pps_short_126_reserved;
> +};
> +
> +/**
> +* struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter Set Metadata
> +*
> +* This structure represents the DSC PPS infoframe required to send the Picture Parameter Set
> +* metadata required before enabling VESA Display Stream Compression. This is based on the
> +* DP Secondary Data Packet structure and comprises of SDP Header as defined in drm_dp_helper.h
> +* and PPS payload.
> +*
> +* @pps_header:
> +*
> +* Header for PPS as per DP SDP header format
> +*
> +* @pps_payload:
> +*
> +* PPS payload fields as per DSC specification Table 4-1
> +*/
> +struct drm_dsc_pps_infoframe {
> +	struct dp_sdp_header pps_header;
> +	struct picture_parameter_set pps_payload;
> +} __packed;
> +
> +#endif /* _DRM_DSC_H_ */
> 
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Re: [PATCH v2 3/4] drm/dsc: Define VESA Display Stream Compression Capabilities

[Harry Wentland]

On 2018-05-14 10:05 PM, Manasi Navare wrote:
> From: Gaurav K Singh <gaurav.k.singh@intel.com>
> 
> This defines all the DSC parameters as per the VESA DSC spec
> that will be required for DSC encoder/decoder
> 
> v2: Define this struct in DRM (From Manasi)
> * Changed the data types to u8/u16 instead of unsigned longs (Manasi)
> * Remove driver specific fields (Manasi)
> * Move this struct definition to DRM (Manasi)
> * Define DSC 1.2 parameters (Manasi)
> * Use DSC_NUM_BUF_RANGES (Manasi)
> * Call it drm_dsc_config (Manasi)
> 
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  include/drm/drm_dsc.h | 111 ++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 111 insertions(+)
> 
> diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> index 5ee72e8..04501e2 100644
> --- a/include/drm/drm_dsc.h
> +++ b/include/drm/drm_dsc.h
> @@ -30,6 +30,117 @@
>  
>  #define DSC_NUM_BUF_RANGES	15
>  
> +/* VESA Display Stream Compression DSC 1.2 constants */
> +#define DSC_NUM_BUF_RANGES		15

Duplicate definition of previous line.

Harry

> +
> +/* Configuration for a single Rate Control model range */
> +struct dsc_rc_range_parameters {
> +	/* Min Quantization Parameters allowed for this range */
> +	u8 range_min_qp;
> +	/* Max Quantization Parameters allowed for this range */
> +	u8 range_max_qp;
> +	/* Bits/group offset to apply to target for this group */
> +	u8 range_bpg_offset;
> +};
> +
> +struct drm_dsc_config {
> +	/* Bits / component for previous reconstructed line buffer */
> +	u8 line_buf_depth;
> +	/* Bits per component to code (must be 8, 10, or 12) */
> +	u8 bits_per_component;
> +	/*
> +	 * Flag indicating to do RGB - YCoCg conversion
> +	 * and back (should be 1 for RGB input)
> +	 */
> +	bool convert_rgb;
> +	u8 slice_count;
> +	/* Slice Width */
> +	u16 slice_width;
> +	/* Slice Height */
> +	u16 slice_height;
> +	/*
> +	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
> +	 * outside of DSC encode/decode algorithm)
> +	 */
> +	bool enable422;
> +	/* Picture Width */
> +	u16 pic_width;
> +	/* Picture Height */
> +	u16 pic_height;
> +	/* Offset to bits/group used by RC to determine QP adjustment */
> +	u8 rc_tgt_offset_high;
> +	/* Offset to bits/group used by RC to determine QP adjustment */
> +	u8 rc_tgt_offset_low;
> +	/* Bits/pixel target << 4 (ie., 4 fractional bits) */
> +	u16 bits_per_pixel;
> +	/*
> +	 * Factor to determine if an edge is present based
> +	 * on the bits produced
> +	 */
> +	u8 rc_edge_factor;
> +	/* Slow down incrementing once the range reaches this value */
> +	u8 rc_quant_incr_limit1;
> +	/* Slow down incrementing once the range reaches this value */
> +	u8 rc_quant_incr_limit0;
> +	/* Number of pixels to delay the initial transmission */
> +	u16 initial_xmit_delay;
> +	/* Number of pixels to delay the VLD on the decoder,not including SSM */
> +	u16  initial_dec_delay;
> +	/* Block prediction enable */
> +	bool block_pred_enable;
> +	/* Bits/group offset to use for first line of the slice */
> +	u8 first_line_bpg_offset;
> +	/* Value to use for RC model offset at slice start */
> +	u16 initial_offset;
> +	/* Thresholds defining each of the buffer ranges */
> +	u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
> +	/* Parameters for each of the RC ranges */
> +	struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> +	/* Total size of RC model */
> +	u16 rc_model_size;
> +	/* Minimum QP where flatness information is sent */
> +	u8 flatness_min_qp;
> +	/* Maximum QP where flatness information is sent */
> +	u8 flatness_max_qp;
> +	/* Initial value for scale factor */
> +	u8 initial_scale_value;
> +	/* Decrement scale factor every scale_decrement_interval groups */
> +	u16 scale_decrement_interval;
> +	/* Increment scale factor every scale_increment_interval groups */
> +	u16 scale_increment_interval;
> +	/* Non-first line BPG offset to use */
> +	u16 nfl_bpg_offset;
> +	/* BPG offset used to enforce slice bit */
> +	u16 slice_bpg_offset;
> +	/* Final RC linear transformation offset value */
> +	u16 final_offset;
> +	/* Enable on-off VBR (ie., disable stuffing bits) */
> +	bool vbr_enable;
> +	/* Mux word size (in bits) for SSM mode */
> +	u8 mux_word_size;
> +	/*
> +	 * The (max) size in bytes of the "chunks" that are
> +	 * used in slice multiplexing
> +	 */
> +	u16 slice_chunk_size;
> +	/* Rate Control buffer siz in bits */
> +	u16 rc_bits;
> +	/* DSC Minor Version */
> +	u8 dsc_version_minor;
> +	/* DSC Major version */
> +	u8 dsc_version_major;
> +	/* Native 4:2:2 support */
> +	bool native_422;
> +	/* Native 4:2:0 support */
> +	bool native_420;
> +	/* Additional bits/grp for seconnd line of slice for native 4:2:0 */
> +	u8 second_line_bpg_offset;
> +	/* Num of bits deallocated for each grp that is not in second line of slice */
> +	u16 nsl_bpg_offset;
> +	/* Offset adj fr second line in Native 4:2:0 mode */
> +	u16 second_line_offset_adj;
> +};
> +
>  /**
>   * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
>   *
> 
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Re: [PATCH v2 2/4] drm/dsc: Define Display Stream Compression PPS infoframe

[Manasi Navare]

On Wed, May 16, 2018 at 02:14:56PM -0400, Harry Wentland wrote:
> On 2018-05-14 10:05 PM, Manasi Navare wrote:
> > This patch defines a new header file for all the DSC 1.2 structures
> > and creates a structure for PPS infoframe which will be used to send
> > picture parameter set secondary data packet for display stream compression.
> > All the PPS infoframe syntax elements are taken from DSC 1.2 specification
> > from VESA.
> > 
> > v2:
> > * Fix the comments for kernel-doc
> > 
> > Cc: dri-devel@lists.freedesktop.org
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> >  include/drm/drm_dsc.h | 437 ++++++++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 437 insertions(+)
> >  create mode 100644 include/drm/drm_dsc.h
> > 
> > diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
> > new file mode 100644
> > index 0000000..5ee72e8
> > --- /dev/null
> > +++ b/include/drm/drm_dsc.h
> > @@ -0,0 +1,437 @@
> > +/*
> > + * Copyright (C) 2018 Intel Corp.
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a
> > + * copy of this software and associated documentation files (the "Software"),
> > + * to deal in the Software without restriction, including without limitation
> > + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors:
> > + * Manasi Navare <manasi.d.navare@intel.com>
> > + */
> > +
> > +#ifndef DRM_DSC_H_
> > +#define DRM_DSC_H_
> > +
> > +#include <drm/drm_dp_helper.h>
> > +
> > +#define DSC_NUM_BUF_RANGES	15
> > +
> > +/**
> > + * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
> > + *
> > + * The VESA DSC standard defines picture parameter set (PPS) which display stream
> > + * compression encoders must communicate to decoders. The PPS is encapsulated
> > + * in 128 bytes (PPS 0 through PPS 127). The fields in this structure are as per
> > + * Table 4.1 in Vesa DSC specification v1.1/v1.2.
> > + * The PPS fields that span over more than a byte should be stored in Big Endian
> > + * format.
> > + */
> > +struct picture_parameter_set {
> > +	/**
> > +	 * @dsc_version_minor:
> > +	 * PPS0[3:0] - Contains Minor version of DSC
> > +	 */
> > +	u8 dsc_version_minor:4;
> > +	/**
> > +	 * @dsc_version_major:
> > +	 * PPS0[7:4] - Contains major version of DSC
> > +	 */
> > +	u8 dsc_version_major:4;
> > +	/**
> > +	 * @pps_identifier:
> > +	 * PPS1[7:0] - Application specific identifier that can be
> > +	 * used to differentiate between different PPS tables.
> > +	 */
> > +	u8 pps_identifier;
> > +	/**
> > +	 * @pps2_reserved:
> > +	 * PPS2[7:0]- RESERVED Byte
> > +	 */
> > +	u8 pps2_reserved;
> > +	/**
> > +	 * @linebuf_depth:
> > +	 * PPS3[3:0] - Contains linebuffer bit depth used to generate
> > +	 * the bitstream. (0x0 - 16 bits for DSc 1.2, 0x8 - 8 bits,
> > +	 * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
> > +	 * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
> > +	 */
> > +	u8 linebuf_depth:4;
> > +	/**
> > +	 * @bits_per_component:
> > +	 * PPS3[7:4] - Bits per component fo rthe original pixels
> 
> typo: "for the"

Yes wll fix that.

> 
> > +	 * of the encoded picture.
> > +	 */
> 
> Would it make sense to indicate in the comments what the values mean?
> 
> From the spec:
> 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2).
> 0x8 = 8bpc.
> 0xA = 10bpc.
> 0xC = 12bpc.
> 0xE = 14bpc (allowed only when dsc_version_minor = 0x2).
> All other encodings are RESERVED.
> 
> Harry

This is definitely a good point. I can add these in the block comment for
bits_per_component like I have added for linebuf_depth.

Regards
Manasi

> 
> > +	u8 bits_per_component:4;
> > +	/**
> > +	 * @bpp_high:
> > +	 * PPS4[1:0] - These are the most significant 2 bits of
> > +	 * compressed BPP bits_per_pixel[9:0] syntax element.
> > +	 */
> > +	u8 bpp_high:2;
> > +	/**
> > +	 * @vbr_enable:
> > +	 * PPS4[2] - 0 = VBR disabled, 1 = VBR enabled
> > +	 */
> > +	u8 vbr_enable:1;
> > +	/**
> > +	 * @simple_422:
> > +	 * PPS4[3] - Indicates if decoder drops samples to
> > +	 * reconstruct the 4:2:2 picture.
> > +	 */
> > +	u8 simple_422:1;
> > +	/**
> > +	 * @convert_rgb:
> > +	 * PPS4[4] - Indicates if DSC color space conversion is active
> > +	 */
> > +	u8 convert_rgb:1;
> > +	/**
> > +	 * @block_pred_enable:
> > +	 * PPS4[5] - Indicates if BP is used to code any groups in picture
> > +	 */
> > +	u8 block_pred_enable:1;
> > +	/**
> > +	 * @pps4_reserved:
> > +	 * PPS4[7:6] - Reseved bits
> > +	 */
> > +	u8 pps4_reserved:2;
> > +	/**
> > +	 * @bpp_low:
> > +	 * PPS5[7:0] - This indicates the lower significant 8 bits of
> > +	 * the compressed BPP bits_per_pixel[9:0] element.
> > +	 */
> > +	u8 bpp_low;
> > +	/**
> > +	 * @pic_height:
> > +	 * PPS6[7:0], PPS7[7:0] -  Specifies the number of pixel rows within
> > +	 * the raster.
> > +	 */
> > +	u16 pic_height;
> > +	/**
> > +	 * @pic_width:
> > +	 * PPS8[7:0], PPS9[7:0] - Number of pixel columns within the raster.
> > +	 */
> > +	u16 pic_width;
> > +	/**
> > +	 * @slice_height:
> > +	 * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
> > +	 */
> > +	u16 slice_height;
> > +	/**
> > +	 * @slice_width:
> > +	 * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
> > +	 */
> > +	u16 slice_width;
> > +	/**
> > +	 * @chunk_size:
> > +	 * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
> > +	 * that are used for slice multiplexing.
> > +	 */
> > +	u16 chunk_size;
> > +	/**
> > +	 * @initial_xmit_delay_high:
> > +	 * PPS16[1:0] - Most Significant two bits of initial transmission delay.
> > +	 * It specifies the number of pixel times that the encoder waits before
> > +	 * transmitting data from its rate buffer.
> > +	 */
> > +	u8 initial_xmit_delay_high:2;
> > +	/**
> > +	 * @pps16_reserved:
> > +	 * PPS16[7:2] - Reserved
> > +	 */
> > +	u8 pps16_reserved:6;
> > +	/**
> > +	 * @initial_xmit_delay_low:
> > +	 * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
> > +	 */
> > +	u8 initial_xmit_delay_low;
> > +	/**
> > +	 * @initial_dec_delay:
> > +	 *
> > +	 * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
> > +	 * of pixel times that the decoder accumulates data in its rate buffer
> > +	 * before starting to decode and output pixels.
> > +	 */
> > +	u16 initial_dec_delay;
> > +	/**
> > +	 * @pps20_reserved:
> > +	 *
> > +	 * PPS20[7:0] - Reserved
> > +	 */
> > +	u8 pps20_reserved;
> > +	/**
> > +	 * @initial_scale_value:
> > +	 * PPS21[5:0] - Initial rcXformScale factor used at beginning
> > +	 * of a slice.
> > +	 */
> > +	u8 initial_scale_value:6;
> > +	/**
> > +	 * @pps21_reserved:
> > +	 * PPS21[7:6] - Reserved
> > +	 */
> > +	u8 pps21_reserved:2;
> > +	/**
> > +	 * @scale_increment_interval:
> > +	 * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
> > +	 * the rcXformScale factor at end of a slice.
> > +	 */
> > +	u16 scale_increment_interval;
> > +	/**
> > +	 * @scale_decrement_interval_high:
> > +	 * PPS24[3:0] - Higher 4 bits indicating number of group times between
> > +	 * decrementing the rcXformScale factor at beginning of a slice.
> > +	 */
> > +	u8 scale_decrement_interval_high:4;
> > +	/**
> > +	 * @pps24_reserved:
> > +	 * PPS24[7:4] - Reserved
> > +	 */
> > +	u8 pps24_reserved:4;
> > +	/**
> > +	 * @scale_decrement_interval_low:
> > +	 * PPS25[7:0] - Lower 8 bits of scale decrement interval
> > +	 */
> > +	u8 scale_decrement_interval_low;
> > +	/**
> > +	 * @pps26_reserved:
> > +	 * PPS26[7:0]
> > +	 */
> > +	u8 pps26_reserved;
> > +	/**
> > +	 * @first_line_bpg_offset:
> > +	 * PPS27[4:0] - Number of additional bits that are allocated
> > +	 * for each group on first line of a slice.
> > +	 */
> > +	u8 first_line_bpg_offset:5;
> > +	/**
> > +	 * @pps27_reserved:
> > +	 * PPS27[7:5]
> > +	 */
> > +	u8 pps27_reserved:3;
> > +	/**
> > +	 * @nfl_bpg_offset:
> > +	 * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
> > +	 * deallocated for each group for groups after the first line of slice.
> > +	 */
> > +	u16 nfl_bpg_offset;
> > +	/**
> > +	 * @slice_bpg_offset:
> > +	 * PPS30, PPS31[7:0] - Number of bits that are deallocated for each group
> > +	 * to enforce the slice constraint.
> > +	 */
> > +	u16 slice_bpg_offset;
> > +	/**
> > +	 * @initial_offset:
> > +	 * PPS32,33[7:0] - Initial value for rcXformOffset
> > +	 */
> > +	u16 initial_offset;
> > +	/**
> > +	 * @final_offset:
> > +	 * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
> > +	 */
> > +	u16 final_offset;
> > +	/**
> > +	 * @flatness_min_qp:
> > +	 * PPS36[4:0] - Minimum QP at which flatness is signaled and
> > +	 * flatness QP adjustment is made.
> > +	 */
> > +	u8 flatness_min_qp:5;
> > +	/**
> > +	 * @pps36_reserved:
> > +	 * PPS36[7:5] - Reserved
> > +	 */
> > +	u8 pps36_reserved:3;
> > +	/**
> > +	 * @flatness_max_qp:
> > +	 * PPS37[4:0] - Max QP at which flatness is signalled and
> > +	 * the flatness adjustment is made.
> > +	 */
> > +	u8 flatness_max_qp:5;
> > +	/**
> > +	 * @pps37_reserved:
> > +	 * PPS37[7:5]
> > +	 */
> > +	u8 pps37_reserved:3;
> > +	/**
> > +	 * @rc_model_size:
> > +	 * PPS38,39[7:0] - Number of bits within RC Model.
> > +	 */
> > +	u16 rc_model_size;
> > +	/**
> > +	 * @rc_edge_factor:
> > +	 * PPS40[3:0] - Ratio of current activity vs, previous
> > +	 * activity to determine presence of edge.
> > +	 */
> > +	u8 rc_edge_factor:4;
> > +	/**
> > +	 * @pps40_reserved:
> > +	 * PPS40[7:4]
> > +	 */
> > +	u8 pps40_reserved:4;
> > +	/**
> > +	 * @rc_quant_incr_limit0:
> > +	 * PPS41[4:0] - QP threshold used in short term RC
> > +	 */
> > +	u8 rc_quant_incr_limit0:5;
> > +	/**
> > +	 * @pps41_reserved:
> > +	 * PPS41[7:5]
> > +	 */
> > +	u8 pps41_reserved:3;
> > +	/**
> > +	 * @rc_quant_incr_limit1:
> > +	 * PPS42[4:0] - QP threshold used in short term RC
> > +	 */
> > +	u8 rc_quant_incr_limit1:5;
> > +	/**
> > +	 * @pps42_reserved:
> > +	 * PPS42[7:5]
> > +	 */
> > +	u8 pps42_reserved:3;
> > +	/**
> > +	 * @rc_tgt_offset_lo:
> > +	 * Lower end of the variability range around the target
> > +	 * bits per group that is allowed by short term RC.
> > +	 */
> > +	u8 rc_tgt_offset_lo:4;
> > +	/**
> > +	 * @rc_tgt_offset_hi:
> > +	 * Upper end of the variability range around the target
> > +	 * bits per group that i allowed by short term rc.
> > +	 */
> > +	u8 rc_tgt_offset_hi:4;
> > +	/**
> > +	 * @rc_buf_thresh:
> > +	 * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
> > +	 * the 15 ranges defined by 14 thresholds.
> > +	 */
> > +	u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
> > +	/**
> > +	 * @rc_range_parameters:
> > +	 * PPS58[7:0] - PPS87[7:0]
> > +	 * Parameters that correspond to each of the 15 ranges.
> > +	 */
> > +	u16 rc_range_parameters[DSC_NUM_BUF_RANGES];
> > +	/**
> > +	 * @native_422:
> > +	 * PPS88[0] - 0 = Native 4:2:2 not used
> > +	 * 1 = Native 4:2:2 used
> > +	 */
> > +	u8 native_422:1;
> > +	/**
> > +	 * @native_420:
> > +	 * PPS88[1] - 0 = Native 4:2:0 not used
> > +	 * 1 = Native 4:2:0 not used.
> > +	 */
> > +	u8 native_420:1;
> > +	/**
> > +	 * @pps88_reserved:
> > +	 * PPS[7:2] - Reserved 6 bits
> > +	 */
> > +	u8 pps88_reserved:6;
> > +	/**
> > +	 * @second_line_bpg_offset:
> > +	 * PPS89[4:0] - Additional bits/group budget for the
> > +	 * second line of a slice in Native 4:2:0 mode.
> > +	 * Set to 0 if DSC minor version is 1 or native420 is 0.
> > +	 */
> > +	u8 second_line_bpg_offset:5;
> > +	/**
> > +	 * @pps89_reserved:
> > +	 * PPS89[7:5] - Reserved
> > +	 */
> > +	u8 pps89_reserved:3;
> > +	/**
> > +	 * @nsl_bpg_offset:
> > +	 * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
> > +	 * for each group that is not in the second line of a slice.
> > +	 */
> > +	u16 nsl_bpg_offset;
> > +	/**
> > +	 * @second_line_offset_adj:
> > +	 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
> > +	 * line in Native 4:2:0 mode.
> > +	 */
> > +	u16 second_line_offset_adj;
> > +	/**
> > +	 * @pps_long_94_reserved:
> > +	 * PPS 94, 95, 96, 97 - Reserved
> > +	 */
> > +	u32 pps_long_94_reserved;
> > +	/**
> > +	 * @pps_long_98_reserved:
> > +	 * PPS 98, 99, 100, 101 - Reserved
> > +	 */
> > +	u32 pps_long_98_reserved;
> > +	/**
> > +	 * @pps_long_102_reserved:
> > +	 * PPS 102, 103, 104, 105 - Reserved
> > +	 */
> > +	u32 pps_long_102_reserved;
> > +	/**
> > +	 * @pps_long_106_reserved:
> > +	 * PPS 106, 107, 108, 109 - reserved
> > +	 */
> > +	u32 pps_long_106_reserved;
> > +	/**
> > +	 * @pps_long_110_reserved:
> > +	 * PPS 110, 111, 112, 113 - reserved
> > +	 */
> > +	u32 pps_long_110_reserved;
> > +	/**
> > +	 * @pps_long_114_reserved:
> > +	 * PPS 114 - 117 - reserved
> > +	 */
> > +	u32 pps_long_114_reserved;
> > +	/**
> > +	 * @pps_long_118_reserved:
> > +	 * PPS 118 - 121 - reserved
> > +	 */
> > +	u32 pps_long_118_reserved;
> > +	/**
> > +	 * @pps_long_122_reserved:
> > +	 * PPS 122- 125 - reserved
> > +	 */
> > +	u32 pps_long_122_reserved;
> > +	/**
> > +	 * @pps_short_126_reserved:
> > +	 * PPS 126, 127 - reserved
> > +	 */
> > +	u16 pps_short_126_reserved;
> > +};
> > +
> > +/**
> > +* struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter Set Metadata
> > +*
> > +* This structure represents the DSC PPS infoframe required to send the Picture Parameter Set
> > +* metadata required before enabling VESA Display Stream Compression. This is based on the
> > +* DP Secondary Data Packet structure and comprises of SDP Header as defined in drm_dp_helper.h
> > +* and PPS payload.
> > +*
> > +* @pps_header:
> > +*
> > +* Header for PPS as per DP SDP header format
> > +*
> > +* @pps_payload:
> > +*
> > +* PPS payload fields as per DSC specification Table 4-1
> > +*/
> > +struct drm_dsc_pps_infoframe {
> > +	struct dp_sdp_header pps_header;
> > +	struct picture_parameter_set pps_payload;
> > +} __packed;
> > +
> > +#endif /* _DRM_DSC_H_ */
> > 
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Re: [PATCH v2 0/4] DRM helpers for Display Stream Compression PPS infoframes

[Harry Wentland]

On 2018-05-14 10:05 PM, Manasi Navare wrote:
> VESA Display Stream Compression is a specification for visually losless
> video compression over display links. The DSC standard also defines
> a picture parameter set (PPS) which encoder must communicate to decoders.
> This is done by encapsulating PPS header and payload bytes in an infoframe
> that can be sent to the display sink using secondary data packets
> as defined in DP 1.4 spec.
> 
> This patch series creates a new files drm_dsc.h and drm_dsc.c
> which define all the DSC related structures and helpers that
> can be called by drivers to form DSC PPS infoframes before
> enabling Display Stream compression on eDP/DP/MIPI
> 
> v2:
> *This is a v2 of the original patch series which adds kernel-doc
> hooks for the new dsc files in drm-kms-helpers.rst. (Daniel Vetter)
> 
> Cc: dri-devel@lists.freedesktop.org
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>

With my comments for patch 2 and 3 addressed patches 1-3 are
Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Patch 4 is
Acked-by: Harry Wentland <harry.wentland@amd.com>

Harry

> 
> Gaurav K Singh (1):
>   drm/dsc: Define VESA Display Stream Compression Capabilities
> 
> Manasi Navare (3):
>   drm/dp: Define payload size for DP SDP PPS packet
>   drm/dsc: Define Display Stream Compression PPS infoframe
>   drm/dsc: Add helpers for DSC picture parameter set infoframes
> 
>  Documentation/gpu/drm-kms-helpers.rst |  12 +
>  drivers/gpu/drm/Makefile              |   2 +-
>  drivers/gpu/drm/drm_dsc.c             | 227 ++++++++++++++
>  include/drm/drm_dp_helper.h           |   1 +
>  include/drm/drm_dsc.h                 | 564 ++++++++++++++++++++++++++++++++++
>  5 files changed, 805 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/drm_dsc.c
>  create mode 100644 include/drm/drm_dsc.h
> 
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[PATCH v3 1/4] drm/dp: Define payload size for DP SDP PPS packet

[Manasi Navare]

DP 1.4 spec defines DP secondary data packet for DSC
picture parameter set. This patch defines its payload size
according to the DP 1.4 specification.

Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
 include/drm/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c015649..d13e512 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -992,6 +992,7 @@ struct dp_sdp_header {
 
 #define EDP_SDP_HEADER_REVISION_MASK		0x1F
 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES	0x1F
+#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
 
 struct edp_vsc_psr {
 	struct dp_sdp_header sdp_header;
-- 
2.7.4

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[PATCH v3 2/4] drm/dsc: Define Display Stream Compression PPS infoframe

[Manasi Navare]

This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.

v3:
* Add a comment for bits_per_component as per DSC spec (Harry Wentland)
v2:
* Fix the comments for kernel-doc

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
 include/drm/drm_dsc.h | 442 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 442 insertions(+)
 create mode 100644 include/drm/drm_dsc.h

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
new file mode 100644
index 0000000..73bd0f1
--- /dev/null
+++ b/include/drm/drm_dsc.h
@@ -0,0 +1,442 @@
+/*
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#ifndef DRM_DSC_H_
+#define DRM_DSC_H_
+
+#include <drm/drm_dp_helper.h>
+
+/* VESA Display Stream Compression DSC 1.2 constants */
+#define DSC_NUM_BUF_RANGES	15
+
+/**
+ * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
+ *
+ * The VESA DSC standard defines picture parameter set (PPS) which display
+ * stream compression encoders must communicate to decoders.
+ * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in
+ * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2.
+ * The PPS fields that span over more than a byte should be stored in Big Endian
+ * format.
+ */
+struct picture_parameter_set {
+	/**
+	 * @dsc_version_minor:
+	 * PPS0[3:0] - Contains Minor version of DSC
+	 */
+	u8 dsc_version_minor:4;
+	/**
+	 * @dsc_version_major:
+	 * PPS0[7:4] - Contains major version of DSC
+	 */
+	u8 dsc_version_major:4;
+	/**
+	 * @pps_identifier:
+	 * PPS1[7:0] - Application specific identifier that can be
+	 * used to differentiate between different PPS tables.
+	 */
+	u8 pps_identifier;
+	/**
+	 * @pps2_reserved:
+	 * PPS2[7:0]- RESERVED Byte
+	 */
+	u8 pps2_reserved;
+	/**
+	 * @linebuf_depth:
+	 * PPS3[3:0] - Contains linebuffer bit depth used to generate
+	 * the bitstream. (0x0 - 16 bits for DSc 1.2, 0x8 - 8 bits,
+	 * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits,
+	 * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2.
+	 */
+	u8 linebuf_depth:4;
+	/**
+	 * @bits_per_component:
+	 * PPS3[7:4] - Bits per component for the original pixels
+	 * of the encoded picture.
+	 * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2)
+	 * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also
+	 * allowed only when dsc_minor_version = 0x2)
+	 */
+	u8 bits_per_component:4;
+	/**
+	 * @bpp_high:
+	 * PPS4[1:0] - These are the most significant 2 bits of
+	 * compressed BPP bits_per_pixel[9:0] syntax element.
+	 */
+	u8 bpp_high:2;
+	/**
+	 * @vbr_enable:
+	 * PPS4[2] - 0 = VBR disabled, 1 = VBR enabled
+	 */
+	u8 vbr_enable:1;
+	/**
+	 * @simple_422:
+	 * PPS4[3] - Indicates if decoder drops samples to
+	 * reconstruct the 4:2:2 picture.
+	 */
+	u8 simple_422:1;
+	/**
+	 * @convert_rgb:
+	 * PPS4[4] - Indicates if DSC color space conversion is active
+	 */
+	u8 convert_rgb:1;
+	/**
+	 * @block_pred_enable:
+	 * PPS4[5] - Indicates if BP is used to code any groups in picture
+	 */
+	u8 block_pred_enable:1;
+	/**
+	 * @pps4_reserved:
+	 * PPS4[7:6] - Reseved bits
+	 */
+	u8 pps4_reserved:2;
+	/**
+	 * @bpp_low:
+	 * PPS5[7:0] - This indicates the lower significant 8 bits of
+	 * the compressed BPP bits_per_pixel[9:0] element.
+	 */
+	u8 bpp_low;
+	/**
+	 * @pic_height:
+	 * PPS6[7:0], PPS7[7:0] -  Specifies the number of pixel rows within
+	 * the raster.
+	 */
+	u16 pic_height;
+	/**
+	 * @pic_width:
+	 * PPS8[7:0], PPS9[7:0] - Number of pixel columns within the raster.
+	 */
+	u16 pic_width;
+	/**
+	 * @slice_height:
+	 * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels.
+	 */
+	u16 slice_height;
+	/**
+	 * @slice_width:
+	 * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels.
+	 */
+	u16 slice_width;
+	/**
+	 * @chunk_size:
+	 * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks
+	 * that are used for slice multiplexing.
+	 */
+	u16 chunk_size;
+	/**
+	 * @initial_xmit_delay_high:
+	 * PPS16[1:0] - Most Significant two bits of initial transmission delay.
+	 * It specifies the number of pixel times that the encoder waits before
+	 * transmitting data from its rate buffer.
+	 */
+	u8 initial_xmit_delay_high:2;
+	/**
+	 * @pps16_reserved:
+	 * PPS16[7:2] - Reserved
+	 */
+	u8 pps16_reserved:6;
+	/**
+	 * @initial_xmit_delay_low:
+	 * PPS17[7:0] - Least significant 8 bits of initial transmission delay.
+	 */
+	u8 initial_xmit_delay_low;
+	/**
+	 * @initial_dec_delay:
+	 *
+	 * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number
+	 * of pixel times that the decoder accumulates data in its rate buffer
+	 * before starting to decode and output pixels.
+	 */
+	u16 initial_dec_delay;
+	/**
+	 * @pps20_reserved:
+	 *
+	 * PPS20[7:0] - Reserved
+	 */
+	u8 pps20_reserved;
+	/**
+	 * @initial_scale_value:
+	 * PPS21[5:0] - Initial rcXformScale factor used at beginning
+	 * of a slice.
+	 */
+	u8 initial_scale_value:6;
+	/**
+	 * @pps21_reserved:
+	 * PPS21[7:6] - Reserved
+	 */
+	u8 pps21_reserved:2;
+	/**
+	 * @scale_increment_interval:
+	 * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing
+	 * the rcXformScale factor at end of a slice.
+	 */
+	u16 scale_increment_interval;
+	/**
+	 * @scale_decrement_interval_high:
+	 * PPS24[3:0] - Higher 4 bits indicating number of group times between
+	 * decrementing the rcXformScale factor at beginning of a slice.
+	 */
+	u8 scale_decrement_interval_high:4;
+	/**
+	 * @pps24_reserved:
+	 * PPS24[7:4] - Reserved
+	 */
+	u8 pps24_reserved:4;
+	/**
+	 * @scale_decrement_interval_low:
+	 * PPS25[7:0] - Lower 8 bits of scale decrement interval
+	 */
+	u8 scale_decrement_interval_low;
+	/**
+	 * @pps26_reserved:
+	 * PPS26[7:0]
+	 */
+	u8 pps26_reserved;
+	/**
+	 * @first_line_bpg_offset:
+	 * PPS27[4:0] - Number of additional bits that are allocated
+	 * for each group on first line of a slice.
+	 */
+	u8 first_line_bpg_offset:5;
+	/**
+	 * @pps27_reserved:
+	 * PPS27[7:5]
+	 */
+	u8 pps27_reserved:3;
+	/**
+	 * @nfl_bpg_offset:
+	 * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits
+	 * deallocated for each group for groups after the first line of slice.
+	 */
+	u16 nfl_bpg_offset;
+	/**
+	 * @slice_bpg_offset:
+	 * PPS30, PPS31[7:0] - Number of bits that are deallocated for each
+	 * group to enforce the slice constraint.
+	 */
+	u16 slice_bpg_offset;
+	/**
+	 * @initial_offset:
+	 * PPS32,33[7:0] - Initial value for rcXformOffset
+	 */
+	u16 initial_offset;
+	/**
+	 * @final_offset:
+	 * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset
+	 */
+	u16 final_offset;
+	/**
+	 * @flatness_min_qp:
+	 * PPS36[4:0] - Minimum QP at which flatness is signaled and
+	 * flatness QP adjustment is made.
+	 */
+	u8 flatness_min_qp:5;
+	/**
+	 * @pps36_reserved:
+	 * PPS36[7:5] - Reserved
+	 */
+	u8 pps36_reserved:3;
+	/**
+	 * @flatness_max_qp:
+	 * PPS37[4:0] - Max QP at which flatness is signalled and
+	 * the flatness adjustment is made.
+	 */
+	u8 flatness_max_qp:5;
+	/**
+	 * @pps37_reserved:
+	 * PPS37[7:5]
+	 */
+	u8 pps37_reserved:3;
+	/**
+	 * @rc_model_size:
+	 * PPS38,39[7:0] - Number of bits within RC Model.
+	 */
+	u16 rc_model_size;
+	/**
+	 * @rc_edge_factor:
+	 * PPS40[3:0] - Ratio of current activity vs, previous
+	 * activity to determine presence of edge.
+	 */
+	u8 rc_edge_factor:4;
+	/**
+	 * @pps40_reserved:
+	 * PPS40[7:4]
+	 */
+	u8 pps40_reserved:4;
+	/**
+	 * @rc_quant_incr_limit0:
+	 * PPS41[4:0] - QP threshold used in short term RC
+	 */
+	u8 rc_quant_incr_limit0:5;
+	/**
+	 * @pps41_reserved:
+	 * PPS41[7:5]
+	 */
+	u8 pps41_reserved:3;
+	/**
+	 * @rc_quant_incr_limit1:
+	 * PPS42[4:0] - QP threshold used in short term RC
+	 */
+	u8 rc_quant_incr_limit1:5;
+	/**
+	 * @pps42_reserved:
+	 * PPS42[7:5]
+	 */
+	u8 pps42_reserved:3;
+	/**
+	 * @rc_tgt_offset_lo:
+	 * Lower end of the variability range around the target
+	 * bits per group that is allowed by short term RC.
+	 */
+	u8 rc_tgt_offset_lo:4;
+	/**
+	 * @rc_tgt_offset_hi:
+	 * Upper end of the variability range around the target
+	 * bits per group that i allowed by short term rc.
+	 */
+	u8 rc_tgt_offset_hi:4;
+	/**
+	 * @rc_buf_thresh:
+	 * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for
+	 * the 15 ranges defined by 14 thresholds.
+	 */
+	u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+	/**
+	 * @rc_range_parameters:
+	 * PPS58[7:0] - PPS87[7:0]
+	 * Parameters that correspond to each of the 15 ranges.
+	 */
+	u16 rc_range_parameters[DSC_NUM_BUF_RANGES];
+	/**
+	 * @native_422:
+	 * PPS88[0] - 0 = Native 4:2:2 not used
+	 * 1 = Native 4:2:2 used
+	 */
+	u8 native_422:1;
+	/**
+	 * @native_420:
+	 * PPS88[1] - 0 = Native 4:2:0 not used
+	 * 1 = Native 4:2:0 not used.
+	 */
+	u8 native_420:1;
+	/**
+	 * @pps88_reserved:
+	 * PPS[7:2] - Reserved 6 bits
+	 */
+	u8 pps88_reserved:6;
+	/**
+	 * @second_line_bpg_offset:
+	 * PPS89[4:0] - Additional bits/group budget for the
+	 * second line of a slice in Native 4:2:0 mode.
+	 * Set to 0 if DSC minor version is 1 or native420 is 0.
+	 */
+	u8 second_line_bpg_offset:5;
+	/**
+	 * @pps89_reserved:
+	 * PPS89[7:5] - Reserved
+	 */
+	u8 pps89_reserved:3;
+	/**
+	 * @nsl_bpg_offset:
+	 * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated
+	 * for each group that is not in the second line of a slice.
+	 */
+	u16 nsl_bpg_offset;
+	/**
+	 * @second_line_offset_adj:
+	 * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second
+	 * line in Native 4:2:0 mode.
+	 */
+	u16 second_line_offset_adj;
+	/**
+	 * @pps_long_94_reserved:
+	 * PPS 94, 95, 96, 97 - Reserved
+	 */
+	u32 pps_long_94_reserved;
+	/**
+	 * @pps_long_98_reserved:
+	 * PPS 98, 99, 100, 101 - Reserved
+	 */
+	u32 pps_long_98_reserved;
+	/**
+	 * @pps_long_102_reserved:
+	 * PPS 102, 103, 104, 105 - Reserved
+	 */
+	u32 pps_long_102_reserved;
+	/**
+	 * @pps_long_106_reserved:
+	 * PPS 106, 107, 108, 109 - reserved
+	 */
+	u32 pps_long_106_reserved;
+	/**
+	 * @pps_long_110_reserved:
+	 * PPS 110, 111, 112, 113 - reserved
+	 */
+	u32 pps_long_110_reserved;
+	/**
+	 * @pps_long_114_reserved:
+	 * PPS 114 - 117 - reserved
+	 */
+	u32 pps_long_114_reserved;
+	/**
+	 * @pps_long_118_reserved:
+	 * PPS 118 - 121 - reserved
+	 */
+	u32 pps_long_118_reserved;
+	/**
+	 * @pps_long_122_reserved:
+	 * PPS 122- 125 - reserved
+	 */
+	u32 pps_long_122_reserved;
+	/**
+	 * @pps_short_126_reserved:
+	 * PPS 126, 127 - reserved
+	 */
+	u16 pps_short_126_reserved;
+};
+
+/**
+ * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter
+ * Set Metadata
+ *
+ * This structure represents the DSC PPS infoframe required to send the Picture
+ * Parameter Set metadata required before enabling VESA Display Stream
+ * Compression. This is based on the DP Secondary Data Packet structure and
+ * comprises of SDP Header as defined in drm_dp_helper.h and PPS payload.
+ *
+ * @pps_header:
+ *
+ * Header for PPS as per DP SDP header format
+ *
+ * @pps_payload:
+ *
+ * PPS payload fields as per DSC specification Table 4-1
+ */
+struct drm_dsc_pps_infoframe {
+	struct dp_sdp_header pps_header;
+	struct picture_parameter_set pps_payload;
+} __packed;
+
+#endif /* _DRM_DSC_H_ */
-- 
2.7.4

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[PATCH v3 3/4] drm/dsc: Define VESA Display Stream Compression Capabilities

[Manasi Navare]

From: Gaurav K Singh <gaurav.k.singh@intel.com>

This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder

v3:
Remove the duplicate define (Harry) (From Manasi)

v2: Define this struct in DRM (From Manasi)
* Changed the data types to u8/u16 instead of unsigned longs (Manasi)
* Remove driver specific fields (Manasi)
* Move this struct definition to DRM (Manasi)
* Define DSC 1.2 parameters (Manasi)
* Use DSC_NUM_BUF_RANGES (Manasi)
* Call it drm_dsc_config (Manasi)

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
 include/drm/drm_dsc.h | 108 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 73bd0f1..7f6209e 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -31,6 +31,114 @@
 /* VESA Display Stream Compression DSC 1.2 constants */
 #define DSC_NUM_BUF_RANGES	15
 
+/* Configuration for a single Rate Control model range */
+struct dsc_rc_range_parameters {
+	/* Min Quantization Parameters allowed for this range */
+	u8 range_min_qp;
+	/* Max Quantization Parameters allowed for this range */
+	u8 range_max_qp;
+	/* Bits/group offset to apply to target for this group */
+	u8 range_bpg_offset;
+};
+
+struct drm_dsc_config {
+	/* Bits / component for previous reconstructed line buffer */
+	u8 line_buf_depth;
+	/* Bits per component to code (must be 8, 10, or 12) */
+	u8 bits_per_component;
+	/*
+	 * Flag indicating to do RGB - YCoCg conversion
+	 * and back (should be 1 for RGB input)
+	 */
+	bool convert_rgb;
+	u8 slice_count;
+	/* Slice Width */
+	u16 slice_width;
+	/* Slice Height */
+	u16 slice_height;
+	/*
+	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+	 * outside of DSC encode/decode algorithm)
+	 */
+	bool enable422;
+	/* Picture Width */
+	u16 pic_width;
+	/* Picture Height */
+	u16 pic_height;
+	/* Offset to bits/group used by RC to determine QP adjustment */
+	u8 rc_tgt_offset_high;
+	/* Offset to bits/group used by RC to determine QP adjustment */
+	u8 rc_tgt_offset_low;
+	/* Bits/pixel target << 4 (ie., 4 fractional bits) */
+	u16 bits_per_pixel;
+	/*
+	 * Factor to determine if an edge is present based
+	 * on the bits produced
+	 */
+	u8 rc_edge_factor;
+	/* Slow down incrementing once the range reaches this value */
+	u8 rc_quant_incr_limit1;
+	/* Slow down incrementing once the range reaches this value */
+	u8 rc_quant_incr_limit0;
+	/* Number of pixels to delay the initial transmission */
+	u16 initial_xmit_delay;
+	/* Number of pixels to delay the VLD on the decoder,not including SSM */
+	u16  initial_dec_delay;
+	/* Block prediction enable */
+	bool block_pred_enable;
+	/* Bits/group offset to use for first line of the slice */
+	u8 first_line_bpg_offset;
+	/* Value to use for RC model offset at slice start */
+	u16 initial_offset;
+	/* Thresholds defining each of the buffer ranges */
+	u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
+	/* Parameters for each of the RC ranges */
+	struct dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+	/* Total size of RC model */
+	u16 rc_model_size;
+	/* Minimum QP where flatness information is sent */
+	u8 flatness_min_qp;
+	/* Maximum QP where flatness information is sent */
+	u8 flatness_max_qp;
+	/* Initial value for scale factor */
+	u8 initial_scale_value;
+	/* Decrement scale factor every scale_decrement_interval groups */
+	u16 scale_decrement_interval;
+	/* Increment scale factor every scale_increment_interval groups */
+	u16 scale_increment_interval;
+	/* Non-first line BPG offset to use */
+	u16 nfl_bpg_offset;
+	/* BPG offset used to enforce slice bit */
+	u16 slice_bpg_offset;
+	/* Final RC linear transformation offset value */
+	u16 final_offset;
+	/* Enable on-off VBR (ie., disable stuffing bits) */
+	bool vbr_enable;
+	/* Mux word size (in bits) for SSM mode */
+	u8 mux_word_size;
+	/*
+	 * The (max) size in bytes of the "chunks" that are
+	 * used in slice multiplexing
+	 */
+	u16 slice_chunk_size;
+	/* Rate Control buffer siz in bits */
+	u16 rc_bits;
+	/* DSC Minor Version */
+	u8 dsc_version_minor;
+	/* DSC Major version */
+	u8 dsc_version_major;
+	/* Native 4:2:2 support */
+	bool native_422;
+	/* Native 4:2:0 support */
+	bool native_420;
+	/* Additional bits/grp for seconnd line of slice for native 4:2:0 */
+	u8 second_line_bpg_offset;
+	/* Num of bits deallocated for each grp that is not in second line of slice */
+	u16 nsl_bpg_offset;
+	/* Offset adj fr second line in Native 4:2:0 mode */
+	u16 second_line_offset_adj;
+};
+
 /**
  * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set
  *
-- 
2.7.4

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[PATCH v3 4/4] drm/dsc: Add helpers for DSC picture parameter set infoframes

[Manasi Navare]

According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload according to the DSC 1.2 specification.

v3:
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst
(Daniel Vetter)

v2:
* Add EXPORT_SYMBOL for the drm functions (Manasi)

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 Documentation/gpu/drm-kms-helpers.rst |  12 ++
 drivers/gpu/drm/Makefile              |   2 +-
 drivers/gpu/drm/drm_dsc.c             | 231 ++++++++++++++++++++++++++++++++++
 include/drm/drm_dsc.h                 |  16 +++
 4 files changed, 260 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/drm_dsc.c

diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst
index e37557b..13837f7 100644
--- a/Documentation/gpu/drm-kms-helpers.rst
+++ b/Documentation/gpu/drm-kms-helpers.rst
@@ -205,6 +205,18 @@ MIPI DSI Helper Functions Reference
 .. kernel-doc:: drivers/gpu/drm/drm_mipi_dsi.c
    :export:
 
+Display Stream Compression Helper Functions Reference
+=====================================================
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :doc: dsc helpers
+
+.. kernel-doc:: include/drm/drm_dsc.h
+   :internal:
+
+.. kernel-doc:: drivers/gpu/drm/drm_dsc.c
+   :export:
+
 Output Probing Helper Functions Reference
 =========================================
 
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 8873d47..df70373 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -31,7 +31,7 @@ drm-$(CONFIG_AGP) += drm_agpsupport.o
 drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
 drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
 
-drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
+drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_dsc.o drm_probe_helper.o \
 		drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
 		drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
 		drm_simple_kms_helper.o drm_modeset_helper.o \
diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c
new file mode 100644
index 0000000..30e567f
--- /dev/null
+++ b/drivers/gpu/drm/drm_dsc.c
@@ -0,0 +1,231 @@
+/*
+ *Copyright © 2018 Intel Corp
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission.  The copyright holders make no representations
+ * about the suitability of this software for any purpose.  It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ *
+ * Author:
+ * Manasi Navare <manasi.d.navare@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_dsc.h>
+
+/**
+ * DOC: dsc helpers
+ *
+ * These functions contain some common logic and helpers to deal with VESA
+ * Display Stream Compression standard required for DSC on Display Port/eDP or
+ * MIPI display interfaces.
+ */
+
+/**
+ * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
+ * for DisplayPort as per the DP 1.4 spec.
+ * @pps_sdp: Secondary data packet for DSC Picture Parameter Set
+ */
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp)
+{
+	memset(&pps_sdp->pps_header, 0, sizeof(pps_sdp->pps_header));
+
+	pps_sdp->pps_header.HB1 = DP_SDP_PPS;
+	pps_sdp->pps_header.HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1;
+}
+EXPORT_SYMBOL(drm_dsc_dp_pps_header_init);
+
+/**
+ * drm_dsc_pps_infoframe_pack() - Populates the DSC PPS infoframe
+ * using the DSC configuration parameters in the order expected
+ * by the DSC Display Sink device. For the DSC, the sink device
+ * expects the PPS payload in the big endian format for the fields
+ * that span more than 1 byte.
+ *
+ * @pps_sdp:
+ * Secondary data packet for DSC Picture Parameter Set
+ * @dsc_cfg:
+ * DSC Configuration data filled by driver
+ * @is_big_endian:
+ * Flag to indicate if HW is Big Endian
+ */
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+				struct drm_dsc_config *dsc_cfg,
+				bool is_big_endian)
+{
+	u8 i = 0;
+
+	memset(&pps_sdp->pps_payload, 0, sizeof(pps_sdp->pps_payload));
+
+	/* PPS 0 */
+	pps_sdp->pps_payload.dsc_version_minor = dsc_cfg->dsc_version_minor;
+	pps_sdp->pps_payload.dsc_version_major = dsc_cfg->dsc_version_major;
+
+	/* PPS 1, 2 is 0 */
+
+	/* PPS 3 */
+	pps_sdp->pps_payload.linebuf_depth = dsc_cfg->line_buf_depth;
+	pps_sdp->pps_payload.bits_per_component = dsc_cfg->bits_per_component;
+
+	/* PPS 4, 5 */
+	pps_sdp->pps_payload.block_pred_enable = (u8)dsc_cfg->block_pred_enable;
+	pps_sdp->pps_payload.convert_rgb = (u8)dsc_cfg->convert_rgb;
+	pps_sdp->pps_payload.simple_422 = (u8)dsc_cfg->enable422;
+	pps_sdp->pps_payload.vbr_enable = (u8)dsc_cfg->vbr_enable;
+	pps_sdp->pps_payload.bpp_high = (u8)((dsc_cfg->bits_per_pixel &
+					      DSC_PPS_BPP_HIGH_MASK) >>
+					     DSC_PPS_MSB_SHIFT);
+	pps_sdp->pps_payload.bpp_low = (u8)(dsc_cfg->bits_per_pixel &
+					    DSC_PPS_LSB_MASK);
+
+	/*
+	 * The DSC panel expects the PPS packet to have big endian format
+	 * for data spanning 2 bytes. So if the HW does not store the data
+	 * in big endian format, it sets big_endian flag to false in which case
+	 * we need to convert from little endian to big endian.
+	 */
+
+	/* PPS 6, 7 */
+	pps_sdp->pps_payload.pic_height = DSC_PPS_SWAP_BYTES(dsc_cfg->pic_height,
+							     is_big_endian);
+
+	/* PPS 8, 9 */
+	pps_sdp->pps_payload.pic_width = DSC_PPS_SWAP_BYTES(dsc_cfg->pic_height,
+							    is_big_endian);
+
+	/* PPS 10, 11 */
+	pps_sdp->pps_payload.slice_height = DSC_PPS_SWAP_BYTES(dsc_cfg->slice_height,
+							       is_big_endian);
+
+	/* PPS 12, 13 */
+	pps_sdp->pps_payload.slice_width = DSC_PPS_SWAP_BYTES(dsc_cfg->slice_width,
+							      is_big_endian);
+
+	/* PPS 14, 15 */
+	pps_sdp->pps_payload.chunk_size = DSC_PPS_SWAP_BYTES(dsc_cfg->slice_chunk_size,
+							     is_big_endian);
+
+	/* PPS 16, 17 */
+	pps_sdp->pps_payload.initial_xmit_delay_high = (u8)((dsc_cfg->initial_xmit_delay &
+							     DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
+							    DSC_PPS_MSB_SHIFT);
+	pps_sdp->pps_payload.initial_xmit_delay_low = (u8)(dsc_cfg->initial_xmit_delay &
+							   DSC_PPS_LSB_MASK);
+
+	/* PPS 18, 19 */
+	pps_sdp->pps_payload.initial_dec_delay = DSC_PPS_SWAP_BYTES(dsc_cfg->initial_dec_delay,
+								    is_big_endian);
+
+	/* PPS 20 is 0 */
+
+	/* PPS 21 */
+	pps_sdp->pps_payload.initial_scale_value = (u8)dsc_cfg->initial_scale_value;
+
+	/* PPS 22, 23 */
+	pps_sdp->pps_payload.scale_increment_interval = DSC_PPS_SWAP_BYTES(dsc_cfg->scale_increment_interval,
+									   is_big_endian);
+
+	/* PPS 24, 25 */
+	pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval &
+								   DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
+								  DSC_PPS_MSB_SHIFT);
+	pps_sdp->pps_payload.scale_decrement_interval_low = (u8)(dsc_cfg->scale_decrement_interval &
+								 DSC_PPS_LSB_MASK);
+
+	/* PPS 27 */
+	pps_sdp->pps_payload.first_line_bpg_offset = (u8)dsc_cfg->first_line_bpg_offset;
+
+	/* PPS 28, 29 */
+	pps_sdp->pps_payload.nfl_bpg_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->nfl_bpg_offset,
+								 is_big_endian);
+
+	/* PPS 30, 31 */
+	pps_sdp->pps_payload.slice_bpg_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->slice_bpg_offset,
+								   is_big_endian);
+
+	/* PPS 32, 33 */
+	pps_sdp->pps_payload.initial_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->initial_offset,
+								 is_big_endian);
+
+	/* PPS 34, 35 */
+	pps_sdp->pps_payload.final_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->final_offset,
+							       is_big_endian);
+
+	/* PPS 36 */
+	pps_sdp->pps_payload.flatness_min_qp = (u8)dsc_cfg->flatness_min_qp;
+
+	/* PPS 37 */
+	pps_sdp->pps_payload.flatness_max_qp = (u8)dsc_cfg->flatness_max_qp;
+
+	/* PPS 38, 39 */
+	pps_sdp->pps_payload.rc_model_size = DSC_PPS_SWAP_BYTES(dsc_cfg->rc_model_size,
+								is_big_endian);
+
+	/* PPS 40 */
+	pps_sdp->pps_payload.rc_edge_factor = (u8)dsc_cfg->rc_edge_factor;
+
+	/* PPS 41 */
+	pps_sdp->pps_payload.rc_quant_incr_limit0 = (u8)dsc_cfg->rc_quant_incr_limit0;
+
+	/* PPS 42 */
+	pps_sdp->pps_payload.rc_quant_incr_limit1 = (u8)dsc_cfg->rc_quant_incr_limit1;
+
+	/* PPS 43 */
+	pps_sdp->pps_payload.rc_tgt_offset_lo = (u8)dsc_cfg->rc_tgt_offset_low;
+	pps_sdp->pps_payload.rc_tgt_offset_hi = (u8)dsc_cfg->rc_tgt_offset_high;
+
+	/* PPS 44 - 57 */
+	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
+		pps_sdp->pps_payload.rc_buf_thresh[i] = dsc_cfg->rc_buf_thresh[i];
+
+	/* PPS 58 - 87 */
+	/*
+	 * For DSC sink programming the RC Range parameter fields
+	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
+	 */
+	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+		pps_sdp->pps_payload.rc_range_parameters[i] =
+			(u16)((dsc_cfg->rc_range_params[i].range_min_qp <<
+			       DSC_PPS_RC_RANGE_MINQP_SHIFT) |
+			      (dsc_cfg->rc_range_params[i].range_max_qp <<
+			       DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
+			      (dsc_cfg->rc_range_params[i].range_bpg_offset));
+		pps_sdp->pps_payload.rc_range_parameters[i] = DSC_PPS_SWAP_BYTES(pps_sdp->pps_payload.rc_range_parameters[i],
+										 is_big_endian);
+	}
+
+	/* PPS 88 */
+	pps_sdp->pps_payload.native_422 = (u8)dsc_cfg->native_422;
+	pps_sdp->pps_payload.native_420 = (u8)dsc_cfg->native_420;
+
+	/* PPS 89 */
+	pps_sdp->pps_payload.second_line_bpg_offset = (u8)dsc_cfg->second_line_bpg_offset;
+
+	/* PPS 90, 91 */
+	pps_sdp->pps_payload.nsl_bpg_offset = DSC_PPS_SWAP_BYTES(dsc_cfg->nsl_bpg_offset,
+								 is_big_endian);
+
+	/* PPS 92, 93 */
+	pps_sdp->pps_payload.second_line_offset_adj = DSC_PPS_SWAP_BYTES(dsc_cfg->second_line_offset_adj,
+									 is_big_endian);
+
+	/* PPS 94 - 127 are O */
+}
+EXPORT_SYMBOL(drm_dsc_pps_infoframe_pack);
diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 7f6209e..039d598 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -26,11 +26,22 @@
 #ifndef DRM_DSC_H_
 #define DRM_DSC_H_
 
+#include <linux/byteorder/generic.h>
 #include <drm/drm_dp_helper.h>
 
 /* VESA Display Stream Compression DSC 1.2 constants */
 #define DSC_NUM_BUF_RANGES	15
 
+/* DSC PPS constants and macros */
+#define DSC_PPS_MSB_SHIFT			8
+#define DSC_PPS_LSB_MASK			(0xFF << 0)
+#define DSC_PPS_BPP_HIGH_MASK			(0x3 << 8)
+#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK	(0x3 << 8)
+#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK		(0xF << 8)
+#define DSC_PPS_RC_RANGE_MINQP_SHIFT		11
+#define DSC_PPS_RC_RANGE_MAXQP_SHIFT		6
+#define DSC_PPS_SWAP_BYTES(val, swap)		((swap) ? val : cpu_to_be16(val))
+
 /* Configuration for a single Rate Control model range */
 struct dsc_rc_range_parameters {
 	/* Min Quantization Parameters allowed for this range */
@@ -547,4 +558,9 @@ struct drm_dsc_pps_infoframe {
 	struct picture_parameter_set pps_payload;
 } __packed;
 
+void drm_dsc_dp_pps_header_init(struct drm_dsc_pps_infoframe *pps_sdp);
+void drm_dsc_pps_infoframe_pack(struct drm_dsc_pps_infoframe *pps_sdp,
+				struct drm_dsc_config *dsc_cfg,
+				bool big_endian);
+
 #endif /* _DRM_DSC_H_ */
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for DRM helpers for Display Stream Compression PPS infoframes (rev6)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev6)
URL   : https://patchwork.freedesktop.org/series/42968/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f915268ebce9 drm/dp: Define payload size for DP SDP PPS packet
dea28cb7e27a drm/dsc: Define Display Stream Compression PPS infoframe
-:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#25: 
new file mode 100644

-:30: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#30: FILE: include/drm/drm_dsc.h:1:
+/*

total: 0 errors, 2 warnings, 0 checks, 442 lines checked
c3afd0709328 drm/dsc: Define VESA Display Stream Compression Capabilities
28641b50ce4d drm/dsc: Add helpers for DSC picture parameter set infoframes
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#14: 
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst

-:64: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#64: 
new file mode 100644

-:69: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#69: FILE: drivers/gpu/drm/drm_dsc.c:1:
+/*

-:210: WARNING:LONG_LINE: line over 100 characters
#210: FILE: drivers/gpu/drm/drm_dsc.c:142:
+	pps_sdp->pps_payload.scale_increment_interval = DSC_PPS_SWAP_BYTES(dsc_cfg->scale_increment_interval,

-:214: WARNING:LONG_LINE: line over 100 characters
#214: FILE: drivers/gpu/drm/drm_dsc.c:146:
+	pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval &

-:215: WARNING:LONG_LINE: line over 100 characters
#215: FILE: drivers/gpu/drm/drm_dsc.c:147:
+								   DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>

-:278: WARNING:LONG_LINE: line over 100 characters
#278: FILE: drivers/gpu/drm/drm_dsc.c:210:
+		pps_sdp->pps_payload.rc_range_parameters[i] = DSC_PPS_SWAP_BYTES(pps_sdp->pps_payload.rc_range_parameters[i],

-:294: WARNING:LONG_LINE: line over 100 characters
#294: FILE: drivers/gpu/drm/drm_dsc.c:226:
+	pps_sdp->pps_payload.second_line_offset_adj = DSC_PPS_SWAP_BYTES(dsc_cfg->second_line_offset_adj,

-:322: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'val' - possible side-effects?
#322: FILE: include/drm/drm_dsc.h:43:
+#define DSC_PPS_SWAP_BYTES(val, swap)		((swap) ? val : cpu_to_be16(val))

total: 0 errors, 8 warnings, 1 checks, 288 lines checked

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✗ Fi.CI.SPARSE: warning for DRM helpers for Display Stream Compression PPS infoframes (rev6)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev6)
URL   : https://patchwork.freedesktop.org/series/42968/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/dp: Define payload size for DP SDP PPS packet
Okay!

Commit: drm/dsc: Define Display Stream Compression PPS infoframe
Okay!

Commit: drm/dsc: Define VESA Display Stream Compression Capabilities
Okay!

Commit: drm/dsc: Add helpers for DSC picture parameter set infoframes
-
+drivers/gpu/drm/drm_dsc.c:106:43: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:110:42: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:114:45: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:118:44: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:122:43: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:133:50: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:142:57: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:156:47: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:160:49: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:164:47: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:168:45: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:178:46: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:210:63: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:222:47: warning: restricted __be16 degrades to integer
+drivers/gpu/drm/drm_dsc.c:226:55: warning: restricted __be16 degrades to integer

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✓ Fi.CI.BAT: success for DRM helpers for Display Stream Compression PPS infoframes (rev6)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev6)
URL   : https://patchwork.freedesktop.org/series/42968/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4201 -> Patchwork_9040 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42968/revisions/6/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9040 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       DMESG-WARN (fdo#105128) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-cnl-y3:          FAIL (fdo#103167, fdo#104724) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    
    ==== Warnings ====

    igt@gem_ringfill@basic-default-hang:
      fi-pnv-d510:        DMESG-WARN (fdo#101600) -> INCOMPLETE (fdo#105000)

    
  fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105000 https://bugs.freedesktop.org/show_bug.cgi?id=105000
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128


== Participating hosts (43 -> 39) ==

  Missing    (4): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4201 -> Patchwork_9040

  CI_DRM_4201: 5e68b6c9b2d2781edec45e84460517704f557126 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9040: 28641b50ce4db9b033993f54fc0fbc6b96866619 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit


== Linux commits ==

28641b50ce4d drm/dsc: Add helpers for DSC picture parameter set infoframes
c3afd0709328 drm/dsc: Define VESA Display Stream Compression Capabilities
dea28cb7e27a drm/dsc: Define Display Stream Compression PPS infoframe
f915268ebce9 drm/dp: Define payload size for DP SDP PPS packet

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9040/issues.html
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✓ Fi.CI.IGT: success for DRM helpers for Display Stream Compression PPS infoframes (rev6)

[Patchwork]

== Series Details ==

Series: DRM helpers for Display Stream Compression PPS infoframes (rev6)
URL   : https://patchwork.freedesktop.org/series/42968/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4201_full -> Patchwork_9040_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9040_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9040_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/42968/revisions/6/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9040_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-vebox:
      shard-kbl:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_9040_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#103060)

    igt@kms_flip_tiling@flip-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724, fdo#103822) +1

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
      shard-glk:          PASS -> FAIL (fdo#104724, fdo#103167) +1

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          FAIL (fdo#105454, fdo#106509) -> PASS

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (9 -> 9) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4201 -> Patchwork_9040

  CI_DRM_4201: 5e68b6c9b2d2781edec45e84460517704f557126 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4487: eccae1360d6d01e73c6af2bd97122cef708207ef @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9040: 28641b50ce4db9b033993f54fc0fbc6b96866619 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4487: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9040/shards.html
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