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From: Paul Mackerras <paulus@ozlabs.org>
To: wei.guo.simon@gmail.com
Cc: linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org,
	kvm@vger.kernel.org
Subject: Re: [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs
Date: Tue, 15 May 2018 16:07:03 +1000	[thread overview]
Message-ID: <20180515060703.GC28451@fergus.ozlabs.ibm.com> (raw)
In-Reply-To: <1519753958-11756-7-git-send-email-wei.guo.simon@gmail.com>

On Wed, Feb 28, 2018 at 01:52:25AM +0800, wei.guo.simon@gmail.com wrote:
> From: Simon Guo <wei.guo.simon@gmail.com>
> 
> The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged
> instructions and can be executed at PR KVM guest without trapping
> into host in problem state. We only emulate mtspr/mfspr
> texasr/tfiar/tfhar at guest PR=0 state.
> 
> When we are emulating mtspr tm sprs at guest PR=0 state, the emulation
> result need to be visible to guest PR=1 state. That is, the actual TM
> SPR val should be loaded into actual registers.
> 
> We already flush TM SPRs into vcpu when switching out of CPU, and load
> TM SPRs when switching back.
> 
> This patch corrects mfspr()/mtspr() emulation for TM SPRs to make the
> actual source/dest based on actual TM SPRs.
> 
> Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
> ---
>  arch/powerpc/include/asm/kvm_book3s.h |  1 +
>  arch/powerpc/kvm/book3s_emulate.c     | 54 ++++++++++++++++++++++++++++-------
>  arch/powerpc/kvm/book3s_pr.c          |  2 +-
>  3 files changed, 46 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
> index 5911c3b..2ecb6a3 100644
> --- a/arch/powerpc/include/asm/kvm_book3s.h
> +++ b/arch/powerpc/include/asm/kvm_book3s.h
> @@ -208,6 +208,7 @@ extern long kvmppc_hv_get_dirty_log_radix(struct kvm *kvm,
>  extern void kvmppc_book3s_dequeue_irqprio(struct kvm_vcpu *vcpu,
>  					  unsigned int vec);
>  extern void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags);
> +extern void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac);
>  extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat,
>  			   bool upper, u32 val);
>  extern void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr);
> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
> index 63af17f..a03533d 100644
> --- a/arch/powerpc/kvm/book3s_emulate.c
> +++ b/arch/powerpc/kvm/book3s_emulate.c
> @@ -523,13 +523,35 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
>  		break;
>  #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
>  	case SPRN_TFHAR:
> -		vcpu->arch.tfhar = spr_val;
> -		break;
>  	case SPRN_TEXASR:
> -		vcpu->arch.texasr = spr_val;
> -		break;
>  	case SPRN_TFIAR:
> -		vcpu->arch.tfiar = spr_val;
> +		if (!cpu_has_feature(CPU_FTR_TM))
> +			break;
> +
> +		if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
> +			kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
> +			emulated = EMULATE_AGAIN;
> +			break;
> +		}
> +
> +		if (MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) {
> +			/* it is illegal to mtspr() TM regs in
> +			 * other than non-transactional state.
> +			 */
> +			kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
> +			emulated = EMULATE_AGAIN;

According to the architecture, mtspr to TFHAR is permitted in
suspended state.

Paul.

WARNING: multiple messages have this Message-ID (diff)
From: Paul Mackerras <paulus@ozlabs.org>
To: wei.guo.simon@gmail.com
Cc: linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org,
	kvm-ppc@vger.kernel.org
Subject: Re: [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs
Date: Tue, 15 May 2018 16:07:03 +1000	[thread overview]
Message-ID: <20180515060703.GC28451@fergus.ozlabs.ibm.com> (raw)
In-Reply-To: <1519753958-11756-7-git-send-email-wei.guo.simon@gmail.com>

On Wed, Feb 28, 2018 at 01:52:25AM +0800, wei.guo.simon@gmail.com wrote:
> From: Simon Guo <wei.guo.simon@gmail.com>
> 
> The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged
> instructions and can be executed at PR KVM guest without trapping
> into host in problem state. We only emulate mtspr/mfspr
> texasr/tfiar/tfhar at guest PR=0 state.
> 
> When we are emulating mtspr tm sprs at guest PR=0 state, the emulation
> result need to be visible to guest PR=1 state. That is, the actual TM
> SPR val should be loaded into actual registers.
> 
> We already flush TM SPRs into vcpu when switching out of CPU, and load
> TM SPRs when switching back.
> 
> This patch corrects mfspr()/mtspr() emulation for TM SPRs to make the
> actual source/dest based on actual TM SPRs.
> 
> Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
> ---
>  arch/powerpc/include/asm/kvm_book3s.h |  1 +
>  arch/powerpc/kvm/book3s_emulate.c     | 54 ++++++++++++++++++++++++++++-------
>  arch/powerpc/kvm/book3s_pr.c          |  2 +-
>  3 files changed, 46 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
> index 5911c3b..2ecb6a3 100644
> --- a/arch/powerpc/include/asm/kvm_book3s.h
> +++ b/arch/powerpc/include/asm/kvm_book3s.h
> @@ -208,6 +208,7 @@ extern long kvmppc_hv_get_dirty_log_radix(struct kvm *kvm,
>  extern void kvmppc_book3s_dequeue_irqprio(struct kvm_vcpu *vcpu,
>  					  unsigned int vec);
>  extern void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags);
> +extern void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac);
>  extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat,
>  			   bool upper, u32 val);
>  extern void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr);
> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
> index 63af17f..a03533d 100644
> --- a/arch/powerpc/kvm/book3s_emulate.c
> +++ b/arch/powerpc/kvm/book3s_emulate.c
> @@ -523,13 +523,35 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
>  		break;
>  #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
>  	case SPRN_TFHAR:
> -		vcpu->arch.tfhar = spr_val;
> -		break;
>  	case SPRN_TEXASR:
> -		vcpu->arch.texasr = spr_val;
> -		break;
>  	case SPRN_TFIAR:
> -		vcpu->arch.tfiar = spr_val;
> +		if (!cpu_has_feature(CPU_FTR_TM))
> +			break;
> +
> +		if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
> +			kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
> +			emulated = EMULATE_AGAIN;
> +			break;
> +		}
> +
> +		if (MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) {
> +			/* it is illegal to mtspr() TM regs in
> +			 * other than non-transactional state.
> +			 */
> +			kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
> +			emulated = EMULATE_AGAIN;

According to the architecture, mtspr to TFHAR is permitted in
suspended state.

Paul.

WARNING: multiple messages have this Message-ID (diff)
From: Paul Mackerras <paulus@ozlabs.org>
To: wei.guo.simon@gmail.com
Cc: linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org,
	kvm@vger.kernel.org
Subject: Re: [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPR
Date: Tue, 15 May 2018 06:07:03 +0000	[thread overview]
Message-ID: <20180515060703.GC28451@fergus.ozlabs.ibm.com> (raw)
In-Reply-To: <1519753958-11756-7-git-send-email-wei.guo.simon@gmail.com>

On Wed, Feb 28, 2018 at 01:52:25AM +0800, wei.guo.simon@gmail.com wrote:
> From: Simon Guo <wei.guo.simon@gmail.com>
> 
> The mfspr/mtspr on TM SPRs(TEXASR/TFIAR/TFHAR) are non-privileged
> instructions and can be executed at PR KVM guest without trapping
> into host in problem state. We only emulate mtspr/mfspr
> texasr/tfiar/tfhar at guest PR=0 state.
> 
> When we are emulating mtspr tm sprs at guest PR=0 state, the emulation
> result need to be visible to guest PR=1 state. That is, the actual TM
> SPR val should be loaded into actual registers.
> 
> We already flush TM SPRs into vcpu when switching out of CPU, and load
> TM SPRs when switching back.
> 
> This patch corrects mfspr()/mtspr() emulation for TM SPRs to make the
> actual source/dest based on actual TM SPRs.
> 
> Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
> ---
>  arch/powerpc/include/asm/kvm_book3s.h |  1 +
>  arch/powerpc/kvm/book3s_emulate.c     | 54 ++++++++++++++++++++++++++++-------
>  arch/powerpc/kvm/book3s_pr.c          |  2 +-
>  3 files changed, 46 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
> index 5911c3b..2ecb6a3 100644
> --- a/arch/powerpc/include/asm/kvm_book3s.h
> +++ b/arch/powerpc/include/asm/kvm_book3s.h
> @@ -208,6 +208,7 @@ extern long kvmppc_hv_get_dirty_log_radix(struct kvm *kvm,
>  extern void kvmppc_book3s_dequeue_irqprio(struct kvm_vcpu *vcpu,
>  					  unsigned int vec);
>  extern void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags);
> +extern void kvmppc_trigger_fac_interrupt(struct kvm_vcpu *vcpu, ulong fac);
>  extern void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat,
>  			   bool upper, u32 val);
>  extern void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr);
> diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
> index 63af17f..a03533d 100644
> --- a/arch/powerpc/kvm/book3s_emulate.c
> +++ b/arch/powerpc/kvm/book3s_emulate.c
> @@ -523,13 +523,35 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
>  		break;
>  #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
>  	case SPRN_TFHAR:
> -		vcpu->arch.tfhar = spr_val;
> -		break;
>  	case SPRN_TEXASR:
> -		vcpu->arch.texasr = spr_val;
> -		break;
>  	case SPRN_TFIAR:
> -		vcpu->arch.tfiar = spr_val;
> +		if (!cpu_has_feature(CPU_FTR_TM))
> +			break;
> +
> +		if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
> +			kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
> +			emulated = EMULATE_AGAIN;
> +			break;
> +		}
> +
> +		if (MSR_TM_ACTIVE(kvmppc_get_msr(vcpu))) {
> +			/* it is illegal to mtspr() TM regs in
> +			 * other than non-transactional state.
> +			 */
> +			kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
> +			emulated = EMULATE_AGAIN;

According to the architecture, mtspr to TFHAR is permitted in
suspended state.

Paul.

  reply	other threads:[~2018-05-15  6:07 UTC|newest]

Thread overview: 78+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-27 17:52 [PATCH v2 11/30] KVM: PPC: Book3S PR: implement RFID TM behavior to suppress change from S0 to N0 wei.guo.simon
2018-02-27 17:52 ` wei.guo.simon
2018-02-27 17:52 ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 12/30] KVM: PPC: Book3S PR: prevent TS bits change in kvmppc_interrupt_pr() wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 13/30] KVM: PPC: Book3S PR: adds new kvmppc_copyto_vcpu_tm/kvmppc_copyfrom_vcpu_tm API for PR KVM wei.guo.simon
2018-02-27 17:52   ` [PATCH v2 13/30] KVM: PPC: Book3S PR: adds new kvmppc_copyto_vcpu_tm/kvmppc_copyfrom_vcpu_tm API for wei.guo.simon
2018-02-27 17:52   ` [PATCH v2 13/30] KVM: PPC: Book3S PR: adds new kvmppc_copyto_vcpu_tm/kvmppc_copyfrom_vcpu_tm API for PR KVM wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 14/30] KVM: PPC: Book3S PR: add kvmppc_save/restore_tm_sprs() APIs wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 15/30] KVM: PPC: Book3S PR: add transaction memory save/restore skeleton for PR KVM wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 16/30] KVM: PPC: Book3S PR: add math support for PR KVM HTM wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-05-15  6:07   ` Paul Mackerras [this message]
2018-05-15  6:07     ` [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPR Paul Mackerras
2018-05-15  6:07     ` [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs Paul Mackerras
2018-05-15 12:58     ` Simon Guo
2018-05-15 12:58       ` [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPR Simon Guo
2018-05-15 12:58       ` [PATCH v2 17/30] KVM: PPC: Book3S PR: make mtspr/mfspr emulation behavior based on active TM SPRs Simon Guo
2018-02-27 17:52 ` [PATCH v2 18/30] KVM: PPC: Book3S PR: always fail transaction in guest privilege state wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-05-15  6:07   ` Paul Mackerras
2018-05-15  6:07     ` Paul Mackerras
2018-05-15  6:07     ` Paul Mackerras
2018-05-16  1:35     ` Simon Guo
2018-05-16  1:35       ` Simon Guo
2018-05-16  1:35       ` Simon Guo
2018-02-27 17:52 ` [PATCH v2 19/30] KVM: PPC: Book3S PR: enable NV reg restore for reading TM SPR at " wei.guo.simon
2018-02-27 17:52   ` [PATCH v2 19/30] KVM: PPC: Book3S PR: enable NV reg restore for reading TM SPR at guest privilege st wei.guo.simon
2018-02-27 17:52   ` [PATCH v2 19/30] KVM: PPC: Book3S PR: enable NV reg restore for reading TM SPR at guest privilege state wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 20/30] KVM: PPC: Book3S PR: adds emulation for treclaim wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 21/30] KVM: PPC: Book3S PR: add emulation for trechkpt in PR KVM wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 22/30] KVM: PPC: Book3S PR: add emulation for tabort. for privilege guest wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 23/30] KVM: PPC: Book3S PR: add guard code to prevent returning to guest with PR=0 and Transactional state wei.guo.simon
2018-02-27 17:52   ` [PATCH v2 23/30] KVM: PPC: Book3S PR: add guard code to prevent returning to guest with PR=0 and Tra wei.guo.simon
2018-02-27 17:52   ` [PATCH v2 23/30] KVM: PPC: Book3S PR: add guard code to prevent returning to guest with PR=0 and Transactional state wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 24/30] KVM: PPC: Book3S PR: Support TAR handling for PR KVM HTM wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 25/30] KVM: PPC: Book3S PR: enable HTM for PR KVM for KVM_CHECK_EXTENSION ioctl wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 26/30] KVM: PPC: move vcpu_load/vcpu_put down to each ioctl case in kvm_arch_vcpu_ioctl wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 27/30] KVM: PPC: remove load/put vcpu for KVM_GET/SET_ONE_REG ioctl wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 28/30] KVM: PPC: remove load/put vcpu for KVM_GET_REGS/KVM_SET_REGS wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52 ` [PATCH v2 29/30] KVM: PPC: add KVM_SET_ONE_REG/KVM_GET_ONE_REG to async ioctl wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-05-15  6:15   ` Paul Mackerras
2018-05-15  6:15     ` Paul Mackerras
2018-05-15  6:15     ` Paul Mackerras
2018-05-16  2:13     ` Simon Guo
2018-05-16  2:13       ` Simon Guo
2018-05-16  2:13       ` Simon Guo
2018-02-27 17:52 ` [PATCH v2 30/30] KVM: PPC: Book3S PR: enable kvmppc_get/set_one_reg_pr() for HTM registers wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon
2018-02-27 17:52   ` wei.guo.simon

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