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From: Boris Brezillon <boris.brezillon@bootlin.com>
To: David Woodhouse <dwmw2@infradead.org>,
	Brian Norris <computersforpeace@gmail.com>,
	Boris Brezillon <boris.brezillon@bootlin.com>,
	Marek Vasut <marek.vasut@gmail.com>,
	Richard Weinberger <richard@nod.at>,
	linux-mtd@lists.infradead.org,
	Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Peter Pan <peterpansjtu@gmail.com>,
	Frieder Schrempf <frieder.schrempf@exceet.de>,
	Vignesh R <vigneshr@ti.com>,
	Xiangsheng Hou <xiangsheng.hou@mediatek.com>
Subject: [PATCH v7 3/5] dt-bindings: Add bindings for SPI NAND devices
Date: Tue, 15 May 2018 17:08:23 +0200	[thread overview]
Message-ID: <20180515150825.19835-4-boris.brezillon@bootlin.com> (raw)
In-Reply-To: <20180515150825.19835-1-boris.brezillon@bootlin.com>

Add bindigns for SPI NAND chips.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
 Documentation/devicetree/bindings/mtd/spi-nand.txt | 27 ++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/spi-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/spi-nand.txt b/Documentation/devicetree/bindings/mtd/spi-nand.txt
new file mode 100644
index 000000000000..d55f80196c63
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/spi-nand.txt
@@ -0,0 +1,27 @@
+SPI NAND flash
+
+Required properties:
+- compatible: should be "spi-nand"
+- reg: should encode the chip-select line used to access the NAND chip
+
+Optional properties
+- spi-max-frequency: maximum frequency of the SPI bus the chip can operate at.
+		     This should encode board limitations (i.e. max freq can't
+		     be achieved due to crosstalk on IO lines).
+		     When unspecified, the driver assumes the chip can run at
+		     the max frequency defined in the spec (information
+		     extracted chip detection time).
+- spi-tx-bus-width: The bus width (number of data wires) that is used for MOSI.
+		    Only encodes the board constraints (i.e. when not all IO
+		    signals are routed on the board). Device constraints are
+		    extracted when detecting the chip, and controller
+		    constraints are exposed by the SPI mem controller. If this
+		    property is missing that means no constraint at the board
+		    level.
+- spi-rx-bus-width: The bus width (number of data wires) that is used for MISO.
+		    Only encodes the board constraints (i.e. when not all IO
+		    signals are routed on the board). Device constraints are
+		    extracted when detecting the chip, and controller
+		    constraints are exposed by the SPI mem controller. If this
+		    property is missing that means no constraint at the board
+		    level.
-- 
2.14.1

  parent reply	other threads:[~2018-05-15 15:09 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-15 15:08 [PATCH v7 0/5] mtd: Add a SPI NAND driver Boris Brezillon
2018-05-15 15:08 ` [PATCH v7 1/5] mtd: nand: Pass mode information to nand_page_io_req Boris Brezillon
2018-06-01 10:11   ` Miquel Raynal
2018-06-01 10:17   ` Frieder Schrempf
2018-06-01 12:55   ` Boris Brezillon
2018-05-15 15:08 ` [PATCH v7 2/5] mtd: nand: Add core infrastructure to support SPI NANDs Boris Brezillon
2018-05-29 10:57   ` Frieder Schrempf
2018-05-29 13:35     ` Boris Brezillon
2018-05-29 14:59       ` Frieder Schrempf
2018-06-01 10:22         ` Frieder Schrempf
2018-05-31  7:30   ` Miquel Raynal
2018-05-31  7:38     ` Boris Brezillon
2018-05-15 15:08 ` Boris Brezillon [this message]
2018-05-15 15:08 ` [PATCH v7 4/5] mtd: nand: spi: Add initial support for Micron MT29F2G01ABAGD Boris Brezillon
2018-05-15 15:08 ` [PATCH v7 5/5] mtd: nand: spi: Add initial support for Winbond W25M02GV Boris Brezillon
2018-05-15 22:59   ` Miquel Raynal
2018-05-16  7:07     ` Boris Brezillon
2018-05-17  6:33 ` [PATCH v7 0/5] mtd: Add a SPI NAND driver Prabhakar Kushwaha
2018-05-17  7:05   ` Boris Brezillon
2018-05-17 10:01     ` Prabhakar Kushwaha
2018-05-17 10:22       ` Frieder Schrempf

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