From: Keith Busch <keith.busch@linux.intel.com>
To: Bharat Kumar Gogada <bharatku@xilinx.com>
Cc: "linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"keith.busch@intel.com" <keith.busch@intel.com>,
"axboe@fb.com" <axboe@fb.com>, "hch@lst.de" <hch@lst.de>,
"sagi@grimberg.me" <sagi@grimberg.me>
Subject: Re: INTMS/INTMC not being used in NVME interrupt handling
Date: Wed, 16 May 2018 08:42:40 -0600 [thread overview]
Message-ID: <20180516144240.GA20223@localhost.localdomain> (raw)
In-Reply-To: <BLUPR0201MB1505371050ED798BE025132BA5920@BLUPR0201MB1505.namprd02.prod.outlook.com>
On Wed, May 16, 2018 at 12:35:15PM +0000, Bharat Kumar Gogada wrote:
> Hi,
>
> As per NVME specification:
> 7.5.1.1 Host Software Interrupt Handling
> It is recommended that host software utilize the Interrupt Mask Set and Interrupt Mask Clear (INTMS/INTMC)
> registers to efficiently handle interrupts when configured to use pin based or MSI messages.
>
> In kernel 4.14, drivers/nvme/host/pci.c function nvme_isr
> doesn't use these registers.
>
> Any reason why these registers are not used in nvme interrupt handler ?
I think you've answered your own question: we process completions in the
interrupt context. The interrupt is already masked at the CPU level in
this context, so there should be no reason to mask them at the device
level.
> Why NVMe driver is not using any bottom half and processing all completion queues
> in interrupt handler ?
Performance.
WARNING: multiple messages have this Message-ID (diff)
From: keith.busch@linux.intel.com (Keith Busch)
Subject: INTMS/INTMC not being used in NVME interrupt handling
Date: Wed, 16 May 2018 08:42:40 -0600 [thread overview]
Message-ID: <20180516144240.GA20223@localhost.localdomain> (raw)
In-Reply-To: <BLUPR0201MB1505371050ED798BE025132BA5920@BLUPR0201MB1505.namprd02.prod.outlook.com>
On Wed, May 16, 2018@12:35:15PM +0000, Bharat Kumar Gogada wrote:
> Hi,
>
> As per NVME specification:
> 7.5.1.1 Host Software Interrupt Handling
> It is recommended that host software utilize the Interrupt Mask Set and Interrupt Mask Clear (INTMS/INTMC)
> registers to efficiently handle interrupts when configured to use pin based or MSI messages.
>
> In kernel 4.14, drivers/nvme/host/pci.c function nvme_isr
> doesn't use these registers.
>
> Any reason why these registers are not used in nvme interrupt handler ?
I think you've answered your own question: we process completions in the
interrupt context. The interrupt is already masked at the CPU level in
this context, so there should be no reason to mask them at the device
level.
> Why NVMe driver is not using any bottom half and processing all completion queues
> in interrupt handler ?
Performance.
next prev parent reply other threads:[~2018-05-16 14:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-16 12:35 INTMS/INTMC not being used in NVME interrupt handling Bharat Kumar Gogada
2018-05-16 12:35 ` Bharat Kumar Gogada
2018-05-16 14:42 ` Keith Busch [this message]
2018-05-16 14:42 ` Keith Busch
2018-05-17 11:15 ` Bharat Kumar Gogada
2018-05-17 11:15 ` Bharat Kumar Gogada
2018-05-17 18:04 ` Keith Busch
2018-05-17 18:04 ` Keith Busch
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