[PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs

[PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs

[Alex Deucher]

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h  | 4 ++++
 drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
index 2b305dd021e8..e6044e27a913 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
@@ -30,4 +30,8 @@
 #define mmDF_CS_AON0_DramBaseAddress0									0x0044
 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX								0
 
+#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0								0x0214
+#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX							0
+
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
index 2ba849798924..a78c99480e2d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
@@ -45,4 +45,8 @@
 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK							0x00000700L
 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK							0xFFFFF000L
 
+//DF_CS_AON0_CoherentSlaveModeCtrlA0
+#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT					0x3
+#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK						0x00000008L
+
 #endif
-- 
2.13.6

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[PATCH 2/4] drm/amdgpu: add new DF callback for ECC setup

[Alex Deucher]

The ForceParWrRMW setting needs to be enabled for ECC, but disabled
when ECC is not enabled.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 03a2c0be0bf2..a59c07590cee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1401,6 +1401,8 @@ struct amdgpu_df_funcs {
 						 bool enable);
 	void (*get_clockgating_state)(struct amdgpu_device *adev,
 				      u32 *flags);
+	void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
+					    bool enable);
 };
 /* Define the HW IP blocks will be used in driver , add more if necessary */
 enum amd_hw_ip_block_type {
-- 
2.13.6

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[PATCH 3/4] drm/amdgpu: add a df 1.7 implementation of enable_ecc_force_par_wr_rmw

[Alex Deucher]

Needed for proper memory setup depending on whether ECC is
enabled on a particular board.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/df_v1_7.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
index 4ffda996660f..9935371db7ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v1_7.c
@@ -102,6 +102,13 @@ static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
 		*flags |= AMD_CG_SUPPORT_DF_MGCG;
 }
 
+static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
+						bool enable)
+{
+	WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
+		       ForceParWrRMW, enable);
+}
+
 const struct amdgpu_df_funcs df_v1_7_funcs = {
 	.init = df_v1_7_init,
 	.enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
@@ -109,4 +116,5 @@ const struct amdgpu_df_funcs df_v1_7_funcs = {
 	.get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
 	.update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
 	.get_clockgating_state = df_v1_7_get_clockgating_state,
+	.enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
 };
-- 
2.13.6

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[PATCH 4/4] drm/amdgpu/gmc9: disable partial wr rmw if ECC is not enabled

[Alex Deucher]

The vbios mistakenly sets this bit on some boards without ECC.
This can lead to reduced performance in some workloads.  Disable
the bit if the board does not have ECC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index b60ed288d314..3c0a85d4e4ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -675,6 +675,7 @@ static int gmc_v9_0_late_init(void *handle)
 			DRM_INFO("ECC is active.\n");
 		} else if (r == 0) {
 			DRM_INFO("ECC is not present.\n");
+			adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false);
 		} else {
 			DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
 			return r;
-- 
2.13.6

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Re: [PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs

[Alex Deucher]

Ping?

On Wed, May 16, 2018 at 4:51 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h  | 4 ++++
>  drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4 ++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> index 2b305dd021e8..e6044e27a913 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> @@ -30,4 +30,8 @@
>  #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
>  #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
>
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0                                                           0x0214
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX                                                  0
> +
> +
>  #endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> index 2ba849798924..a78c99480e2d 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> @@ -45,4 +45,8 @@
>  #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                 0x00000700L
>  #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                 0xFFFFF000L
>
> +//DF_CS_AON0_CoherentSlaveModeCtrlA0
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT                                       0x3
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK                                         0x00000008L
> +
>  #endif
> --
> 2.13.6
>
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RE: [PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs

[Zhang, Hawking]

Series is Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: 2018年5月19日 3:48
To: amd-gfx list <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: Re: [PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs

Ping?

On Wed, May 16, 2018 at 4:51 PM, Alex Deucher <alexdeucher@gmail.com> wrote:
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h  | 4 ++++  
> drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4 ++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h 
> b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> index 2b305dd021e8..e6044e27a913 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> @@ -30,4 +30,8 @@
>  #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
>  #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
>
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0                                                           0x0214
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX                                                  0
> +
> +
>  #endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h 
> b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> index 2ba849798924..a78c99480e2d 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> @@ -45,4 +45,8 @@
>  #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                 0x00000700L
>  #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                 0xFFFFF000L
>
> +//DF_CS_AON0_CoherentSlaveModeCtrlA0
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT                                       0x3
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK                                         0x00000008L
> +
>  #endif
> --
> 2.13.6
>
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Re: [PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs

[Zhang, Jerry (Junwei)]

On 05/17/2018 04:51 AM, Alex Deucher wrote:
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

> ---
>   drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h  | 4 ++++
>   drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4 ++++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> index 2b305dd021e8..e6044e27a913 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> @@ -30,4 +30,8 @@
>   #define mmDF_CS_AON0_DramBaseAddress0									0x0044
>   #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX								0
>
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0								0x0214
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX							0
> +
> +
>   #endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> index 2ba849798924..a78c99480e2d 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> @@ -45,4 +45,8 @@
>   #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK							0x00000700L
>   #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK							0xFFFFF000L
>
> +//DF_CS_AON0_CoherentSlaveModeCtrlA0
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT					0x3
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK						0x00000008L
> +
>   #endif
>
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Re: [PATCH 1/4] drm/amdgpu: add new DF 1.7 register defs

[Zhang, Jerry (Junwei)]

On 05/17/2018 04:51 AM, Alex Deucher wrote:
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Series is
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

> ---
>   drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h  | 4 ++++
>   drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h | 4 ++++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> index 2b305dd021e8..e6044e27a913 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h
> @@ -30,4 +30,8 @@
>   #define mmDF_CS_AON0_DramBaseAddress0									0x0044
>   #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX								0
>
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0								0x0214
> +#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX							0
> +
> +
>   #endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> index 2ba849798924..a78c99480e2d 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h
> @@ -45,4 +45,8 @@
>   #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK							0x00000700L
>   #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK							0xFFFFF000L
>
> +//DF_CS_AON0_CoherentSlaveModeCtrlA0
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT					0x3
> +#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK						0x00000008L
> +
>   #endif
>
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